From ccf772495692c98d3c0af995bc423cb08ad80d92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 15 Nov 2013 07:55:23 +0000 Subject: [PATCH] fixed comments --- BaS_gcc/sources/mmu.S | 6 +++--- BaS_gcc/sources/pci.c | 7 ++++++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/BaS_gcc/sources/mmu.S b/BaS_gcc/sources/mmu.S index 5480ae2..1c42e22 100644 --- a/BaS_gcc/sources/mmu.S +++ b/BaS_gcc/sources/mmu.S @@ -210,10 +210,10 @@ _mmu_init: // move.l #0x80000000|std_mmutr,d0 move.l #0x80000000|nocache_precise_mmudr|MCF_MMU_MMUDR_LK,d1 - move.l d0,MCF_MMU_MMUTR + move.l d0,MCF_MMU_MMUTR move.l d1,MCF_MMU_MMUDR - move.l d2,MCF_MMU_MMUOR // mapped to ffffxxx, precise, - move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise, + move.l d2,MCF_MMU_MMUOR + move.l d3,MCF_MMU_MMUOR // maps (locked) the last MB (this is where BaS .data and .bss resides) of physical SDRAM to the same physical address move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0 diff --git a/BaS_gcc/sources/pci.c b/BaS_gcc/sources/pci.c index 52b94e6..ccf87dd 100644 --- a/BaS_gcc/sources/pci.c +++ b/BaS_gcc/sources/pci.c @@ -749,6 +749,7 @@ void init_pci(void) | MCF_PCIARB_PACR_INTMINTEN /* enable "internal master broken" interrupt */ | MCF_PCIARB_PACR_EXTMINTEN(0x1F); /* enable "external master broken" interrupt */ +#ifdef _NOT_USED_ /* since this is already done in sysinit.c */ #if MACHINE_FIREBEE //MCF_PAD_PAR_PCIBG = 0x3f; // FIXME: MiNT initialization hangs if this is enabled ??? //MCF_PAD_PAR_PCIBR = 0x3f; @@ -756,6 +757,7 @@ void init_pci(void) MCF_PAD_PAR_PCIBG = 0x3ff; /* enable all PCI bus grant and bus requests on the LITE board */ MCF_PAD_PAR_PCIBR = 0x3ff; #endif /* MACHINE_FIREBEE */ +#endif /* _NOT_USED_ */ MCF_PCI_PCISCR = MCF_PCI_PCISCR_M | /* memory access control enabled */ MCF_PCI_PCISCR_B | /* bus master enabled */ @@ -796,7 +798,10 @@ void init_pci(void) MCF_PCI_PCIIWCR_WINCTRL0_E | MCF_PCI_PCIIWCR_WINCTRL1_E; - /* initialize target control register */ + /* + * Initialize target control register. + * Used when an external bus master accesses the Coldfire PCI as target + */ MCF_PCI_PCIBAR0 = 0x40000000; /* 256 kB window */ MCF_PCI_PCITBATR0 = (uint32_t) &_MBAR[0] | MCF_PCI_PCITBATR0_EN; /* target base address translation register 0 */ MCF_PCI_PCIBAR1 = 0; /* 1GB window */