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started "full fledged" testbench to analyze where fb_ta_n gets lost

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This commit is contained in:
Markus Fröschle
2014-12-23 14:56:53 +00:00
parent 5c9253c6a9
commit c197609be6
7 changed files with 518 additions and 44 deletions
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4
vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd
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@@ -50,7 +50,7 @@ use ieee.numeric_std.all;
entity FBEE_BLITTER is
port(
RESETn : in std_logic;
reset_n : in std_logic;
CLK_MAIN : in std_logic;
CLK_DDR0 : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0);
@@ -59,7 +59,7 @@ entity FBEE_BLITTER is
FB_SIZE0 : in std_logic;
fb_cs_n : in std_logic_vector(3 downto 1);
fb_oe_n : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_EN : out std_logic;

2
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
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@@ -262,11 +262,11 @@ BEGIN
fb_le(3) <= NOT fb_wr_n WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0';
-- video data access:
video_ddr_ta <= '1' WHEN fb_regddr = fr_s0 AND ddr_cs = '1' ELSE
'1' WHEN fb_regddr = fr_s1 AND ddr_cs = '1' ELSE
'1' WHEN fb_regddr = fr_s2 AND fb_regddr_next = fr_s3 ELSE
'1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0';
-- fb_vdoe # VIDEO_OE.
-- Write access for video data:

70
vhdl/rtl/vhdl/Firebee/Firebee.vhd
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@@ -833,31 +833,31 @@ BEGIN
ddrwr_d_sel1 => ddrwr_d_sel(1)
);
-- I_BLITTER: FBEE_BLITTER
-- PORT MAP(
-- resetn => reset_n,
-- clk_main => clk_main,
-- clk_ddr0 => clk_ddr(0),
-- fb_adr => fb_adr,
-- fb_ale => fb_ale,
-- fb_size1 => fb_size(1),
-- fb_size0 => fb_size(0),
-- fb_cs_n => fb_cs_n,
-- fb_oe_n => fb_oe_n,
-- fb_wr_n => fb_wr_n,
-- data_in => fb_ad,
-- data_out => data_out_blitter,
-- DATA_EN => data_en_blitter,
-- blitter_adr => blitter_adr,
-- blitter_sig => blitter_sig,
-- blitter_wr => blitter_wr,
-- blitter_on => blitter_on,
-- blitter_run => blitter_run,
-- BLITTER_DIN => vd_vz,
-- blitter_dout => blitter_dout,
-- blitter_ta => blitter_ta,
-- blitter_dack_sr => blitter_dack_sr
-- );
I_BLITTER: FBEE_BLITTER
PORT MAP(
reset_n => reset_n,
clk_main => clk_main,
clk_ddr0 => clk_ddr(0),
fb_adr => fb_adr,
fb_ale => fb_ale,
fb_size1 => fb_size(1),
fb_size0 => fb_size(0),
fb_cs_n => fb_cs_n,
fb_oe_n => fb_oe_n,
fb_wr_n => fb_wr_n,
data_in => fb_ad,
data_out => data_out_blitter,
DATA_EN => data_en_blitter,
blitter_adr => blitter_adr,
blitter_sig => blitter_sig,
blitter_wr => blitter_wr,
blitter_on => blitter_on,
blitter_run => blitter_run,
BLITTER_DIN => vd_vz,
blitter_dout => blitter_dout,
blitter_ta => blitter_ta,
blitter_dack_sr => blitter_dack_sr
);
I_VIDEOSYSTEM: VIDEO_SYSTEM
PORT MAP(
@@ -879,8 +879,8 @@ BEGIN
fb_ad_en_31_16 => fb_ad_en_31_16_video,
fb_ad_en_15_0 => fb_ad_en_15_0_video,
fb_ale => fb_ale,
fb_cs_n => fb_cs_n,
fb_oe_n => fb_oe_n,
fb_cs_n => fb_cs_n,
fb_oe_n => fb_oe_n,
fb_wr_n => FB_WR_n,
fb_size1 => fb_size(1),
fb_size0 => fb_size(0),
@@ -896,10 +896,10 @@ BEGIN
blue => vb,
vsync => vsync_i,
hsync => hsync_i,
sync_n => sync_n,
blank_n => blank_i_n,
sync_n => sync_n,
blank_n => blank_i_n,
pd_vga_n => pd_vga_n,
pd_vga_n => pd_vga_n,
video_mod_ta => video_mod_ta,
vd_vz => vd_vz,
@@ -917,7 +917,7 @@ BEGIN
I_INTHANDLER: INTHANDLER
PORT MAP(
clk_main => clk_main,
reset_n => reset_n,
reset_n => reset_n,
fb_adr => fb_adr,
fb_cs_n => fb_cs_n(2 DOWNTO 1),
fb_oe_n => fb_oe_n,
@@ -957,9 +957,9 @@ BEGIN
fb_adr => fb_adr(26 DOWNTO 0),
fb_ale => fb_ale,
fb_size => fb_size,
fb_cs_n => fb_cs_n(2 DOWNTO 1),
fb_oe_n => fb_oe_n,
fb_wr_n => fb_wr_n,
fb_cs_n => fb_cs_n(2 DOWNTO 1),
fb_oe_n => fb_oe_n,
fb_wr_n => fb_wr_n,
fb_ad_IN => fb_ad,
fb_ad_OUT => fb_ad_out_dma,
fb_ad_EN_31_24 => fb_ad_en_31_24_dma,
@@ -979,7 +979,7 @@ BEGIN
DATA_IN_FDC => data_out_fdc,
DATA_IN_SCSI => data_out_scsi,
data_out_fdc_SCSI => data_in_fdc_scsi,
data_out_fdc_SCSI => data_in_fdc_scsi,
DMA_DRQ_IN => drq_fdc,
DMA_DRQ_OUT => drq_dma,

2
vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd
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@@ -340,7 +340,7 @@ PACKAGE firebee_pkg IS
COMPONENT FBEE_BLITTER is
PORT(
RESETn : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
clk_main : IN STD_LOGIC;
CLK_DDR0 : IN STD_LOGIC;
fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

2
vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
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@@ -242,7 +242,7 @@ BEGIN
ccr <= ccr_i;
inter_zei <= inter_zei_i;
video_mod_ta <= video_mod_ta_i;
vr_rd <= vr_rd_i;
vr_rd <= vr_rd_i;
clk_pixel <= clk_pixel_i;
-- Byte selectors: