diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index 3737578..447f5ad 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -55,7 +55,7 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation -set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ddr_ctlr_tb -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH firebee_tb -section_id eda_simulation set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name USE_CONFIGURATION_DEVICE OFF @@ -639,8 +639,6 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_DDR_OUT set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_25M -set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb -set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb set_location_assignment PIN_AB18 -to VCAS_n set_location_assignment PIN_W17 -to VRAS_n set_instance_assignment -name IO_STANDARD "2.5 V" -to VRAS_n @@ -690,4 +688,12 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[3] set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4] set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name VHDL_FILE ../../../testbenches/firebee_tb.vhd +set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb +set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb +set_global_assignment -name EDA_TEST_BENCH_NAME firebee_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME firebee_tb -section_id firebee_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 s" -section_id firebee_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME firebee_tb -section_id firebee_tb +set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb \ No newline at end of file diff --git a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd index ebfc3b3..c072dbb 100644 --- a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd +++ b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd @@ -50,7 +50,7 @@ use ieee.numeric_std.all; entity FBEE_BLITTER is port( - RESETn : in std_logic; + reset_n : in std_logic; CLK_MAIN : in std_logic; CLK_DDR0 : in std_logic; FB_ADR : in std_logic_vector(31 downto 0); @@ -59,7 +59,7 @@ entity FBEE_BLITTER is FB_SIZE0 : in std_logic; fb_cs_n : in std_logic_vector(3 downto 1); fb_oe_n : in std_logic; - FB_WRn : in std_logic; + fb_wr_n : in std_logic; DATA_IN : in std_logic_vector(31 downto 0); DATA_OUT : out std_logic_vector(31 downto 0); DATA_EN : out std_logic; diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index 6d0cad7..e0ce91a 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -262,11 +262,11 @@ BEGIN fb_le(3) <= NOT fb_wr_n WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0'; -- video data access: + video_ddr_ta <= '1' WHEN fb_regddr = fr_s0 AND ddr_cs = '1' ELSE '1' WHEN fb_regddr = fr_s1 AND ddr_cs = '1' ELSE '1' WHEN fb_regddr = fr_s2 AND fb_regddr_next = fr_s3 ELSE '1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0'; - -- fb_vdoe # VIDEO_OE. -- Write access for video data: diff --git a/vhdl/rtl/vhdl/Firebee/Firebee.vhd b/vhdl/rtl/vhdl/Firebee/Firebee.vhd index 810dd0f..dcb0cea 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee.vhd @@ -833,31 +833,31 @@ BEGIN ddrwr_d_sel1 => ddrwr_d_sel(1) ); --- I_BLITTER: FBEE_BLITTER --- PORT MAP( --- resetn => reset_n, --- clk_main => clk_main, --- clk_ddr0 => clk_ddr(0), --- fb_adr => fb_adr, --- fb_ale => fb_ale, --- fb_size1 => fb_size(1), --- fb_size0 => fb_size(0), --- fb_cs_n => fb_cs_n, --- fb_oe_n => fb_oe_n, --- fb_wr_n => fb_wr_n, --- data_in => fb_ad, --- data_out => data_out_blitter, --- DATA_EN => data_en_blitter, --- blitter_adr => blitter_adr, --- blitter_sig => blitter_sig, --- blitter_wr => blitter_wr, --- blitter_on => blitter_on, --- blitter_run => blitter_run, --- BLITTER_DIN => vd_vz, --- blitter_dout => blitter_dout, --- blitter_ta => blitter_ta, --- blitter_dack_sr => blitter_dack_sr --- ); + I_BLITTER: FBEE_BLITTER + PORT MAP( + reset_n => reset_n, + clk_main => clk_main, + clk_ddr0 => clk_ddr(0), + fb_adr => fb_adr, + fb_ale => fb_ale, + fb_size1 => fb_size(1), + fb_size0 => fb_size(0), + fb_cs_n => fb_cs_n, + fb_oe_n => fb_oe_n, + fb_wr_n => fb_wr_n, + data_in => fb_ad, + data_out => data_out_blitter, + DATA_EN => data_en_blitter, + blitter_adr => blitter_adr, + blitter_sig => blitter_sig, + blitter_wr => blitter_wr, + blitter_on => blitter_on, + blitter_run => blitter_run, + BLITTER_DIN => vd_vz, + blitter_dout => blitter_dout, + blitter_ta => blitter_ta, + blitter_dack_sr => blitter_dack_sr + ); I_VIDEOSYSTEM: VIDEO_SYSTEM PORT MAP( @@ -879,8 +879,8 @@ BEGIN fb_ad_en_31_16 => fb_ad_en_31_16_video, fb_ad_en_15_0 => fb_ad_en_15_0_video, fb_ale => fb_ale, - fb_cs_n => fb_cs_n, - fb_oe_n => fb_oe_n, + fb_cs_n => fb_cs_n, + fb_oe_n => fb_oe_n, fb_wr_n => FB_WR_n, fb_size1 => fb_size(1), fb_size0 => fb_size(0), @@ -896,10 +896,10 @@ BEGIN blue => vb, vsync => vsync_i, hsync => hsync_i, - sync_n => sync_n, - blank_n => blank_i_n, + sync_n => sync_n, + blank_n => blank_i_n, - pd_vga_n => pd_vga_n, + pd_vga_n => pd_vga_n, video_mod_ta => video_mod_ta, vd_vz => vd_vz, @@ -917,7 +917,7 @@ BEGIN I_INTHANDLER: INTHANDLER PORT MAP( clk_main => clk_main, - reset_n => reset_n, + reset_n => reset_n, fb_adr => fb_adr, fb_cs_n => fb_cs_n(2 DOWNTO 1), fb_oe_n => fb_oe_n, @@ -957,9 +957,9 @@ BEGIN fb_adr => fb_adr(26 DOWNTO 0), fb_ale => fb_ale, fb_size => fb_size, - fb_cs_n => fb_cs_n(2 DOWNTO 1), - fb_oe_n => fb_oe_n, - fb_wr_n => fb_wr_n, + fb_cs_n => fb_cs_n(2 DOWNTO 1), + fb_oe_n => fb_oe_n, + fb_wr_n => fb_wr_n, fb_ad_IN => fb_ad, fb_ad_OUT => fb_ad_out_dma, fb_ad_EN_31_24 => fb_ad_en_31_24_dma, @@ -979,7 +979,7 @@ BEGIN DATA_IN_FDC => data_out_fdc, DATA_IN_SCSI => data_out_scsi, - data_out_fdc_SCSI => data_in_fdc_scsi, + data_out_fdc_SCSI => data_in_fdc_scsi, DMA_DRQ_IN => drq_fdc, DMA_DRQ_OUT => drq_dma, diff --git a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd index 0551586..de78ff2 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd @@ -340,7 +340,7 @@ PACKAGE firebee_pkg IS COMPONENT FBEE_BLITTER is PORT( - RESETn : IN STD_LOGIC; + reset_n : IN STD_LOGIC; clk_main : IN STD_LOGIC; CLK_DDR0 : IN STD_LOGIC; fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); diff --git a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd index a53f880..dcfd28b 100644 --- a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd +++ b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd @@ -242,7 +242,7 @@ BEGIN ccr <= ccr_i; inter_zei <= inter_zei_i; video_mod_ta <= video_mod_ta_i; - vr_rd <= vr_rd_i; + vr_rd <= vr_rd_i; clk_pixel <= clk_pixel_i; -- Byte selectors: diff --git a/vhdl/testbenches/firebee_tb.vhd b/vhdl/testbenches/firebee_tb.vhd new file mode 100644 index 0000000..fd1e115 --- /dev/null +++ b/vhdl/testbenches/firebee_tb.vhd @@ -0,0 +1,468 @@ +LIBRARY work; + USE work.firebee_pkg.ALL; +-- USE work.ddr2_ram_model_pkg.ALL; + +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.ALL; + +USE std.textio.ALL; + + +ENTITY firebee_tb IS +END firebee_tb; + + +ARCHITECTURE beh OF firebee_tb IS + COMPONENT firebee IS + PORT( + rsto_mcf_n : IN STD_LOGIC; -- reset SIGNAL from Coldfire + clk_33m : IN STD_LOGIC; -- 33 MHz clock + clk_main : IN STD_LOGIC; -- 33 MHz clock + + clk_24m576 : OUT STD_LOGIC; -- + clk_25m : OUT STD_LOGIC; + clk_ddr_out : OUT STD_LOGIC; + clk_ddr_out_n : OUT STD_LOGIC; + clk_usb : OUT STD_LOGIC; + + fb_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); + fb_ale : IN STD_LOGIC; + fb_burst_n : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR (3 DOWNTO 1); + fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + fb_oe_n : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; + fb_ta_n : OUT STD_LOGIC; + + dack1_n : IN STD_LOGIC; + dreq1_n : OUT STD_LOGIC; + + master_n : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. + tout0_n : IN STD_LOGIC; -- Not used so far. + + led_fpga_ok : OUT STD_LOGIC; + reserved_1 : OUT STD_LOGIC; + + va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); + ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + vwe_n : OUT STD_LOGIC; + vcas_n : OUT STD_LOGIC; + vras_n : OUT STD_LOGIC; + vcs_n : OUT STD_LOGIC; + + clk_pixel : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + vsync : OUT STD_LOGIC; + hsync : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; + + vr : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + vg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + vb : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + + vdm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + + vd : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); + vd_qs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + + pd_vga_n : OUT STD_LOGIC; + vcke : OUT STD_LOGIC; + pic_int : IN STD_LOGIC; + e0_int : IN STD_LOGIC; + dvi_int : IN STD_LOGIC; + pci_inta_n : IN STD_LOGIC; + pci_intb_n : IN STD_LOGIC; + pci_intc_n : IN STD_LOGIC; + pci_intd_n : IN STD_LOGIC; + + irq_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 2); + tin0 : OUT STD_LOGIC; + + ym_qa : OUT STD_LOGIC; + ym_qb : OUT STD_LOGIC; + ym_qc : OUT STD_LOGIC; + + lp_d : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); + lp_dir : OUT STD_LOGIC; + + dsa_d : OUT STD_LOGIC; + lp_str : OUT STD_LOGIC; + dtr : OUT STD_LOGIC; + rts : OUT STD_LOGIC; + cts : IN STD_LOGIC; + ri : IN STD_LOGIC; + dcd : IN STD_LOGIC; + lp_busy : IN STD_LOGIC; + rxd : IN STD_LOGIC; + txd : OUT STD_LOGIC; + midi_in : IN STD_LOGIC; + midi_olr : OUT STD_LOGIC; + midi_tlr : OUT STD_LOGIC; + pic_amkb_rx : IN STD_LOGIC; + amkb_rx : IN STD_LOGIC; + amkb_tx : OUT STD_LOGIC; + dack0_n : IN STD_LOGIC; -- Not used. + + scsi_drqn : IN STD_LOGIC; + SCSI_MSGn : IN STD_LOGIC; + SCSI_CDn : IN STD_LOGIC; + SCSI_IOn : IN STD_LOGIC; + SCSI_ACKn : OUT STD_LOGIC; + SCSI_ATNn : OUT STD_LOGIC; + SCSI_SELn : INOUT STD_LOGIC; + SCSI_BUSYn : INOUT STD_LOGIC; + SCSI_RSTn : INOUT STD_LOGIC; + SCSI_DIR : OUT STD_LOGIC; + SCSI_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); + SCSI_PAR : INOUT STD_LOGIC; + + ACSI_DIR : OUT STD_LOGIC; + ACSI_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); + ACSI_CSn : OUT STD_LOGIC; + ACSI_A1 : OUT STD_LOGIC; + ACSI_reset_n : OUT STD_LOGIC; + ACSI_ACKn : OUT STD_LOGIC; + ACSI_DRQn : IN STD_LOGIC; + ACSI_INTn : IN STD_LOGIC; + + FDD_DCHGn : IN STD_LOGIC; + FDD_SDSELn : OUT STD_LOGIC; + FDD_HD_DD : IN STD_LOGIC; + FDD_RDn : IN STD_LOGIC; + FDD_TRACK00 : IN STD_LOGIC; + FDD_INDEXn : IN STD_LOGIC; + FDD_WPn : IN STD_LOGIC; + FDD_MOT_ON : OUT STD_LOGIC; + FDD_WR_GATE : OUT STD_LOGIC; + FDD_WDn : OUT STD_LOGIC; + FDD_STEP : OUT STD_LOGIC; + FDD_STEP_DIR : OUT STD_LOGIC; + + ROM4n : OUT STD_LOGIC; + ROM3n : OUT STD_LOGIC; + + RP_UDSn : OUT STD_LOGIC; + RP_ldsn : OUT STD_LOGIC; + SD_CLK : OUT STD_LOGIC; + SD_D3 : INOUT STD_LOGIC; + SD_CMD_D1 : INOUT STD_LOGIC; + SD_D0 : IN STD_LOGIC; + SD_D1 : IN STD_LOGIC; + SD_D2 : IN STD_LOGIC; + SD_caRD_DETECT : IN STD_LOGIC; + SD_WP : IN STD_LOGIC; + + CF_WP : IN STD_LOGIC; + CF_CSn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + + DSP_IO : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0); + DSP_SRD : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); + DSP_SRCSn : OUT STD_LOGIC; + DSP_SRBLEn : OUT STD_LOGIC; + DSP_SRBHEn : OUT STD_LOGIC; + DSP_SRWEn : OUT STD_LOGIC; + DSP_SROEn : OUT STD_LOGIC; + + ide_int : IN STD_LOGIC; + ide_rdy : IN STD_LOGIC; + ide_res : OUT STD_LOGIC; + IDE_WRn : OUT STD_LOGIC; + IDE_RDn : OUT STD_LOGIC; + IDE_CSn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT firebee; + + SIGNAL clock : STD_LOGIC := '0'; -- main clock + + SIGNAL rsto_mcf_n : STD_LOGIC; -- reset SIGNAL from Coldfire + SIGNAL clk_33m : STD_LOGIC; -- 33 MHz clock + SIGNAL clk_main : STD_LOGIC; -- 33 MHz clock + + SIGNAL clk_24m576 : STD_LOGIC; -- + SIGNAL clk_25m : STD_LOGIC; + SIGNAL clk_ddr_out : STD_LOGIC; + SIGNAL clk_ddr_out_n : STD_LOGIC; + SIGNAL clk_usb : STD_LOGIC; + + SIGNAL fb_ad : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL fb_ale : STD_LOGIC; + SIGNAL fb_burst_n : STD_LOGIC; + SIGNAL fb_cs_n : STD_LOGIC_VECTOR (3 DOWNTO 1); + SIGNAL fb_size : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL fb_oe_n : STD_LOGIC; + SIGNAL fb_wr_n : STD_LOGIC; + SIGNAL fb_ta_n : STD_LOGIC; + + SIGNAL dack1_n : STD_LOGIC; + SIGNAL dreq1_n : STD_LOGIC; + + SIGNAL master_n : STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. + SIGNAL tout0_n : STD_LOGIC; -- Not used so far. + + SIGNAL led_fpga_ok : STD_LOGIC; + SIGNAL reserved_1 : STD_LOGIC; + + SIGNAL va : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL ba : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL vwe_n : STD_LOGIC; + SIGNAL vcas_n : STD_LOGIC; + SIGNAL vras_n : STD_LOGIC; + SIGNAL vcs_n : STD_LOGIC; + + SIGNAL clk_pixel : STD_LOGIC; + SIGNAL sync_n : STD_LOGIC; + SIGNAL vsync : STD_LOGIC; + SIGNAL hsync : STD_LOGIC; + SIGNAL blank_n : STD_LOGIC; + + SIGNAL vr : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL vg : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL vb : STD_LOGIC_VECTOR (7 DOWNTO 0); + + SIGNAL vdm : STD_LOGIC_VECTOR (3 DOWNTO 0); + + SIGNAL vd : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL vd_qs : STD_LOGIC_VECTOR (3 DOWNTO 0); + + SIGNAL pd_vga_n : STD_LOGIC; + SIGNAL vcke : STD_LOGIC; + SIGNAL pic_int : STD_LOGIC; + SIGNAL e0_int : STD_LOGIC; + SIGNAL dvi_int : STD_LOGIC; + SIGNAL pci_inta_n : STD_LOGIC; + SIGNAL pci_intb_n : STD_LOGIC; + SIGNAL pci_intc_n : STD_LOGIC; + SIGNAL pci_intd_n : STD_LOGIC; + + SIGNAL irq_n : STD_LOGIC_VECTOR (7 DOWNTO 2); + SIGNAL tin0 : STD_LOGIC; + + SIGNAL ym_qa : STD_LOGIC; + SIGNAL ym_qb : STD_LOGIC; + SIGNAL ym_qc : STD_LOGIC; + + SIGNAL lp_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL lp_dir : STD_LOGIC; + + SIGNAL dsa_d : STD_LOGIC; + SIGNAL lp_str : STD_LOGIC; + SIGNAL dtr : STD_LOGIC; + SIGNAL rts : STD_LOGIC; + SIGNAL cts : STD_LOGIC; + SIGNAL ri : STD_LOGIC; + SIGNAL dcd : STD_LOGIC; + SIGNAL lp_busy : STD_LOGIC; + SIGNAL rxd : STD_LOGIC; + SIGNAL txd : STD_LOGIC; + SIGNAL midi_in : STD_LOGIC; + SIGNAL midi_olr : STD_LOGIC; + SIGNAL midi_tlr : STD_LOGIC; + SIGNAL pic_amkb_rx : STD_LOGIC; + SIGNAL amkb_rx : STD_LOGIC; + SIGNAL amkb_tx : STD_LOGIC; + SIGNAL dack0_n : STD_LOGIC; -- Not used. + + SIGNAL scsi_drqn : STD_LOGIC; + SIGNAL SCSI_MSGn : STD_LOGIC; + SIGNAL SCSI_CDn : STD_LOGIC; + SIGNAL SCSI_IOn : STD_LOGIC; + SIGNAL SCSI_ACKn : STD_LOGIC; + SIGNAL SCSI_ATNn : STD_LOGIC; + SIGNAL SCSI_SELn : STD_LOGIC; + SIGNAL SCSI_BUSYn : STD_LOGIC; + SIGNAL SCSI_RSTn : STD_LOGIC; + SIGNAL SCSI_DIR : STD_LOGIC; + SIGNAL SCSI_D : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL SCSI_PAR : STD_LOGIC; + + SIGNAL ACSI_DIR : STD_LOGIC; + SIGNAL ACSI_D : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL ACSI_CSn : STD_LOGIC; + SIGNAL ACSI_A1 : STD_LOGIC; + SIGNAL ACSI_reset_n : STD_LOGIC; + SIGNAL ACSI_ACKn : STD_LOGIC; + SIGNAL ACSI_DRQn : STD_LOGIC; + SIGNAL ACSI_INTn : STD_LOGIC; + + SIGNAL FDD_DCHGn : STD_LOGIC; + SIGNAL FDD_SDSELn : STD_LOGIC; + SIGNAL FDD_HD_DD : STD_LOGIC; + SIGNAL FDD_RDn : STD_LOGIC; + SIGNAL FDD_TRACK00 : STD_LOGIC; + SIGNAL FDD_INDEXn : STD_LOGIC; + SIGNAL FDD_WPn : STD_LOGIC; + SIGNAL FDD_MOT_ON : STD_LOGIC; + SIGNAL FDD_WR_GATE : STD_LOGIC; + SIGNAL FDD_WDn : STD_LOGIC; + SIGNAL FDD_STEP : STD_LOGIC; + SIGNAL FDD_STEP_DIR : STD_LOGIC; + + SIGNAL ROM4n : STD_LOGIC; + SIGNAL ROM3n : STD_LOGIC; + + SIGNAL RP_UDSn : STD_LOGIC; + SIGNAL RP_ldsn : STD_LOGIC; + SIGNAL SD_CLK : STD_LOGIC; + SIGNAL SD_D3 : STD_LOGIC; + SIGNAL SD_CMD_D1 : STD_LOGIC; + SIGNAL SD_D0 : STD_LOGIC; + SIGNAL SD_D1 : STD_LOGIC; + SIGNAL SD_D2 : STD_LOGIC; + SIGNAL SD_caRD_DETECT : STD_LOGIC; + SIGNAL SD_WP : STD_LOGIC; + + SIGNAL CF_WP : STD_LOGIC; + SIGNAL CF_CSn : STD_LOGIC_VECTOR (1 DOWNTO 0); + + SIGNAL DSP_IO : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL DSP_SRD : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL DSP_SRCSn : STD_LOGIC; + SIGNAL DSP_SRBLEn : STD_LOGIC; + SIGNAL DSP_SRBHEn : STD_LOGIC; + SIGNAL DSP_SRWEn : STD_LOGIC; + SIGNAL DSP_SROEn : STD_LOGIC; + + SIGNAL ide_int : STD_LOGIC; + SIGNAL ide_rdy : STD_LOGIC; + SIGNAL ide_res : STD_LOGIC; + SIGNAL IDE_WRn : STD_LOGIC; + SIGNAL IDE_RDn : STD_LOGIC; + SIGNAL IDE_CSn : STD_LOGIC_VECTOR (1 DOWNTO 0); + +BEGIN + I_FIREBEE : firebee + PORT MAP ( + rsto_mcf_n => rsto_mcf_n, + clk_33m => clk_33m, + clk_main => clk_main, + clk_24m576 => clk_24m576, + clk_25m => clk_25m, + clk_ddr_out => clk_ddr_out, + clk_ddr_out_n => clk_ddr_out_n, + clk_usb => clk_usb, + fb_ad => fb_ad, + fb_ale => fb_ale, + fb_burst_n => fb_burst_n, + fb_cs_n => fb_cs_n, + fb_size => fb_size, + fb_oe_n => fb_oe_n, + fb_wr_n => fb_wr_n, + fb_ta_n => fb_ta_n, + dack1_n => dack1_n, + dreq1_n => dreq1_n, + master_n => master_n, + tout0_n => tout0_n, + led_fpga_ok => led_fpga_ok, + reserved_1 => reserved_1, + va => va, + ba => ba, + vwe_n => vwe_n, + vcas_n => vcas_n, + vras_n => vras_n, + vcs_n => vcs_n, + clk_pixel => clk_pixel, + sync_n => sync_n, + vsync => vsync, + hsync => hsync, + blank_n => blank_n, + vr => vr, + vg => vg, + vb => vb, + vdm => vdm, + vd => vd, + vd_qs => vd_qs, + pd_vga_n => pd_vga_n, + vcke => vcke, + pic_int => pic_int, + e0_int => e0_int, + dvi_int => dvi_int, + pci_inta_n => pci_inta_n, + pci_intb_n => pci_intb_n, + pci_intc_n => pci_intc_n, + pci_intd_n => pci_intd_n, + irq_n => irq_n, + tin0 => tin0, + ym_qa => ym_qa, + ym_qb => ym_qb, + ym_qc => ym_qc, + lp_d => lp_d, + lp_dir => lp_dir, + dsa_d => dsa_d, + lp_str => lp_str, + dtr => dtr, + rts => rts, + cts => cts, + ri => ri, + dcd => dcd, + lp_busy => lp_busy, + rxd => rxd, + txd => txd, + midi_in => midi_in, + midi_olr => midi_olr, + midi_tlr => midi_tlr, + pic_amkb_rx => pic_amkb_rx, + amkb_rx => amkb_rx, + amkb_tx => amkb_tx, + dack0_n => dack0_n, + scsi_drqn => scsi_drqn, + SCSI_MSGn => scsi_msgn, + SCSI_CDn => scsi_cdn, + SCSI_IOn => scsi_ion, + SCSI_ACKn => scsi_ackn, + SCSI_ATNn => scsi_atnn, + SCSI_SELn => scsi_seln, + SCSI_BUSYn => scsi_busyn, + SCSI_RSTn => scsi_rstn, + SCSI_DIR => scsi_dir, + SCSI_D => scsi_d, + SCSI_PAR => scsi_par, + ACSI_DIR => acsi_dir, + ACSI_D => acsi_d, + ACSI_CSn => acsi_csn, + ACSI_A1 => acsi_a1, + ACSI_reset_n => acsi_reset_n, + ACSI_ACKn => acsi_ackn, + ACSI_DRQn => acsi_drqn, + ACSI_INTn => acsi_intn, + FDD_DCHGn => fdd_dchgn, + FDD_SDSELn => fdd_sdseln, + FDD_HD_DD => fdd_hd_dd, + FDD_RDn => fdd_rdn, + FDD_TRACK00 => fdd_track00, + FDD_INDEXn => fdd_indexn, + FDD_WPn => fdd_wpn, + FDD_MOT_ON => fdd_mot_on, + FDD_WR_GATE => fdd_wr_gate, + FDD_WDn => fdd_wdn, + FDD_STEP => fdd_step, + FDD_STEP_DIR => fdd_step_dir, + ROM4n => rom4n, + ROM3n => rom3n, + RP_UDSn => rp_udsn, + RP_ldsn => rp_ldsn, + SD_CLK => sd_clk, + SD_D3 => sd_d3, + SD_CMD_D1 => sd_cmd_d1, + SD_D0 => sd_d0, + SD_D1 => sd_d1, + SD_D2 => sd_d2, + SD_caRD_DETECT => sd_card_detect, + SD_WP => sd_wp, + CF_WP => cf_wp, + CF_CSn => cf_csn, + DSP_IO => dsp_io, + DSP_SRD => dsp_srd, + DSP_SRCSn => dsp_srcsn, + DSP_SRBLEn => dsp_srblen, + DSP_SRBHEn => dsp_srbhen, + DSP_SRWEn => dsp_srwen, + DSP_SROEn => dsp_sroen, + ide_int => ide_int, + ide_rdy => ide_rdy, + ide_res => ide_res, + IDE_WRn => ide_wrn, + IDE_RDn => ide_rdn, + IDE_CSn => ide_csn + ); +END beh; \ No newline at end of file