started "full fledged" testbench to analyze where fb_ta_n gets lost
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@@ -55,7 +55,7 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ddr_ctlr_tb -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH firebee_tb -section_id eda_simulation
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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@@ -639,8 +639,6 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_DDR_OUT
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set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_25M
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
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set_location_assignment PIN_AB18 -to VCAS_n
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set_location_assignment PIN_W17 -to VRAS_n
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set_instance_assignment -name IO_STANDARD "2.5 V" -to VRAS_n
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@@ -690,4 +688,12 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[3]
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set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4]
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set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
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set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name VHDL_FILE ../../../testbenches/firebee_tb.vhd
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
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set_global_assignment -name EDA_TEST_BENCH_NAME firebee_tb -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME firebee_tb -section_id firebee_tb
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set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 s" -section_id firebee_tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME firebee_tb -section_id firebee_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb
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