Firebee/FireBee_SVN
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fixed various "comparison with different length" errors

Browse Source
This commit is contained in:
Markus Fröschle
2014-08-20 05:44:46 +00:00
parent 27824cd8e6
commit bc33af04ab
6 changed files with 331 additions and 331 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
View File

@@ -306,9 +306,9 @@ begin
DDR_NEXT_STATE <= DS_T4W; DDR_NEXT_STATE <= DS_T4W;
elsif DDR_ACCESS = BLITTER and BLITTER_WR = '1' then elsif DDR_ACCESS = BLITTER and BLITTER_WR = '1' then
DDR_NEXT_STATE <= DS_T4W; DDR_NEXT_STATE <= DS_T4W;
elsif DDR_ACCESS = CPU then -- CPU? elsif DDR_ACCESS = CPU then -- CPU?
DDR_NEXT_STATE <= DS_T4R; DDR_NEXT_STATE <= DS_T4R;
elsif DDR_ACCESS = FIFO then -- FIFO? elsif DDR_ACCESS = FIFO then -- FIFO?
DDR_NEXT_STATE <= DS_T4F; DDR_NEXT_STATE <= DS_T4F;
elsif DDR_ACCESS = BLITTER then elsif DDR_ACCESS = BLITTER then
DDR_NEXT_STATE <= DS_T4R; DDR_NEXT_STATE <= DS_T4R;
@@ -463,8 +463,8 @@ begin
end case; end case;
end process DDR_STATE_DEC; end process DDR_STATE_DEC;
P_CLK0: process P_CLK0: process
begin begin
wait until rising_edge(DDRCLK0); wait until rising_edge(DDRCLK0);
-- Default assignments; -- Default assignments;

70
vhdl/rtl/vhdl/DMA/fbee_dma.vhd
View File

@@ -216,17 +216,17 @@ begin
DMA_BYTECNT(16 downto 9) when DMA_DATA_CS = '1' and DMA_MODE(4) = '1' and FB_OEn = '0' else DMA_BYTECNT(16 downto 9) when DMA_DATA_CS = '1' and DMA_MODE(4) = '1' and FB_OEn = '0' else
"0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & FLOPPY_HD_DD when WDC_BSL_CS = '1' and FB_OEn = '0' else "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & FLOPPY_HD_DD when WDC_BSL_CS = '1' and FB_OEn = '0' else
RDF_AZ(7 downto 0) when DMA_AZ_CS = '1' and FB_OEn = '0' else RDF_AZ(7 downto 0) when DMA_AZ_CS = '1' and FB_OEn = '0' else
SNDMACTL when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_OEn = '0' else SNDMACTL when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else
SNDBASHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_OEn = '0' else SNDBASHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else
SNDBASMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"2" and FB_OEn = '0' else SNDBASMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"2" and FB_OEn = '0' else
SNDBASLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"3" and FB_OEn = '0' else SNDBASLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"3" and FB_OEn = '0' else
SNDADRHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"4" and FB_OEn = '0' else SNDADRHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"4" and FB_OEn = '0' else
SNDADRMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"5" and FB_OEn = '0' else SNDADRMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"5" and FB_OEn = '0' else
SNDADRLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"6" and FB_OEn = '0' else SNDADRLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"6" and FB_OEn = '0' else
SNDENDHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"7" and FB_OEn = '0' else SNDENDHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"7" and FB_OEn = '0' else
SNDENDMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_OEn = '0' else SNDENDMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else
SNDENDLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_OEn = '0' else SNDENDLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else
SNDMODE when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_OEn = '0' else SNDMODE when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else
DMA_HIGH when DMA_HIGH_CS = '1' and FB_OEn = '0' else DMA_HIGH when DMA_HIGH_CS = '1' and FB_OEn = '0' else
DMA_MID when DMA_MID_CS = '1' and FB_OEn = '0' else DMA_MID when DMA_MID_CS = '1' and FB_OEn = '0' else
DMA_LOW when DMA_LOW_CS = '1' and FB_OEn = '0' else DMA_LOW when DMA_LOW_CS = '1' and FB_OEn = '0' else
@@ -275,22 +275,22 @@ begin
SCSI_CS <= SCSI_CS_I; SCSI_CS <= SCSI_CS_I;
DMA_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 DMA_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C303" else '0'; -- F8606/2
DMA_DATA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 DMA_DATA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C302" else '0'; -- F8604/2
FDC_CS <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "00" and FB_B1 = '1' else '0'; FDC_CS <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "00" and FB_B1 = '1' else '0';
SCSI_CS_I <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "01" and FB_B1 = '1' else '0'; SCSI_CS_I <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "01" and FB_B1 = '1' else '0';
DMA_AZ_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG DMA_AZ_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"002010C" else '0'; -- F002'010C LONG
DMA_TOP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 DMA_TOP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C304" and FB_B0 = '1' else '0'; -- F8608/2
DMA_HIGH_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 DMA_HIGH_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C304" and FB_B1 = '1' else '0'; -- F8609/2
DMA_MID_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 DMA_MID_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C305" and FB_B1 = '1' else '0'; -- F860B/2
DMA_LOW_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 DMA_LOW_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C306" and FB_B1 = '1' else '0'; -- F860D/2
DMA_DIRECT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD DMA_DIRECT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20100" else '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG DMA_ADR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20104" else '0'; -- F002'0104 LONG
DMA_BYTECNT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG DMA_BYTECNT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20108" else '0'; -- F002'0108 LONG
DMA_SND_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 6) = x"3E24" else '0'; -- F8900-F893F DMA_SND_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(20 downto 6) = 15x"3E24" else '0'; -- F8900-F893F
FCF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY FCF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY
DMA_CS <= FCF_CS or DMA_MODE_CS or DMA_SND_CS or DMA_ADR_CS or DMA_DIRECT_CS or DMA_BYTECNT_CS; DMA_CS <= FCF_CS or DMA_MODE_CS or DMA_SND_CS or DMA_ADR_CS or DMA_DIRECT_CS or DMA_BYTECNT_CS;
WDC_BSL_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 WDC_BSL_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C307" else '0'; -- F860E/2
FCF_APH <= '1' when FB_ALE = '1' and FB_AD_IN(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY FCF_APH <= '1' when FB_ALE = '1' and FB_AD_IN(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY
@@ -462,27 +462,27 @@ begin
SNDENDLO <= x"00"; SNDENDLO <= x"00";
SNDMODE <= x"00"; SNDMODE <= x"00";
elsif CLK_MAIN = '1' and CLK_MAIN' event then elsif CLK_MAIN = '1' and CLK_MAIN' event then
if DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_WRn = '0' and FB_B1 ='1' then if DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_WRn = '0' and FB_B1 ='1' then
SNDMACTL <= FB_AD_IN(23 downto 16); SNDMACTL <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_WRn = '0' and FB_B1 ='1' then
SNDBASHI <= FB_AD_IN(23 downto 16); SNDBASHI <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"2" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"2" and FB_WRn = '0' and FB_B1 ='1' then
SNDBASMI <= FB_AD_IN(23downto 16); SNDBASMI <= FB_AD_IN(23downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"3" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"3" and FB_WRn = '0' and FB_B1 ='1' then
SNDBASLO <= FB_AD_IN(23 downto 16); SNDBASLO <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"4" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"4" and FB_WRn = '0' and FB_B1 ='1' then
SNDADRHI <= FB_AD_IN(23 downto 16); SNDADRHI <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"5" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"5" and FB_WRn = '0' and FB_B1 ='1' then
SNDADRMI <= FB_AD_IN(23 downto 16); SNDADRMI <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"6" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"6" and FB_WRn = '0' and FB_B1 ='1' then
SNDADRLO <= FB_AD_IN(23 downto 16); SNDADRLO <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"7" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"7" and FB_WRn = '0' and FB_B1 ='1' then
SNDENDHI <= FB_AD_IN(23 downto 16); SNDENDHI <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_WRn = '0' and FB_B1 ='1' then
SNDENDMI <= FB_AD_IN(23 downto 16); SNDENDMI <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_WRn = '0' and FB_B1 ='1' then
SNDENDLO <= FB_AD_IN(23 downto 16); SNDENDLO <= FB_AD_IN(23 downto 16);
elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_WRn = '0' and FB_B1 ='1' then elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_WRn = '0' and FB_B1 ='1' then
SNDMODE <= FB_AD_IN(23 downto 16); SNDMODE <= FB_AD_IN(23 downto 16);
end if; end if;
end if; end if;

50
vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
View File

@@ -96,11 +96,11 @@ use ieee.numeric_std.all;
entity firebee is entity firebee is
port( port(
RSTO_MCFn : in std_logic; RSTO_MCFn : in std_logic; -- reset signal from Coldfire
CLK_33M : in std_logic; CLK_33M : in std_logic; -- 33 MHz clock
CLK_MAIN : in std_logic; CLK_MAIN : in std_logic; -- 33 MHz clock
CLK_24M576 : out std_logic; CLK_24M576 : out std_logic; --
CLK_25M : out std_logic; CLK_25M : out std_logic;
CLK_DDR_OUT : out std_logic; CLK_DDR_OUT : out std_logic;
CLK_DDR_OUTn : out std_logic; CLK_DDR_OUTn : out std_logic;
@@ -118,7 +118,7 @@ entity firebee is
DACK1n : in std_logic; DACK1n : in std_logic;
DREQ1n : out std_logic; DREQ1n : out std_logic;
MASTERn : in std_logic; -- Not used so far. MASTERn : in std_logic; -- determines if the Firebee is PCI master (='0') or slave. Not used so far.
TOUT0n : in std_logic; -- Not used so far. TOUT0n : in std_logic; -- Not used so far.
LED_FPGA_OK : out std_logic; LED_FPGA_OK : out std_logic;
@@ -323,8 +323,8 @@ architecture Structure of firebee is
); );
end component; end component;
signal ACIA_CS : std_logic; signal ACIA_CS : std_logic;
signal ACIA_IRQn : std_logic; signal ACIA_IRQn : std_logic;
signal ACSI_D_OUT : std_logic_vector(7 downto 0); signal ACSI_D_OUT : std_logic_vector(7 downto 0);
signal ACSI_D_EN : std_logic; signal ACSI_D_EN : std_logic;
signal BLANK_In : std_logic; signal BLANK_In : std_logic;
@@ -567,7 +567,7 @@ begin
LED_FPGA_OK <= TIMEBASE(17); LED_FPGA_OK <= TIMEBASE(17);
FALCON_IO_TA <= ACIA_CS or SNDCS or not DTACK_OUT_MFPn or PADDLE_CS or IDE_CF_TA or DMA_CS; FALCON_IO_TA <= ACIA_CS or SNDCS or not DTACK_OUT_MFPn or PADDLE_CS or IDE_CF_TA or DMA_CS;
FB_TAn <= '0' when (BLITTER_TA or VIDEO_DDR_TA or VIDEO_MOD_TA or FALCON_IO_TA or DSP_TA or INT_HANDLER_TA)= '1' else '1'; FB_TAn <= '0' when (BLITTER_TA or VIDEO_DDR_TA or VIDEO_MOD_TA or FALCON_IO_TA or DSP_TA or INT_HANDLER_TA)= '1' else 'Z';
ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 3) & "000" = x"FFFC00" else '0'; -- FFFC00 - FFFC07 ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 3) & "000" = x"FFFC00" else '0'; -- FFFC00 - FFFC07
MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000" = x"FFFA00" else '0'; -- FFFA00/40 MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000" = x"FFFA00" else '0'; -- FFFA00/40
@@ -625,14 +625,14 @@ begin
x"00" when MFP_INTACK = '1' and FB_OEn = '0' else x"00" when MFP_INTACK = '1' and FB_OEn = '0' else
DATA_OUT_ACIA_I when ACIA_CS = '1' and FB_ADR(2) = '0' and FB_OEn = '0' else DATA_OUT_ACIA_I when ACIA_CS = '1' and FB_ADR(2) = '0' and FB_OEn = '0' else
DATA_OUT_ACIA_II when ACIA_CS = '1' and FB_ADR(2) = '1' and FB_OEn = '0' else DATA_OUT_ACIA_II when ACIA_CS = '1' and FB_ADR(2) = '1' and FB_OEn = '0' else
x"BF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_OEn = '0' else x"BF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"A" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"A" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"B" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"B" and FB_OEn = '0' else
x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_OEn = '0' else x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else
x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"11" and FB_OEn = '0' else (others => 'Z'); x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"11" and FB_OEn = '0' else (others => 'Z');
FB_AD(23 downto 16) <= DATA_OUT_BLITTER(23 downto 16) when DATA_EN_BLITTER = '1' else FB_AD(23 downto 16) <= DATA_OUT_BLITTER(23 downto 16) when DATA_EN_BLITTER = '1' else
VDP_Q1(23 downto 16) when FB_VDOE = x"2" else VDP_Q1(23 downto 16) when FB_VDOE = x"2" else
@@ -647,14 +647,14 @@ begin
DATA_OUT_MFP when MFP_CS = '1' and FB_OEn = '0' else DATA_OUT_MFP when MFP_CS = '1' and FB_OEn = '0' else
x"00" when MFP_INTACK = '1' and FB_OEn = '0' else x"00" when MFP_INTACK = '1' and FB_OEn = '0' else
FB_AD_OUT_RTC when FB_AD_EN_RTC = '1' else FB_AD_OUT_RTC when FB_AD_EN_RTC = '1' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"A" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"A" and FB_OEn = '0' else
x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"B" and FB_OEn = '0' else x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"B" and FB_OEn = '0' else
x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_OEn = '0' else x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else
x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"11" and FB_OEn = '0' else (others => 'Z'); x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"11" and FB_OEn = '0' else (others => 'Z');
FB_AD(15 downto 8) <= DATA_OUT_BLITTER(15 downto 8) when DATA_EN_BLITTER = '1' else FB_AD(15 downto 8) <= DATA_OUT_BLITTER(15 downto 8) when DATA_EN_BLITTER = '1' else
VDP_Q1(15 downto 8) when FB_VDOE = x"2" else VDP_Q1(15 downto 8) when FB_VDOE = x"2" else
@@ -682,7 +682,7 @@ begin
begin begin
wait until rising_edge(DDR_SYNC_66M); wait until rising_edge(DDR_SYNC_66M);
if FB_ALE = '1' then if FB_ALE = '1' then
FB_ADR <= FB_AD; FB_ADR <= FB_AD; -- latch Flexbus address
end if; end if;
-- --
if VD_EN_I = '0' then if VD_EN_I = '0' then

2
vhdl/rtl/vhdl/Interrupt/interrupt.vhd
View File

@@ -192,7 +192,7 @@ begin
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND
-- IF video ADR changes: -- IF video ADR changes:
TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2. TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = 19x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2.
P_INT_LATCH : process P_INT_LATCH : process
begin begin

24
vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd
View File

@@ -95,7 +95,7 @@ architecture BEHAVIOUR of IDE_CF_SD_ROM is
signal CMD_STATE : CMD_STATES; signal CMD_STATE : CMD_STATES;
signal NEXT_CMD_STATE : CMD_STATES; signal NEXT_CMD_STATE : CMD_STATES;
signal ROM_CS : STD_LOGIC; signal ROM_CS : std_logic;
signal IDE_CF_CS : std_logic; signal IDE_CF_CS : std_logic;
signal NEXT_IDE_RDn : std_logic; signal NEXT_IDE_RDn : std_logic;
signal NEXT_IDE_WRn : std_logic; signal NEXT_IDE_WRn : std_logic;
@@ -105,17 +105,17 @@ begin
RP_UDSn <= '0' when FB_WRn = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; RP_UDSn <= '0' when FB_WRn = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1';
RP_LDSn <= '0' when FB_WRn = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; RP_LDSn <= '0' when FB_WRn = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1';
IDE_CF_CS <= '1' when FB_CS1n = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 IDE_CF_CS <= '1' when FB_CS1n = '0' and FB_ADR(19 downto 7) = 13x"1" else '0'; -- FFF0'0000/80
IDE_CSn(0) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F IDE_CSn(0) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = 15x"2" else -- FFF0'0040-FFF0'005F
'0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F '0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = 15x"0" else '1'; -- FFFO'0000-FFF0'001F
IDE_CSn(1) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F IDE_CSn(1) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = 15x"3" else -- FFF0'0060-FFF0'007F
'0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F '0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = 15x"1" else '1'; -- FFFO'0020-FFF0'003F
CF_CSn(0) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F CF_CSn(0) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = 15x"0" else -- FFFO'0000-FFF0'001F
'0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F '0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = 15x"2" else '1'; -- FFFO'0040-FFF0'005F
CF_CSn(1) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F CF_CSn(1) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = 15x"1" else -- FFF0'0020-FFF0'003F
'0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F '0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = 15x"3" else '1'; -- FFFO'0060-FFF0'007F
IDE_DRQn <= '0'; IDE_DRQn <= '0';
@@ -175,6 +175,6 @@ begin
SD_CMD_D1_OUT <= '0'; SD_CMD_D1_OUT <= '0';
SD_CMD_D1_EN <= '0'; SD_CMD_D1_EN <= '0';
ROM4n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" and FB_ADR(16) = '0' else '1'; -- FFF A'0000/2'0000 ROM4n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '0' else '1'; -- FFF A'0000/2'0000
ROM3n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" and FB_ADR(16) = '1' else '1'; -- FFF A'0000/2'0000 ROM3n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '1' else '1'; -- FFF A'0000/2'0000
end architecture BEHAVIOUR; end architecture BEHAVIOUR;