diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index 629a139..c374e2a 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -306,9 +306,9 @@ begin DDR_NEXT_STATE <= DS_T4W; elsif DDR_ACCESS = BLITTER and BLITTER_WR = '1' then DDR_NEXT_STATE <= DS_T4W; - elsif DDR_ACCESS = CPU then -- CPU? + elsif DDR_ACCESS = CPU then -- CPU? DDR_NEXT_STATE <= DS_T4R; - elsif DDR_ACCESS = FIFO then -- FIFO? + elsif DDR_ACCESS = FIFO then -- FIFO? DDR_NEXT_STATE <= DS_T4F; elsif DDR_ACCESS = BLITTER then DDR_NEXT_STATE <= DS_T4R; @@ -463,8 +463,8 @@ begin end case; end process DDR_STATE_DEC; - P_CLK0: process - begin + P_CLK0: process + begin wait until rising_edge(DDRCLK0); -- Default assignments; @@ -857,4 +857,4 @@ end architecture BEHAVIOUR; -- BA_P : latched BA, wenn FIFO_AC, BLITTER_AC -- BA_S : latch for default BA -- ---FB_SIZE ersetzen. \ No newline at end of file +--FB_SIZE ersetzen. diff --git a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd index c414627..4e4c6d7 100644 --- a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd +++ b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd @@ -216,17 +216,17 @@ begin DMA_BYTECNT(16 downto 9) when DMA_DATA_CS = '1' and DMA_MODE(4) = '1' and FB_OEn = '0' else "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & FLOPPY_HD_DD when WDC_BSL_CS = '1' and FB_OEn = '0' else RDF_AZ(7 downto 0) when DMA_AZ_CS = '1' and FB_OEn = '0' else - SNDMACTL when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_OEn = '0' else - SNDBASHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_OEn = '0' else - SNDBASMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"2" and FB_OEn = '0' else - SNDBASLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"3" and FB_OEn = '0' else - SNDADRHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"4" and FB_OEn = '0' else - SNDADRMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"5" and FB_OEn = '0' else - SNDADRLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"6" and FB_OEn = '0' else - SNDENDHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"7" and FB_OEn = '0' else - SNDENDMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_OEn = '0' else - SNDENDLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_OEn = '0' else - SNDMODE when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_OEn = '0' else + SNDMACTL when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else + SNDBASHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else + SNDBASMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"2" and FB_OEn = '0' else + SNDBASLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"3" and FB_OEn = '0' else + SNDADRHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"4" and FB_OEn = '0' else + SNDADRMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"5" and FB_OEn = '0' else + SNDADRLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"6" and FB_OEn = '0' else + SNDENDHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"7" and FB_OEn = '0' else + SNDENDMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else + SNDENDLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else + SNDMODE when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else DMA_HIGH when DMA_HIGH_CS = '1' and FB_OEn = '0' else DMA_MID when DMA_MID_CS = '1' and FB_OEn = '0' else DMA_LOW when DMA_LOW_CS = '1' and FB_OEn = '0' else @@ -275,22 +275,22 @@ begin SCSI_CS <= SCSI_CS_I; - DMA_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 - DMA_DATA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 + DMA_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C303" else '0'; -- F8606/2 + DMA_DATA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C302" else '0'; -- F8604/2 FDC_CS <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "00" and FB_B1 = '1' else '0'; SCSI_CS_I <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "01" and FB_B1 = '1' else '0'; - DMA_AZ_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG - DMA_TOP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 - DMA_HIGH_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 - DMA_MID_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 - DMA_LOW_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 - DMA_DIRECT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD - DMA_ADR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG - DMA_BYTECNT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG - DMA_SND_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 6) = x"3E24" else '0'; -- F8900-F893F - FCF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY + DMA_AZ_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"002010C" else '0'; -- F002'010C LONG + DMA_TOP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 + DMA_HIGH_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 + DMA_MID_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 + DMA_LOW_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 + DMA_DIRECT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20100" else '0'; -- F002'0100 WORD + DMA_ADR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20104" else '0'; -- F002'0104 LONG + DMA_BYTECNT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20108" else '0'; -- F002'0108 LONG + DMA_SND_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(20 downto 6) = 15x"3E24" else '0'; -- F8900-F893F + FCF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY DMA_CS <= FCF_CS or DMA_MODE_CS or DMA_SND_CS or DMA_ADR_CS or DMA_DIRECT_CS or DMA_BYTECNT_CS; - WDC_BSL_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 + WDC_BSL_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C307" else '0'; -- F860E/2 FCF_APH <= '1' when FB_ALE = '1' and FB_AD_IN(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY @@ -462,27 +462,27 @@ begin SNDENDLO <= x"00"; SNDMODE <= x"00"; elsif CLK_MAIN = '1' and CLK_MAIN' event then - if DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_WRn = '0' and FB_B1 ='1' then + if DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_WRn = '0' and FB_B1 ='1' then SNDMACTL <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_WRn = '0' and FB_B1 ='1' then SNDBASHI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"2" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"2" and FB_WRn = '0' and FB_B1 ='1' then SNDBASMI <= FB_AD_IN(23downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"3" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"3" and FB_WRn = '0' and FB_B1 ='1' then SNDBASLO <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"4" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"4" and FB_WRn = '0' and FB_B1 ='1' then SNDADRHI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"5" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"5" and FB_WRn = '0' and FB_B1 ='1' then SNDADRMI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"6" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"6" and FB_WRn = '0' and FB_B1 ='1' then SNDADRLO <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"7" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"7" and FB_WRn = '0' and FB_B1 ='1' then SNDENDHI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_WRn = '0' and FB_B1 ='1' then SNDENDMI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_WRn = '0' and FB_B1 ='1' then SNDENDLO <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_WRn = '0' and FB_B1 ='1' then + elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_WRn = '0' and FB_B1 ='1' then SNDMODE <= FB_AD_IN(23 downto 16); end if; end if; @@ -586,4 +586,4 @@ begin end if; end case; end process FCF_DECODER; -end architecture BEHAVIOUR; \ No newline at end of file +end architecture BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd index 2e7dbf4..3d29d8a 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd +++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd @@ -96,11 +96,11 @@ use ieee.numeric_std.all; entity firebee is port( - RSTO_MCFn : in std_logic; - CLK_33M : in std_logic; - CLK_MAIN : in std_logic; + RSTO_MCFn : in std_logic; -- reset signal from Coldfire + CLK_33M : in std_logic; -- 33 MHz clock + CLK_MAIN : in std_logic; -- 33 MHz clock - CLK_24M576 : out std_logic; + CLK_24M576 : out std_logic; -- CLK_25M : out std_logic; CLK_DDR_OUT : out std_logic; CLK_DDR_OUTn : out std_logic; @@ -118,7 +118,7 @@ entity firebee is DACK1n : in std_logic; DREQ1n : out std_logic; - MASTERn : in std_logic; -- Not used so far. + MASTERn : in std_logic; -- determines if the Firebee is PCI master (='0') or slave. Not used so far. TOUT0n : in std_logic; -- Not used so far. LED_FPGA_OK : out std_logic; @@ -323,8 +323,8 @@ architecture Structure of firebee is ); end component; - signal ACIA_CS : std_logic; - signal ACIA_IRQn : std_logic; + signal ACIA_CS : std_logic; + signal ACIA_IRQn : std_logic; signal ACSI_D_OUT : std_logic_vector(7 downto 0); signal ACSI_D_EN : std_logic; signal BLANK_In : std_logic; @@ -567,7 +567,7 @@ begin LED_FPGA_OK <= TIMEBASE(17); FALCON_IO_TA <= ACIA_CS or SNDCS or not DTACK_OUT_MFPn or PADDLE_CS or IDE_CF_TA or DMA_CS; - FB_TAn <= '0' when (BLITTER_TA or VIDEO_DDR_TA or VIDEO_MOD_TA or FALCON_IO_TA or DSP_TA or INT_HANDLER_TA)= '1' else '1'; + FB_TAn <= '0' when (BLITTER_TA or VIDEO_DDR_TA or VIDEO_MOD_TA or FALCON_IO_TA or DSP_TA or INT_HANDLER_TA)= '1' else 'Z'; ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 3) & "000" = x"FFFC00" else '0'; -- FFFC00 - FFFC07 MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000" = x"FFFA00" else '0'; -- FFFA00/40 @@ -625,14 +625,14 @@ begin x"00" when MFP_INTACK = '1' and FB_OEn = '0' else DATA_OUT_ACIA_I when ACIA_CS = '1' and FB_ADR(2) = '0' and FB_OEn = '0' else DATA_OUT_ACIA_II when ACIA_CS = '1' and FB_ADR(2) = '1' and FB_OEn = '0' else - x"BF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"A" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"B" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"11" and FB_OEn = '0' else (others => 'Z'); + x"BF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"A" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"B" and FB_OEn = '0' else + x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else + x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"11" and FB_OEn = '0' else (others => 'Z'); FB_AD(23 downto 16) <= DATA_OUT_BLITTER(23 downto 16) when DATA_EN_BLITTER = '1' else VDP_Q1(23 downto 16) when FB_VDOE = x"2" else @@ -647,14 +647,14 @@ begin DATA_OUT_MFP when MFP_CS = '1' and FB_OEn = '0' else x"00" when MFP_INTACK = '1' and FB_OEn = '0' else FB_AD_OUT_RTC when FB_AD_EN_RTC = '1' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"0" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"1" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"8" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"9" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"A" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"B" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"10" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = x"11" and FB_OEn = '0' else (others => 'Z'); + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"A" and FB_OEn = '0' else + x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"B" and FB_OEn = '0' else + x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else + x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"11" and FB_OEn = '0' else (others => 'Z'); FB_AD(15 downto 8) <= DATA_OUT_BLITTER(15 downto 8) when DATA_EN_BLITTER = '1' else VDP_Q1(15 downto 8) when FB_VDOE = x"2" else @@ -682,7 +682,7 @@ begin begin wait until rising_edge(DDR_SYNC_66M); if FB_ALE = '1' then - FB_ADR <= FB_AD; + FB_ADR <= FB_AD; -- latch Flexbus address end if; -- if VD_EN_I = '0' then @@ -1318,4 +1318,4 @@ configuration FULL of firebee is for Structure -- default configuration end for; -end configuration FULL; \ No newline at end of file +end configuration FULL; diff --git a/vhdl/rtl/vhdl/Interrupt/interrupt.vhd b/vhdl/rtl/vhdl/Interrupt/interrupt.vhd index d76224f..ed504a7 100644 --- a/vhdl/rtl/vhdl/Interrupt/interrupt.vhd +++ b/vhdl/rtl/vhdl/Interrupt/interrupt.vhd @@ -192,7 +192,7 @@ begin -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND -- IF video ADR changes: - TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2. + TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = 19x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2. P_INT_LATCH : process begin diff --git a/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd b/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd index e642fcd..399a13b 100644 --- a/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd +++ b/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd @@ -95,7 +95,7 @@ architecture BEHAVIOUR of IDE_CF_SD_ROM is signal CMD_STATE : CMD_STATES; signal NEXT_CMD_STATE : CMD_STATES; - signal ROM_CS : STD_LOGIC; + signal ROM_CS : std_logic; signal IDE_CF_CS : std_logic; signal NEXT_IDE_RDn : std_logic; signal NEXT_IDE_WRn : std_logic; @@ -105,17 +105,17 @@ begin RP_UDSn <= '0' when FB_WRn = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; RP_LDSn <= '0' when FB_WRn = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; - IDE_CF_CS <= '1' when FB_CS1n = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 + IDE_CF_CS <= '1' when FB_CS1n = '0' and FB_ADR(19 downto 7) = 13x"1" else '0'; -- FFF0'0000/80 - IDE_CSn(0) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F - '0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F - IDE_CSn(1) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F - '0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F + IDE_CSn(0) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = 15x"2" else -- FFF0'0040-FFF0'005F + '0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = 15x"0" else '1'; -- FFFO'0000-FFF0'001F + IDE_CSn(1) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = 15x"3" else -- FFF0'0060-FFF0'007F + '0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = 15x"1" else '1'; -- FFFO'0020-FFF0'003F - CF_CSn(0) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F - '0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F - CF_CSn(1) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F - '0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F + CF_CSn(0) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = 15x"0" else -- FFFO'0000-FFF0'001F + '0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = 15x"2" else '1'; -- FFFO'0040-FFF0'005F + CF_CSn(1) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = 15x"1" else -- FFF0'0020-FFF0'003F + '0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = 15x"3" else '1'; -- FFFO'0060-FFF0'007F IDE_DRQn <= '0'; @@ -175,6 +175,6 @@ begin SD_CMD_D1_OUT <= '0'; SD_CMD_D1_EN <= '0'; - ROM4n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" and FB_ADR(16) = '0' else '1'; -- FFF A'0000/2'0000 - ROM3n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" and FB_ADR(16) = '1' else '1'; -- FFF A'0000/2'0000 + ROM4n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '0' else '1'; -- FFF A'0000/2'0000 + ROM3n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '1' else '1'; -- FFF A'0000/2'0000 end architecture BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/WF5380/wf5380_soc_top.vhd b/vhdl/rtl/vhdl/WF5380/wf5380_soc_top.vhd index 8cd6a50..72719c9 100644 --- a/vhdl/rtl/vhdl/WF5380/wf5380_soc_top.vhd +++ b/vhdl/rtl/vhdl/WF5380/wf5380_soc_top.vhd @@ -1,33 +1,33 @@ ---------------------------------------------------------------------- ---- ---- ----- WF5380 IP Core ---- ----- ---- ----- Description: ---- ----- This model provides an asynchronous SCSI interface compa- ---- ----- tible to the DP5380 from National Semiconductor and others. ---- ----- ---- ----- Some remarks to the required input clock: ---- ----- This core is provided for a 16MHz input clock. To use other ---- ----- frequencies, it is necessary to modify the following proces- ---- ----- ses in the control file section: ---- ----- P_BUSFREE, DELAY_800, INTERRUPTS. ---- ----- ---- ----- This file is the top level file without tree state buses for ---- ----- use in 'systems on chip' designs. ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- Some remarks to the required input clock: ---- +---- This core is provided for a 16MHz input clock. To use other ---- +---- frequencies, it is necessary to modify the following proces- ---- +---- ses in the control file section: ---- +---- P_BUSFREE, DELAY_800, INTERRUPTS. ---- +---- ---- +---- This file is the top level file without tree state buses for ---- +---- use in 'systems on chip' designs. ---- +---- ---- ---- ---- ----- ---- ---- Author(s): ---- ---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ---- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright � 2009-2010 Wolfgang Foerster Inventronik GmbH. ---- ----- All rights reserved. No portion of this sourcecode may be ---- ----- reproduced or transmitted in any form by any means, whether ---- ----- by electronic, mechanical, photocopying, recording or ---- ----- otherwise, without my written permission. ---- ----- ---- ----------------------------------------------------------------------- +---------------------------------------------------------------------- +---- ---- +---- Copyright � 2009-2010 Wolfgang Foerster Inventronik GmbH. ---- +---- All rights reserved. No portion of this sourcecode may be ---- +---- reproduced or transmitted in any form by any means, whether ---- +---- by electronic, mechanical, photocopying, recording or ---- +---- otherwise, without my written permission. ---- +---- ---- +---------------------------------------------------------------------- -- -- Revision History -- @@ -42,8 +42,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -entity WF5380_TOP_SOC is - port ( +entity WF5380_TOP_SOC is + port ( -- System controls: CLK : in std_logic; -- Use a 16MHz Clock. RESETn : in std_logic; @@ -51,237 +51,237 @@ entity WF5380_TOP_SOC is -- Address and data: ADR : in std_logic_vector(2 downto 0); DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; -- Bus and DMA controls: - CSn : in std_logic; - RDn : in std_logic; - WRn : in std_logic; - EOPn : in std_logic; - DACKn : in std_logic; - DRQ : out std_logic; - INT : out std_logic; - READY : out std_logic; + CSn : in std_logic; + RDn : in std_logic; + WRn : in std_logic; + EOPn : in std_logic; + DACKn : in std_logic; + DRQ : out std_logic; + INT : out std_logic; + READY : out std_logic; -- SCSI bus: DB_INn : in std_logic_vector(7 downto 0); - DB_OUTn : out std_logic_vector(7 downto 0); - DB_EN : out std_logic; - DBP_INn : in std_logic; - DBP_OUTn : out std_logic; - DBP_EN : out std_logic; - RST_INn : in std_logic; - RST_OUTn : out std_logic; - RST_EN : out std_logic; - BSY_INn : in std_logic; - BSY_OUTn : out std_logic; - BSY_EN : out std_logic; - SEL_INn : in std_logic; - SEL_OUTn : out std_logic; - SEL_EN : out std_logic; - ACK_INn : in std_logic; - ACK_OUTn : out std_logic; - ACK_EN : out std_logic; - ATN_INn : in std_logic; - ATN_OUTn : out std_logic; - ATN_EN : out std_logic; - REQ_INn : in std_logic; - REQ_OUTn : out std_logic; - REQ_EN : out std_logic; - IOn_IN : in std_logic; - IOn_OUT : out std_logic; - IO_EN : out std_logic; - CDn_IN : in std_logic; - CDn_OUT : out std_logic; - CD_EN : out std_logic; - MSG_INn : in std_logic; - MSG_OUTn : out std_logic; - MSG_EN : out std_logic + DB_OUTn : out std_logic_vector(7 downto 0); + DB_EN : out std_logic; + DBP_INn : in std_logic; + DBP_OUTn : out std_logic; + DBP_EN : out std_logic; + RST_INn : in std_logic; + RST_OUTn : out std_logic; + RST_EN : out std_logic; + BSY_INn : in std_logic; + BSY_OUTn : out std_logic; + BSY_EN : out std_logic; + SEL_INn : in std_logic; + SEL_OUTn : out std_logic; + SEL_EN : out std_logic; + ACK_INn : in std_logic; + ACK_OUTn : out std_logic; + ACK_EN : out std_logic; + ATN_INn : in std_logic; + ATN_OUTn : out std_logic; + ATN_EN : out std_logic; + REQ_INn : in std_logic; + REQ_OUTn : out std_logic; + REQ_EN : out std_logic; + IOn_IN : in std_logic; + IOn_OUT : out std_logic; + IO_EN : out std_logic; + CDn_IN : in std_logic; + CDn_OUT : out std_logic; + CD_EN : out std_logic; + MSG_INn : in std_logic; + MSG_OUTn : out std_logic; + MSG_EN : out std_logic ); end entity WF5380_TOP_SOC; -architecture STRUCTURE of WF5380_TOP_SOC is -signal ACK_OUT_CTRLn : std_logic; -signal AIP : std_logic; -signal ARB : std_logic; -signal ARB_EN : std_logic; -signal BLK : std_logic; -signal BSR : std_logic_vector(7 downto 0); -signal BSY_DISn : std_logic; -signal BSY_ERR : std_logic; -signal BSY_OUT_CTRLn : std_logic; -signal CHK_PAR : std_logic; -signal CSD : std_logic_vector(7 downto 0); -signal CSB : std_logic_vector(7 downto 0); -signal DATA_EN_CTRL : std_logic; -signal DB_EN_I : std_logic; -signal DMA_ACTIVE : std_logic; -signal DMA_EN : std_logic; -signal DMA_DIS : std_logic; -signal DMA_SND : std_logic; -signal DRQ_I : std_logic; -signal EDMA : std_logic; -signal EOP_EN : std_logic; -signal ICR : std_logic_vector(7 downto 0); -signal IDR_WR : std_logic; -signal INT_I : std_logic; -signal LA : std_logic; -signal ODR : std_logic_vector(7 downto 0); -signal ODR_WR : std_logic; -signal PCHK : std_logic; -signal PHSM : std_logic; -signal PINT_EN : std_logic; -signal REQ_OUT_CTRLn : std_logic; -signal RPI : std_logic; -signal RST : std_logic; -signal SDI : std_logic; -signal SDS : std_logic; -signal SDT : std_logic; -signal SER : std_logic_vector(7 downto 0); -signal SER_ID : std_logic; -signal SPER : std_logic; -signal TARG : std_logic; -signal TCR : std_logic_vector(3 downto 0); +architecture STRUCTURE of WF5380_TOP_SOC is +signal ACK_OUT_CTRLn : std_logic; +signal AIP : std_logic; +signal ARB : std_logic; +signal ARB_EN : std_logic; +signal BLK : std_logic; +signal BSR : std_logic_vector(7 downto 0); +signal BSY_DISn : std_logic; +signal BSY_ERR : std_logic; +signal BSY_OUT_CTRLn : std_logic; +signal CHK_PAR : std_logic; +signal CSD : std_logic_vector(7 downto 0); +signal CSB : std_logic_vector(7 downto 0); +signal DATA_EN_CTRL : std_logic; +signal DB_EN_I : std_logic; +signal DMA_ACTIVE : std_logic; +signal DMA_EN : std_logic; +signal DMA_DIS : std_logic; +signal DMA_SND : std_logic; +signal DRQ_I : std_logic; +signal EDMA : std_logic; +signal EOP_EN : std_logic; +signal ICR : std_logic_vector(7 downto 0); +signal IDR_WR : std_logic; +signal INT_I : std_logic; +signal LA : std_logic; +signal ODR : std_logic_vector(7 downto 0); +signal ODR_WR : std_logic; +signal PCHK : std_logic; +signal PHSM : std_logic; +signal PINT_EN : std_logic; +signal REQ_OUT_CTRLn : std_logic; +signal RPI : std_logic; +signal RST : std_logic; +signal SDI : std_logic; +signal SDS : std_logic; +signal SDT : std_logic; +signal SER : std_logic_vector(7 downto 0); +signal SER_ID : std_logic; +signal SPER : std_logic; +signal TARG : std_logic; +signal TCR : std_logic_vector(3 downto 0); begin - EDMA <= '1' when EOPn = '0' and DACKn = '0' and RDn = '0' else - '1' when EOPn = '0' and DACKn = '0' and WRn = '0' else '0'; - - PHSM <= '1' when DMA_ACTIVE = '0' else -- Always true, if there is no DMA. - '1' when DMA_ACTIVE = '1' and REQ_INn = '0' and CDn_In = TCR(1) and IOn_IN = TCR(0) and MSG_INn = TCR(2) else '0'; -- Phasematch. - - DMA_DIS <= '1' when DMA_ACTIVE = '1' and BSY_INn = '1' else '0'; - - SER_ID <= '1' when SER /= x"00" and SER = not CSD else '0'; - - DRQ <= DRQ_I; - INT <= INT_I; - - -- Pay attention: the SCSI bus is driven with inverted signals. - ACK_OUTn <= ACK_OUT_CTRLn when DMA_ACTIVE = '1' else not ICR(4); -- Valid in initiator mode. - REQ_OUTn <= REQ_OUT_CTRLn when DMA_ACTIVE = '1' else not TCR(3); -- Valid in Target mode. - BSY_OUTn <= '0' when BSY_OUT_CTRLn = '0' and TARG = '0' else -- Valid in initiator mode. - '0' when ICR(3) = '1' else '1'; - ATN_OUTn <= not ICR(1); -- Valid in initiator mode. - SEL_OUTn <= not ICR(2); -- Valid in initiator mode. - IOn_OUT <= not TCR(0); -- Valid in Target mode. - CDn_OUT <= not TCR(1); -- Valid in Target mode. - MSG_OUTn <= not TCR(2); -- Valid in Target mode. - RST_OUTn <= not RST; - - DB_OUTn <= not ODR; - DBP_OUTn <= not SPER; - - CSD <= not DB_INn; - CSB <= not RST_INn & not BSY_INn & not REQ_INn & not MSG_INn & not CDn_IN & not IOn_IN & not SEL_INn & not DBP_INn; - BSR <= EDMA & DRQ_I & SPER & INT_I & PHSM & BSY_ERR & not ATN_INn & not ACK_INn; - - -- Hi impedance control: - ATN_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. - SEL_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. - BSY_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. - ACK_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. - IO_EN <= '1' when TARG = '1' else '0'; -- Target mode. - CD_EN <= '1' when TARG = '1' else '0'; -- Target mode. - MSG_EN <= '1' when TARG = '1' else '0'; -- Target mode. - REQ_EN <= '1' when TARG = '1' else '0'; -- Target mode. - RST_EN <= '1' when RST = '1' else '0'; -- Open drain control. - - -- Data enables: - DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arstd_logicration. - '1' when ICR(0) = '1' and TARG = '1' and DMA_SND = '1' else -- Target 'Send' mode. - '1' when ICR(0) = '1' and TARG = '0' and IOn_IN = '0' and PHSM = '1' else - '1' when ICR(6) = '1' else '0'; -- Test mode enable. - - DB_EN <= DB_EN_I; - DBP_EN <= DB_EN_I; - - I_REGISTERS: WF5380_REGISTERS - port map( - CLK => CLK, - RESETn => RESETn, - ADR => ADR, - DATA_IN => DATA_IN, - DATA_OUT => DATA_OUT, - DATA_EN => DATA_EN, - CSn => CSn, - RDn => RDn, - WRn => WRn, - RSTn => RST_INn, - RST => RST, - ARB_EN => ARB_EN, - DMA_ACTIVE => DMA_ACTIVE, - DMA_EN => DMA_EN, - BSY_DISn => BSY_DISn, - EOP_EN => EOP_EN, - PINT_EN => PINT_EN, - SPER => SPER, - TARG => TARG, - BLK => BLK, - DMA_DIS => DMA_DIS, - IDR_WR => IDR_WR, - ODR_WR => ODR_WR, - CHK_PAR => CHK_PAR, - AIP => AIP, - ARB => ARB, - LA => LA, - CSD => CSD, - CSB => CSB, - BSR => BSR, - ODR_OUT => ODR, - ICR_OUT => ICR, - TCR_OUT => TCR, - SER_OUT => SER, - SDS => SDS, - SDT => SDT, - SDI => SDI, - RPI => RPI - ); - - I_CONTROL: WF5380_CONTROL - port map( - CLK => CLK, - RESETn => RESETn, - BSY_INn => BSY_INn, - BSY_OUTn => BSY_OUT_CTRLn, - DATA_EN => DATA_EN_CTRL, - SEL_INn => SEL_INn, - ARB_EN => ARB_EN, - BSY_DISn => BSY_DISn, - RSTn => RST_INn, - ARB => ARB, - AIP => AIP, - LA => LA, - ACK_INn => ACK_INn, - ACK_OUTn => ACK_OUT_CTRLn, - REQ_INn => REQ_INn, - REQ_OUTn => REQ_OUT_CTRLn, - DACKn => DACKn, - READY => READY, - DRQ => DRQ_I, - TARG => TARG, - BLK => BLK, - PINT_EN => PINT_EN, - SPER => SPER, - SER_ID => SER_ID, - RPI => RPI, - DMA_EN => DMA_EN, - SDS => SDS, - SDT => SDT, - SDI => SDI, - EOP_EN => EOP_EN, - EOPn => EOPn, - PHSM => PHSM, - INT => INT_I, - IDR_WR => IDR_WR, - ODR_WR => ODR_WR, - CHK_PAR => CHK_PAR, - BSY_ERR => BSY_ERR, - DMA_SND => DMA_SND, - DMA_ACTIVE => DMA_ACTIVE - ); -end STRUCTURE; - -architecture LIGHT of WF5380_TOP_SOC is -begin -end LIGHT; \ No newline at end of file + EDMA <= '1' when EOPn = '0' and DACKn = '0' and RDn = '0' else + '1' when EOPn = '0' and DACKn = '0' and WRn = '0' else '0'; + + PHSM <= '1' when DMA_ACTIVE = '0' else -- Always true, if there is no DMA. + '1' when DMA_ACTIVE = '1' and REQ_INn = '0' and CDn_In = TCR(1) and IOn_IN = TCR(0) and MSG_INn = TCR(2) else '0'; -- Phasematch. + + DMA_DIS <= '1' when DMA_ACTIVE = '1' and BSY_INn = '1' else '0'; + + SER_ID <= '1' when SER /= x"00" and SER = not CSD else '0'; + + DRQ <= DRQ_I; + INT <= INT_I; + + -- Pay attention: the SCSI bus is driven with inverted signals. + ACK_OUTn <= ACK_OUT_CTRLn when DMA_ACTIVE = '1' else not ICR(4); -- Valid in initiator mode. + REQ_OUTn <= REQ_OUT_CTRLn when DMA_ACTIVE = '1' else not TCR(3); -- Valid in Target mode. + BSY_OUTn <= '0' when BSY_OUT_CTRLn = '0' and TARG = '0' else -- Valid in initiator mode. + '0' when ICR(3) = '1' else '1'; + ATN_OUTn <= not ICR(1); -- Valid in initiator mode. + SEL_OUTn <= not ICR(2); -- Valid in initiator mode. + IOn_OUT <= not TCR(0); -- Valid in Target mode. + CDn_OUT <= not TCR(1); -- Valid in Target mode. + MSG_OUTn <= not TCR(2); -- Valid in Target mode. + RST_OUTn <= not RST; + + DB_OUTn <= not ODR; + DBP_OUTn <= not SPER; + + CSD <= not DB_INn; + CSB <= not RST_INn & not BSY_INn & not REQ_INn & not MSG_INn & not CDn_IN & not IOn_IN & not SEL_INn & not DBP_INn; + BSR <= EDMA & DRQ_I & SPER & INT_I & PHSM & BSY_ERR & not ATN_INn & not ACK_INn; + + -- Hi impedance control: + ATN_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + SEL_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + BSY_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + ACK_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + IO_EN <= '1' when TARG = '1' else '0'; -- Target mode. + CD_EN <= '1' when TARG = '1' else '0'; -- Target mode. + MSG_EN <= '1' when TARG = '1' else '0'; -- Target mode. + REQ_EN <= '1' when TARG = '1' else '0'; -- Target mode. + RST_EN <= '1' when RST = '1' else '0'; -- Open drain control. + + -- Data enables: + DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arstd_logicration. + '1' when ICR(0) = '1' and TARG = '1' and DMA_SND = '1' else -- Target 'Send' mode. + '1' when ICR(0) = '1' and TARG = '0' and IOn_IN = '0' and PHSM = '1' else + '1' when ICR(6) = '1' else '0'; -- Test mode enable. + + DB_EN <= DB_EN_I; + DBP_EN <= DB_EN_I; + + I_REGISTERS: WF5380_REGISTERS + port map( + CLK => CLK, + RESETn => RESETn, + ADR => ADR, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + CSn => CSn, + RDn => RDn, + WRn => WRn, + RSTn => RST_INn, + RST => RST, + ARB_EN => ARB_EN, + DMA_ACTIVE => DMA_ACTIVE, + DMA_EN => DMA_EN, + BSY_DISn => BSY_DISn, + EOP_EN => EOP_EN, + PINT_EN => PINT_EN, + SPER => SPER, + TARG => TARG, + BLK => BLK, + DMA_DIS => DMA_DIS, + IDR_WR => IDR_WR, + ODR_WR => ODR_WR, + CHK_PAR => CHK_PAR, + AIP => AIP, + ARB => ARB, + LA => LA, + CSD => CSD, + CSB => CSB, + BSR => BSR, + ODR_OUT => ODR, + ICR_OUT => ICR, + TCR_OUT => TCR, + SER_OUT => SER, + SDS => SDS, + SDT => SDT, + SDI => SDI, + RPI => RPI + ); + + I_CONTROL: WF5380_CONTROL + port map( + CLK => CLK, + RESETn => RESETn, + BSY_INn => BSY_INn, + BSY_OUTn => BSY_OUT_CTRLn, + DATA_EN => DATA_EN_CTRL, + SEL_INn => SEL_INn, + ARB_EN => ARB_EN, + BSY_DISn => BSY_DISn, + RSTn => RST_INn, + ARB => ARB, + AIP => AIP, + LA => LA, + ACK_INn => ACK_INn, + ACK_OUTn => ACK_OUT_CTRLn, + REQ_INn => REQ_INn, + REQ_OUTn => REQ_OUT_CTRLn, + DACKn => DACKn, + READY => READY, + DRQ => DRQ_I, + TARG => TARG, + BLK => BLK, + PINT_EN => PINT_EN, + SPER => SPER, + SER_ID => SER_ID, + RPI => RPI, + DMA_EN => DMA_EN, + SDS => SDS, + SDT => SDT, + SDI => SDI, + EOP_EN => EOP_EN, + EOPn => EOPn, + PHSM => PHSM, + INT => INT_I, + IDR_WR => IDR_WR, + ODR_WR => ODR_WR, + CHK_PAR => CHK_PAR, + BSY_ERR => BSY_ERR, + DMA_SND => DMA_SND, + DMA_ACTIVE => DMA_ACTIVE + ); +end STRUCTURE; + +architecture LIGHT of WF5380_TOP_SOC is +begin +end LIGHT;