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worked on testbench

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This commit is contained in:
Markus Fröschle
2014-06-11 16:41:25 +00:00
parent 2c29f6a232
commit 8d0ede14c8
8 changed files with 832 additions and 729 deletions
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6
vhdl/backend/Altera/Firebee/altpll4.mif
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@@ -1,4 +1,4 @@
-- Copyright (C) 1991-2012 Altera Corporation
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
@@ -17,8 +17,8 @@
-- Device Part: -
-- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: D:/WF/Projects/VHDL-Designs/Firebee-WF/rtl/vhdl/Firebee_V1//altpll4.mif
-- Generated: Tue Jul 17 11:06:24 2012
-- File Name: /home/likewise-open/BAT/froesm1/Dokumente/Development/workspace/vhdl/backend/Altera/Firebee/altpll4.mif
-- Generated: Tue Jun 10 12:41:45 2014
WIDTH=1;
DEPTH=144;

22
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C40F484C6
set_global_assignment -name TOP_LEVEL_ENTITY firebee
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -380,8 +380,8 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
@@ -401,7 +401,7 @@ set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name AUTO_RAM_RECOGNITION OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
@@ -582,8 +582,8 @@ set_location_assignment PIN_H2 -to SCSI_MSGn
set_location_assignment PIN_J3 -to SCSI_IOn
set_location_assignment PIN_U1 -to SCSI_DRQn
set_location_assignment PIN_H1 -to SCSI_CDn
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
@@ -591,8 +591,7 @@ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_global_assignment -name EDA_TEST_BENCH_NAME ddr_ctlr_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr_ctlr_tb -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr_ctrl_tb -section_id ddr_ctlr_tb
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[1]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[2]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[3]"
@@ -670,4 +669,11 @@ set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.vhd
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll4.qip
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb -library work
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
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@@ -737,7 +737,7 @@ DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS
BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2);
FIFO_ROW_ADR <= std_logic_vector(VIDEO_ADR_CNT(22 downto 10));
FIFO_BA <= std_logic_vector(VIDEO_ADR_CNT)(9 downto 8);
FIFO_BA <= std_logic_vector(VIDEO_ADR_CNT(9 downto 8));
FIFO_COL_ADR <= VIDEO_ADR_CNT(7 downto 0) & "00";
VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D;

3
vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
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@@ -765,7 +765,8 @@ begin
VDP_OUT <= BLITTER_DOUT(63 downto 0) when "11",
BLITTER_DOUT(127 downto 64) when "10",
FB_DDR(63 downto 0) when "01",
FB_DDR(127 downto 64) when "00";
FB_DDR(127 downto 64) when "00",
(others => 'Z') when others;
VD_EN_I <= SR_DDR_WR or DDR_WR;

2
vhdl/rtl/vhdl/Firebee_V1/altpll4.qip
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@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll4.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]

8
vhdl/rtl/vhdl/Firebee_V1/altpll4.vhd
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@@ -14,7 +14,7 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
@@ -209,7 +209,7 @@ BEGIN
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5,
scan_chain_mif_file => "altpll4.mif"
scan_chain_mif_file => "../../../backend/Altera/Firebee/altpll4.mif"
)
PORT MAP (
areset => areset,
@@ -292,7 +292,7 @@ END SYN;
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "../../../backend/Altera/Firebee/altpll4.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
@@ -365,7 +365,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif"
-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "../../../backend/Altera/Firebee/altpll4.mif"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"

72
vhdl/rtl/vhdl/Video/Video_Top.vhd
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@@ -48,7 +48,7 @@ use work.firebee_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity VIDEO_SYSTEM is
port(
@@ -159,7 +159,6 @@ signal CLUT_ST_OUT : std_logic_vector(11 downto 0);
signal CLUT_ADR : std_logic_vector(7 downto 0);
signal CLUT_ADR_A : std_logic_vector(7 downto 0);
signal CLUT_ADR_MUX : std_logic_vector(3 downto 0);
signal CLUT_SHIFT_IN : std_logic_vector(5 downto 0);
signal CLUT_SHIFT_LOAD : std_logic;
@@ -208,61 +207,78 @@ signal CC_16 : std_logic_vector(23 downto 0);
signal CLK_PIXEL_I : std_logic;
signal VD_OUT_I : std_logic_vector(31 downto 0);
signal ZR_C8 : std_logic_vector(7 downto 0);
begin
CLK_PIXEL <= CLK_PIXEL_I;
FIFO_CLR <= FIFO_CLR_I;
P_CLUT_ST_MC: process
-- This is the dual ported ram for the ST colour lookup tables.
variable clut_fa_index : integer;
variable clut_st_index : integer;
variable clut_fi_index : integer;
begin
clut_st_index := to_integer(unsigned(FB_ADR(4 downto 1)));
clut_fa_index := to_integer(unsigned(FB_ADR(9 downto 2)));
clut_fi_index := to_integer(unsigned(FB_ADR(9 downto 2)));
wait until CLK_MAIN = '1' and CLK_MAIN' event;
if CLUT_ST_WR(0) = '1' then
CLUT_ST(conv_integer(FB_ADR(4 downto 1)))(11 downto 8) <= FB_AD_IN(27 downto 24);
CLUT_ST(clut_st_index)(11 downto 8) <= FB_AD_IN(27 downto 24);
end if;
if CLUT_ST_WR(1) = '1' then
CLUT_ST(conv_integer(FB_ADR(4 downto 1)))(7 downto 0) <= FB_AD_IN(23 downto 16);
CLUT_ST(clut_st_index)(7 downto 0) <= FB_AD_IN(23 downto 16);
end if;
--
if CLUT_FA_WR(0) = '1' then
CLUT_FA(conv_integer(FB_ADR(9 downto 2)))(17 downto 12) <= FB_AD_IN(31 downto 26);
CLUT_FA(clut_fa_index)(17 downto 12) <= FB_AD_IN(31 downto 26);
end if;
if CLUT_FA_WR(1) = '1' then
CLUT_FA(conv_integer(FB_ADR(9 downto 2)))(11 downto 6) <= FB_AD_IN(23 downto 18);
CLUT_FA(clut_fa_index)(11 downto 6) <= FB_AD_IN(23 downto 18);
end if;
if CLUT_FA_WR(3) = '1' then
CLUT_FA(conv_integer(FB_ADR(9 downto 2)))(5 downto 0) <= FB_AD_IN(23 downto 18);
CLUT_FA(clut_fa_index)(5 downto 0) <= FB_AD_IN(23 downto 18);
end if;
--
if CLUT_FBEE_WR(1) = '1' then
CLUT_FI(conv_integer(FB_ADR(9 downto 2)))(23 downto 16) <= FB_AD_IN(23 downto 16);
CLUT_FI(clut_fi_index)(23 downto 16) <= FB_AD_IN(23 downto 16);
end if;
if CLUT_FBEE_WR(2) = '1' then
CLUT_FI(conv_integer(FB_ADR(9 downto 2)))(15 downto 8) <= FB_AD_IN(15 downto 8);
CLUT_FI(clut_fi_index)(15 downto 8) <= FB_AD_IN(15 downto 8);
end if;
if CLUT_FBEE_WR(3) = '1' then
CLUT_FI(conv_integer(FB_ADR(9 downto 2)))(7 downto 0) <= FB_AD_IN(7 downto 0);
CLUT_FI(clut_fi_index)(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
--
CLUT_ST_OUT <= CLUT_ST(conv_integer(FB_ADR(4 downto 1)));
CLUT_FA_OUT <= CLUT_FA(conv_integer(FB_ADR(9 downto 2)));
CLUT_FBEE_OUT <= CLUT_FI(conv_integer(FB_ADR(9 downto 2)));
CLUT_ST_OUT <= CLUT_ST(clut_st_index);
CLUT_FA_OUT <= CLUT_FA(clut_fa_index);
CLUT_FBEE_OUT <= CLUT_FI(clut_fi_index);
end process P_CLUT_ST_MC;
P_CLUT_ST_PX: process
variable clut_fa_index : integer;
variable clut_st_index : integer;
variable clut_fi_index : integer;
-- This is the dual ported ram for the ST colour lookup tables.
begin
clut_st_index := to_integer(unsigned(CLUT_ADR(3 downto 0)));
clut_fa_index := to_integer(unsigned(CLUT_ADR));
clut_fi_index := to_integer(unsigned(ZR_C8));
wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
CLUT_ST_R <= CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(8) & CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(11 downto 9);
CLUT_ST_G <= CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(4) & CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(7 downto 5);
CLUT_ST_B <= CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(0) & CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(3 downto 1);
CLUT_FA_R <= CLUT_FA(conv_integer(CLUT_ADR))(17 downto 12);
CLUT_FA_G <= CLUT_FA(conv_integer(CLUT_ADR))(11 downto 6);
CLUT_FA_B <= CLUT_FA(conv_integer(CLUT_ADR))(5 downto 0);
CLUT_FBEE_R <= CLUT_FI(conv_integer(ZR_C8))(23 downto 16);
CLUT_FBEE_G <= CLUT_FI(conv_integer(ZR_C8))(15 downto 8);
CLUT_FBEE_B <= CLUT_FI(conv_integer(ZR_C8))(7 downto 0);
CLUT_ST_R <= CLUT_ST(clut_st_index)(8) & CLUT_ST(clut_st_index)(11 downto 9);
CLUT_ST_G <= CLUT_ST(clut_st_index)(4) & CLUT_ST(clut_st_index)(7 downto 5);
CLUT_ST_B <= CLUT_ST(clut_st_index)(0) & CLUT_ST(clut_st_index)(3 downto 1);
CLUT_FA_R <= CLUT_FA(clut_fa_index)(17 downto 12);
CLUT_FA_G <= CLUT_FA(clut_fa_index)(11 downto 6);
CLUT_FA_B <= CLUT_FA(clut_fa_index)(5 downto 0);
CLUT_FBEE_R <= CLUT_FI(clut_fi_index)(23 downto 16);
CLUT_FBEE_G <= CLUT_FI(clut_fi_index)(15 downto 8);
CLUT_FBEE_B <= CLUT_FI(clut_fi_index)(7 downto 0);
end process P_CLUT_ST_PX;
P_VIDEO_OUT: process
@@ -294,6 +310,7 @@ begin
when "10" => CC24_I := FIFO_D(63 downto 32);
when "01" => CC24_I := FIFO_D(95 downto 64);
when "00" => CC24_I := FIFO_D(127 downto 96);
when others => CC24_I := (others => 'Z');
end case;
--
CC_24 <= CC24_I;
@@ -307,6 +324,7 @@ begin
when "010" => CC_I := FIFO_D(95 downto 80);
when "001" => CC_I := FIFO_D(111 downto 96);
when "000" => CC_I := FIFO_D(127 downto 112);
when others => CC_I := (others => 'X');
end case;
--
CC_16 <= CC_I(15 downto 11) & "000" & CC_I(10 downto 5) & "00" & CC_I(4 downto 0) & "000";
@@ -328,6 +346,7 @@ begin
when x"2" => ZR_C8_I := FIFO_D(111 downto 104);
when x"1" => ZR_C8_I := FIFO_D(119 downto 112);
when x"0" => ZR_C8_I := FIFO_D(127 downto 120);
when others => ZR_C8_I := (others => 'X');
end case;
--
case COLOR1 is
@@ -453,7 +472,8 @@ begin
VDM_B(31 downto 0) & VDM_A(127 downto 32) when x"C",
VDM_B(23 downto 0) & VDM_A(127 downto 24) when x"D",
VDM_B(15 downto 0) & VDM_A(127 downto 16) when x"E",
VDM_B(7 downto 0) & VDM_A(127 downto 8) when x"F";
VDM_B(7 downto 0) & VDM_A(127 downto 8) when x"F",
(others => 'X') when others;
I_FIFO_DC0: lpm_fifo_dc0
port map(

90
vhdl/testbenches/ddr_ctlr_tb.vhd
View File

@@ -1,3 +1,6 @@
library work;
use work.firebee_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@@ -10,8 +13,45 @@ architecture beh of ddr_ctlr_tb is
signal clock_33 : std_logic := '0'; -- 33 MHz clock
signal ddr_clk : std_logic := '0'; -- ddr clock
signal vec : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal o : std_logic_vector(31 downto 0);
signal FB_ADR : std_logic_vector(31 downto 0);
signal DDR_SYNC_66M : std_logic;
signal FB_CS1n : std_logic;
signal FB_OEn : std_logic;
signal FB_SIZE0 : std_logic;
signal FB_SIZE1 : std_logic;
signal FB_ALE : std_logic;
signal FB_WRn : std_logic;
signal FIFO_CLR : std_logic;
signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0);
signal BLITTER_ADR : std_logic_vector(31 downto 0);
signal BLITTER_SIG : std_logic;
signal BLITTER_WR : std_logic;
signal DDRCLK0 : std_logic;
signal CLK_33M : std_logic;
signal FIFO_MW : std_logic_vector(8 downto 0);
signal VA : std_logic_vector(12 downto 0);
signal VWEn : std_logic;
signal VRASn : std_logic;
signal VCSn : std_logic;
signal VCKE : std_logic;
signal VCASn : std_logic;
signal FB_LE : std_logic_vector(3 downto 0);
signal FB_VDOE : std_logic_vector(3 downto 0);
signal SR_FIFO_WRE : std_logic;
signal SR_DDR_FB : std_logic;
signal SR_DDR_WR : std_logic;
signal SR_DDRWR_D_SEL: std_logic;
signal SR_VDMP : std_logic_vector(7 downto 0);
signal VIDEO_DDR_TA : std_logic;
signal SR_BLITTER_DACK : std_logic;
signal BA : std_logic_vector(1 downto 0);
signal DDRWR_D_SEL1 : std_logic;
signal VDM_SEL : std_logic_vector(3 downto 0);
signal DATA_IN : std_logic_vector(31 downto 0);
signal DATA_OUT : std_logic_vector(31 downto 16);
signal DATA_EN_H : std_logic;
signal DATA_EN_L : std_logic;
component DDR_CTRL_V1
port(
CLK_MAIN : in std_logic;
@@ -60,8 +100,44 @@ begin
port map
(
CLK_MAIN => clock,
vec_in => vec,
vec_out => o
DDR_SYNC_66M => DDR_SYNC_66M,
FB_ADR => FB_ADR,
FB_CS1n => FB_CS1n,
FB_OEn => FB_OEn,
FB_SIZE0 => FB_SIZE0,
FB_SIZE1 => FB_SIZE1,
FB_ALE => FB_ALE,
FB_WRn => FB_WRn,
FIFO_CLR => FIFO_CLR,
VIDEO_RAM_CTR => VIDEO_RAM_CTR,
BLITTER_ADR => BLITTER_ADR,
BLITTER_SIG => BLITTER_SIG,
BLITTER_WR => BLITTER_WR,
DDRCLK0 => DDRCLK0,
CLK_33M => CLK_33M,
FIFO_MW => FIFO_MW,
VA => VA,
VWEn => VWEn,
VRASn => VRASn,
VCSn => VCSn,
VCKE => VCKE,
VCASn => VCASn,
FB_LE => FB_LE,
FB_VDOE => FB_VDOE,
SR_FIFO_WRE => SR_FIFO_WRE,
SR_DDR_FB => SR_DDR_FB,
SR_DDR_WR => SR_DDR_WR,
SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
SR_VDMP => SR_VDMP,
VIDEO_DDR_TA => VIDEO_DDR_TA,
SR_BLITTER_DACK => SR_BLITTER_DACK,
BA => BA,
DDRWR_D_SEL1 => DDRWR_D_SEL1,
VDM_SEL => VDM_SEL,
DATA_IN => DATA_IN,
DATA_OUT => DATA_OUT,
DATA_EN_H => DATA_EN_H,
DATA_EN_L => DATA_EN_L
);
stimulate_clock : process
@@ -72,11 +148,11 @@ begin
stimulate : process
begin
vec <= "00000000000000000000000000000001";
FB_ADR <= "00000000000000000000000000000001";
wait for 20 ps;
vec <= "10000000000000000000000000000000";
FB_ADR <= "10000000000000000000000000000000";
wait for 20 ps;
vec <= "00000000000000000000000000000101";
FB_ADR <= "00000000000000000000000000000101";
wait for 20 ps;
end process;
end beh;