From 8d0ede14c8c7efb8c903c94bf491e1e4f34407a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 11 Jun 2014 16:41:25 +0000 Subject: [PATCH] worked on testbench --- vhdl/backend/Altera/Firebee/altpll4.mif | 348 +++--- vhdl/backend/Altera/Firebee/firebee.qsf | 22 +- vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd | 2 +- vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd | 3 +- vhdl/rtl/vhdl/Firebee_V1/altpll4.qip | 2 +- vhdl/rtl/vhdl/Firebee_V1/altpll4.vhd | 8 +- vhdl/rtl/vhdl/Video/Video_Top.vhd | 1086 ++++++++++--------- vhdl/testbenches/ddr_ctlr_tb.vhd | 90 +- 8 files changed, 832 insertions(+), 729 deletions(-) diff --git a/vhdl/backend/Altera/Firebee/altpll4.mif b/vhdl/backend/Altera/Firebee/altpll4.mif index 08595de..f5e024c 100644 --- a/vhdl/backend/Altera/Firebee/altpll4.mif +++ b/vhdl/backend/Altera/Firebee/altpll4.mif @@ -1,174 +1,174 @@ --- Copyright (C) 1991-2012 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - --- MIF file representing initial state of PLL Scan Chain --- Device Family: Cyclone III --- Device Part: - --- Device Speed Grade: 8 --- PLL Scan Chain: Fast PLL (144 bits) --- File Name: D:/WF/Projects/VHDL-Designs/Firebee-WF/rtl/vhdl/Firebee_V1//altpll4.mif --- Generated: Tue Jul 17 11:06:24 2012 - -WIDTH=1; -DEPTH=144; - -ADDRESS_RADIX=UNS; -DATA_RADIX=UNS; - -CONTENT BEGIN - 0 : 0; -- Reserved Bits = 0 (1 bit(s)) - 1 : 0; -- Reserved Bits = 0 (1 bit(s)) - 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) - 3 : 0; - 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) - 5 : 1; - 6 : 0; - 7 : 1; - 8 : 1; - 9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1) - 10 : 0; -- Reserved Bits = 0 (5 bit(s)) - 11 : 0; - 12 : 0; - 13 : 0; - 14 : 0; - 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) - 16 : 0; - 17 : 1; - 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) - 19 : 0; -- N counter: High Count = 0 (8 bit(s)) - 20 : 0; - 21 : 0; - 22 : 0; - 23 : 0; - 24 : 0; - 25 : 0; - 26 : 0; - 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) - 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) - 29 : 0; - 30 : 0; - 31 : 0; - 32 : 0; - 33 : 0; - 34 : 0; - 35 : 0; - 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) - 37 : 0; -- M counter: High Count = 16 (8 bit(s)) - 38 : 0; - 39 : 0; - 40 : 1; - 41 : 0; - 42 : 0; - 43 : 0; - 44 : 0; - 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) - 46 : 0; -- M counter: Low Count = 16 (8 bit(s)) - 47 : 0; - 48 : 0; - 49 : 1; - 50 : 0; - 51 : 0; - 52 : 0; - 53 : 0; - 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) - 55 : 0; -- clk0 counter: High Count = 6 (8 bit(s)) - 56 : 0; - 57 : 0; - 58 : 0; - 59 : 0; - 60 : 1; - 61 : 1; - 62 : 0; - 63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s)) - 64 : 0; -- clk0 counter: Low Count = 5 (8 bit(s)) - 65 : 0; - 66 : 0; - 67 : 0; - 68 : 0; - 69 : 1; - 70 : 0; - 71 : 1; - 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) - 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) - 74 : 0; - 75 : 0; - 76 : 0; - 77 : 0; - 78 : 0; - 79 : 0; - 80 : 0; - 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) - 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) - 83 : 0; - 84 : 0; - 85 : 0; - 86 : 0; - 87 : 0; - 88 : 0; - 89 : 0; - 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) - 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) - 92 : 0; - 93 : 0; - 94 : 0; - 95 : 0; - 96 : 0; - 97 : 0; - 98 : 0; - 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) - 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) - 101 : 0; - 102 : 0; - 103 : 0; - 104 : 0; - 105 : 0; - 106 : 0; - 107 : 0; - 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) - 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) - 110 : 0; - 111 : 0; - 112 : 0; - 113 : 0; - 114 : 0; - 115 : 0; - 116 : 0; - 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) - 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) - 119 : 0; - 120 : 0; - 121 : 0; - 122 : 0; - 123 : 0; - 124 : 0; - 125 : 0; - 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) - 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) - 128 : 0; - 129 : 0; - 130 : 0; - 131 : 0; - 132 : 0; - 133 : 0; - 134 : 0; - 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) - 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) - 137 : 0; - 138 : 0; - 139 : 0; - 140 : 0; - 141 : 0; - 142 : 0; - 143 : 0; -END; +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- MIF file representing initial state of PLL Scan Chain +-- Device Family: Cyclone III +-- Device Part: - +-- Device Speed Grade: 8 +-- PLL Scan Chain: Fast PLL (144 bits) +-- File Name: /home/likewise-open/BAT/froesm1/Dokumente/Development/workspace/vhdl/backend/Altera/Firebee/altpll4.mif +-- Generated: Tue Jun 10 12:41:45 2014 + +WIDTH=1; +DEPTH=144; + +ADDRESS_RADIX=UNS; +DATA_RADIX=UNS; + +CONTENT BEGIN + 0 : 0; -- Reserved Bits = 0 (1 bit(s)) + 1 : 0; -- Reserved Bits = 0 (1 bit(s)) + 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) + 3 : 0; + 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) + 5 : 1; + 6 : 0; + 7 : 1; + 8 : 1; + 9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1) + 10 : 0; -- Reserved Bits = 0 (5 bit(s)) + 11 : 0; + 12 : 0; + 13 : 0; + 14 : 0; + 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) + 16 : 0; + 17 : 1; + 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) + 19 : 0; -- N counter: High Count = 0 (8 bit(s)) + 20 : 0; + 21 : 0; + 22 : 0; + 23 : 0; + 24 : 0; + 25 : 0; + 26 : 0; + 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) + 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) + 29 : 0; + 30 : 0; + 31 : 0; + 32 : 0; + 33 : 0; + 34 : 0; + 35 : 0; + 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) + 37 : 0; -- M counter: High Count = 16 (8 bit(s)) + 38 : 0; + 39 : 0; + 40 : 1; + 41 : 0; + 42 : 0; + 43 : 0; + 44 : 0; + 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) + 46 : 0; -- M counter: Low Count = 16 (8 bit(s)) + 47 : 0; + 48 : 0; + 49 : 1; + 50 : 0; + 51 : 0; + 52 : 0; + 53 : 0; + 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) + 55 : 0; -- clk0 counter: High Count = 6 (8 bit(s)) + 56 : 0; + 57 : 0; + 58 : 0; + 59 : 0; + 60 : 1; + 61 : 1; + 62 : 0; + 63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s)) + 64 : 0; -- clk0 counter: Low Count = 5 (8 bit(s)) + 65 : 0; + 66 : 0; + 67 : 0; + 68 : 0; + 69 : 1; + 70 : 0; + 71 : 1; + 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) + 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) + 74 : 0; + 75 : 0; + 76 : 0; + 77 : 0; + 78 : 0; + 79 : 0; + 80 : 0; + 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) + 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) + 83 : 0; + 84 : 0; + 85 : 0; + 86 : 0; + 87 : 0; + 88 : 0; + 89 : 0; + 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) + 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) + 92 : 0; + 93 : 0; + 94 : 0; + 95 : 0; + 96 : 0; + 97 : 0; + 98 : 0; + 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) + 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) + 101 : 0; + 102 : 0; + 103 : 0; + 104 : 0; + 105 : 0; + 106 : 0; + 107 : 0; + 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) + 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) + 110 : 0; + 111 : 0; + 112 : 0; + 113 : 0; + 114 : 0; + 115 : 0; + 116 : 0; + 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) + 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) + 119 : 0; + 120 : 0; + 121 : 0; + 122 : 0; + 123 : 0; + 124 : 0; + 125 : 0; + 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) + 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) + 128 : 0; + 129 : 0; + 130 : 0; + 131 : 0; + 132 : 0; + 133 : 0; + 134 : 0; + 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) + 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) + 137 : 0; + 138 : 0; + 139 : 0; + 140 : 0; + 141 : 0; + 142 : 0; + 143 : 0; +END; diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index 099a825..b1c6443 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C40F484C6 set_global_assignment -name TOP_LEVEL_ENTITY firebee set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -380,8 +380,8 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name MUX_RESTRUCTURE ON set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS" @@ -401,7 +401,7 @@ set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF set_global_assignment -name AUTO_RAM_RECOGNITION OFF set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF @@ -582,8 +582,8 @@ set_location_assignment PIN_H2 -to SCSI_MSGn set_location_assignment PIN_J3 -to SCSI_IOn set_location_assignment PIN_U1 -to SCSI_DRQn set_location_assignment PIN_H1 -to SCSI_CDn -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL @@ -591,8 +591,7 @@ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL set_global_assignment -name EDA_TEST_BENCH_NAME ddr_ctlr_tb -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id ddr_ctlr_tb -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr_ctlr_tb -section_id ddr_ctlr_tb -set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr_ctrl_tb -section_id ddr_ctlr_tb set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[1]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[2]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[3]" @@ -670,4 +669,11 @@ set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.vhd set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll4.qip +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb -library work set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index 9b8e5f4..a829809 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -737,7 +737,7 @@ DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); FIFO_ROW_ADR <= std_logic_vector(VIDEO_ADR_CNT(22 downto 10)); - FIFO_BA <= std_logic_vector(VIDEO_ADR_CNT)(9 downto 8); + FIFO_BA <= std_logic_vector(VIDEO_ADR_CNT(9 downto 8)); FIFO_COL_ADR <= VIDEO_ADR_CNT(7 downto 0) & "00"; VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D; diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd index 87379b7..1ac5ab3 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd +++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd @@ -765,7 +765,8 @@ begin VDP_OUT <= BLITTER_DOUT(63 downto 0) when "11", BLITTER_DOUT(127 downto 64) when "10", FB_DDR(63 downto 0) when "01", - FB_DDR(127 downto 64) when "00"; + FB_DDR(127 downto 64) when "00", + (others => 'Z') when others; VD_EN_I <= SR_DDR_WR or DDR_WR; diff --git a/vhdl/rtl/vhdl/Firebee_V1/altpll4.qip b/vhdl/rtl/vhdl/Firebee_V1/altpll4.qip index 4995044..23959fe 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/altpll4.qip +++ b/vhdl/rtl/vhdl/Firebee_V1/altpll4.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name IP_TOOL_VERSION "13.0" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll4.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] diff --git a/vhdl/rtl/vhdl/Firebee_V1/altpll4.vhd b/vhdl/rtl/vhdl/Firebee_V1/altpll4.vhd index 931584a..f6a12cc 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/altpll4.vhd +++ b/vhdl/rtl/vhdl/Firebee_V1/altpll4.vhd @@ -14,7 +14,7 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -- ************************************************************ @@ -209,7 +209,7 @@ BEGIN port_extclk3 => "PORT_UNUSED", self_reset_on_loss_lock => "OFF", width_clock => 5, - scan_chain_mif_file => "altpll4.mif" + scan_chain_mif_file => "../../../backend/Altera/Firebee/altpll4.mif" ) PORT MAP ( areset => areset, @@ -292,7 +292,7 @@ END SYN; -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "../../../backend/Altera/Firebee/altpll4.mif" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" @@ -365,7 +365,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif" +-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "../../../backend/Altera/Firebee/altpll4.mif" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" diff --git a/vhdl/rtl/vhdl/Video/Video_Top.vhd b/vhdl/rtl/vhdl/Video/Video_Top.vhd index 9a44bf5..8f14e61 100644 --- a/vhdl/rtl/vhdl/Video/Video_Top.vhd +++ b/vhdl/rtl/vhdl/Video/Video_Top.vhd @@ -1,533 +1,553 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This design unit provides the video toplevel of the 'Firebee'---- ----- computer. It is optimized for the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- ----- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2012 Wolfgang Förster ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K12B 20120801 WF --- Initial Release of the second edition. --- ST colours enhanced to 4 bit colour mode (STE compatibility). - -library work; -use work.firebee_pkg.all; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity VIDEO_SYSTEM is - port( - CLK_MAIN : in std_logic; - CLK_33M : in std_logic; - CLK_25M : in std_logic; - CLK_VIDEO : in std_logic; - CLK_DDR3 : in std_logic; - CLK_DDR2 : in std_logic; - CLK_DDR0 : in std_logic; - CLK_PIXEL : out std_logic; - - VR_D : in std_logic_vector(8 downto 0); - VR_BUSY : in std_logic; - - FB_ADR : in std_logic_vector(31 downto 0); - FB_AD_IN : in std_logic_vector(31 downto 0); - FB_AD_OUT : out std_logic_vector(31 downto 0); - FB_AD_EN_31_16 : out std_logic; -- Hi word. - FB_AD_EN_15_0 : out std_logic; -- Low word. - FB_ALE : in std_logic; - FB_CSn : in std_logic_vector(3 downto 1); - FB_OEn : in std_logic; - FB_WRn : in std_logic; - FB_SIZE1 : in std_logic; - FB_SIZE0 : in std_logic; - - VDP_IN : in std_logic_vector(63 downto 0); - - VR_RD : out std_logic; - VR_WR : out std_logic; - VIDEO_RECONFIG : out std_logic; - - RED : out std_logic_vector(7 downto 0); - GREEN : out std_logic_vector(7 downto 0); - BLUE : out std_logic_vector(7 downto 0); - VSYNC : out std_logic; - HSYNC : out std_logic; - SYNCn : out std_logic; - BLANKn : out std_logic; - - PD_VGAn : out std_logic; - VIDEO_MOD_TA : out std_logic; - - VD_VZ : out std_logic_vector(127 downto 0); - SR_FIFO_WRE : in std_logic; - SR_VDMP : in std_logic_vector(7 downto 0); - FIFO_MW : out std_logic_vector(8 downto 0); - VDM_SEL : in std_logic_vector(3 downto 0); - VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); - FIFO_CLR : out std_logic; - VDM : out std_logic_vector(3 downto 0); - - BLITTER_RUN : in std_logic; - BLITTER_ON : out std_logic - ); -end entity VIDEO_SYSTEM; - -architecture BEHAVIOUR of VIDEO_SYSTEM is -component lpm_fifo_dc0 - port( - aclr : in std_logic := '0'; - data : in std_logic_vector (127 downto 0); - rdclk : in std_logic ; - rdreq : in std_logic ; - wrclk : in std_logic ; - wrreq : in std_logic ; - q : out std_logic_vector (127 downto 0); - rdempty : out STD_LOGIC ; - wrusedw : out std_logic_vector (8 downto 0) - ); -end component; - -component lpm_fifoDZ is - port( - aclr : in std_logic ; - clock : in std_logic ; - data : in std_logic_vector (127 downto 0); - rdreq : in std_logic ; - wrreq : in std_logic ; - q : out std_logic_vector (127 downto 0) - ); -end component; - -type CLUT_SHIFTREG_TYPE is array(0 to 7) of std_logic_vector(15 downto 0); -type CLUT_ST_TYPE is array(0 to 15) of std_logic_vector(11 downto 0); -type CLUT_FA_TYPE is array(0 to 255) of std_logic_vector(17 downto 0); -type CLUT_FBEE_TYPE is array(0 to 255) of std_logic_vector(23 downto 0); - -signal CLUT_FA : CLUT_FA_TYPE; -signal CLUT_FI : CLUT_FBEE_TYPE; -signal CLUT_ST : CLUT_ST_TYPE; - -signal CLUT_FA_R : std_logic_vector(5 downto 0); -signal CLUT_FA_G : std_logic_vector(5 downto 0); -signal CLUT_FA_B : std_logic_vector(5 downto 0); -signal CLUT_FBEE_R : std_logic_vector(7 downto 0); -signal CLUT_FBEE_G : std_logic_vector(7 downto 0); -signal CLUT_FBEE_B : std_logic_vector(7 downto 0); -signal CLUT_ST_R : std_logic_vector(3 downto 0); -signal CLUT_ST_G : std_logic_vector(3 downto 0); -signal CLUT_ST_B : std_logic_vector(3 downto 0); - -signal CLUT_FA_OUT : std_logic_vector(17 downto 0); -signal CLUT_FBEE_OUT : std_logic_vector(23 downto 0); -signal CLUT_ST_OUT : std_logic_vector(11 downto 0); - -signal CLUT_ADR : std_logic_vector(7 downto 0); -signal CLUT_ADR_A : std_logic_vector(7 downto 0); -signal CLUT_ADR_MUX : std_logic_vector(3 downto 0); - -signal CLUT_SHIFT_IN : std_logic_vector(5 downto 0); - -signal CLUT_SHIFT_LOAD : std_logic; -signal CLUT_OFF : std_logic_vector(3 downto 0); -signal CLUT_FBEE_RD : std_logic; -signal CLUT_FBEE_WR : std_logic_vector(3 downto 0); -signal CLUT_FA_RDH : std_logic; -signal CLUT_FA_RDL : std_logic; -signal CLUT_FA_WR : std_logic_vector(3 downto 0); -signal CLUT_ST_RD : std_logic; -signal CLUT_ST_WR : std_logic_vector(1 downto 0); - -signal DATA_OUT_VIDEO_CTRL : std_logic_vector(31 downto 0); -signal DATA_EN_H_VIDEO_CTRL : std_logic; -signal DATA_EN_L_VIDEO_CTRL : std_logic; - -signal COLOR1 : std_logic; -signal COLOR2 : std_logic; -signal COLOR4 : std_logic; -signal COLOR8 : std_logic; -signal CCR : std_logic_vector(23 downto 0); -signal CC_SEL : std_logic_vector(2 downto 0); - -signal FIFO_CLR_I : std_logic; -signal DOP_FIFO_CLR : std_logic; -signal FIFO_WRE : std_logic; - -signal FIFO_RD_REQ_128 : std_logic; -signal FIFO_RD_REQ_512 : std_logic; -signal FIFO_RDE : std_logic; -signal INTER_ZEI : std_logic; -signal FIFO_D_OUT_128 : std_logic_vector(127 downto 0); -signal FIFO_D_OUT_512 : std_logic_vector(127 downto 0); -signal FIFO_D_IN_512 : std_logic_vector(127 downto 0); -signal FIFO_D : std_logic_vector(127 downto 0); - -signal VD_VZ_I : std_logic_vector(127 downto 0); -signal VDM_A : std_logic_vector(127 downto 0); -signal VDM_B : std_logic_vector(127 downto 0); -signal VDM_C : std_logic_vector(127 downto 0); -signal V_DMA_SEL : std_logic_vector(3 downto 0); -signal VDMP : std_logic_vector(7 downto 0); -signal VDMP_I : std_logic_vector(7 downto 0); -signal CC_24 : std_logic_vector(31 downto 0); -signal CC_16 : std_logic_vector(23 downto 0); -signal CLK_PIXEL_I : std_logic; -signal VD_OUT_I : std_logic_vector(31 downto 0); -signal ZR_C8 : std_logic_vector(7 downto 0); -begin - CLK_PIXEL <= CLK_PIXEL_I; - - FIFO_CLR <= FIFO_CLR_I; - - P_CLUT_ST_MC: process - - -- This is the dual ported ram for the ST colour lookup tables. - begin - wait until CLK_MAIN = '1' and CLK_MAIN' event; - if CLUT_ST_WR(0) = '1' then - CLUT_ST(conv_integer(FB_ADR(4 downto 1)))(11 downto 8) <= FB_AD_IN(27 downto 24); - end if; - if CLUT_ST_WR(1) = '1' then - CLUT_ST(conv_integer(FB_ADR(4 downto 1)))(7 downto 0) <= FB_AD_IN(23 downto 16); - end if; - -- - if CLUT_FA_WR(0) = '1' then - CLUT_FA(conv_integer(FB_ADR(9 downto 2)))(17 downto 12) <= FB_AD_IN(31 downto 26); - end if; - if CLUT_FA_WR(1) = '1' then - CLUT_FA(conv_integer(FB_ADR(9 downto 2)))(11 downto 6) <= FB_AD_IN(23 downto 18); - end if; - if CLUT_FA_WR(3) = '1' then - CLUT_FA(conv_integer(FB_ADR(9 downto 2)))(5 downto 0) <= FB_AD_IN(23 downto 18); - end if; - -- - if CLUT_FBEE_WR(1) = '1' then - CLUT_FI(conv_integer(FB_ADR(9 downto 2)))(23 downto 16) <= FB_AD_IN(23 downto 16); - end if; - if CLUT_FBEE_WR(2) = '1' then - CLUT_FI(conv_integer(FB_ADR(9 downto 2)))(15 downto 8) <= FB_AD_IN(15 downto 8); - end if; - if CLUT_FBEE_WR(3) = '1' then - CLUT_FI(conv_integer(FB_ADR(9 downto 2)))(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; - -- - CLUT_ST_OUT <= CLUT_ST(conv_integer(FB_ADR(4 downto 1))); - CLUT_FA_OUT <= CLUT_FA(conv_integer(FB_ADR(9 downto 2))); - CLUT_FBEE_OUT <= CLUT_FI(conv_integer(FB_ADR(9 downto 2))); - end process P_CLUT_ST_MC; - - P_CLUT_ST_PX: process - -- This is the dual ported ram for the ST colour lookup tables. - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - CLUT_ST_R <= CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(8) & CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(11 downto 9); - CLUT_ST_G <= CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(4) & CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(7 downto 5); - CLUT_ST_B <= CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(0) & CLUT_ST(conv_integer(CLUT_ADR(3 downto 0)))(3 downto 1); - CLUT_FA_R <= CLUT_FA(conv_integer(CLUT_ADR))(17 downto 12); - CLUT_FA_G <= CLUT_FA(conv_integer(CLUT_ADR))(11 downto 6); - CLUT_FA_B <= CLUT_FA(conv_integer(CLUT_ADR))(5 downto 0); - CLUT_FBEE_R <= CLUT_FI(conv_integer(ZR_C8))(23 downto 16); - CLUT_FBEE_G <= CLUT_FI(conv_integer(ZR_C8))(15 downto 8); - CLUT_FBEE_B <= CLUT_FI(conv_integer(ZR_C8))(7 downto 0); - end process P_CLUT_ST_PX; - - P_VIDEO_OUT: process - variable VIDEO_OUT : std_logic_vector(23 downto 0); - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - case CC_SEL is - when "111" => VIDEO_OUT := CCR; -- Register type video. - when "110" => VIDEO_OUT := CC_24(23 downto 0); -- 3 byte FIFO type video. - when "101" => VIDEO_OUT := CC_16; -- 2 byte FIFO type video. - when "100" => VIDEO_OUT := CLUT_FBEE_R & CLUT_FBEE_G & CLUT_FBEE_B; -- Firebee type video. - when "001" => VIDEO_OUT := CLUT_FA_R & "00" & CLUT_FA_G & "00" & CLUT_FA_B & "00"; -- Falcon type video. - when "000" => VIDEO_OUT := CLUT_ST_R & x"0" & CLUT_ST_G & x"0" & CLUT_ST_B & x"0"; -- ST type video. - when others => VIDEO_OUT := (others => '0'); - end case; - RED <= VIDEO_OUT(23 downto 16); - GREEN <= VIDEO_OUT(15 downto 8); - BLUE <= VIDEO_OUT(7 downto 0); - end process P_VIDEO_OUT; - - P_CC: process - variable CC24_I : std_logic_vector(31 downto 0); - variable CC_I : std_logic_vector(15 downto 0); - variable ZR_C8_I : std_logic_vector(7 downto 0); - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - case CLUT_ADR_MUX(1 downto 0) is - when "11" => CC24_I := FIFO_D(31 downto 0); - when "10" => CC24_I := FIFO_D(63 downto 32); - when "01" => CC24_I := FIFO_D(95 downto 64); - when "00" => CC24_I := FIFO_D(127 downto 96); - end case; - -- - CC_24 <= CC24_I; - -- - case CLUT_ADR_MUX(2 downto 0) is - when "111" => CC_I := FIFO_D(15 downto 0); - when "110" => CC_I := FIFO_D(31 downto 16); - when "101" => CC_I := FIFO_D(47 downto 32); - when "100" => CC_I := FIFO_D(63 downto 48); - when "011" => CC_I := FIFO_D(79 downto 64); - when "010" => CC_I := FIFO_D(95 downto 80); - when "001" => CC_I := FIFO_D(111 downto 96); - when "000" => CC_I := FIFO_D(127 downto 112); - end case; - -- - CC_16 <= CC_I(15 downto 11) & "000" & CC_I(10 downto 5) & "00" & CC_I(4 downto 0) & "000"; - -- - case CLUT_ADR_MUX(3 downto 0) is - when x"F" => ZR_C8_I := FIFO_D(7 downto 0); - when x"E" => ZR_C8_I := FIFO_D(15 downto 8); - when x"D" => ZR_C8_I := FIFO_D(23 downto 16); - when x"C" => ZR_C8_I := FIFO_D(31 downto 24); - when x"B" => ZR_C8_I := FIFO_D(39 downto 32); - when x"A" => ZR_C8_I := FIFO_D(47 downto 40); - when x"9" => ZR_C8_I := FIFO_D(55 downto 48); - when x"8" => ZR_C8_I := FIFO_D(63 downto 56); - when x"7" => ZR_C8_I := FIFO_D(71 downto 64); - when x"6" => ZR_C8_I := FIFO_D(79 downto 72); - when x"5" => ZR_C8_I := FIFO_D(87 downto 80); - when x"4" => ZR_C8_I := FIFO_D(95 downto 88); - when x"3" => ZR_C8_I := FIFO_D(103 downto 96); - when x"2" => ZR_C8_I := FIFO_D(111 downto 104); - when x"1" => ZR_C8_I := FIFO_D(119 downto 112); - when x"0" => ZR_C8_I := FIFO_D(127 downto 120); - end case; - -- - case COLOR1 is - when '1' => ZR_C8 <= ZR_C8_I; - when others => ZR_C8 <= "0000000" & ZR_C8_I(0); - end case; - end process P_CC; - - CLUT_SHIFT_IN <= CLUT_ADR_A(6 downto 1) when COLOR4 = '0' and COLOR2 = '0' else - CLUT_ADR_A(7 downto 2) when COLOR4 = '0' and COLOR2 = '1' else - "00" & CLUT_ADR_A(7 downto 4) when COLOR4 = '1' and COLOR2 = '0' else "000000"; - - FIFO_RD_REQ_128 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '1' else '0'; - FIFO_RD_REQ_512 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '0' else '0'; - - FIFO_DMUX: process - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - if FIFO_RDE = '1' and INTER_ZEI = '1' then - FIFO_D <= FIFO_D_OUT_128; - elsif FIFO_RDE = '1' then - FIFO_D <= FIFO_D_OUT_512; - end if; - end process FIFO_DMUX; - - CLUT_SHIFTREGS: process - variable CLUT_SHIFTREG : CLUT_SHIFTREG_TYPE; - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - CLUT_SHIFT_LOAD <= FIFO_RDE; - if CLUT_SHIFT_LOAD = '1' then - for i in 0 to 7 loop - CLUT_SHIFTREG(7 - i) := FIFO_D((i+1)*16 -1 downto i*16); - end loop; - else - CLUT_SHIFTREG(7) := CLUT_SHIFTREG(7)(14 downto 0) & CLUT_ADR_A(0); - CLUT_SHIFTREG(6) := CLUT_SHIFTREG(6)(14 downto 0) & CLUT_ADR_A(7); - CLUT_SHIFTREG(5) := CLUT_SHIFTREG(5)(14 downto 0) & CLUT_SHIFT_IN(5); - CLUT_SHIFTREG(4) := CLUT_SHIFTREG(4)(14 downto 0) & CLUT_SHIFT_IN(4); - CLUT_SHIFTREG(3) := CLUT_SHIFTREG(3)(14 downto 0) & CLUT_SHIFT_IN(3); - CLUT_SHIFTREG(2) := CLUT_SHIFTREG(2)(14 downto 0) & CLUT_SHIFT_IN(2); - CLUT_SHIFTREG(1) := CLUT_SHIFTREG(1)(14 downto 0) & CLUT_SHIFT_IN(1); - CLUT_SHIFTREG(0) := CLUT_SHIFTREG(0)(14 downto 0) & CLUT_SHIFT_IN(0); - end if; - -- - for i in 0 to 7 loop - CLUT_ADR_A(i) <= CLUT_SHIFTREG(i)(15); - end loop; - end process CLUT_SHIFTREGS; - - CLUT_ADR(7) <= CLUT_OFF(3) or (CLUT_ADR_A(7) and COLOR8); - CLUT_ADR(6) <= CLUT_OFF(2) or (CLUT_ADR_A(6) and COLOR8); - CLUT_ADR(5) <= CLUT_OFF(1) or (CLUT_ADR_A(5) and COLOR8); - CLUT_ADR(4) <= CLUT_OFF(0) or (CLUT_ADR_A(4) and COLOR8); - CLUT_ADR(3) <= CLUT_ADR_A(3) and (COLOR8 or COLOR4); - CLUT_ADR(2) <= CLUT_ADR_A(2) and (COLOR8 or COLOR4); - CLUT_ADR(1) <= CLUT_ADR_A(1) and (COLOR8 or COLOR4 or COLOR2); - CLUT_ADR(0) <= CLUT_ADR_A(0); - - FB_AD_OUT <= x"0" & CLUT_ST_OUT & x"0000" when CLUT_ST_RD = '1' else - CLUT_FA_OUT(17 downto 12) & "00" & CLUT_FA_OUT(11 downto 6) & "00" & x"0000" when CLUT_FA_RDH = '1' else - x"00" & CLUT_FA_OUT(5 downto 0) & "00" & x"0000" when CLUT_FA_RDL = '1' else - x"00" & CLUT_FBEE_OUT when CLUT_FBEE_RD = '1' else - DATA_OUT_VIDEO_CTRL when DATA_EN_H_VIDEO_CTRL = '1' else -- Use upper word. - DATA_OUT_VIDEO_CTRL when DATA_EN_L_VIDEO_CTRL = '1' else (others => '0'); -- Use lower word. - - FB_AD_EN_31_16 <= '1' when CLUT_FBEE_RD = '1' else - '1' when CLUT_FA_RDH = '1' else - '1' when DATA_EN_H_VIDEO_CTRL = '1' else '0'; - - FB_AD_EN_15_0 <= '1' when CLUT_FBEE_RD = '1' else - '1' when CLUT_FA_RDL = '1' else - '1' when DATA_EN_L_VIDEO_CTRL = '1' else '0'; - - VD_VZ <= VD_VZ_I; - - DFF_CLK0: process - begin - wait until CLK_DDR0 = '1' and CLK_DDR0' event; - VD_VZ_I <= VD_VZ_I(63 downto 0) & VDP_IN(63 downto 0); - -- - if FIFO_WRE = '1' then - VDM_A <= VD_VZ_I; - VDM_B <= VDM_A; - end if; - end process DFF_CLK0; - - DFF_CLK2: process - begin - wait until CLK_DDR2 = '1' and CLK_DDR2' event; - VDMP <= SR_VDMP; - end process DFF_CLK2; - - DFF_CLK3: process - begin - wait until CLK_DDR3 = '1' and CLK_DDR3' event; - VDMP_I <= VDMP; - end process DFF_CLK3; - - VDM <= VDMP_I(7 downto 4) when CLK_DDR3 = '1' else VDMP_I(3 downto 0); - - SHIFT_CLK0: process - variable TMP : std_logic_vector(4 downto 0); - begin - wait until CLK_DDR0 = '1' and CLK_DDR0' event; - TMP := SR_FIFO_WRE & TMP(4 downto 1); - FIFO_WRE <= TMP(0); - end process SHIFT_CLK0; - - with VDM_SEL select - VDM_C <= VDM_B when x"0", - VDM_B(119 downto 0) & VDM_A(127 downto 120) when x"1", - VDM_B(111 downto 0) & VDM_A(127 downto 112) when x"2", - VDM_B(103 downto 0) & VDM_A(127 downto 104) when x"3", - VDM_B(95 downto 0) & VDM_A(127 downto 96) when x"4", - VDM_B(87 downto 0) & VDM_A(127 downto 88) when x"5", - VDM_B(79 downto 0) & VDM_A(127 downto 80) when x"6", - VDM_B(71 downto 0) & VDM_A(127 downto 72) when x"7", - VDM_B(63 downto 0) & VDM_A(127 downto 64) when x"8", - VDM_B(55 downto 0) & VDM_A(127 downto 56) when x"9", - VDM_B(47 downto 0) & VDM_A(127 downto 48) when x"A", - VDM_B(39 downto 0) & VDM_A(127 downto 40) when x"B", - VDM_B(31 downto 0) & VDM_A(127 downto 32) when x"C", - VDM_B(23 downto 0) & VDM_A(127 downto 24) when x"D", - VDM_B(15 downto 0) & VDM_A(127 downto 16) when x"E", - VDM_B(7 downto 0) & VDM_A(127 downto 8) when x"F"; - - I_FIFO_DC0: lpm_fifo_dc0 - port map( - aclr => FIFO_CLR_I, - data => VDM_C, - rdclk => CLK_PIXEL_I, - rdreq => FIFO_RD_REQ_512, - wrclk => CLK_DDR0, - wrreq => FIFO_WRE, - q => FIFO_D_OUT_512, - --rdempty =>, -- Not used. - wrusedw => FIFO_MW - ); - - I_FIFO_DZ: lpm_fifoDZ - port map( - aclr => DOP_FIFO_CLR, - clock => CLK_PIXEL_I, - data => FIFO_D_OUT_512, - rdreq => FIFO_RD_REQ_128, - wrreq => FIFO_RD_REQ_512, - q => FIFO_D_OUT_128 - ); - - I_VIDEO_CTRL: VIDEO_CTRL - port map( - CLK_MAIN => CLK_MAIN, - FB_CSn(1) => FB_CSn(1), - FB_CSn(2) => FB_CSn(2), - FB_WRn => FB_WRn, - FB_OEn => FB_OEn, - FB_SIZE(0) => FB_SIZE0, - FB_SIZE(1) => FB_SIZE1, - FB_ADR => FB_ADR, - CLK33M => CLK_33M, - CLK25M => CLK_25M, - BLITTER_RUN => BLITTER_RUN, - CLK_VIDEO => CLK_VIDEO, - VR_D => VR_D, - VR_BUSY => VR_BUSY, - COLOR8 => COLOR8, - FBEE_CLUT_RD => CLUT_FBEE_RD, - COLOR1 => COLOR1, - FALCON_CLUT_RDH => CLUT_FA_RDH, - FALCON_CLUT_RDL => CLUT_FA_RDL, - FALCON_CLUT_WR => CLUT_FA_WR, - CLUT_ST_RD => CLUT_ST_RD, - CLUT_ST_WR => CLUT_ST_WR, - CLUT_MUX_ADR => CLUT_ADR_MUX, - HSYNC => HSYNC, - VSYNC => VSYNC, - BLANKn => BLANKn, - SYNCn => SYNCn, - PD_VGAn => PD_VGAn, - FIFO_RDE => FIFO_RDE, - COLOR2 => COLOR2, - COLOR4 => COLOR4, - CLK_PIXEL => CLK_PIXEL_I, - CLUT_OFF => CLUT_OFF, - BLITTER_ON => BLITTER_ON, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - VIDEO_MOD_TA => VIDEO_MOD_TA, - CCR => CCR, - CCSEL => CC_SEL, - FBEE_CLUT_WR => CLUT_FBEE_WR, - INTER_ZEI => INTER_ZEI, - DOP_FIFO_CLR => DOP_FIFO_CLR, - VIDEO_RECONFIG => VIDEO_RECONFIG, - VR_WR => VR_WR, - VR_RD => VR_RD, - FIFO_CLR => FIFO_CLR_I, - DATA_IN => FB_AD_IN, - DATA_OUT => DATA_OUT_VIDEO_CTRL, - DATA_EN_H => DATA_EN_H_VIDEO_CTRL, - DATA_EN_L => DATA_EN_L_VIDEO_CTRL - ); -end architecture; +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- +---- ---- +---- Description: ---- +---- This design unit provides the video toplevel of the 'Firebee'---- +---- computer. It is optimized for the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- +---- tion of the Firebee configware originally provided by Fredi ---- +---- Ashwanden and Wolfgang Förster. This release is in compa- ---- +---- rision to the first edition completely written in VHDL. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2012 Wolfgang Förster ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K12B 20120801 WF +-- Initial Release of the second edition. +-- ST colours enhanced to 4 bit colour mode (STE compatibility). + +library work; +use work.firebee_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity VIDEO_SYSTEM is + port( + CLK_MAIN : in std_logic; + CLK_33M : in std_logic; + CLK_25M : in std_logic; + CLK_VIDEO : in std_logic; + CLK_DDR3 : in std_logic; + CLK_DDR2 : in std_logic; + CLK_DDR0 : in std_logic; + CLK_PIXEL : out std_logic; + + VR_D : in std_logic_vector(8 downto 0); + VR_BUSY : in std_logic; + + FB_ADR : in std_logic_vector(31 downto 0); + FB_AD_IN : in std_logic_vector(31 downto 0); + FB_AD_OUT : out std_logic_vector(31 downto 0); + FB_AD_EN_31_16 : out std_logic; -- Hi word. + FB_AD_EN_15_0 : out std_logic; -- Low word. + FB_ALE : in std_logic; + FB_CSn : in std_logic_vector(3 downto 1); + FB_OEn : in std_logic; + FB_WRn : in std_logic; + FB_SIZE1 : in std_logic; + FB_SIZE0 : in std_logic; + + VDP_IN : in std_logic_vector(63 downto 0); + + VR_RD : out std_logic; + VR_WR : out std_logic; + VIDEO_RECONFIG : out std_logic; + + RED : out std_logic_vector(7 downto 0); + GREEN : out std_logic_vector(7 downto 0); + BLUE : out std_logic_vector(7 downto 0); + VSYNC : out std_logic; + HSYNC : out std_logic; + SYNCn : out std_logic; + BLANKn : out std_logic; + + PD_VGAn : out std_logic; + VIDEO_MOD_TA : out std_logic; + + VD_VZ : out std_logic_vector(127 downto 0); + SR_FIFO_WRE : in std_logic; + SR_VDMP : in std_logic_vector(7 downto 0); + FIFO_MW : out std_logic_vector(8 downto 0); + VDM_SEL : in std_logic_vector(3 downto 0); + VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); + FIFO_CLR : out std_logic; + VDM : out std_logic_vector(3 downto 0); + + BLITTER_RUN : in std_logic; + BLITTER_ON : out std_logic + ); +end entity VIDEO_SYSTEM; + +architecture BEHAVIOUR of VIDEO_SYSTEM is + component lpm_fifo_dc0 + port( + aclr : in std_logic := '0'; + data : in std_logic_vector (127 downto 0); + rdclk : in std_logic ; + rdreq : in std_logic ; + wrclk : in std_logic ; + wrreq : in std_logic ; + q : out std_logic_vector (127 downto 0); + rdempty : out STD_LOGIC ; + wrusedw : out std_logic_vector (8 downto 0) + ); + end component; + + component lpm_fifoDZ is + port( + aclr : in std_logic ; + clock : in std_logic ; + data : in std_logic_vector (127 downto 0); + rdreq : in std_logic ; + wrreq : in std_logic ; + q : out std_logic_vector (127 downto 0) + ); + end component; + + type CLUT_SHIFTREG_TYPE is array(0 to 7) of std_logic_vector(15 downto 0); + type CLUT_ST_TYPE is array(0 to 15) of std_logic_vector(11 downto 0); + type CLUT_FA_TYPE is array(0 to 255) of std_logic_vector(17 downto 0); + type CLUT_FBEE_TYPE is array(0 to 255) of std_logic_vector(23 downto 0); + + signal CLUT_FA : CLUT_FA_TYPE; + signal CLUT_FI : CLUT_FBEE_TYPE; + signal CLUT_ST : CLUT_ST_TYPE; + + signal CLUT_FA_R : std_logic_vector(5 downto 0); + signal CLUT_FA_G : std_logic_vector(5 downto 0); + signal CLUT_FA_B : std_logic_vector(5 downto 0); + signal CLUT_FBEE_R : std_logic_vector(7 downto 0); + signal CLUT_FBEE_G : std_logic_vector(7 downto 0); + signal CLUT_FBEE_B : std_logic_vector(7 downto 0); + signal CLUT_ST_R : std_logic_vector(3 downto 0); + signal CLUT_ST_G : std_logic_vector(3 downto 0); + signal CLUT_ST_B : std_logic_vector(3 downto 0); + + signal CLUT_FA_OUT : std_logic_vector(17 downto 0); + signal CLUT_FBEE_OUT : std_logic_vector(23 downto 0); + signal CLUT_ST_OUT : std_logic_vector(11 downto 0); + + signal CLUT_ADR : std_logic_vector(7 downto 0); + signal CLUT_ADR_A : std_logic_vector(7 downto 0); + signal CLUT_ADR_MUX : std_logic_vector(3 downto 0); + signal CLUT_SHIFT_IN : std_logic_vector(5 downto 0); + + signal CLUT_SHIFT_LOAD : std_logic; + signal CLUT_OFF : std_logic_vector(3 downto 0); + signal CLUT_FBEE_RD : std_logic; + signal CLUT_FBEE_WR : std_logic_vector(3 downto 0); + signal CLUT_FA_RDH : std_logic; + signal CLUT_FA_RDL : std_logic; + signal CLUT_FA_WR : std_logic_vector(3 downto 0); + signal CLUT_ST_RD : std_logic; + signal CLUT_ST_WR : std_logic_vector(1 downto 0); + + signal DATA_OUT_VIDEO_CTRL : std_logic_vector(31 downto 0); + signal DATA_EN_H_VIDEO_CTRL : std_logic; + signal DATA_EN_L_VIDEO_CTRL : std_logic; + + signal COLOR1 : std_logic; + signal COLOR2 : std_logic; + signal COLOR4 : std_logic; + signal COLOR8 : std_logic; + signal CCR : std_logic_vector(23 downto 0); + signal CC_SEL : std_logic_vector(2 downto 0); + + signal FIFO_CLR_I : std_logic; + signal DOP_FIFO_CLR : std_logic; + signal FIFO_WRE : std_logic; + + signal FIFO_RD_REQ_128 : std_logic; + signal FIFO_RD_REQ_512 : std_logic; + signal FIFO_RDE : std_logic; + signal INTER_ZEI : std_logic; + signal FIFO_D_OUT_128 : std_logic_vector(127 downto 0); + signal FIFO_D_OUT_512 : std_logic_vector(127 downto 0); + signal FIFO_D_IN_512 : std_logic_vector(127 downto 0); + signal FIFO_D : std_logic_vector(127 downto 0); + + signal VD_VZ_I : std_logic_vector(127 downto 0); + signal VDM_A : std_logic_vector(127 downto 0); + signal VDM_B : std_logic_vector(127 downto 0); + signal VDM_C : std_logic_vector(127 downto 0); + signal V_DMA_SEL : std_logic_vector(3 downto 0); + signal VDMP : std_logic_vector(7 downto 0); + signal VDMP_I : std_logic_vector(7 downto 0); + signal CC_24 : std_logic_vector(31 downto 0); + signal CC_16 : std_logic_vector(23 downto 0); + signal CLK_PIXEL_I : std_logic; + signal VD_OUT_I : std_logic_vector(31 downto 0); + signal ZR_C8 : std_logic_vector(7 downto 0); + +begin + CLK_PIXEL <= CLK_PIXEL_I; + + FIFO_CLR <= FIFO_CLR_I; + + P_CLUT_ST_MC: process + -- This is the dual ported ram for the ST colour lookup tables. + variable clut_fa_index : integer; + variable clut_st_index : integer; + variable clut_fi_index : integer; + begin + clut_st_index := to_integer(unsigned(FB_ADR(4 downto 1))); + clut_fa_index := to_integer(unsigned(FB_ADR(9 downto 2))); + clut_fi_index := to_integer(unsigned(FB_ADR(9 downto 2))); + + wait until CLK_MAIN = '1' and CLK_MAIN' event; + if CLUT_ST_WR(0) = '1' then + CLUT_ST(clut_st_index)(11 downto 8) <= FB_AD_IN(27 downto 24); + end if; + if CLUT_ST_WR(1) = '1' then + CLUT_ST(clut_st_index)(7 downto 0) <= FB_AD_IN(23 downto 16); + end if; + + if CLUT_FA_WR(0) = '1' then + CLUT_FA(clut_fa_index)(17 downto 12) <= FB_AD_IN(31 downto 26); + end if; + if CLUT_FA_WR(1) = '1' then + CLUT_FA(clut_fa_index)(11 downto 6) <= FB_AD_IN(23 downto 18); + end if; + if CLUT_FA_WR(3) = '1' then + CLUT_FA(clut_fa_index)(5 downto 0) <= FB_AD_IN(23 downto 18); + end if; + + if CLUT_FBEE_WR(1) = '1' then + CLUT_FI(clut_fi_index)(23 downto 16) <= FB_AD_IN(23 downto 16); + end if; + if CLUT_FBEE_WR(2) = '1' then + CLUT_FI(clut_fi_index)(15 downto 8) <= FB_AD_IN(15 downto 8); + end if; + if CLUT_FBEE_WR(3) = '1' then + CLUT_FI(clut_fi_index)(7 downto 0) <= FB_AD_IN(7 downto 0); + end if; + -- + CLUT_ST_OUT <= CLUT_ST(clut_st_index); + CLUT_FA_OUT <= CLUT_FA(clut_fa_index); + CLUT_FBEE_OUT <= CLUT_FI(clut_fi_index); + end process P_CLUT_ST_MC; + + P_CLUT_ST_PX: process + variable clut_fa_index : integer; + variable clut_st_index : integer; + variable clut_fi_index : integer; + -- This is the dual ported ram for the ST colour lookup tables. + begin + clut_st_index := to_integer(unsigned(CLUT_ADR(3 downto 0))); + clut_fa_index := to_integer(unsigned(CLUT_ADR)); + clut_fi_index := to_integer(unsigned(ZR_C8)); + + wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; + + CLUT_ST_R <= CLUT_ST(clut_st_index)(8) & CLUT_ST(clut_st_index)(11 downto 9); + CLUT_ST_G <= CLUT_ST(clut_st_index)(4) & CLUT_ST(clut_st_index)(7 downto 5); + CLUT_ST_B <= CLUT_ST(clut_st_index)(0) & CLUT_ST(clut_st_index)(3 downto 1); + + CLUT_FA_R <= CLUT_FA(clut_fa_index)(17 downto 12); + CLUT_FA_G <= CLUT_FA(clut_fa_index)(11 downto 6); + CLUT_FA_B <= CLUT_FA(clut_fa_index)(5 downto 0); + + CLUT_FBEE_R <= CLUT_FI(clut_fi_index)(23 downto 16); + CLUT_FBEE_G <= CLUT_FI(clut_fi_index)(15 downto 8); + CLUT_FBEE_B <= CLUT_FI(clut_fi_index)(7 downto 0); + end process P_CLUT_ST_PX; + + P_VIDEO_OUT: process + variable VIDEO_OUT : std_logic_vector(23 downto 0); + begin + wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; + case CC_SEL is + when "111" => VIDEO_OUT := CCR; -- Register type video. + when "110" => VIDEO_OUT := CC_24(23 downto 0); -- 3 byte FIFO type video. + when "101" => VIDEO_OUT := CC_16; -- 2 byte FIFO type video. + when "100" => VIDEO_OUT := CLUT_FBEE_R & CLUT_FBEE_G & CLUT_FBEE_B; -- Firebee type video. + when "001" => VIDEO_OUT := CLUT_FA_R & "00" & CLUT_FA_G & "00" & CLUT_FA_B & "00"; -- Falcon type video. + when "000" => VIDEO_OUT := CLUT_ST_R & x"0" & CLUT_ST_G & x"0" & CLUT_ST_B & x"0"; -- ST type video. + when others => VIDEO_OUT := (others => '0'); + end case; + RED <= VIDEO_OUT(23 downto 16); + GREEN <= VIDEO_OUT(15 downto 8); + BLUE <= VIDEO_OUT(7 downto 0); + end process P_VIDEO_OUT; + + P_CC: process + variable CC24_I : std_logic_vector(31 downto 0); + variable CC_I : std_logic_vector(15 downto 0); + variable ZR_C8_I : std_logic_vector(7 downto 0); + begin + wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; + case CLUT_ADR_MUX(1 downto 0) is + when "11" => CC24_I := FIFO_D(31 downto 0); + when "10" => CC24_I := FIFO_D(63 downto 32); + when "01" => CC24_I := FIFO_D(95 downto 64); + when "00" => CC24_I := FIFO_D(127 downto 96); + when others => CC24_I := (others => 'Z'); + end case; + -- + CC_24 <= CC24_I; + -- + case CLUT_ADR_MUX(2 downto 0) is + when "111" => CC_I := FIFO_D(15 downto 0); + when "110" => CC_I := FIFO_D(31 downto 16); + when "101" => CC_I := FIFO_D(47 downto 32); + when "100" => CC_I := FIFO_D(63 downto 48); + when "011" => CC_I := FIFO_D(79 downto 64); + when "010" => CC_I := FIFO_D(95 downto 80); + when "001" => CC_I := FIFO_D(111 downto 96); + when "000" => CC_I := FIFO_D(127 downto 112); + when others => CC_I := (others => 'X'); + end case; + -- + CC_16 <= CC_I(15 downto 11) & "000" & CC_I(10 downto 5) & "00" & CC_I(4 downto 0) & "000"; + -- + case CLUT_ADR_MUX(3 downto 0) is + when x"F" => ZR_C8_I := FIFO_D(7 downto 0); + when x"E" => ZR_C8_I := FIFO_D(15 downto 8); + when x"D" => ZR_C8_I := FIFO_D(23 downto 16); + when x"C" => ZR_C8_I := FIFO_D(31 downto 24); + when x"B" => ZR_C8_I := FIFO_D(39 downto 32); + when x"A" => ZR_C8_I := FIFO_D(47 downto 40); + when x"9" => ZR_C8_I := FIFO_D(55 downto 48); + when x"8" => ZR_C8_I := FIFO_D(63 downto 56); + when x"7" => ZR_C8_I := FIFO_D(71 downto 64); + when x"6" => ZR_C8_I := FIFO_D(79 downto 72); + when x"5" => ZR_C8_I := FIFO_D(87 downto 80); + when x"4" => ZR_C8_I := FIFO_D(95 downto 88); + when x"3" => ZR_C8_I := FIFO_D(103 downto 96); + when x"2" => ZR_C8_I := FIFO_D(111 downto 104); + when x"1" => ZR_C8_I := FIFO_D(119 downto 112); + when x"0" => ZR_C8_I := FIFO_D(127 downto 120); + when others => ZR_C8_I := (others => 'X'); + end case; + -- + case COLOR1 is + when '1' => ZR_C8 <= ZR_C8_I; + when others => ZR_C8 <= "0000000" & ZR_C8_I(0); + end case; + end process P_CC; + + CLUT_SHIFT_IN <= CLUT_ADR_A(6 downto 1) when COLOR4 = '0' and COLOR2 = '0' else + CLUT_ADR_A(7 downto 2) when COLOR4 = '0' and COLOR2 = '1' else + "00" & CLUT_ADR_A(7 downto 4) when COLOR4 = '1' and COLOR2 = '0' else "000000"; + + FIFO_RD_REQ_128 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '1' else '0'; + FIFO_RD_REQ_512 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '0' else '0'; + + FIFO_DMUX: process + begin + wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; + if FIFO_RDE = '1' and INTER_ZEI = '1' then + FIFO_D <= FIFO_D_OUT_128; + elsif FIFO_RDE = '1' then + FIFO_D <= FIFO_D_OUT_512; + end if; + end process FIFO_DMUX; + + CLUT_SHIFTREGS: process + variable CLUT_SHIFTREG : CLUT_SHIFTREG_TYPE; + begin + wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; + CLUT_SHIFT_LOAD <= FIFO_RDE; + if CLUT_SHIFT_LOAD = '1' then + for i in 0 to 7 loop + CLUT_SHIFTREG(7 - i) := FIFO_D((i+1)*16 -1 downto i*16); + end loop; + else + CLUT_SHIFTREG(7) := CLUT_SHIFTREG(7)(14 downto 0) & CLUT_ADR_A(0); + CLUT_SHIFTREG(6) := CLUT_SHIFTREG(6)(14 downto 0) & CLUT_ADR_A(7); + CLUT_SHIFTREG(5) := CLUT_SHIFTREG(5)(14 downto 0) & CLUT_SHIFT_IN(5); + CLUT_SHIFTREG(4) := CLUT_SHIFTREG(4)(14 downto 0) & CLUT_SHIFT_IN(4); + CLUT_SHIFTREG(3) := CLUT_SHIFTREG(3)(14 downto 0) & CLUT_SHIFT_IN(3); + CLUT_SHIFTREG(2) := CLUT_SHIFTREG(2)(14 downto 0) & CLUT_SHIFT_IN(2); + CLUT_SHIFTREG(1) := CLUT_SHIFTREG(1)(14 downto 0) & CLUT_SHIFT_IN(1); + CLUT_SHIFTREG(0) := CLUT_SHIFTREG(0)(14 downto 0) & CLUT_SHIFT_IN(0); + end if; + -- + for i in 0 to 7 loop + CLUT_ADR_A(i) <= CLUT_SHIFTREG(i)(15); + end loop; + end process CLUT_SHIFTREGS; + + CLUT_ADR(7) <= CLUT_OFF(3) or (CLUT_ADR_A(7) and COLOR8); + CLUT_ADR(6) <= CLUT_OFF(2) or (CLUT_ADR_A(6) and COLOR8); + CLUT_ADR(5) <= CLUT_OFF(1) or (CLUT_ADR_A(5) and COLOR8); + CLUT_ADR(4) <= CLUT_OFF(0) or (CLUT_ADR_A(4) and COLOR8); + CLUT_ADR(3) <= CLUT_ADR_A(3) and (COLOR8 or COLOR4); + CLUT_ADR(2) <= CLUT_ADR_A(2) and (COLOR8 or COLOR4); + CLUT_ADR(1) <= CLUT_ADR_A(1) and (COLOR8 or COLOR4 or COLOR2); + CLUT_ADR(0) <= CLUT_ADR_A(0); + + FB_AD_OUT <= x"0" & CLUT_ST_OUT & x"0000" when CLUT_ST_RD = '1' else + CLUT_FA_OUT(17 downto 12) & "00" & CLUT_FA_OUT(11 downto 6) & "00" & x"0000" when CLUT_FA_RDH = '1' else + x"00" & CLUT_FA_OUT(5 downto 0) & "00" & x"0000" when CLUT_FA_RDL = '1' else + x"00" & CLUT_FBEE_OUT when CLUT_FBEE_RD = '1' else + DATA_OUT_VIDEO_CTRL when DATA_EN_H_VIDEO_CTRL = '1' else -- Use upper word. + DATA_OUT_VIDEO_CTRL when DATA_EN_L_VIDEO_CTRL = '1' else (others => '0'); -- Use lower word. + + FB_AD_EN_31_16 <= '1' when CLUT_FBEE_RD = '1' else + '1' when CLUT_FA_RDH = '1' else + '1' when DATA_EN_H_VIDEO_CTRL = '1' else '0'; + + FB_AD_EN_15_0 <= '1' when CLUT_FBEE_RD = '1' else + '1' when CLUT_FA_RDL = '1' else + '1' when DATA_EN_L_VIDEO_CTRL = '1' else '0'; + + VD_VZ <= VD_VZ_I; + + DFF_CLK0: process + begin + wait until CLK_DDR0 = '1' and CLK_DDR0' event; + VD_VZ_I <= VD_VZ_I(63 downto 0) & VDP_IN(63 downto 0); + -- + if FIFO_WRE = '1' then + VDM_A <= VD_VZ_I; + VDM_B <= VDM_A; + end if; + end process DFF_CLK0; + + DFF_CLK2: process + begin + wait until CLK_DDR2 = '1' and CLK_DDR2' event; + VDMP <= SR_VDMP; + end process DFF_CLK2; + + DFF_CLK3: process + begin + wait until CLK_DDR3 = '1' and CLK_DDR3' event; + VDMP_I <= VDMP; + end process DFF_CLK3; + + VDM <= VDMP_I(7 downto 4) when CLK_DDR3 = '1' else VDMP_I(3 downto 0); + + SHIFT_CLK0: process + variable TMP : std_logic_vector(4 downto 0); + begin + wait until CLK_DDR0 = '1' and CLK_DDR0' event; + TMP := SR_FIFO_WRE & TMP(4 downto 1); + FIFO_WRE <= TMP(0); + end process SHIFT_CLK0; + + with VDM_SEL select + VDM_C <= VDM_B when x"0", + VDM_B(119 downto 0) & VDM_A(127 downto 120) when x"1", + VDM_B(111 downto 0) & VDM_A(127 downto 112) when x"2", + VDM_B(103 downto 0) & VDM_A(127 downto 104) when x"3", + VDM_B(95 downto 0) & VDM_A(127 downto 96) when x"4", + VDM_B(87 downto 0) & VDM_A(127 downto 88) when x"5", + VDM_B(79 downto 0) & VDM_A(127 downto 80) when x"6", + VDM_B(71 downto 0) & VDM_A(127 downto 72) when x"7", + VDM_B(63 downto 0) & VDM_A(127 downto 64) when x"8", + VDM_B(55 downto 0) & VDM_A(127 downto 56) when x"9", + VDM_B(47 downto 0) & VDM_A(127 downto 48) when x"A", + VDM_B(39 downto 0) & VDM_A(127 downto 40) when x"B", + VDM_B(31 downto 0) & VDM_A(127 downto 32) when x"C", + VDM_B(23 downto 0) & VDM_A(127 downto 24) when x"D", + VDM_B(15 downto 0) & VDM_A(127 downto 16) when x"E", + VDM_B(7 downto 0) & VDM_A(127 downto 8) when x"F", + (others => 'X') when others; + + I_FIFO_DC0: lpm_fifo_dc0 + port map( + aclr => FIFO_CLR_I, + data => VDM_C, + rdclk => CLK_PIXEL_I, + rdreq => FIFO_RD_REQ_512, + wrclk => CLK_DDR0, + wrreq => FIFO_WRE, + q => FIFO_D_OUT_512, + --rdempty =>, -- Not used. + wrusedw => FIFO_MW + ); + + I_FIFO_DZ: lpm_fifoDZ + port map( + aclr => DOP_FIFO_CLR, + clock => CLK_PIXEL_I, + data => FIFO_D_OUT_512, + rdreq => FIFO_RD_REQ_128, + wrreq => FIFO_RD_REQ_512, + q => FIFO_D_OUT_128 + ); + + I_VIDEO_CTRL: VIDEO_CTRL + port map( + CLK_MAIN => CLK_MAIN, + FB_CSn(1) => FB_CSn(1), + FB_CSn(2) => FB_CSn(2), + FB_WRn => FB_WRn, + FB_OEn => FB_OEn, + FB_SIZE(0) => FB_SIZE0, + FB_SIZE(1) => FB_SIZE1, + FB_ADR => FB_ADR, + CLK33M => CLK_33M, + CLK25M => CLK_25M, + BLITTER_RUN => BLITTER_RUN, + CLK_VIDEO => CLK_VIDEO, + VR_D => VR_D, + VR_BUSY => VR_BUSY, + COLOR8 => COLOR8, + FBEE_CLUT_RD => CLUT_FBEE_RD, + COLOR1 => COLOR1, + FALCON_CLUT_RDH => CLUT_FA_RDH, + FALCON_CLUT_RDL => CLUT_FA_RDL, + FALCON_CLUT_WR => CLUT_FA_WR, + CLUT_ST_RD => CLUT_ST_RD, + CLUT_ST_WR => CLUT_ST_WR, + CLUT_MUX_ADR => CLUT_ADR_MUX, + HSYNC => HSYNC, + VSYNC => VSYNC, + BLANKn => BLANKn, + SYNCn => SYNCn, + PD_VGAn => PD_VGAn, + FIFO_RDE => FIFO_RDE, + COLOR2 => COLOR2, + COLOR4 => COLOR4, + CLK_PIXEL => CLK_PIXEL_I, + CLUT_OFF => CLUT_OFF, + BLITTER_ON => BLITTER_ON, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + VIDEO_MOD_TA => VIDEO_MOD_TA, + CCR => CCR, + CCSEL => CC_SEL, + FBEE_CLUT_WR => CLUT_FBEE_WR, + INTER_ZEI => INTER_ZEI, + DOP_FIFO_CLR => DOP_FIFO_CLR, + VIDEO_RECONFIG => VIDEO_RECONFIG, + VR_WR => VR_WR, + VR_RD => VR_RD, + FIFO_CLR => FIFO_CLR_I, + DATA_IN => FB_AD_IN, + DATA_OUT => DATA_OUT_VIDEO_CTRL, + DATA_EN_H => DATA_EN_H_VIDEO_CTRL, + DATA_EN_L => DATA_EN_L_VIDEO_CTRL + ); +end architecture; diff --git a/vhdl/testbenches/ddr_ctlr_tb.vhd b/vhdl/testbenches/ddr_ctlr_tb.vhd index 590c573..217e7b2 100644 --- a/vhdl/testbenches/ddr_ctlr_tb.vhd +++ b/vhdl/testbenches/ddr_ctlr_tb.vhd @@ -1,3 +1,6 @@ +library work; +use work.firebee_pkg.all; + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -10,8 +13,45 @@ architecture beh of ddr_ctlr_tb is signal clock_33 : std_logic := '0'; -- 33 MHz clock signal ddr_clk : std_logic := '0'; -- ddr clock - signal vec : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; - signal o : std_logic_vector(31 downto 0); + signal FB_ADR : std_logic_vector(31 downto 0); + signal DDR_SYNC_66M : std_logic; + signal FB_CS1n : std_logic; + signal FB_OEn : std_logic; + signal FB_SIZE0 : std_logic; + signal FB_SIZE1 : std_logic; + signal FB_ALE : std_logic; + signal FB_WRn : std_logic; + signal FIFO_CLR : std_logic; + signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0); + signal BLITTER_ADR : std_logic_vector(31 downto 0); + signal BLITTER_SIG : std_logic; + signal BLITTER_WR : std_logic; + signal DDRCLK0 : std_logic; + signal CLK_33M : std_logic; + signal FIFO_MW : std_logic_vector(8 downto 0); + signal VA : std_logic_vector(12 downto 0); + signal VWEn : std_logic; + signal VRASn : std_logic; + signal VCSn : std_logic; + signal VCKE : std_logic; + signal VCASn : std_logic; + signal FB_LE : std_logic_vector(3 downto 0); + signal FB_VDOE : std_logic_vector(3 downto 0); + signal SR_FIFO_WRE : std_logic; + signal SR_DDR_FB : std_logic; + signal SR_DDR_WR : std_logic; + signal SR_DDRWR_D_SEL: std_logic; + signal SR_VDMP : std_logic_vector(7 downto 0); + signal VIDEO_DDR_TA : std_logic; + signal SR_BLITTER_DACK : std_logic; + signal BA : std_logic_vector(1 downto 0); + signal DDRWR_D_SEL1 : std_logic; + signal VDM_SEL : std_logic_vector(3 downto 0); + signal DATA_IN : std_logic_vector(31 downto 0); + signal DATA_OUT : std_logic_vector(31 downto 16); + signal DATA_EN_H : std_logic; + signal DATA_EN_L : std_logic; + component DDR_CTRL_V1 port( CLK_MAIN : in std_logic; @@ -60,8 +100,44 @@ begin port map ( CLK_MAIN => clock, - vec_in => vec, - vec_out => o + DDR_SYNC_66M => DDR_SYNC_66M, + FB_ADR => FB_ADR, + FB_CS1n => FB_CS1n, + FB_OEn => FB_OEn, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + FB_ALE => FB_ALE, + FB_WRn => FB_WRn, + FIFO_CLR => FIFO_CLR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + BLITTER_ADR => BLITTER_ADR, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + DDRCLK0 => DDRCLK0, + CLK_33M => CLK_33M, + FIFO_MW => FIFO_MW, + VA => VA, + VWEn => VWEn, + VRASn => VRASn, + VCSn => VCSn, + VCKE => VCKE, + VCASn => VCASn, + FB_LE => FB_LE, + FB_VDOE => FB_VDOE, + SR_FIFO_WRE => SR_FIFO_WRE, + SR_DDR_FB => SR_DDR_FB, + SR_DDR_WR => SR_DDR_WR, + SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, + SR_VDMP => SR_VDMP, + VIDEO_DDR_TA => VIDEO_DDR_TA, + SR_BLITTER_DACK => SR_BLITTER_DACK, + BA => BA, + DDRWR_D_SEL1 => DDRWR_D_SEL1, + VDM_SEL => VDM_SEL, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_EN_H => DATA_EN_H, + DATA_EN_L => DATA_EN_L ); stimulate_clock : process @@ -72,11 +148,11 @@ begin stimulate : process begin - vec <= "00000000000000000000000000000001"; + FB_ADR <= "00000000000000000000000000000001"; wait for 20 ps; - vec <= "10000000000000000000000000000000"; + FB_ADR <= "10000000000000000000000000000000"; wait for 20 ps; - vec <= "00000000000000000000000000000101"; + FB_ADR <= "00000000000000000000000000000101"; wait for 20 ps; end process; end beh;