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worked on testbench

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This commit is contained in:
Markus Fröschle
2014-06-11 16:41:25 +00:00
parent 2c29f6a232
commit 8d0ede14c8
8 changed files with 832 additions and 729 deletions
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348
vhdl/backend/Altera/Firebee/altpll4.mif
View File

@@ -1,174 +1,174 @@
-- Copyright (C) 1991-2012 Altera Corporation -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions -- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic -- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing -- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any -- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject -- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License -- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License -- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including, -- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of -- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by -- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the -- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. -- applicable agreement for further details.
-- MIF file representing initial state of PLL Scan Chain -- MIF file representing initial state of PLL Scan Chain
-- Device Family: Cyclone III -- Device Family: Cyclone III
-- Device Part: - -- Device Part: -
-- Device Speed Grade: 8 -- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits) -- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: D:/WF/Projects/VHDL-Designs/Firebee-WF/rtl/vhdl/Firebee_V1//altpll4.mif -- File Name: /home/likewise-open/BAT/froesm1/Dokumente/Development/workspace/vhdl/backend/Altera/Firebee/altpll4.mif
-- Generated: Tue Jul 17 11:06:24 2012 -- Generated: Tue Jun 10 12:41:45 2014
WIDTH=1; WIDTH=1;
DEPTH=144; DEPTH=144;
ADDRESS_RADIX=UNS; ADDRESS_RADIX=UNS;
DATA_RADIX=UNS; DATA_RADIX=UNS;
CONTENT BEGIN CONTENT BEGIN
0 : 0; -- Reserved Bits = 0 (1 bit(s)) 0 : 0; -- Reserved Bits = 0 (1 bit(s))
1 : 0; -- Reserved Bits = 0 (1 bit(s)) 1 : 0; -- Reserved Bits = 0 (1 bit(s))
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
3 : 0; 3 : 0;
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
5 : 1; 5 : 1;
6 : 0; 6 : 0;
7 : 1; 7 : 1;
8 : 1; 8 : 1;
9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1) 9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1)
10 : 0; -- Reserved Bits = 0 (5 bit(s)) 10 : 0; -- Reserved Bits = 0 (5 bit(s))
11 : 0; 11 : 0;
12 : 0; 12 : 0;
13 : 0; 13 : 0;
14 : 0; 14 : 0;
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
16 : 0; 16 : 0;
17 : 1; 17 : 1;
18 : 1; -- N counter: Bypass = 1 (1 bit(s)) 18 : 1; -- N counter: Bypass = 1 (1 bit(s))
19 : 0; -- N counter: High Count = 0 (8 bit(s)) 19 : 0; -- N counter: High Count = 0 (8 bit(s))
20 : 0; 20 : 0;
21 : 0; 21 : 0;
22 : 0; 22 : 0;
23 : 0; 23 : 0;
24 : 0; 24 : 0;
25 : 0; 25 : 0;
26 : 0; 26 : 0;
27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) 27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
28 : 0; -- N counter: Low Count = 0 (8 bit(s)) 28 : 0; -- N counter: Low Count = 0 (8 bit(s))
29 : 0; 29 : 0;
30 : 0; 30 : 0;
31 : 0; 31 : 0;
32 : 0; 32 : 0;
33 : 0; 33 : 0;
34 : 0; 34 : 0;
35 : 0; 35 : 0;
36 : 0; -- M counter: Bypass = 0 (1 bit(s)) 36 : 0; -- M counter: Bypass = 0 (1 bit(s))
37 : 0; -- M counter: High Count = 16 (8 bit(s)) 37 : 0; -- M counter: High Count = 16 (8 bit(s))
38 : 0; 38 : 0;
39 : 0; 39 : 0;
40 : 1; 40 : 1;
41 : 0; 41 : 0;
42 : 0; 42 : 0;
43 : 0; 43 : 0;
44 : 0; 44 : 0;
45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) 45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
46 : 0; -- M counter: Low Count = 16 (8 bit(s)) 46 : 0; -- M counter: Low Count = 16 (8 bit(s))
47 : 0; 47 : 0;
48 : 0; 48 : 0;
49 : 1; 49 : 1;
50 : 0; 50 : 0;
51 : 0; 51 : 0;
52 : 0; 52 : 0;
53 : 0; 53 : 0;
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
55 : 0; -- clk0 counter: High Count = 6 (8 bit(s)) 55 : 0; -- clk0 counter: High Count = 6 (8 bit(s))
56 : 0; 56 : 0;
57 : 0; 57 : 0;
58 : 0; 58 : 0;
59 : 0; 59 : 0;
60 : 1; 60 : 1;
61 : 1; 61 : 1;
62 : 0; 62 : 0;
63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s)) 63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
64 : 0; -- clk0 counter: Low Count = 5 (8 bit(s)) 64 : 0; -- clk0 counter: Low Count = 5 (8 bit(s))
65 : 0; 65 : 0;
66 : 0; 66 : 0;
67 : 0; 67 : 0;
68 : 0; 68 : 0;
69 : 1; 69 : 1;
70 : 0; 70 : 0;
71 : 1; 71 : 1;
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
74 : 0; 74 : 0;
75 : 0; 75 : 0;
76 : 0; 76 : 0;
77 : 0; 77 : 0;
78 : 0; 78 : 0;
79 : 0; 79 : 0;
80 : 0; 80 : 0;
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
83 : 0; 83 : 0;
84 : 0; 84 : 0;
85 : 0; 85 : 0;
86 : 0; 86 : 0;
87 : 0; 87 : 0;
88 : 0; 88 : 0;
89 : 0; 89 : 0;
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
92 : 0; 92 : 0;
93 : 0; 93 : 0;
94 : 0; 94 : 0;
95 : 0; 95 : 0;
96 : 0; 96 : 0;
97 : 0; 97 : 0;
98 : 0; 98 : 0;
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
101 : 0; 101 : 0;
102 : 0; 102 : 0;
103 : 0; 103 : 0;
104 : 0; 104 : 0;
105 : 0; 105 : 0;
106 : 0; 106 : 0;
107 : 0; 107 : 0;
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
110 : 0; 110 : 0;
111 : 0; 111 : 0;
112 : 0; 112 : 0;
113 : 0; 113 : 0;
114 : 0; 114 : 0;
115 : 0; 115 : 0;
116 : 0; 116 : 0;
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
119 : 0; 119 : 0;
120 : 0; 120 : 0;
121 : 0; 121 : 0;
122 : 0; 122 : 0;
123 : 0; 123 : 0;
124 : 0; 124 : 0;
125 : 0; 125 : 0;
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
128 : 0; 128 : 0;
129 : 0; 129 : 0;
130 : 0; 130 : 0;
131 : 0; 131 : 0;
132 : 0; 132 : 0;
133 : 0; 133 : 0;
134 : 0; 134 : 0;
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
137 : 0; 137 : 0;
138 : 0; 138 : 0;
139 : 0; 139 : 0;
140 : 0; 140 : 0;
141 : 0; 141 : 0;
142 : 0; 142 : 0;
143 : 0; 143 : 0;
END; END;

22
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C40F484C6
set_global_assignment -name TOP_LEVEL_ENTITY firebee set_global_assignment -name TOP_LEVEL_ENTITY firebee
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014" set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -380,8 +380,8 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name MUX_RESTRUCTURE ON set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS" set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
@@ -401,7 +401,7 @@ set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name AUTO_RAM_RECOGNITION OFF set_global_assignment -name AUTO_RAM_RECOGNITION OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
@@ -582,8 +582,8 @@ set_location_assignment PIN_H2 -to SCSI_MSGn
set_location_assignment PIN_J3 -to SCSI_IOn set_location_assignment PIN_J3 -to SCSI_IOn
set_location_assignment PIN_U1 -to SCSI_DRQn set_location_assignment PIN_U1 -to SCSI_DRQn
set_location_assignment PIN_H1 -to SCSI_CDn set_location_assignment PIN_H1 -to SCSI_CDn
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
@@ -591,8 +591,7 @@ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_global_assignment -name EDA_TEST_BENCH_NAME ddr_ctlr_tb -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME ddr_ctlr_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ddr_ctlr_tb set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr_ctlr_tb -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr_ctrl_tb -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[1]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[1]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[2]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[2]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[3]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[3]"
@@ -670,4 +669,11 @@ set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.vhd
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll4.qip
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb -library work
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
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@@ -737,7 +737,7 @@ DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS
BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2);
FIFO_ROW_ADR <= std_logic_vector(VIDEO_ADR_CNT(22 downto 10)); FIFO_ROW_ADR <= std_logic_vector(VIDEO_ADR_CNT(22 downto 10));
FIFO_BA <= std_logic_vector(VIDEO_ADR_CNT)(9 downto 8); FIFO_BA <= std_logic_vector(VIDEO_ADR_CNT(9 downto 8));
FIFO_COL_ADR <= VIDEO_ADR_CNT(7 downto 0) & "00"; FIFO_COL_ADR <= VIDEO_ADR_CNT(7 downto 0) & "00";
VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D; VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D;

3
vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
View File

@@ -765,7 +765,8 @@ begin
VDP_OUT <= BLITTER_DOUT(63 downto 0) when "11", VDP_OUT <= BLITTER_DOUT(63 downto 0) when "11",
BLITTER_DOUT(127 downto 64) when "10", BLITTER_DOUT(127 downto 64) when "10",
FB_DDR(63 downto 0) when "01", FB_DDR(63 downto 0) when "01",
FB_DDR(127 downto 64) when "00"; FB_DDR(127 downto 64) when "00",
(others => 'Z') when others;
VD_EN_I <= SR_DDR_WR or DDR_WR; VD_EN_I <= SR_DDR_WR or DDR_WR;

2
vhdl/rtl/vhdl/Firebee_V1/altpll4.qip
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@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1" set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll4.vhd"] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll4.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]

8
vhdl/rtl/vhdl/Firebee_V1/altpll4.vhd
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@@ -14,7 +14,7 @@
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition -- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************ -- ************************************************************
@@ -209,7 +209,7 @@ BEGIN
port_extclk3 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF", self_reset_on_loss_lock => "OFF",
width_clock => 5, width_clock => 5,
scan_chain_mif_file => "altpll4.mif" scan_chain_mif_file => "../../../backend/Altera/Firebee/altpll4.mif"
) )
PORT MAP ( PORT MAP (
areset => areset, areset => areset,
@@ -292,7 +292,7 @@ END SYN;
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "../../../backend/Altera/Firebee/altpll4.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
@@ -365,7 +365,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif" -- Retrieval info: CONSTANT: scan_chain_mif_file STRING "../../../backend/Altera/Firebee/altpll4.mif"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"

1086
vhdl/rtl/vhdl/Video/Video_Top.vhd
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File diff suppressed because it is too large Load Diff

90
vhdl/testbenches/ddr_ctlr_tb.vhd
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@@ -1,3 +1,6 @@
library work;
use work.firebee_pkg.all;
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@@ -10,8 +13,45 @@ architecture beh of ddr_ctlr_tb is
signal clock_33 : std_logic := '0'; -- 33 MHz clock signal clock_33 : std_logic := '0'; -- 33 MHz clock
signal ddr_clk : std_logic := '0'; -- ddr clock signal ddr_clk : std_logic := '0'; -- ddr clock
signal vec : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; signal FB_ADR : std_logic_vector(31 downto 0);
signal o : std_logic_vector(31 downto 0); signal DDR_SYNC_66M : std_logic;
signal FB_CS1n : std_logic;
signal FB_OEn : std_logic;
signal FB_SIZE0 : std_logic;
signal FB_SIZE1 : std_logic;
signal FB_ALE : std_logic;
signal FB_WRn : std_logic;
signal FIFO_CLR : std_logic;
signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0);
signal BLITTER_ADR : std_logic_vector(31 downto 0);
signal BLITTER_SIG : std_logic;
signal BLITTER_WR : std_logic;
signal DDRCLK0 : std_logic;
signal CLK_33M : std_logic;
signal FIFO_MW : std_logic_vector(8 downto 0);
signal VA : std_logic_vector(12 downto 0);
signal VWEn : std_logic;
signal VRASn : std_logic;
signal VCSn : std_logic;
signal VCKE : std_logic;
signal VCASn : std_logic;
signal FB_LE : std_logic_vector(3 downto 0);
signal FB_VDOE : std_logic_vector(3 downto 0);
signal SR_FIFO_WRE : std_logic;
signal SR_DDR_FB : std_logic;
signal SR_DDR_WR : std_logic;
signal SR_DDRWR_D_SEL: std_logic;
signal SR_VDMP : std_logic_vector(7 downto 0);
signal VIDEO_DDR_TA : std_logic;
signal SR_BLITTER_DACK : std_logic;
signal BA : std_logic_vector(1 downto 0);
signal DDRWR_D_SEL1 : std_logic;
signal VDM_SEL : std_logic_vector(3 downto 0);
signal DATA_IN : std_logic_vector(31 downto 0);
signal DATA_OUT : std_logic_vector(31 downto 16);
signal DATA_EN_H : std_logic;
signal DATA_EN_L : std_logic;
component DDR_CTRL_V1 component DDR_CTRL_V1
port( port(
CLK_MAIN : in std_logic; CLK_MAIN : in std_logic;
@@ -60,8 +100,44 @@ begin
port map port map
( (
CLK_MAIN => clock, CLK_MAIN => clock,
vec_in => vec, DDR_SYNC_66M => DDR_SYNC_66M,
vec_out => o FB_ADR => FB_ADR,
FB_CS1n => FB_CS1n,
FB_OEn => FB_OEn,
FB_SIZE0 => FB_SIZE0,
FB_SIZE1 => FB_SIZE1,
FB_ALE => FB_ALE,
FB_WRn => FB_WRn,
FIFO_CLR => FIFO_CLR,
VIDEO_RAM_CTR => VIDEO_RAM_CTR,
BLITTER_ADR => BLITTER_ADR,
BLITTER_SIG => BLITTER_SIG,
BLITTER_WR => BLITTER_WR,
DDRCLK0 => DDRCLK0,
CLK_33M => CLK_33M,
FIFO_MW => FIFO_MW,
VA => VA,
VWEn => VWEn,
VRASn => VRASn,
VCSn => VCSn,
VCKE => VCKE,
VCASn => VCASn,
FB_LE => FB_LE,
FB_VDOE => FB_VDOE,
SR_FIFO_WRE => SR_FIFO_WRE,
SR_DDR_FB => SR_DDR_FB,
SR_DDR_WR => SR_DDR_WR,
SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
SR_VDMP => SR_VDMP,
VIDEO_DDR_TA => VIDEO_DDR_TA,
SR_BLITTER_DACK => SR_BLITTER_DACK,
BA => BA,
DDRWR_D_SEL1 => DDRWR_D_SEL1,
VDM_SEL => VDM_SEL,
DATA_IN => DATA_IN,
DATA_OUT => DATA_OUT,
DATA_EN_H => DATA_EN_H,
DATA_EN_L => DATA_EN_L
); );
stimulate_clock : process stimulate_clock : process
@@ -72,11 +148,11 @@ begin
stimulate : process stimulate : process
begin begin
vec <= "00000000000000000000000000000001"; FB_ADR <= "00000000000000000000000000000001";
wait for 20 ps; wait for 20 ps;
vec <= "10000000000000000000000000000000"; FB_ADR <= "10000000000000000000000000000000";
wait for 20 ps; wait for 20 ps;
vec <= "00000000000000000000000000000101"; FB_ADR <= "00000000000000000000000000000101";
wait for 20 ps; wait for 20 ps;
end process; end process;
end beh; end beh;