added more constraints

makes it basically working, but still some pixel errors

DSP/DSP.vhd

@@ -1,18 +1,18 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
+-- WARNING: Do NOT edit the input AND output ports in this file in a text
 -- editor if you plan to continue editing the block that represents it in
 -- the Block Editor! File corruption is VERY likely to occur.
 
 -- Copyright (C) 1991-2008 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
+-- AND other software AND tools, AND its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
+-- functions, AND any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
+-- (including device programming or simulation files), AND any 
 -- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
+-- to the terms AND conditions of the Altera Program License 
 -- Subscription Agreement, Altera MegaCore Function License 
 -- Agreement, or other applicable license agreement, including, 
 -- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
+-- programming logic devices manufactured by Altera AND sold by 
 -- Altera or its authorized distributors.  Please refer to the 
 -- applicable agreement for further details.
 
@@ -21,59 +21,57 @@
 -- Created on Tue Sep 08 16:24:57 2009
 
 LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+    USE ieee.std_logic_1164.all;
 
 
 --  Entity Declaration
 
-ENTITY DSP IS
+ENTITY dsp IS
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 	PORT
 	(
-		CLK33M : IN STD_LOGIC;
+		CLK33M      : IN std_logic;
-		MAIN_CLK : IN STD_LOGIC;
+		MAIN_CLK    : IN std_logic;
-		nFB_OE : IN STD_LOGIC;
+		nFB_OE      : IN std_logic;
-		nFB_WR : IN STD_LOGIC;
+		nFB_WR      : IN std_logic;
-		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS1     : IN std_logic;
-		nFB_CS2 : IN STD_LOGIC;
+		nFB_CS2     : IN std_logic;
-		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE0    : IN std_logic;
-		FB_SIZE1 : IN STD_LOGIC;
+		FB_SIZE1    : IN std_logic;
-		nFB_BURST : IN STD_LOGIC;
+		nFB_BURST   : IN std_logic;
-		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		FB_ADR      : IN std_logic_vector(31 DOWNTO 0);
-		nRSTO : IN STD_LOGIC;
+		nRSTO       : IN std_logic;
-		nFB_CS3 : IN STD_LOGIC;
+		nFB_CS3     : IN std_logic;
-		nSRCS : INOUT STD_LOGIC;
+		nSRCS       : INOUT std_logic;
-		nSRBLE : OUT STD_LOGIC;
+		nSRBLE      : OUT std_logic;
-		nSRBHE : OUT STD_LOGIC;
+		nSRBHE      : OUT std_logic;
-		nSRWE : OUT STD_LOGIC;
+		nSRWE       : OUT std_logic;
-		nSROE : OUT STD_LOGIC;
+		nSROE       : OUT std_logic;
-		DSP_INT : OUT STD_LOGIC;
+		DSP_INT     : OUT std_logic;
-		DSP_TA : OUT STD_LOGIC;
+		DSP_TA      : OUT std_logic;
-		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		FB_AD       : INOUT std_logic_vector(31 DOWNTO 0);
-		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
+		IO          : INOUT std_logic_vector(17 DOWNTO 0);
-		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
+		SRD         : INOUT std_logic_vector(15 DOWNTO 0)
 	);
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 	
-END DSP;
+END dsp;
 
 
 --  Architecture Body
 
-ARCHITECTURE DSP_architecture OF DSP IS
+ARCHITECTURE rtl OF dsp IS
 
 	
 BEGIN
-	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
+	nSRCS  <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1';	--nFB_CS3;
-	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
+	nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1';
-	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
+	nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; 
-	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
+	nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1';
-	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
+	nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1';
 	DSP_INT <= '0';
 	DSP_TA <= '0';
-	IO(17 downto 0) <= FB_ADR(18 downto 1);
+	IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1);
-	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ";
-	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ";
-	
+END rtl;
-	
-END DSP_architecture;

FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd

@@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
 component WF2149IP_WAVE
 	port(
 		RESETn		: in bit;
-		SYS_CLK		: in bit;
+		SYS_CLK		: in std_logic;
 
 		WAV_STRB	: in bit;
 

FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd

@@ -76,130 +76,130 @@
 --   Minor changes.
 --
 
-library ieee;
+LIBRARY ieee;
-use ieee.std_logic_1164.all;
+    USE ieee.std_logic_1164.ALL;
-use work.wf2149ip_pkg.all;
+    USE work.wf2149ip_pkg.ALL;
 
-entity WF2149IP_TOP_SOC is
+ENTITY WF2149IP_TOP_SOC IS
-	port(
+	PORT(
 		
-		SYS_CLK		: in bit; -- Read the inforation in the header!
+		SYS_CLK		: IN std_logic; -- Read the inforation in the header!
-		RESETn   	: in bit;
+		RESETn   	: IN bit;
 
-		WAV_CLK		: in bit; -- Read the inforation in the header!
+		WAV_CLK		: IN bit; -- Read the inforation in the header!
-		SELn		: in bit;
+		SELn		: IN bit;
 		
-		BDIR		: in bit;
+		BDIR		: IN bit;
-		BC2, BC1	: in bit;
+		BC2, BC1	: IN bit;
 
-		A9n, A8		: in bit;
+		A9n, A8		: IN bit;
-		DA_IN		: in std_logic_vector(7 downto 0);
+		DA_IN		: IN std_logic_vector(7 DOWNTO 0);
-		DA_OUT		: out std_logic_vector(7 downto 0);
+		DA_OUT		: OUT std_logic_vector(7 DOWNTO 0);
-		DA_EN		: out bit;
+		DA_EN		: OUT bit;
 		
-		IO_A_IN		: in bit_vector(7 downto 0);
+		IO_A_IN		: IN bit_vector(7 DOWNTO 0);
-		IO_A_OUT	: out bit_vector(7 downto 0);
+		IO_A_OUT	: OUT bit_vector(7 DOWNTO 0);
-		IO_A_EN		: out bit;
+		IO_A_EN		: OUT bit;
-		IO_B_IN		: in bit_vector(7 downto 0);
+		IO_B_IN		: IN bit_vector(7 DOWNTO 0);
-		IO_B_OUT	: out bit_vector(7 downto 0);
+		IO_B_OUT	: OUT bit_vector(7 DOWNTO 0);
-		IO_B_EN		: out bit;
+		IO_B_EN		: OUT bit;
 
-		OUT_A		: out bit; -- Analog (PWM) outputs.
+		OUT_A		: OUT bit; -- Analog (PWM) outputs.
-		OUT_B		: out bit;
+		OUT_B		: OUT bit;
-		OUT_C		: out bit
+		OUT_C		: OUT bit
 	);
-end WF2149IP_TOP_SOC;
+END WF2149IP_TOP_SOC;
 
-architecture STRUCTURE of WF2149IP_TOP_SOC is
+ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS
-signal BUSCYCLE		: BUSCYCLES;
+    SIGNAL BUSCYCLE		: BUSCYCLES;
-signal DATA_OUT_I	: std_logic_vector(7 downto 0);
+    SIGNAL DATA_OUT_I	: std_logic_vector(7 DOWNTO 0);
-signal DATA_EN_I	: bit;
+    SIGNAL DATA_EN_I	: bit;
-signal WAV_STRB		: bit;
+    SIGNAL WAV_STRB		: bit;
-signal ADR_I		: bit_vector(3 downto 0);
+    SIGNAL ADR_I		: bit_vector(3 DOWNTO 0);
-signal CTRL_REG		: bit_vector(7 downto 0);
+    SIGNAL CTRL_REG		: bit_vector(7 DOWNTO 0);
-signal PORT_A		: bit_vector(7 downto 0);
+    SIGNAL PORT_A		: bit_vector(7 DOWNTO 0);
-signal PORT_B		: bit_vector(7 downto 0);
+    SIGNAL PORT_B		: bit_vector(7 DOWNTO 0);
-  SIGNAL bsel : bit_vector(2 DOWNTO 0);
+BEGIN
-begin
+	P_WAVSTRB: PROCESS(RESETn, SYS_CLK)
-	P_WAVSTRB: process(RESETn, SYS_CLK)
+        VARIABLE LOCK	: boolean;
-	variable LOCK	: boolean;
+        VARIABLE TMP	: bit;
-	variable TMP	: bit;
+	BEGIN
-	begin
+		IF RESETn = '0' THEN
-		if RESETn = '0' then
 			LOCK := false;
 			TMP := '0';
-		elsif SYS_CLK = '1' and SYS_CLK' event then
+		ELSIF rising_edge(SYS_CLK) THEN
-			if WAV_CLK = '1' and LOCK = false then
+			IF WAV_CLK = '1' and LOCK = false THEN
 				LOCK := true;
 				TMP := not TMP; -- Divider by 2.
-				case SELn is
+				
-					when '1' 	=> WAV_STRB <= '1';
+                CASE SELn IS
-					when others => WAV_STRB <= TMP;
+					WHEN '1' 	=> WAV_STRB <= '1';
-				end case;
+					WHEN OTHERS => WAV_STRB <= TMP;
-			elsif WAV_CLK = '0' then
+				END CASE;
+			ELSIF WAV_CLK = '0' THEN
 				LOCK := false;
 				WAV_STRB <= '0';
-			else
+			ELSE
 				WAV_STRB <= '0';
-			end if;
+			END IF;
-		end if;
+		END IF;
-	end process P_WAVSTRB;		
+	END PROCESS P_WAVSTRB;		
-  bsel <= bdir & bc2 & bc1;
-	with bsel select
-		BUSCYCLE <= INACTIVE	when "000" | "010" | "101",
-					ADDRESS 	when "001" | "100" | "111",
-					R_READ 		when "011",
-					R_WRITE 	when "110";
 
-	ADDRESSLATCH: process(RESETn, SYS_CLK)
+	WITH BDIR & BC2 & BC1 SELECT
+		BUSCYCLE <= INACTIVE	WHEN "000" | "010" | "101",
+					ADDRESS 	WHEN "001" | "100" | "111",
+					R_READ 		WHEN "011",
+					R_WRITE 	WHEN "110";
+
+	ADDRESSLATCH: PROCESS(RESETn, SYS_CLK)
 	-- This process is responsible to store the desired register
 	-- address. The default (after reset) is channel A fine tone 
 	-- adjustment.
-	begin
+	BEGIN
-		if RESETn = '0' then
+		IF RESETn = '0' THEN
-			ADR_I <= (others => '0');
+			ADR_I <= (OTHERS => '0');
-        elsif SYS_CLK = '1' and SYS_CLK' event then
+        ELSIF rising_edge(SYS_CLK) THEN
-			if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
+			IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN
-				ADR_I <= To_BitVector(DA_IN(3 downto 0));
+				ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0));
-			end if;
+			END IF;
-		end if;
+		END IF;
-	end process ADDRESSLATCH;	
+	END PROCESS ADDRESSLATCH;	
 
-	P_CTRL_REG: process(RESETn, SYS_CLK)
+	P_CTRL_REG: PROCESS(RESETn, SYS_CLK)
 	-- THIS is the Control register for the mixer and for the I/O ports.
-	begin
+	BEGIN
-		if RESETn = '0' then
+		IF RESETn = '0' THEN
 			CTRL_REG <= x"00";
-		elsif SYS_CLK = '1' and SYS_CLK' event then
+		ELSIF rising_edge(SYS_CLK) THEN
-			if BUSCYCLE = R_WRITE and ADR_I = x"7" then
+			IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN
 				CTRL_REG <= To_BitVector(DA_IN);
-			end if;
+			END IF;
-		end if;
+		END IF;
-	end process P_CTRL_REG;
+	END PROCESS P_CTRL_REG;
 	
-	DIG_PORTS: process(RESETn, SYS_CLK)
+	DIG_PORTS: PROCESS(RESETn, SYS_CLK)
-	begin
+	BEGIN
-		if RESETn = '0' then
+		IF RESETn = '0' THEN
 			PORT_A <= x"00";
 			PORT_B <= x"00";
-		elsif SYS_CLK = '1' and SYS_CLK' event then
+		ELSIF rising_edge(SYS_CLK) THEN
-			if BUSCYCLE = R_WRITE and ADR_I = x"E" then
+			IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN
 				PORT_A <= To_BitVector(DA_IN);
-			elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
+			ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN
 				PORT_B <= To_BitVector(DA_IN);
-			end if;
+			END IF;
-		end if;	
+		END IF;	
-	end process DIG_PORTS;
+	END PROCESS DIG_PORTS;
 	-- Set port direction to input or to output:
-	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';
+	IO_A_EN	<= '1' WHEN CTRL_REG(6) = '1' ELSE '0';
-	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
+	IO_B_EN <= '1' WHEN CTRL_REG(7) = '1' ELSE '0';
 	IO_A_OUT <= PORT_A;
 	IO_B_OUT <= PORT_B;
 
 	I_PSG_WAVE: WF2149IP_WAVE
-		port map(
+		PORT MAP(
 			RESETn		=> RESETn,
-			SYS_CLK	=> SYS_CLK,
+			SYS_CLK	    => SYS_CLK,
 
 			WAV_STRB	=> WAV_STRB,
 
@@ -209,7 +209,7 @@ begin
 			DATA_EN		=> DATA_EN_I,
 			
 			BUSCYCLE	=> BUSCYCLE,
-			CTRL_REG	=> CTRL_REG(5 downto 0),
+			CTRL_REG	=> CTRL_REG(5 DOWNTO 0),
 						
 			OUT_A		=> OUT_A,
 			OUT_B		=> OUT_B,
@@ -217,14 +217,14 @@ begin
 		);
 
 	-- Read the ports and registers:
-	DA_EN <= 	'1' when DATA_EN_I = '1' else
+	DA_EN <= 	'1' WHEN DATA_EN_I = '1' ELSE
-				'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
+				'1' WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE
-				'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
+				'1' WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE
-				'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
+				'1' WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE '0';
 				
-	DA_OUT <= 	DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
+	DA_OUT <= 	DATA_OUT_I WHEN DATA_EN_I = '1' ELSE -- WAV stuff.
-				To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
+				To_StdLogicVector(IO_A_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE
-				To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
+				To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE
-				To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
+				To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0');
 
-end STRUCTURE;
+END rtl;

FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd

@@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all;
 entity WF2149IP_WAVE is
 	port(
 		RESETn		: in bit;
-		SYS_CLK		: in bit;
+		SYS_CLK		: in std_logic;
 
 		WAV_STRB	: in bit;
 

FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd

@@ -60,8 +60,8 @@
 --
 
 library ieee;
-use ieee.std_logic_1164.all;
+    use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+    use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_TOP_SOC is
   port (

Interrupt_Handler/interrupt_handler.tdf

@@ -17,64 +17,64 @@ INCLUDE "lpm_bustri_BYT.inc";
 SUBDESIGN interrupt_handler
 (
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	MAIN_CLK : INPUT;
+	MAIN_CLK            : INPUT;
-	nFB_WR : INPUT;
+	nFB_WR              : INPUT;
-	nFB_CS1 : INPUT;
+	nFB_CS1             : INPUT;
-	nFB_CS2 : INPUT;
+	nFB_CS2             : INPUT;
-	FB_SIZE0 : INPUT;
+	FB_SIZE0            : INPUT;
-	FB_SIZE1 : INPUT;
+	FB_SIZE1            : INPUT;
-	FB_ADR[31..0] : INPUT;
+	FB_ADR[31..0]       : INPUT;
-	PIC_INT : INPUT;
+	PIC_INT             : INPUT;
-	E0_INT : INPUT;
+	E0_INT              : INPUT;
-	DVI_INT : INPUT;
+	DVI_INT             : INPUT;
-	nPCI_INTA : INPUT;
+	nPCI_INTA           : INPUT;
-	nPCI_INTB : INPUT;
+	nPCI_INTB           : INPUT;
-	nPCI_INTC : INPUT;
+	nPCI_INTC           : INPUT;
-	nPCI_INTD : INPUT;
+	nPCI_INTD           : INPUT;
-	nMFP_INT : INPUT;
+	nMFP_INT            : INPUT;
-	nFB_OE : INPUT;
+	nFB_OE              : INPUT;
-	DSP_INT : INPUT;
+	DSP_INT             : INPUT;
-	VSYNC : INPUT;
+	VSYNC               : INPUT;
-	HSYNC : INPUT;
+	HSYNC               : INPUT;
-	DMA_DRQ : INPUT;
+	DMA_DRQ             : INPUT;
-	nIRQ[7..2] : OUTPUT;
+	nIRQ[7..2]          : OUTPUT;
-	INT_HANDLER_TA : OUTPUT;
+	INT_HANDLER_TA      : OUTPUT;
-	ACP_CONF[31..0] : OUTPUT;
+	ACP_CONF[31..0]     : OUTPUT;
-	TIN0 : OUTPUT;
+	TIN0                : OUTPUT;
-	FB_AD[31..0] : BIDIR;
+	FB_AD[31..0]        : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
 
 VARIABLE
-	FB_B[3..0]				:NODE;
+	FB_B[3..0]				    :NODE;
-	INT_CTR[31..0]			:DFFE;
+	INT_CTR[31..0]			    :DFFE;
-	INT_CTR_CS				:NODE;
+	INT_CTR_CS				    :NODE;
-	INT_LATCH[31..0]		:DFF;
+	INT_LATCH[31..0]		    :DFF;
-	INT_LATCH_CS			:NODE;
+	INT_LATCH_CS			    :NODE;
-	INT_CLEAR[31..0]		:DFF;
+	INT_CLEAR[31..0]		    :DFF;
-	INT_CLEAR_CS			:NODE;
+	INT_CLEAR_CS			    :NODE;
-	INT_IN[31..0]			:NODE;
+	INT_IN[31..0]			    :NODE;
-	INT_ENA[31..0]			:DFFE;
+	INT_ENA[31..0]			    :DFFE;
-	INT_ENA_CS				:NODE;
+	INT_ENA_CS				    :NODE;
-	ACP_CONF[31..0]			:DFFE;
+	ACP_CONF[31..0]			    :DFFE;
-	ACP_CONF_CS				:NODE;
+	ACP_CONF_CS				    :NODE;
-	PSEUDO_BUS_ERROR		:NODE;
+	PSEUDO_BUS_ERROR		    :NODE;
-	UHR_AS					:NODE;
+	UHR_AS					    :NODE;
-	UHR_DS					:NODE;
+	UHR_DS					    :NODE;
-	RTC_ADR[5..0]			:DFFE;
+	RTC_ADR[5..0]			    :DFFE;
-	ACHTELSEKUNDEN[2..0]	:DFFE;
+	ACHTELSEKUNDEN[2..0]	    :DFFE;
-	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
+	WERTE[7..0][63..0]		    :DFFE;			-- WERTE REGISTER 0-63
-	PIC_INT_SYNC[2..0]		:DFF;
+	PIC_INT_SYNC[2..0]		    :DFF;
-	INC_SEC					:NODE;
+	INC_SEC					    :NODE;
-	INC_MIN					:NODE;
+	INC_MIN					    :NODE;
-	INC_STD					:NODE;
+	INC_STD					    :NODE;
-	INC_TAG					:NODE;
+	INC_TAG					    :NODE;
 	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
-	WINTERZEIT				:NODE;
+	WINTERZEIT				    :NODE;
-	SOMMERZEIT				:NODE;
+	SOMMERZEIT				    :NODE;
-	INC_MONAT				:NODE;
+	INC_MONAT				    :NODE;
-	INC_JAHR				:NODE;
+	INC_JAHR				    :NODE;
-	UPDATE_ON				:NODE;
+	UPDATE_ON				    :NODE;
 	
 BEGIN
 -- BYT SELECT
@@ -91,7 +91,7 @@ BEGIN
 		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
 		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
 
--- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
+-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
 	INT_CTR[].CLK = MAIN_CLK;
 	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
 	INT_CTR[] = FB_AD[];
@@ -99,6 +99,7 @@ BEGIN
 	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
 	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
 	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
+    
 -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
 	INT_ENA[].CLK = MAIN_CLK;
 	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
@@ -107,6 +108,7 @@ BEGIN
 	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
 	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
 	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
+    
 -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
 	INT_CLEAR[].CLK = MAIN_CLK;
 	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
@@ -114,8 +116,10 @@ BEGIN
 	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
 	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
 	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
+    
 -- INTERRUPT LATCH REGISTER READ ONLY
 	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
+    
 -- INTERRUPT
 	!nIRQ2 = HSYNC 						& INT_ENA[26];
 	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
@@ -139,6 +143,7 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
 							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
 							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
 							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+                            
 -- IF VIDEO ADR CHANGE
 TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
 
@@ -176,6 +181,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	INT_IN29 = INT_LATCH[]!=H"00000000";
 	INT_IN30 = !nMFP_INT; 
 	INT_IN31 = DMA_DRQ; 
+    
 --***************************************************************************************
 -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
 	ACP_CONF[].CLK = MAIN_CLK;
@@ -324,9 +330,12 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
 	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
 	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
-	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	
+    PIC_INT_SYNC[].CLK = MAIN_CLK;
+    PIC_INT_SYNC[0] = PIC_INT;
 	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
 	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
+    
 	UPDATE_ON = !WERTE[7][11];		
 	WERTE[6][10].CLRN = GND;	-- KEIN UIP
 	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
@@ -334,48 +343,57 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
 	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
 	WERTE[7][13] = VCC;	-- IMMER RICHTIG
--- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
+    
+-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
 	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
 	WERTE[0][13] = SOMMERZEIT;
 	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
 	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
+    
 -- ACHTELSEKUNDEN
 	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
 	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
 	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
+    
 -- SEKUNDEN
 	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
-	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN Z<>HLEN BIS 59
+	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN Z<>HLEN BIS 59
 	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
+    
 -- MINUTEN
 	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
-	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN Z<>HLEN BIS 59
+	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN Z<>HLEN BIS 59
 	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
+    
 -- STUNDEN
 	INC_STD = INC_MIN & WERTE[][2]==59;							  
-	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN Z<>HLEN BIS 23
+	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN Z<>HLEN BIS 23
 	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
 -- WOCHENTAG UND TAG 
+
 	INC_TAG = INC_STD & WERTE[][2]==23;						
-	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG Z<>HLEN BIS 7
+	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG Z<>HLEN BIS 7
 			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
 	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
 	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
 							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
 							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
 							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
-	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG Z<>HLEN BIS MONATSENDE
+	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG Z<>HLEN BIS MONATSENDE
 			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
 	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
+
 -- MONATE
 	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
-	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE Z<>HLEN BIS 12
+	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE Z<>HLEN BIS 12
 			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
 	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
+    
 -- JAHR		   
 	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
-	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE Z<>HLEN BIS 99
+	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE Z<>HLEN BIS 99
 	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
+    
 -- TRISTATE OUTPUT
 
 	FB_AD[31..24] = lpm_bustri_BYT(
@@ -457,6 +475,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 				 # INT_CLEAR_CS & INT_IN[23..16]
 				 # ACP_CONF_CS  & ACP_CONF[23..16]
 				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+                  
 	FB_AD[15..8] = lpm_bustri_BYT(
 					INT_CTR_CS   & INT_CTR[15..8] 
 				  #	INT_ENA_CS   & INT_ENA[15..8]
@@ -464,6 +483,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 				  # INT_CLEAR_CS & INT_IN[15..8]
 				  # ACP_CONF_CS  & ACP_CONF[15..8]
 				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+                  
 	FB_AD[7..0] = lpm_bustri_BYT(
 					INT_CTR_CS   & INT_CTR[7..0] 
 				  #	INT_ENA_CS   & INT_ENA[7..0]

Video/BLITTER/BLITTER.vhd

@@ -26,7 +26,7 @@ USE ieee.std_logic_1164.all;
 
 --  Entity Declaration
 
-ENTITY BLITTER IS
+ENTITY blitter IS
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 	PORT
 	(
@@ -61,7 +61,7 @@ END BLITTER;
 
 --  Architecture Body
 
-ARCHITECTURE BLITTER_architecture OF BLITTER IS
+ARCHITECTURE BLITTER_architecture OF blitter IS
 
 	
 BEGIN

Video/DDR_CTR.tdf

@@ -58,9 +58,9 @@ SUBDESIGN DDR_CTR
 )
 
 VARIABLE
-	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3);	
-	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+	DDR_SM					:MACHINE WITH STATES(DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8,				-- START (NORMAL 8 CYCLES TOTAL = 60ns)
-													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+													    DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, 	 					-- CONFIG 
 												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
 												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
 												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
@@ -129,7 +129,8 @@ VARIABLE
 	
 BEGIN
 	LINE =  FB_SIZE0 &  FB_SIZE1;
--- BYT SELECT
+
+    -- BYT SELECT
 	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
 	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
@@ -140,7 +141,8 @@ BEGIN
 	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
 		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+
+    -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
 	FB_REGDDR.CLK = MAIN_CLK;
 	CASE FB_REGDDR IS
 		WHEN FR_WAIT => 
@@ -198,7 +200,8 @@ BEGIN
 				FB_REGDDR = FR_WAIT;
 			END IF;
 	END CASE;
--- DDR STEUERUNG -----------------------------------------------------
+
+    -- DDR STEUERUNG -----------------------------------------------------
 -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
 	VCKE = VIDEO_RAM_CTR0;
 	nVCS = !VIDEO_RAM_CTR1;
@@ -220,34 +223,39 @@ BEGIN
 	FIFO_AC.CLK = DDRCLK0;
 	BLITTER_AC.CLK = DDRCLK0;
 	DDRWR_D_SEL1 = BLITTER_AC;
--- SELECT LOGIC
+
+    -- SELECT LOGIC
 	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
 	DDR_CS.CLK = MAIN_CLK;
 	DDR_CS.ENA = FB_ALE;
 	DDR_CS	 = DDR_SEL;
--- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
+
+    -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
 	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
 			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
-			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SP<53>TER
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SP<53>TER
 	CPU_REQ.CLK = DDR_SYNC_66M;
 	CPU_REQ = CPU_SIG 
 			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
 	BUS_CYC.CLK = DDRCLK0;
 	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+    
 	-- STATE MACHINE SYNCHRONISIEREN -----------------
 	MCS[].CLK = DDRCLK0;
 	MCS0 = MAIN_CLK;
 	MCS1 = MCS0;		
 	CPU_DDR_SYNC.CLK = DDRCLK0;
 	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
-	---------------------------------------------------
+	
+    ---------------------------------------------------
 	VA_S[].CLK = DDRCLK0;
 	BA_S[].CLK = DDRCLK0;
 	VA[] =  VA_S[];
 	BA[] =  BA_S[];
 	VA_P[].CLK = DDRCLK0;
 	BA_P[].CLK = DDRCLK0;
--- DDR STATE MACHINE  -----------------------------------------------
+
+    -- DDR STATE MACHINE  -----------------------------------------------
 	DDR_SM.CLK = DDRCLK0;
 	CASE DDR_SM IS
 		WHEN DS_T1 =>
@@ -336,12 +344,13 @@ BEGIN
 					END IF;
 				END IF;
 			END IF;
--- READ			
+
+        -- READ			
 		WHEN DS_T4R =>
 			CPU_AC = CPU_AC;
 			BLITTER_AC = BLITTER_AC;
 			VCAS = VCC;															
-			SR_DDR_FB = CPU_AC;										-- READ DATEN F<>R CPU
+			SR_DDR_FB = CPU_AC;										-- READ DATEN F<>R CPU
 			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
 			DDR_SM = DS_T5R;	
 			
@@ -357,7 +366,8 @@ BEGIN
 				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
 				DDR_SM = DS_CB6;
 			END IF;
--- WRITE			
+
+        -- WRITE			
 		WHEN DS_T4W =>
 			CPU_AC = CPU_AC;
 			BLITTER_AC = BLITTER_AC;
@@ -383,7 +393,7 @@ BEGIN
 			VCAS = VCC;															
 			VWE  = VCC;
 			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
-			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
+			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
 			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
 			DDR_SM = DS_T7W;
 
@@ -391,7 +401,7 @@ BEGIN
 			CPU_AC = CPU_AC;
 			BLITTER_AC = BLITTER_AC;
 			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
-			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
+			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
 			DDR_SM = DS_T8W;
 
 		WHEN DS_T8W =>								 
@@ -407,7 +417,8 @@ BEGIN
 				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
 				DDR_SM = DS_CB6;
 			END IF;
--- FIFO READ 
+
+        -- FIFO READ 
 		WHEN DS_T4F =>
 			VCAS = VCC;															
 			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
@@ -497,7 +508,8 @@ BEGIN
 				DDR_SM = DS_T7F;
 			END IF;	
 
--- CONFIG CYCLUS
+
+        -- CONFIG CYCLUS
 		WHEN DS_C2 =>
 			DDR_SM = DS_C3;
 		WHEN DS_C3 =>
@@ -520,18 +532,20 @@ BEGIN
 			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
 			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
 			DDR_SM = DS_N8;
--- CLOSE FIFO BANK
+
+        -- CLOSE FIFO BANK
 		WHEN DS_CB6 =>
 			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- B<>NKE SCHLIESSEN
+			VRAS = VCC;									-- B<>NKE SCHLIESSEN
 			VWE = VCC;
 			DDR_SM = DS_N7;
 		WHEN DS_CB8 =>
 			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- B<>NKE SCHLIESSEN
+			VRAS = VCC;									-- B<>NKE SCHLIESSEN
 			VWE = VCC;
 			DDR_SM = DS_T1;
--- REFRESH 70NS = 10 ZYCLEN
+
+        -- REFRESH 70NS = 10 ZYCLEN
 		WHEN DS_R2 =>
 			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
 				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
@@ -552,7 +566,8 @@ BEGIN
 			DDR_SM = DS_R6;
 		WHEN DS_R6 =>
 			DDR_SM = DS_N5;
--- LEERSCHLAUFE			
+
+        -- LEERSCHLAUFE			
 		WHEN DS_N5 =>
 			DDR_SM = DS_N6;
 		WHEN DS_N6 =>
@@ -584,14 +599,14 @@ BEGIN
 	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
 	FIFO_BANK_OK.CLK = DDRCLK0;
 	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-	-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
+	-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
 	CLR_FIFO_SYNC.CLK =DDRCLK0;
 	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
 	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
 	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
 	STOP.CLK = DDRCLK0;
 	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-	-- Z<>HLEN -----------------------------------------------
+	-- Z<>HLEN -----------------------------------------------
 	VIDEO_ADR_CNT[].CLK = DDRCLK0;
 	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
 	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
@@ -608,12 +623,12 @@ BEGIN
 -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
 -----------------------------------------------------------------------------------------
 	DDR_REFRESH_CNT[].CLK = CLK33M;
-	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- Z<>HLEN 0-2047 
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- Z<>HLEN 0-2047 
 	REFRESH_TIME.CLK = DDRCLK0;
 	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
 	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
 	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
-	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
 					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
 	DDR_REFRESH_REQ.CLK = DDRCLK0;
 	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;

Video/VIDEO_MOD_MUX_CLUTCTR.tdf

@@ -1,4 +1,4 @@
-TITLE "VIDEO MODUSE UND CLUT CONTROL";
+TITLE "VIDEO MODI AND CLUT CONTROL";
 
 -- CREATED BY FREDI ASCHWANDEN
 
@@ -8,58 +8,58 @@ INCLUDE "lpm_bustri_BYT.inc";
 -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
 -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
 
-SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+SUBDESIGN video_mod_mux_clutctr
 (
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
+	nRSTO                   : INPUT;
-	MAIN_CLK : INPUT;
+	MAIN_CLK                : INPUT;
-	nFB_CS1 : INPUT;
+	nFB_CS1                 : INPUT;
-	nFB_CS2 : INPUT;
+	nFB_CS2                 : INPUT;
-	nFB_CS3 : INPUT;
+	nFB_CS3                 : INPUT;
-	nFB_WR : INPUT;
+	nFB_WR                  : INPUT;
-	nFB_OE : INPUT;
+	nFB_OE                  : INPUT;
-	FB_SIZE0 : INPUT;
+	FB_SIZE0                : INPUT;
-	FB_SIZE1 : INPUT;
+	FB_SIZE1                : INPUT;
-	nFB_BURST : INPUT;
+	nFB_BURST               : INPUT;
-	FB_ADR[31..0] : INPUT;
+	FB_ADR[31..0]           : INPUT;
-	CLK33M : INPUT;
+	CLK33M                  : INPUT;
-	CLK25M : INPUT;
+	CLK25M                  : INPUT;
-	BLITTER_RUN : INPUT;
+	BLITTER_RUN             : INPUT;
-	CLK_VIDEO : INPUT;
+	CLK_VIDEO               : INPUT;
-	VR_D[8..0] : INPUT;
+	VR_D[8..0]              : INPUT;
-	VR_BUSY : INPUT;
+	VR_BUSY                 : INPUT;
-	COLOR8 : OUTPUT;
+	COLOR8                  : OUTPUT;
-	ACP_CLUT_RD : OUTPUT;
+	ACP_CLUT_RD             : OUTPUT;
-	COLOR1 : OUTPUT;
+	COLOR1                  : OUTPUT;
-	FALCON_CLUT_RDH : OUTPUT;
+	FALCON_CLUT_RDH         : OUTPUT;
-	FALCON_CLUT_RDL : OUTPUT;
+	FALCON_CLUT_RDL         : OUTPUT;
-	FALCON_CLUT_WR[3..0] : OUTPUT;
+	FALCON_CLUT_WR[3..0]    : OUTPUT;
-	ST_CLUT_RD : OUTPUT;
+	ST_CLUT_RD              : OUTPUT;
-	ST_CLUT_WR[1..0] : OUTPUT;
+	ST_CLUT_WR[1..0]        : OUTPUT;
-	CLUT_MUX_ADR[3..0] : OUTPUT;
+	CLUT_MUX_ADR[3..0]      : OUTPUT;
-	HSYNC : OUTPUT;
+	HSYNC                   : OUTPUT;
-	VSYNC : OUTPUT;
+	VSYNC                   : OUTPUT;
-	nBLANK : OUTPUT;
+	nBLANK                  : OUTPUT;
-	nSYNC : OUTPUT;
+	nSYNC                   : OUTPUT;
-	nPD_VGA : OUTPUT;
+	nPD_VGA                 : OUTPUT;
-	FIFO_RDE : OUTPUT;
+	FIFO_RDE                : OUTPUT;
-	COLOR2 : OUTPUT;
+	COLOR2                  : OUTPUT;
-	COLOR4 : OUTPUT;
+	COLOR4                  : OUTPUT;
-	PIXEL_CLK : OUTPUT;
+	PIXEL_CLK               : OUTPUT;
-	CLUT_OFF[3..0] : OUTPUT;
+	CLUT_OFF[3..0]          : OUTPUT;
-	BLITTER_ON : OUTPUT;
+	BLITTER_ON              : OUTPUT;
-	VIDEO_RAM_CTR[15..0] : OUTPUT;
+	VIDEO_RAM_CTR[15..0]    : OUTPUT;
-	VIDEO_MOD_TA : OUTPUT;
+	VIDEO_MOD_TA            : OUTPUT;
-	CCR[23..0] : OUTPUT;
+	CCR[23..0]              : OUTPUT;
-	CCSEL[2..0] : OUTPUT;
+	CCSEL[2..0]             : OUTPUT;
-	ACP_CLUT_WR[3..0] : OUTPUT;
+	ACP_CLUT_WR[3..0]       : OUTPUT;
-	INTER_ZEI : OUTPUT;
+	INTER_ZEI               : OUTPUT;
-	DOP_FIFO_CLR : OUTPUT;
+	DOP_FIFO_CLR            : OUTPUT;
-	VIDEO_RECONFIG : OUTPUT;
+	VIDEO_RECONFIG          : OUTPUT;
-	VR_WR : OUTPUT;
+	VR_WR                   : OUTPUT;
-	VR_RD : OUTPUT;
+	VR_RD                   : OUTPUT;
-	CLR_FIFO : OUTPUT;
+	CLR_FIFO                : OUTPUT;
-	FB_AD[31..0] : BIDIR;
+	FB_AD[31..0]            : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
 
@@ -98,12 +98,12 @@ VARIABLE
 	VDL_LWD[15..0]				:DFFE;
 	VDL_LWD_CS					:NODE;
 -- DIV. CONTROL REGISTER
-	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	CLUT_TA						:DFF;  			-- needs one wait state
 	HSYNC						:DFF;
 	HSYNC_I[7..0]				:DFF;
-	HSY_LEN[7..0]				:DFF;			-- L<EFBFBD>NGE HSYNC PULS IN PIXEL_CLK
+	HSY_LEN[7..0]				:DFF;			-- length of hsync pulse in pixel_clk
 	HSYNC_START					:DFF;
-	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	LAST						:DFF;			-- reached last pixel of a line
 	VSYNC						:DFF;
 	VSYNC_START					:DFFE;
 	VSYNC_I[2..0]				:DFFE;
@@ -191,60 +191,90 @@ VARIABLE
 	VDL_VCT_CS					:NODE;
 	VDL_VMD[3..0]				:DFFE;
 	VDL_VMD_CS					:NODE;
+    ACP_VCTR6_DUP               : NODE;
 
 BEGIN
--- BYT SELECT 32 BIT
+    -- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B0 = FB_ADR[1..0] == 0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+	FB_B1 = FB_ADR[1..0] == 1								-- ADR==1
 		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+	FB_B2 = FB_ADR[1..0] == 2								-- ADR==2
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+	FB_B3 = FB_ADR[1..0] == 3								-- ADR==3
 		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
+
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+    -- BYT SELECT 16 BIT
-	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+	FB_16B0 = FB_ADR[0] == 0;								-- ADR==0
+	FB_16B1 = FB_ADR[0] == 1								-- ADR==1
 		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
--- ACP CLUT --
+
-	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+    -- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0";		-- 0-3FF/1024
 	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
 	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
-	CLUT_TA.CLK = MAIN_CLK;
+	
+    CLUT_TA.CLK = MAIN_CLK;
 	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
---FALCON CLUT --
+
-	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+    
+    --FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10] == H"3E6";				-- $F9800/$400
 	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
 	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
 	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
 	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
--- ST CLUT --
+
-	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+    
+    -- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5] == H"7C12";					-- $F8240/$20
 	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
 	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
--- ST SHIFT MODE
+
+    
+    -- ST SHIFT MODE
 	ST_SHIFT_MODE[].CLK = MAIN_CLK;
-	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130";			-- $F8260/2
 	ST_SHIFT_MODE[] = FB_AD[25..24];
 	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	
-	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+    COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+	COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
--- FALCON SHIFT MODE
+	COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+
+    
+    -- FALCON SHIFT MODE
 	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
-	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133";			-- $F8266/2
 	FALCON_SHIFT_MODE[] = FB_AD[26..16];
 	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
 	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
-	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	
-	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+    CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	
+    COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
 	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
 	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
 	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+
+    
+    -- ACP VIDEO CONTROL
+    -- BIT 0=ACP VIDEO ON,
+    --     1=POWER ON VIDEO DAC,
+    --     2=ACP 24BIT,
+    --     3=ACP 16BIT,
+    --     4=ACP 8BIT,
+    --     5=ACP 1BIT,
+    --     6=FALCON SHIFT MODE,
+    --     7=ST SHIFT MODE,
+    --     9..8= VCLK FREQUENZ,
+    --     15=-SYNC ALLOWED,
+    --     31..16=VIDEO_RAM_CTR,
+    --     25=RANDFARBE EINSCHALTEN,
+    --     26=STANDARD ATARI SYNCS
 	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100";						-- $400/4
 	ACP_VCTR[31..8] = FB_AD[31..8];
 	ACP_VCTR[5..0] = FB_AD[5..0];
 	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,9 +283,11 @@ BEGIN
 	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
 	ACP_VIDEO_ON = ACP_VCTR0;
 	nPD_VGA = ACP_VCTR1;
-	-- ATARI MODUS
+	
-	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFL<46>SUNG
+    -- ATARI MODUS
-	-- HORIZONTAL TIMING 640x480
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFL<46>SUNG
+	
+    -- HORIZONTAL TIMING 640x480
 	ATARI_HH[].CLK = MAIN_CLK;
 	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
 	ATARI_HH[] = FB_AD[];
@@ -263,7 +295,8 @@ BEGIN
 	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
 	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
 	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 640x480
+	
+    -- VERTIKAL TIMING 640x480
 	ATARI_VH[].CLK = MAIN_CLK;
 	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
 	ATARI_VH[] = FB_AD[];
@@ -271,7 +304,8 @@ BEGIN
 	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
 	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
 	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
-	-- HORIZONTAL TIMING 320x240
+	
+    -- HORIZONTAL TIMING 320x240
 	ATARI_HL[].CLK = MAIN_CLK;
 	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
 	ATARI_HL[] = FB_AD[];
@@ -279,7 +313,8 @@ BEGIN
 	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
 	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
 	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 320x240
+	
+    -- VERTIKAL TIMING 320x240
 	ATARI_VL[].CLK = MAIN_CLK;
 	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
 	ATARI_VL[] = FB_AD[];
@@ -287,7 +322,9 @@ BEGIN
 	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
 	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
 	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
--- VIDEO PLL CONFIG
+
+    
+    -- VIDEO PLL CONFIG
 	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
 	VR_WR.CLK = MAIN_CLK;
 	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
@@ -298,21 +335,28 @@ BEGIN
 	VR_FRQ[].CLK = MAIN_CLK;
 	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
 	VR_FRQ[] = FB_AD[23..16];
--- VIDEO PLL RECONFIG
+
+    -- VIDEO PLL RECONFIG
 	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
 	VIDEO_RECONFIG.CLK = MAIN_CLK;
 	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
-------------------------------------------------------------------------------------------------------------------------
+
+    ------------------------------------------------------------------------------------------------------------------------
 	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
--------------- COLOR MODE IM ACP SETZEN	
+
+    -------------- COLOR MODE IM ACP SETZEN	
 	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
 	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
 	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
 	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
 	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
--- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+
+    -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
 	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+    
+    -- duplicate ACP_VCTR6 according to TimeQuest recommendations
+    ACP_VCTR6_DUP      = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ACP_VCTR6_DUP;
 	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
 	FALCON_VIDEO	   = ACP_VCTR7;
 	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
@@ -325,118 +369,140 @@ BEGIN
 			# B"101" & COLOR16
 			# B"110" & COLOR24
 			# B"111" & RAND_ON;
--- DIVERSE (VIDEO)-REGISTER ----------------------------
+
--- RANDFARBE
+    -- DIVERSE (VIDEO)-REGISTER ----------------------------
+
+    -- RANDFARBE
 	CCR[].CLK = MAIN_CLK;
 	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
 	CCR[] = FB_AD[23..0];
 	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
 	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
 	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
---SYS CTR
+
+    --SYS CTR
 	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
 	SYS_CTR[].CLK = MAIN_CLK;
 	SYS_CTR[6..0] = FB_AD[22..16];
 	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
 	BLITTER_ON = !SYS_CTR3;
---VDL_LOF
+
+    --VDL_LOF
 	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
 	VDL_LOF[].CLK = MAIN_CLK;
 	VDL_LOF[] = FB_AD[31..16];
 	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
 	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
---VDL_LWD
+
+    --VDL_LWD
 	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
 	VDL_LWD[].CLK = MAIN_CLK;
 	VDL_LWD[] = FB_AD[31..16];
 	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
 	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
--- HORIZONTAL
+
--- VDL_HHT
+    -- HORIZONTAL
+
+    -- VDL_HHT
 	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
 	VDL_HHT[].CLK = MAIN_CLK;
 	VDL_HHT[] = FB_AD[27..16];
 	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
 	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
--- VDL_HBE
+
+    -- VDL_HBE
 	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
 	VDL_HBE[].CLK = MAIN_CLK;
 	VDL_HBE[] = FB_AD[27..16];
 	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
 	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
--- VDL_HDB
+
+    -- VDL_HDB
 	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
 	VDL_HDB[].CLK = MAIN_CLK;
 	VDL_HDB[] = FB_AD[27..16];
 	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
 	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
--- VDL_HDE
+
+    -- VDL_HDE
 	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
 	VDL_HDE[].CLK = MAIN_CLK;
 	VDL_HDE[] = FB_AD[27..16];
 	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
 	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
--- VDL_HBB
+
+    -- VDL_HBB
 	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
 	VDL_HBB[].CLK = MAIN_CLK;
 	VDL_HBB[] = FB_AD[27..16];
 	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
 	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
--- VDL_HSS
+
+    -- VDL_HSS
 	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
 	VDL_HSS[].CLK = MAIN_CLK;
 	VDL_HSS[] = FB_AD[27..16];
 	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
 	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
--- VERTIKAL
+
--- VDL_VBE
+    -- VERTIKAL
+
+    -- VDL_VBE
 	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
 	VDL_VBE[].CLK = MAIN_CLK;
 	VDL_VBE[] = FB_AD[26..16];
 	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
 	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
--- VDL_VDB
+
+    -- VDL_VDB
 	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
 	VDL_VDB[].CLK = MAIN_CLK;
 	VDL_VDB[] = FB_AD[26..16];
 	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
 	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
--- VDL_VDE
+
+    -- VDL_VDE
 	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
 	VDL_VDE[].CLK = MAIN_CLK;
 	VDL_VDE[] = FB_AD[26..16];
 	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
 	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
--- VDL_VBB
+
+    -- VDL_VBB
 	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
 	VDL_VBB[].CLK = MAIN_CLK;
 	VDL_VBB[] = FB_AD[26..16];
 	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
 	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
--- VDL_VSS
+
+    -- VDL_VSS
 	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
 	VDL_VSS[].CLK = MAIN_CLK;
 	VDL_VSS[] = FB_AD[26..16];
 	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
 	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
--- VDL_VFT
+
+    -- VDL_VFT
 	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
 	VDL_VFT[].CLK = MAIN_CLK;
 	VDL_VFT[] = FB_AD[26..16];
 	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
 	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
--- VDL_VCT
+
+    -- VDL_VCT
 	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
 	VDL_VCT[].CLK = MAIN_CLK;
 	VDL_VCT[] = FB_AD[24..16];
 	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
 	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
--- VDL_VMD
+
+    -- VDL_VMD
 	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
 	VDL_VMD[].CLK = MAIN_CLK;
 	VDL_VMD[] = FB_AD[19..16];
 	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
---- REGISTER OUT
+
+    --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
 						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
 					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
@@ -484,8 +550,9 @@ BEGIN
 				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
 				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
 	
--- VIDEO AUSGABE SETZEN
+
-	CLK17M.CLK = CLK33M;
+    -- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = MAIN_CLK;
 	CLK17M = !CLK17M;
 	CLK13M.CLK = CLK25M;
 	CLK13M = !CLK13M;
@@ -496,9 +563,10 @@ BEGIN
 			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
 			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
 			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
---------------------------------------------------------------
+
--- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
+    --------------------------------------------------------------
-----------------------------------------------------------------
+    -- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
+    ----------------------------------------------------------------
 	HSY_LEN[].CLK = MAIN_CLK;		
 	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
 			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
@@ -517,14 +585,15 @@ BEGIN
 	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
 			   #  640 & !VDL_VMD2;
 					
--- DOPPELZEILENMODUS
+
+    -- DOPPELZEILENMODUS
 	DOP_ZEI.CLK = MAIN_CLK;
 	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
 	INTER_ZEI.CLK = PIXEL_CLK;
 	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
 	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
 	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
 					
 	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
 					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
@@ -566,7 +635,8 @@ BEGIN
 					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
 					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
 					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
--- Z<>HLER
+
+    -- Z<>HLER
 	LAST.CLK = PIXEL_CLK;
 	LAST = VHCNT[]==(H_TOTAL[]-2);
 	VHCNT[].CLK = PIXEL_CLK;
@@ -574,10 +644,11 @@ BEGIN
 	VVCNT[].CLK = PIXEL_CLK;
 	VVCNT[].ENA = LAST;
 	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
--- DISPLAY ON OFF
+
+    -- DISPLAY ON OFF
 	DPO_ZL.CLK = PIXEL_CLK;
 	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
-	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
 	DPO_ON.CLK = PIXEL_CLK;
 	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
 	DPO_OFF.CLK = PIXEL_CLK;
@@ -585,31 +656,35 @@ BEGIN
 	DISP_ON.CLK = PIXEL_CLK;
 	DISP_ON = DISP_ON & !DPO_OFF 
 			# DPO_ON & DPO_ZL;
--- DATENTRANSFER ON OFF
+
+    -- DATENTRANSFER ON OFF
 	VDO_ON.CLK = PIXEL_CLK;
 	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
 	VDO_OFF.CLK = PIXEL_CLK;
 	VDO_OFF = VHCNT[]==HDIS_END[];
 	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
 	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
 	VDTRON.CLK = PIXEL_CLK;
 	VDTRON = VDTRON & !VDO_OFF
 		   # VDO_ON & VDO_ZL;
--- VERZ<52>GERUNG UND SYNC	
+
+    -- VERZ<52>GERUNG UND SYNC	
 	HSYNC_START.CLK = PIXEL_CLK;
 	HSYNC_START = VHCNT[]==HS_START[]-3;
 	HSYNC_I[].CLK = PIXEL_CLK;
 	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
 			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_START.CLK = PIXEL_CLK;
+	
+    VSYNC_START.CLK = PIXEL_CLK;
 	VSYNC_START.ENA = LAST;
 	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
 	VSYNC_I[].CLK = PIXEL_CLK;
 	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
 	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
-			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterz<72>hlen bis 0
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterz<72>hlen bis 0
-	VERZ[][].CLK = PIXEL_CLK;
+	
+    VERZ[][].CLK = PIXEL_CLK;
 	VERZ[][1] = VERZ[][0];
 	VERZ[][2] = VERZ[][1];
 	VERZ[][3] = VERZ[][2];
@@ -619,20 +694,25 @@ BEGIN
 	VERZ[][7] = VERZ[][6];
 	VERZ[][8] = VERZ[][7];
 	VERZ[][9] = VERZ[][8];
-	VERZ[0][0] = DISP_ON;
+	
+    VERZ[0][0] = DISP_ON;
 	VERZ[1][0] = HSYNC_I[]!=0;
 	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
 	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
-	nBLANK.CLK = PIXEL_CLK;
+	
+    nBLANK.CLK = PIXEL_CLK;
 	nBLANK =  VERZ[0][8];
-	HSYNC.CLK = PIXEL_CLK;
+	
+    HSYNC.CLK = PIXEL_CLK;
 	HSYNC  =  VERZ[1][9];
 	VSYNC.CLK = PIXEL_CLK;
 	VSYNC  =  VERZ[2][9];
-	nSYNC  = GND;
+	
--- RANDFARBE MACHEN ------------------------------------
+    nSYNC  = GND;
+
+    -- RANDFARBE MACHEN ------------------------------------
 	RAND[].CLK = PIXEL_CLK;
 	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
 	RAND[1] = RAND[0];
@@ -642,19 +722,20 @@ BEGIN
 	RAND[5] = RAND[4];
 	RAND[6] = RAND[5];
 	RAND_ON = RAND[6];
-----------------------------------------------------------
+
+    ----------------------------------------------------------
 	CLR_FIFO.CLK = PIXEL_CLK;
 	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE L<>SCHEN
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE L<>SCHEN
 	START_ZEILE.CLK = PIXEL_CLK;
 	START_ZEILE.ENA = LAST;
 	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
 	SYNC_PIX.CLK = PIXEL_CLK;
-	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
+	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SYNC_PIX1.CLK = PIXEL_CLK;
-	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
+	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SYNC_PIX2.CLK = PIXEL_CLK;
-	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
+	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
 	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
 	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
@@ -665,7 +746,7 @@ BEGIN
 			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
 			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
 			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
-			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
 	
 	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
 	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 

Video/altddio_bidir0.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,82 +18,82 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 272 144)
+	(rect 0 0 240 136)
-	(text "altddio_bidir0" (rect 94 0 202 17)(font "Dialog" (font_size 10)))
+	(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 129 26 140)(font "Arial" ))
+	(text "inst" (rect 8 120 25 132)(font "Arial" ))
 	(port
-		(pt 0 48)
+		(pt 0 24)
 		(input)
-		(text "datain_h[31..0]" (rect 0 0 97 13)(font "Dialog" (font_size 8)))
+		(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
-		(text "datain_h[31..0]" (rect 4 35 87 47)(font "Dialog" (font_size 8)))
+		(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 96 48)(line_width 3))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
 	)
 	(port
-		(pt 0 64)
+		(pt 0 40)
 		(input)
-		(text "datain_l[31..0]" (rect 0 0 93 13)(font "Dialog" (font_size 8)))
+		(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
-		(text "datain_l[31..0]" (rect 4 51 83 63)(font "Dialog" (font_size 8)))
+		(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 96 64)(line_width 3))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
 	)
 	(port
-		(pt 0 80)
+		(pt 0 56)
 		(input)
-		(text "oe" (rect 0 0 16 13)(font "Dialog" (font_size 8)))
+		(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
-		(text "oe" (rect 4 67 18 79)(font "Dialog" (font_size 8)))
+		(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
-		(line (pt 0 80)(pt 96 80))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
-		(pt 0 96)
+		(pt 0 72)
 		(input)
-		(text "inclock" (rect 0 0 47 13)(font "Dialog" (font_size 8)))
+		(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
-		(text "inclock" (rect 4 83 43 95)(font "Dialog" (font_size 8)))
+		(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 96 96))
+		(line (pt 0 72)(pt 88 72)(line_width 1))
 	)
 	(port
-		(pt 0 112)
+		(pt 0 88)
 		(input)
-		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 99 52 111)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
-		(line (pt 0 112)(pt 96 112))
+		(line (pt 0 88)(pt 88 88)(line_width 1))
 	)
 	(port
-		(pt 272 48)
+		(pt 240 24)
 		(output)
-		(text "dataout_h[31..0]" (rect 0 0 106 13)(font "Dialog" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
-		(text "dataout_h[31..0]" (rect 176 35 267 47)(font "Dialog" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
-		(line (pt 272 48)(pt 160 48)(line_width 3))
+		(line (pt 240 24)(pt 144 24)(line_width 3))
 	)
 	(port
-		(pt 272 64)
+		(pt 240 40)
 		(output)
-		(text "dataout_l[31..0]" (rect 0 0 102 13)(font "Dialog" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
-		(text "dataout_l[31..0]" (rect 180 51 267 63)(font "Dialog" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
-		(line (pt 272 64)(pt 160 64)(line_width 3))
+		(line (pt 240 40)(pt 144 40)(line_width 3))
 	)
 	(port
-		(pt 272 80)
+		(pt 240 72)
 		(output)
-		(text "padio[31..0]" (rect 0 0 77 13)(font "Dialog" (font_size 8)))
+		(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
-		(text "padio[31..0]" (rect 201 67 268 79)(font "Dialog" (font_size 8)))
+		(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
-		(line (pt 272 80)(pt 160 80)(line_width 3))
+		(line (pt 240 72)(pt 144 72)(line_width 3))
 	)
 	(port
-		(pt 272 96)
+		(pt 240 56)
-		(output)
+		(bidir)
-		(text "combout[31..0]" (rect 0 0 99 13)(font "Dialog" (font_size 8)))
+		(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
-		(text "combout[31..0]" (rect 183 83 267 95)(font "Dialog" (font_size 8)))
+		(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
-		(line (pt 272 96)(pt 160 96)(line_width 3))
+		(line (pt 240 56)(pt 144 56)(line_width 3))
 	)
 	(drawing
-		(line (pt 96 32)(pt 160 32))
+		(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
-		(line (pt 160 32)(pt 160 128))
+		(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
-		(line (pt 96 128)(pt 160 128))
+		(text "power up" (rect 92 90 129 102)(font "Arial" ))
-		(line (pt 96 32)(pt 96 128))
+		(text "low" (rect 92 100 105 112)(font "Arial" ))
-		(line (pt 0 0)(pt 272 0))
+		(line (pt 88 16)(pt 144 16)(line_width 1))
-		(line (pt 272 0)(pt 272 144))
+		(line (pt 144 16)(pt 144 112)(line_width 1))
-		(line (pt 0 144)(pt 272 144))
+		(line (pt 144 112)(pt 88 112)(line_width 1))
-		(line (pt 0 0)(pt 0 144))
+		(line (pt 88 112)(pt 88 16)(line_width 1))
 	)
 )

Video/altddio_bidir0.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -19,7 +19,7 @@ component altddio_bidir0
 		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
 		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
 		inclock		: IN STD_LOGIC ;
-		oe		: IN STD_LOGIC ;
+		oe		: IN STD_LOGIC  := '1';
 		outclock		: IN STD_LOGIC ;
 		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
 		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

Video/altddio_bidir0.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/altddio_bidir0.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]

Video/altddio_bidir0.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %ALTDDIO_BIDIR%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: ALTDDIO_BIDIR 
+-- MODULE: altddio_bidir 
 
 -- ============================================================
 -- File Name: altddio_bidir0.vhd
 -- Megafunction Name(s):
--- 			ALTDDIO_BIDIR
+-- 			altddio_bidir
 --
 -- Simulation Library Files(s):
 -- 			altera_mf
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -37,7 +37,7 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 
 LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
+USE altera_mf.all;
 
 ENTITY altddio_bidir0 IS
 	PORT
@@ -45,7 +45,7 @@ ENTITY altddio_bidir0 IS
 		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
 		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
 		inclock		: IN STD_LOGIC ;
-		oe		: IN STD_LOGIC ;
+		oe		: IN STD_LOGIC  := '1';
 		outclock		: IN STD_LOGIC ;
 		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
 		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
@@ -61,31 +61,56 @@ ARCHITECTURE SYN OF altddio_bidir0 IS
 	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
 	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (31 DOWNTO 0);
 
+
+
+	COMPONENT altddio_bidir
+	GENERIC (
+		extend_oe_disable		: STRING;
+		implement_input_in_lcell		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			outclock	: IN STD_LOGIC ;
+			padio	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			inclock	: IN STD_LOGIC ;
+			dataout_h	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			oe	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			combout	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			dataout_l	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
 BEGIN
-	combout    <= sub_wire0(31 DOWNTO 0);
+	dataout_h    <= sub_wire0(31 DOWNTO 0);
-	dataout_h    <= sub_wire1(31 DOWNTO 0);
+	combout    <= sub_wire1(31 DOWNTO 0);
 	dataout_l    <= sub_wire2(31 DOWNTO 0);
 
-	ALTDDIO_BIDIR_component : ALTDDIO_BIDIR
+	altddio_bidir_component : altddio_bidir
 	GENERIC MAP (
-		extend_oe_disable => "OFF",
+		extend_oe_disable => "UNUSED",
 		implement_input_in_lcell => "ON",
 		intended_device_family => "Cyclone III",
 		invert_output => "OFF",
-		lpm_hint => "UNUSED",
 		lpm_type => "altddio_bidir",
-		oe_reg => "UNREGISTERED",
+		oe_reg => "UNUSED",
 		power_up_high => "OFF",
 		width => 32
 	)
 	PORT MAP (
-		datain_h => datain_h,
-		datain_l => datain_l,
-		oe => oe,
 		outclock => outclock,
 		inclock => inclock,
-		combout => sub_wire0,
+		oe => oe,
-		dataout_h => sub_wire1,
+		datain_h => datain_h,
+		datain_l => datain_l,
+		dataout_h => sub_wire0,
+		combout => sub_wire1,
 		dataout_l => sub_wire2,
 		padio => padio
 	);
@@ -97,40 +122,51 @@ END SYN;
 -- ============================================================
 -- CNX file retrieval info
 -- ============================================================
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
+-- Retrieval info: PRIVATE: OE NUMERIC "1"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
+-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
+-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
 -- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
--- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
--- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
 -- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
 -- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
--- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL "combout[31..0]"
+-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
--- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
+-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
--- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL "datain_h[31..0]"
+-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
+-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
+-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
+-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
 -- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
--- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL "datain_l[31..0]"
 -- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
--- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL "dataout_h[31..0]"
--- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
--- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL "dataout_l[31..0]"
--- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
--- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
--- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
--- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe"
--- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
--- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL "padio[31..0]"
 -- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE FALSE
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.qip TRUE FALSE
+-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE TRUE
+-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE TRUE
+-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE TRUE
+-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE TRUE
+-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE FALSE
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: altera_mf

Video/altddio_out0.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,47 +18,47 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 256 112)
+	(rect 0 0 232 120)
-	(text "altddio_out0" (rect 89 0 188 17)(font "Dialog" (font_size 10)))
+	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 97 26 108)(font "Arial" ))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
 	(port
-		(pt 0 48)
+		(pt 0 24)
 		(input)
-		(text "datain_h[3..0]" (rect 0 0 89 13)(font "Dialog" (font_size 8)))
+		(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
-		(text "datain_h[3..0]" (rect 4 35 80 47)(font "Dialog" (font_size 8)))
+		(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 96 48)(line_width 3))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
 	)
 	(port
-		(pt 0 64)
+		(pt 0 40)
 		(input)
-		(text "datain_l[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8)))
+		(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
-		(text "datain_l[3..0]" (rect 4 51 76 63)(font "Dialog" (font_size 8)))
+		(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 96 64)(line_width 3))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
 	)
 	(port
-		(pt 0 80)
+		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
-		(line (pt 0 80)(pt 96 80))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
-		(pt 256 48)
+		(pt 232 24)
 		(output)
-		(text "dataout[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8)))
+		(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
-		(text "dataout[3..0]" (rect 180 35 252 47)(font "Dialog" (font_size 8)))
+		(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
-		(line (pt 256 48)(pt 160 48)(line_width 3))
+		(line (pt 232 24)(pt 152 24)(line_width 3))
 	)
 	(drawing
-		(line (pt 96 32)(pt 160 32))
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
-		(line (pt 160 32)(pt 160 96))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
-		(line (pt 96 96)(pt 160 96))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
-		(line (pt 96 32)(pt 96 96))
+		(text "high" (rect 92 84 109 96)(font "Arial" ))
-		(line (pt 0 0)(pt 256 0))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
-		(line (pt 256 0)(pt 256 112))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
-		(line (pt 0 112)(pt 256 112))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
-		(line (pt 0 0)(pt 0 112))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
 	)
 )

Video/altddio_out0.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/altddio_out0.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/altddio_out0.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]

Video/altddio_out0.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %ALTDDIO_OUT%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: ALTDDIO_OUT 
+-- MODULE: altddio_out 
 
 -- ============================================================
 -- File Name: altddio_out0.vhd
 -- Megafunction Name(s):
--- 			ALTDDIO_OUT
+-- 			altddio_out
 --
 -- Simulation Library Files(s):
 -- 			altera_mf
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -37,7 +37,7 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 
 LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
+USE altera_mf.all;
 
 ENTITY altddio_out0 IS
 	PORT
@@ -54,24 +54,43 @@ ARCHITECTURE SYN OF altddio_out0 IS
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
 
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
 BEGIN
 	dataout    <= sub_wire0(3 DOWNTO 0);
 
-	ALTDDIO_OUT_component : ALTDDIO_OUT
+	altddio_out_component : altddio_out
 	GENERIC MAP (
-		extend_oe_disable => "OFF",
+		extend_oe_disable => "UNUSED",
 		intended_device_family => "Cyclone III",
 		invert_output => "ON",
-		lpm_hint => "UNUSED",
 		lpm_type => "altddio_out",
-		oe_reg => "UNREGISTERED",
+		oe_reg => "UNUSED",
 		power_up_high => "ON",
 		width => 4
 	)
 	PORT MAP (
+		outclock => outclock,
 		datain_h => datain_h,
 		datain_l => datain_l,
-		outclock => outclock,
 		dataout => sub_wire0
 	);
 
@@ -82,29 +101,36 @@ END SYN;
 -- ============================================================
 -- CNX file retrieval info
 -- ============================================================
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
--- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
--- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
 -- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
 -- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
--- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL "datain_h[3..0]"
+-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
+-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
 -- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
--- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL "datain_l[3..0]"
 -- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
--- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"
 -- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
 -- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE FALSE
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.qip TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: altera_mf

Video/altddio_out2.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,47 +18,47 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 256 112)
+	(rect 0 0 232 120)
-	(text "altddio_out2" (rect 89 0 188 17)(font "Dialog" (font_size 10)))
+	(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 97 26 108)(font "Arial" ))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
 	(port
-		(pt 0 48)
+		(pt 0 24)
 		(input)
-		(text "datain_h[23..0]" (rect 0 0 97 13)(font "Dialog" (font_size 8)))
+		(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
-		(text "datain_h[23..0]" (rect 4 35 87 47)(font "Dialog" (font_size 8)))
+		(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 96 48)(line_width 3))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
 	)
 	(port
-		(pt 0 64)
+		(pt 0 40)
 		(input)
-		(text "datain_l[23..0]" (rect 0 0 93 13)(font "Dialog" (font_size 8)))
+		(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
-		(text "datain_l[23..0]" (rect 4 51 83 63)(font "Dialog" (font_size 8)))
+		(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 96 64)(line_width 3))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
 	)
 	(port
-		(pt 0 80)
+		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
-		(line (pt 0 80)(pt 96 80))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
-		(pt 256 48)
+		(pt 232 24)
 		(output)
-		(text "dataout[23..0]" (rect 0 0 92 13)(font "Dialog" (font_size 8)))
+		(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
-		(text "dataout[23..0]" (rect 173 35 252 47)(font "Dialog" (font_size 8)))
+		(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
-		(line (pt 256 48)(pt 160 48)(line_width 3))
+		(line (pt 232 24)(pt 152 24)(line_width 3))
 	)
 	(drawing
-		(line (pt 96 32)(pt 160 32))
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
-		(line (pt 160 32)(pt 160 96))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
-		(line (pt 96 96)(pt 160 96))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
-		(line (pt 96 32)(pt 96 96))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
-		(line (pt 0 0)(pt 256 0))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
-		(line (pt 256 0)(pt 256 112))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
-		(line (pt 0 112)(pt 256 112))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
-		(line (pt 0 0)(pt 0 112))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
 	)
 )

Video/altddio_out2.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/altddio_out2.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/altddio_out2.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]

Video/altddio_out2.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %ALTDDIO_OUT%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: ALTDDIO_OUT 
+-- MODULE: altddio_out 
 
 -- ============================================================
 -- File Name: altddio_out2.vhd
 -- Megafunction Name(s):
--- 			ALTDDIO_OUT
+-- 			altddio_out
 --
 -- Simulation Library Files(s):
 -- 			altera_mf
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -37,7 +37,7 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 
 LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
+USE altera_mf.all;
 
 ENTITY altddio_out2 IS
 	PORT
@@ -54,24 +54,43 @@ ARCHITECTURE SYN OF altddio_out2 IS
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
 
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+	END COMPONENT;
+
 BEGIN
 	dataout    <= sub_wire0(23 DOWNTO 0);
 
-	ALTDDIO_OUT_component : ALTDDIO_OUT
+	altddio_out_component : altddio_out
 	GENERIC MAP (
-		extend_oe_disable => "OFF",
+		extend_oe_disable => "UNUSED",
 		intended_device_family => "Cyclone III",
 		invert_output => "OFF",
-		lpm_hint => "UNUSED",
 		lpm_type => "altddio_out",
-		oe_reg => "UNREGISTERED",
+		oe_reg => "UNUSED",
 		power_up_high => "OFF",
 		width => 24
 	)
 	PORT MAP (
+		outclock => outclock,
 		datain_h => datain_h,
 		datain_l => datain_l,
-		outclock => outclock,
 		dataout => sub_wire0
 	);
 
@@ -82,29 +101,36 @@ END SYN;
 -- ============================================================
 -- CNX file retrieval info
 -- ============================================================
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
--- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
--- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
 -- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
 -- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
--- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL "datain_h[23..0]"
+-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
+-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
 -- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
--- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL "datain_l[23..0]"
 -- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
--- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL "dataout[23..0]"
 -- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
 -- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE FALSE
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.qip TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: altera_mf

Video/lpm_constant0.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,32 +18,25 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 112 48)
+	(rect 0 0 96 48)
-	(text "lpm_constant0" (rect 14 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
 	(port
-		(pt 112 24)
+		(pt 96 24)
 		(output)
-		(text "result[4..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 112 24)(pt 96 24)(line_width 3))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "5" (rect 99 27 204 64)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
-		(line (pt 106 20)(pt 98 28))
+		(text "5" (rect 87 25 92 37)(font "Arial" ))
-		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
-		(line (pt 16 16)(pt 96 16))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
-		(line (pt 16 32)(pt 96 32))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
-		(line (pt 96 16)(pt 96 32))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
-		(line (pt 0 0)(pt 114 0))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
-		(line (pt 114 0)(pt 114 50))
-		(line (pt 0 50)(pt 114 50))
-		(line (pt 0 0)(pt 0 50))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_constant0.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_constant0.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]

Video/lpm_constant0.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_CONSTANT%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_CONSTANT 
+-- MODULE: lpm_constant 
 
 -- ============================================================
 -- File Name: lpm_constant0.vhd
 -- Megafunction Name(s):
--- 			LPM_CONSTANT
+-- 			lpm_constant
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant0 IS
 BEGIN
 	result    <= sub_wire0(4 DOWNTO 0);
 
-	LPM_CONSTANT_component : LPM_CONSTANT
+	lpm_constant_component : lpm_constant
 	GENERIC MAP (
 		lpm_cvalue => 0,
 		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
@@ -93,17 +93,16 @@ END SYN;
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: Value NUMERIC "0"
 -- Retrieval info: PRIVATE: nBit NUMERIC "5"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
--- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL "result[4..0]"
+-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
 -- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_constant1.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,32 +18,25 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 112 48)
+	(rect 0 0 96 48)
-	(text "lpm_constant1" (rect 14 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
 	(port
-		(pt 112 24)
+		(pt 96 24)
 		(output)
-		(text "result[1..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 112 24)(pt 96 24)(line_width 3))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "2" (rect 99 27 204 64)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
-		(line (pt 106 20)(pt 98 28))
+		(text "2" (rect 87 25 92 37)(font "Arial" ))
-		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
-		(line (pt 16 16)(pt 96 16))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
-		(line (pt 16 32)(pt 96 32))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
-		(line (pt 96 16)(pt 96 32))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
-		(line (pt 0 0)(pt 114 0))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
-		(line (pt 114 0)(pt 114 50))
-		(line (pt 0 50)(pt 114 50))
-		(line (pt 0 0)(pt 0 50))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_constant1.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_constant1.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_constant1.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]

Video/lpm_constant1.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_CONSTANT%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_CONSTANT 
+-- MODULE: lpm_constant 
 
 -- ============================================================
 -- File Name: lpm_constant1.vhd
 -- Megafunction Name(s):
--- 			LPM_CONSTANT
+-- 			lpm_constant
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant1 IS
 BEGIN
 	result    <= sub_wire0(1 DOWNTO 0);
 
-	LPM_CONSTANT_component : LPM_CONSTANT
+	lpm_constant_component : lpm_constant
 	GENERIC MAP (
 		lpm_cvalue => 0,
 		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
@@ -93,17 +93,16 @@ END SYN;
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: Value NUMERIC "0"
 -- Retrieval info: PRIVATE: nBit NUMERIC "2"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
--- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL "result[1..0]"
+-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0]
 -- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_constant2.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,32 +18,25 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 112 48)
+	(rect 0 0 96 48)
-	(text "lpm_constant2" (rect 14 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
 	(port
-		(pt 112 24)
+		(pt 96 24)
 		(output)
-		(text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 112 24)(pt 96 24)(line_width 3))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "8" (rect 99 27 204 64)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
-		(line (pt 106 20)(pt 98 28))
+		(text "8" (rect 87 25 92 37)(font "Arial" ))
-		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
-		(line (pt 16 16)(pt 96 16))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
-		(line (pt 16 32)(pt 96 32))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
-		(line (pt 96 16)(pt 96 32))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
-		(line (pt 0 0)(pt 114 0))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
-		(line (pt 114 0)(pt 114 50))
-		(line (pt 0 50)(pt 114 50))
-		(line (pt 0 0)(pt 0 50))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_constant2.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_constant2.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]

Video/lpm_constant2.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_CONSTANT%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_CONSTANT 
+-- MODULE: lpm_constant 
 
 -- ============================================================
 -- File Name: lpm_constant2.vhd
 -- Megafunction Name(s):
--- 			LPM_CONSTANT
+-- 			lpm_constant
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant2 IS
 BEGIN
 	result    <= sub_wire0(7 DOWNTO 0);
 
-	LPM_CONSTANT_component : LPM_CONSTANT
+	lpm_constant_component : lpm_constant
 	GENERIC MAP (
 		lpm_cvalue => 0,
 		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
@@ -93,17 +93,16 @@ END SYN;
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: Value NUMERIC "0"
 -- Retrieval info: PRIVATE: nBit NUMERIC "8"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
 -- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_constant3.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,32 +18,25 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 112 48)
+	(rect 0 0 96 48)
-	(text "lpm_constant3" (rect 14 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
 	(port
-		(pt 112 24)
+		(pt 96 24)
 		(output)
-		(text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 112 24)(pt 96 24)(line_width 3))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "7" (rect 99 27 204 64)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
-		(line (pt 106 20)(pt 98 28))
+		(text "7" (rect 87 25 92 37)(font "Arial" ))
-		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
-		(line (pt 16 16)(pt 96 16))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
-		(line (pt 16 32)(pt 96 32))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
-		(line (pt 96 16)(pt 96 32))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
-		(line (pt 0 0)(pt 114 0))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
-		(line (pt 114 0)(pt 114 50))
-		(line (pt 0 50)(pt 114 50))
-		(line (pt 0 0)(pt 0 50))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_constant3.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_constant3.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]

Video/lpm_constant3.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_CONSTANT%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_CONSTANT 
+-- MODULE: lpm_constant 
 
 -- ============================================================
 -- File Name: lpm_constant3.vhd
 -- Megafunction Name(s):
--- 			LPM_CONSTANT
+-- 			lpm_constant
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant3 IS
 BEGIN
 	result    <= sub_wire0(6 DOWNTO 0);
 
-	LPM_CONSTANT_component : LPM_CONSTANT
+	lpm_constant_component : lpm_constant
 	GENERIC MAP (
 		lpm_cvalue => 0,
 		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
@@ -93,17 +93,16 @@ END SYN;
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: Value NUMERIC "0"
 -- Retrieval info: PRIVATE: nBit NUMERIC "7"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
--- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
 -- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_mux0.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,74 +18,66 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 144 128)
+	(rect 0 0 152 128)
-	(text "lpm_mux0" (rect 43 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 113 26 124)(font "Arial" ))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data3x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data3x[31..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data2x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data2x[31..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data1x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data1x[31..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data0x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data0x[31..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
+		(text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 91 29 103)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 64 104))
+		(line (pt 0 104)(pt 72 104)(line_width 1))
 	)
 	(port
-		(pt 72 128)
+		(pt 80 128)
 		(input)
-		(text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
-		(text "sel[1..0]" (rect 66 73 78 111)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8)))
-		(line (pt 72 128)(pt 72 116)(line_width 3))
+		(line (pt 80 128)(pt 80 116)(line_width 3))
 	)
 	(port
-		(pt 144 72)
+		(pt 152 72)
 		(output)
-		(text "result[31..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "result[31..0]" (rect 85 59 142 71)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8)))
-		(line (pt 144 72)(pt 80 72)(line_width 3))
+		(line (pt 152 72)(pt 88 72)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 120))
+		(line (pt 72 24)(pt 72 120)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 88 32)(pt 88 112)(line_width 1))
-		(line (pt 64 120)(pt 80 112))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
-		(line (pt 80 32)(pt 80 112))
+		(line (pt 72 120)(pt 88 112)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 72 98)(pt 78 104)(line_width 1))
-		(line (pt 146 0)(pt 146 130))
+		(line (pt 78 104)(pt 72 110)(line_width 1))
-		(line (pt 0 130)(pt 146 130))
-		(line (pt 0 0)(pt 0 130))
-		(line (pt 64 98)(pt 70 104))
-		(line (pt 70 104)(pt 64 110))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_mux0.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux0.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux0.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]

Video/lpm_mux0.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_mux0.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -199,7 +199,7 @@ BEGIN
 	sub_wire2(0, 30)    <= sub_wire5(30);
 	sub_wire2(0, 31)    <= sub_wire5(31);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_pipeline => 4,
 		lpm_size => 4,
@@ -208,9 +208,9 @@ BEGIN
 		lpm_widths => 2
 	)
 	PORT MAP (
+		sel => sel,
 		clock => clock,
 		data => sub_wire2,
-		sel => sel,
 		result => sub_wire0
 	);
 
@@ -223,30 +223,29 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL "data0x[31..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0]
--- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL "data1x[31..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0]
--- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL "data2x[31..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0]
--- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL "data3x[31..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0]
--- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
--- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
--- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
--- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
--- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
--- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
 -- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_mux1.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,102 +18,94 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 144 192)
+	(rect 0 0 152 192)
-	(text "lpm_mux1" (rect 43 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 177 26 188)(font "Arial" ))
+	(text "inst" (rect 8 176 25 188)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data7x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data7x[15..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data6x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data6x[15..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data5x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data5x[15..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data4x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data4x[15..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data3x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data3x[15..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 64 104)(line_width 3))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data2x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data2x[15..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 64 120)(line_width 3))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data1x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data1x[15..0]" (rect 4 123 67 135)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
-		(line (pt 0 136)(pt 64 136)(line_width 3))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data0x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data0x[15..0]" (rect 4 139 67 151)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 64 152)(line_width 3))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 155 29 167)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 64 168))
+		(line (pt 0 168)(pt 72 168)(line_width 1))
 	)
 	(port
-		(pt 72 192)
+		(pt 80 192)
 		(input)
-		(text "sel[2..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
-		(text "sel[2..0]" (rect 66 137 78 175)(font "Arial" (font_size 8))(vertical))
+		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
-		(line (pt 72 192)(pt 72 180)(line_width 3))
+		(line (pt 80 192)(pt 80 180)(line_width 3))
 	)
 	(port
-		(pt 144 104)
+		(pt 152 104)
 		(output)
-		(text "result[15..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "result[15..0]" (rect 85 91 142 103)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
-		(line (pt 144 104)(pt 80 104)(line_width 3))
+		(line (pt 152 104)(pt 88 104)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 184))
+		(line (pt 72 24)(pt 72 184)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 88 32)(pt 88 176)(line_width 1))
-		(line (pt 64 184)(pt 80 176))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
-		(line (pt 80 32)(pt 80 176))
+		(line (pt 72 184)(pt 88 176)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 72 162)(pt 78 168)(line_width 1))
-		(line (pt 146 0)(pt 146 194))
+		(line (pt 78 168)(pt 72 174)(line_width 1))
-		(line (pt 0 194)(pt 146 194))
-		(line (pt 0 0)(pt 0 194))
-		(line (pt 64 162)(pt 70 168))
-		(line (pt 70 168)(pt 64 174))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_mux1.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux1.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux1.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]

Video/lpm_mux1.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_mux1.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -211,7 +211,7 @@ BEGIN
 	sub_wire2(0, 14)    <= sub_wire9(14);
 	sub_wire2(0, 15)    <= sub_wire9(15);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_pipeline => 4,
 		lpm_size => 8,
@@ -220,9 +220,9 @@ BEGIN
 		lpm_widths => 3
 	)
 	PORT MAP (
+		sel => sel,
 		clock => clock,
 		data => sub_wire2,
-		sel => sel,
 		result => sub_wire0
 	);
 
@@ -235,38 +235,37 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0]
--- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0]
--- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0]
--- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0]
--- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]"
+-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0]
--- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]"
+-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0]
--- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]"
+-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0]
--- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]"
+-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0]
--- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
+-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
--- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
--- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
 -- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_mux2.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,158 +18,150 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 144 320)
-	(text "lpm_mux2" (rect 43 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 305 26 316)(font "Arial" ))
+	(text "inst" (rect 8 304 25 316)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data15x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data15x[7..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data14x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data14x[7..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data13x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data13x[7..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data12x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data12x[7..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data11x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data11x[7..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
+		(text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 64 104)(line_width 3))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data10x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data10x[7..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 64 120)(line_width 3))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data9x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data9x[7..0]" (rect 4 123 61 135)(font "Arial" (font_size 8)))
+		(text "data9x[7..0]" (rect 4 123 60 136)(font "Arial" (font_size 8)))
-		(line (pt 0 136)(pt 64 136)(line_width 3))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data8x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data8x[7..0]" (rect 4 139 61 151)(font "Arial" (font_size 8)))
+		(text "data8x[7..0]" (rect 4 139 60 152)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 64 152)(line_width 3))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "data7x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data7x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data7x[7..0]" (rect 4 155 61 167)(font "Arial" (font_size 8)))
+		(text "data7x[7..0]" (rect 4 155 60 168)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 64 168)(line_width 3))
+		(line (pt 0 168)(pt 72 168)(line_width 3))
 	)
 	(port
 		(pt 0 184)
 		(input)
-		(text "data6x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data6x[7..0]" (rect 4 171 61 183)(font "Arial" (font_size 8)))
+		(text "data6x[7..0]" (rect 4 171 60 184)(font "Arial" (font_size 8)))
-		(line (pt 0 184)(pt 64 184)(line_width 3))
+		(line (pt 0 184)(pt 72 184)(line_width 3))
 	)
 	(port
 		(pt 0 200)
 		(input)
-		(text "data5x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data5x[7..0]" (rect 4 187 61 199)(font "Arial" (font_size 8)))
+		(text "data5x[7..0]" (rect 4 187 60 200)(font "Arial" (font_size 8)))
-		(line (pt 0 200)(pt 64 200)(line_width 3))
+		(line (pt 0 200)(pt 72 200)(line_width 3))
 	)
 	(port
 		(pt 0 216)
 		(input)
-		(text "data4x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data4x[7..0]" (rect 4 203 61 215)(font "Arial" (font_size 8)))
+		(text "data4x[7..0]" (rect 4 203 60 216)(font "Arial" (font_size 8)))
-		(line (pt 0 216)(pt 64 216)(line_width 3))
+		(line (pt 0 216)(pt 72 216)(line_width 3))
 	)
 	(port
 		(pt 0 232)
 		(input)
-		(text "data3x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data3x[7..0]" (rect 4 219 61 231)(font "Arial" (font_size 8)))
+		(text "data3x[7..0]" (rect 4 219 60 232)(font "Arial" (font_size 8)))
-		(line (pt 0 232)(pt 64 232)(line_width 3))
+		(line (pt 0 232)(pt 72 232)(line_width 3))
 	)
 	(port
 		(pt 0 248)
 		(input)
-		(text "data2x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data2x[7..0]" (rect 4 235 61 247)(font "Arial" (font_size 8)))
+		(text "data2x[7..0]" (rect 4 235 60 248)(font "Arial" (font_size 8)))
-		(line (pt 0 248)(pt 64 248)(line_width 3))
+		(line (pt 0 248)(pt 72 248)(line_width 3))
 	)
 	(port
 		(pt 0 264)
 		(input)
-		(text "data1x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data1x[7..0]" (rect 4 251 61 263)(font "Arial" (font_size 8)))
+		(text "data1x[7..0]" (rect 4 251 60 264)(font "Arial" (font_size 8)))
-		(line (pt 0 264)(pt 64 264)(line_width 3))
+		(line (pt 0 264)(pt 72 264)(line_width 3))
 	)
 	(port
 		(pt 0 280)
 		(input)
-		(text "data0x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data0x[7..0]" (rect 4 267 61 279)(font "Arial" (font_size 8)))
+		(text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8)))
-		(line (pt 0 280)(pt 64 280)(line_width 3))
+		(line (pt 0 280)(pt 72 280)(line_width 3))
 	)
 	(port
 		(pt 0 296)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 283 29 295)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8)))
-		(line (pt 0 296)(pt 64 296))
+		(line (pt 0 296)(pt 72 296)(line_width 1))
 	)
 	(port
-		(pt 72 320)
+		(pt 80 320)
 		(input)
-		(text "sel[3..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
-		(text "sel[3..0]" (rect 66 265 78 303)(font "Arial" (font_size 8))(vertical))
+		(text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8)))
-		(line (pt 72 320)(pt 72 308)(line_width 3))
+		(line (pt 80 320)(pt 80 308)(line_width 3))
 	)
 	(port
 		(pt 144 168)
 		(output)
-		(text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "result[7..0]" (rect 91 155 142 167)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8)))
-		(line (pt 144 168)(pt 80 168)(line_width 3))
+		(line (pt 144 168)(pt 88 168)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 312))
+		(line (pt 72 24)(pt 72 312)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 88 32)(pt 88 304)(line_width 1))
-		(line (pt 64 312)(pt 80 304))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
-		(line (pt 80 32)(pt 80 304))
+		(line (pt 72 312)(pt 88 304)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 72 290)(pt 78 296)(line_width 1))
-		(line (pt 146 0)(pt 146 322))
+		(line (pt 78 296)(pt 72 302)(line_width 1))
-		(line (pt 0 322)(pt 146 322))
-		(line (pt 0 0)(pt 0 322))
-		(line (pt 64 290)(pt 70 296))
-		(line (pt 70 296)(pt 64 302))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_mux2.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux2.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux2.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"]

Video/lpm_mux2.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_mux2.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -235,7 +235,7 @@ BEGIN
 	sub_wire2(0, 6)    <= sub_wire17(6);
 	sub_wire2(0, 7)    <= sub_wire17(7);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_pipeline => 2,
 		lpm_size => 16,
@@ -244,9 +244,9 @@ BEGIN
 		lpm_widths => 4
 	)
 	PORT MAP (
+		sel => sel,
 		clock => clock,
 		data => sub_wire2,
-		sel => sel,
 		result => sub_wire0
 	);
 
@@ -259,54 +259,53 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0]
--- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL "data10x[7..0]"
+-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0]
--- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL "data11x[7..0]"
+-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0]
--- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL "data12x[7..0]"
+-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0]
--- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL "data13x[7..0]"
+-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0]
--- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL "data14x[7..0]"
+-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0]
--- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL "data15x[7..0]"
+-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0]
--- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0]
--- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0]
--- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0]
--- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL "data4x[7..0]"
+-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0]
--- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL "data5x[7..0]"
+-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0]
--- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL "data6x[7..0]"
+-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0]
--- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL "data7x[7..0]"
+-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0]
--- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL "data8x[7..0]"
+-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0]
--- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL "data9x[7..0]"
+-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0]
--- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
--- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
+-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
--- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
 -- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
+-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_mux3.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,51 +18,43 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 80 80)
-	(text "lpm_mux3" (rect 11 0 85 16)(font "Arial" (font_size 10)))
+	(text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 65 26 76)(font "Arial" ))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data1" (rect 0 0 33 13)(font "Arial" (font_size 8)))
+		(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
-		(text "data1" (rect 4 27 32 39)(font "Arial" (font_size 8)))
+		(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 32 40))
+		(line (pt 0 40)(pt 32 40)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data0" (rect 0 0 33 13)(font "Arial" (font_size 8)))
+		(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
-		(text "data0" (rect 4 43 32 55)(font "Arial" (font_size 8)))
+		(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 32 56))
+		(line (pt 0 56)(pt 32 56)(line_width 1))
 	)
 	(port
 		(pt 40 80)
 		(input)
-		(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
-		(text "sel" (rect 34 49 46 63)(font "Arial" (font_size 8))(vertical))
+		(text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8)))
-		(line (pt 40 80)(pt 40 68))
+		(line (pt 40 80)(pt 40 68)(line_width 1))
 	)
 	(port
 		(pt 80 48)
 		(output)
-		(text "result" (rect 0 0 33 13)(font "Arial" (font_size 8)))
+		(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
-		(text "result" (rect 51 35 78 47)(font "Arial" (font_size 8)))
+		(text "result" (rect 50 35 75 48)(font "Arial" (font_size 8)))
-		(line (pt 80 48)(pt 48 48))
+		(line (pt 80 48)(pt 48 48)(line_width 1))
 	)
 	(drawing
-		(line (pt 32 24)(pt 32 72))
+		(line (pt 32 24)(pt 32 72)(line_width 1))
-		(line (pt 32 24)(pt 48 32))
+		(line (pt 48 32)(pt 48 64)(line_width 1))
-		(line (pt 32 72)(pt 48 64))
+		(line (pt 32 24)(pt 48 32)(line_width 1))
-		(line (pt 48 32)(pt 48 64))
+		(line (pt 32 72)(pt 48 64)(line_width 1))
-		(line (pt 0 0)(pt 82 0))
-		(line (pt 82 0)(pt 82 82))
-		(line (pt 0 82)(pt 82 82))
-		(line (pt 0 0)(pt 0 82))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_mux3.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux3.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"]

Video/lpm_mux3.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_mux3.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -57,22 +57,22 @@ ARCHITECTURE SYN OF lpm_mux3 IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC ;
 
 BEGIN
-	sub_wire4    <= data0;
+	sub_wire6    <= data0;
 	sub_wire1    <= sub_wire0(0);
 	result    <= sub_wire1;
-	sub_wire2    <= data1;
+	sub_wire2    <= sel;
-	sub_wire3(1, 0)    <= sub_wire2;
+	sub_wire3(0)    <= sub_wire2;
-	sub_wire3(0, 0)    <= sub_wire4;
+	sub_wire4    <= data1;
-	sub_wire5    <= sel;
+	sub_wire5(1, 0)    <= sub_wire4;
-	sub_wire6(0)    <= sub_wire5;
+	sub_wire5(0, 0)    <= sub_wire6;
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_size => 2,
 		lpm_type => "LPM_MUX",
@@ -80,8 +80,8 @@ BEGIN
 		lpm_widths => 1
 	)
 	PORT MAP (
-		data => sub_wire3,
+		sel => sub_wire3,
-		sel => sub_wire6,
+		data => sub_wire5,
 		result => sub_wire0
 	);
 
@@ -94,23 +94,22 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
--- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
+-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
--- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
+-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
--- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
+-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
--- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
--- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
--- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
--- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
 -- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
+-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_mux4.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,51 +18,43 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 144 80)
+	(rect 0 0 136 80)
-	(text "lpm_mux4" (rect 43 0 118 16)(font "Arial" (font_size 10)))
+	(text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 65 26 76)(font "Arial" ))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data1x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data1x[6..0]" (rect 4 27 61 39)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 64 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data0x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data0x[6..0]" (rect 4 43 61 55)(font "Arial" (font_size 8)))
+		(text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 64 56)(line_width 3))
 	)
 	(port
 		(pt 72 80)
 		(input)
-		(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
-		(text "sel" (rect 66 49 78 63)(font "Arial" (font_size 8))(vertical))
+		(text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8)))
-		(line (pt 72 80)(pt 72 68))
+		(line (pt 72 80)(pt 72 68)(line_width 1))
 	)
 	(port
-		(pt 144 48)
+		(pt 136 48)
 		(output)
-		(text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "result[6..0]" (rect 91 35 142 47)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8)))
-		(line (pt 144 48)(pt 80 48)(line_width 3))
+		(line (pt 136 48)(pt 80 48)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 72))
+		(line (pt 64 24)(pt 64 72)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 80 32)(pt 80 64)(line_width 1))
-		(line (pt 64 72)(pt 80 64))
+		(line (pt 64 24)(pt 80 32)(line_width 1))
-		(line (pt 80 32)(pt 80 64))
+		(line (pt 64 72)(pt 80 64)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
-		(line (pt 146 0)(pt 146 82))
-		(line (pt 0 82)(pt 146 82))
-		(line (pt 0 0)(pt 0 82))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_mux4.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux4.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"]

Video/lpm_mux4.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_mux4.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -55,34 +55,34 @@ ARCHITECTURE SYN OF lpm_mux4 IS
 --	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (6 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (6 DOWNTO 0);
 
 BEGIN
-	sub_wire3    <= data0x(6 DOWNTO 0);
+	sub_wire5    <= data0x(6 DOWNTO 0);
 	result    <= sub_wire0(6 DOWNTO 0);
-	sub_wire1    <= data1x(6 DOWNTO 0);
+	sub_wire1    <= sel;
-	sub_wire2(1, 0)    <= sub_wire1(0);
+	sub_wire2(0)    <= sub_wire1;
-	sub_wire2(1, 1)    <= sub_wire1(1);
+	sub_wire3    <= data1x(6 DOWNTO 0);
-	sub_wire2(1, 2)    <= sub_wire1(2);
+	sub_wire4(1, 0)    <= sub_wire3(0);
-	sub_wire2(1, 3)    <= sub_wire1(3);
+	sub_wire4(1, 1)    <= sub_wire3(1);
-	sub_wire2(1, 4)    <= sub_wire1(4);
+	sub_wire4(1, 2)    <= sub_wire3(2);
-	sub_wire2(1, 5)    <= sub_wire1(5);
+	sub_wire4(1, 3)    <= sub_wire3(3);
-	sub_wire2(1, 6)    <= sub_wire1(6);
+	sub_wire4(1, 4)    <= sub_wire3(4);
-	sub_wire2(0, 0)    <= sub_wire3(0);
+	sub_wire4(1, 5)    <= sub_wire3(5);
-	sub_wire2(0, 1)    <= sub_wire3(1);
+	sub_wire4(1, 6)    <= sub_wire3(6);
-	sub_wire2(0, 2)    <= sub_wire3(2);
+	sub_wire4(0, 0)    <= sub_wire5(0);
-	sub_wire2(0, 3)    <= sub_wire3(3);
+	sub_wire4(0, 1)    <= sub_wire5(1);
-	sub_wire2(0, 4)    <= sub_wire3(4);
+	sub_wire4(0, 2)    <= sub_wire5(2);
-	sub_wire2(0, 5)    <= sub_wire3(5);
+	sub_wire4(0, 3)    <= sub_wire5(3);
-	sub_wire2(0, 6)    <= sub_wire3(6);
+	sub_wire4(0, 4)    <= sub_wire5(4);
-	sub_wire4    <= sel;
+	sub_wire4(0, 5)    <= sub_wire5(5);
-	sub_wire5(0)    <= sub_wire4;
+	sub_wire4(0, 6)    <= sub_wire5(6);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_size => 2,
 		lpm_type => "LPM_MUX",
@@ -90,8 +90,8 @@ BEGIN
 		lpm_widths => 1
 	)
 	PORT MAP (
-		data => sub_wire2,
+		sel => sub_wire2,
-		sel => sub_wire5,
+		data => sub_wire4,
 		result => sub_wire0
 	);
 
@@ -104,23 +104,22 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
--- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL "data0x[6..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0]
--- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL "data1x[6..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0]
--- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
--- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
--- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
--- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
--- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
 -- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
+-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_mux5.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,65 +18,57 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 144 112)
+	(rect 0 0 152 112)
-	(text "lpm_mux5" (rect 43 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 97 26 108)(font "Arial" ))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data3x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data3x[63..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data2x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data2x[63..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data1x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data1x[63..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data0x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data0x[63..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
-		(pt 72 112)
+		(pt 80 112)
 		(input)
-		(text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
-		(text "sel[1..0]" (rect 66 57 78 95)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8)))
-		(line (pt 72 112)(pt 72 100)(line_width 3))
+		(line (pt 80 112)(pt 80 100)(line_width 3))
 	)
 	(port
-		(pt 144 64)
+		(pt 152 64)
 		(output)
-		(text "result[63..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "result[63..0]" (rect 85 51 142 63)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8)))
-		(line (pt 144 64)(pt 80 64)(line_width 3))
+		(line (pt 152 64)(pt 88 64)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 104))
+		(line (pt 72 24)(pt 72 104)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 88 32)(pt 88 96)(line_width 1))
-		(line (pt 64 104)(pt 80 96))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
-		(line (pt 80 32)(pt 80 96))
+		(line (pt 72 104)(pt 88 96)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
-		(line (pt 146 0)(pt 146 114))
-		(line (pt 0 114)(pt 146 114))
-		(line (pt 0 0)(pt 0 114))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_mux5.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux5.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux5.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"]

Video/lpm_mux5.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_mux5.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -326,7 +326,7 @@ BEGIN
 	sub_wire2(0, 62)    <= sub_wire5(62);
 	sub_wire2(0, 63)    <= sub_wire5(63);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_size => 4,
 		lpm_type => "LPM_MUX",
@@ -334,8 +334,8 @@ BEGIN
 		lpm_widths => 2
 	)
 	PORT MAP (
-		data => sub_wire2,
 		sel => sel,
+		data => sub_wire2,
 		result => sub_wire0
 	);
 
@@ -348,27 +348,26 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
--- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL "data0x[63..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0]
--- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL "data1x[63..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0]
--- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL "data2x[63..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0]
--- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL "data3x[63..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0]
--- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
+-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0]
--- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
--- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
--- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
--- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
--- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
--- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
 -- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_mux6.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,102 +18,94 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 144 192)
+	(rect 0 0 152 192)
-	(text "lpm_mux6" (rect 43 0 117 16)(font "Arial" (font_size 10)))
+	(text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 177 26 188)(font "Arial" ))
+	(text "inst" (rect 8 176 25 188)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data7x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data7x[23..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data6x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data6x[23..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data5x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data5x[23..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data4x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data4x[23..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data3x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data3x[23..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 64 104)(line_width 3))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data2x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data2x[23..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 64 120)(line_width 3))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data1x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data1x[23..0]" (rect 4 123 67 135)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
-		(line (pt 0 136)(pt 64 136)(line_width 3))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data0x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "data0x[23..0]" (rect 4 139 67 151)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 64 152)(line_width 3))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 155 29 167)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 64 168))
+		(line (pt 0 168)(pt 72 168)(line_width 1))
 	)
 	(port
-		(pt 72 192)
+		(pt 80 192)
 		(input)
-		(text "sel[2..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
-		(text "sel[2..0]" (rect 66 137 78 175)(font "Arial" (font_size 8))(vertical))
+		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
-		(line (pt 72 192)(pt 72 180)(line_width 3))
+		(line (pt 80 192)(pt 80 180)(line_width 3))
 	)
 	(port
-		(pt 144 104)
+		(pt 152 104)
 		(output)
-		(text "result[23..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "result[23..0]" (rect 85 91 142 103)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
-		(line (pt 144 104)(pt 80 104)(line_width 3))
+		(line (pt 152 104)(pt 88 104)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 184))
+		(line (pt 72 24)(pt 72 184)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 88 32)(pt 88 176)(line_width 1))
-		(line (pt 64 184)(pt 80 176))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
-		(line (pt 80 32)(pt 80 176))
+		(line (pt 72 184)(pt 88 176)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 72 162)(pt 78 168)(line_width 1))
-		(line (pt 146 0)(pt 146 194))
+		(line (pt 78 168)(pt 72 174)(line_width 1))
-		(line (pt 0 194)(pt 146 194))
-		(line (pt 0 0)(pt 0 194))
-		(line (pt 64 162)(pt 70 168))
-		(line (pt 70 168)(pt 64 174))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_mux6.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux6.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_mux6.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"]

Video/lpm_mux6.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_mux6.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -275,7 +275,7 @@ BEGIN
 	sub_wire2(0, 22)    <= sub_wire9(22);
 	sub_wire2(0, 23)    <= sub_wire9(23);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_pipeline => 2,
 		lpm_size => 8,
@@ -284,9 +284,9 @@ BEGIN
 		lpm_widths => 3
 	)
 	PORT MAP (
+		sel => sel,
 		clock => clock,
 		data => sub_wire2,
-		sel => sel,
 		result => sub_wire0
 	);
 
@@ -299,38 +299,37 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL "data0x[23..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0]
--- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL "data1x[23..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0]
--- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL "data2x[23..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0]
--- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL "data3x[23..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0]
--- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL "data4x[23..0]"
+-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0]
--- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL "data5x[23..0]"
+-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0]
--- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL "data6x[23..0]"
+-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0]
--- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL "data7x[23..0]"
+-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0]
--- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
+-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0]
--- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
--- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
 -- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_muxDZ.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2009 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,67 +18,59 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 144 112)
+	(rect 0 0 168 112)
-	(text "lpm_muxDZ" (rect 37 0 123 16)(font "Arial" (font_size 10)))
+	(text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 97 26 108)(font "Arial" ))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data1x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data1x[127..0]" (rect 4 27 73 39)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 80 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data0x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data0x[127..0]" (rect 4 43 73 55)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 80 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 59 29 71)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72))
+		(line (pt 0 72)(pt 80 72)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "clken" (rect 0 0 30 13)(font "Arial" (font_size 8)))
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clken" (rect 4 75 29 87)(font "Arial" (font_size 8)))
+		(text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88))
+		(line (pt 0 88)(pt 80 88)(line_width 1))
 	)
 	(port
-		(pt 72 112)
+		(pt 88 112)
 		(input)
-		(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
-		(text "sel" (rect 66 81 78 95)(font "Arial" (font_size 8))(vertical))
+		(text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8)))
-		(line (pt 72 112)(pt 72 100))
+		(line (pt 88 112)(pt 88 100)(line_width 1))
 	)
 	(port
-		(pt 144 64)
+		(pt 168 64)
 		(output)
-		(text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "result[127..0]" (rect 79 51 142 63)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8)))
-		(line (pt 144 64)(pt 80 64)(line_width 3))
+		(line (pt 168 64)(pt 96 64)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 104))
+		(line (pt 80 24)(pt 80 104)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 96 32)(pt 96 96)(line_width 1))
-		(line (pt 64 104)(pt 80 96))
+		(line (pt 80 24)(pt 96 32)(line_width 1))
-		(line (pt 80 32)(pt 80 96))
+		(line (pt 80 104)(pt 96 96)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 80 66)(pt 86 72)(line_width 1))
-		(line (pt 146 0)(pt 146 114))
+		(line (pt 86 72)(pt 80 78)(line_width 1))
-		(line (pt 0 114)(pt 146 114))
-		(line (pt 0 0)(pt 0 114))
-		(line (pt 64 66)(pt 70 72))
-		(line (pt 70 72)(pt 64 78))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_muxDZ.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2009 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_muxDZ.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"]

Video/lpm_muxDZ.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_muxDZ.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2009 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -57,276 +57,276 @@ ARCHITECTURE SYN OF lpm_muxdz IS
 --	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (127 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (127 DOWNTO 0);
 
 BEGIN
-	sub_wire3    <= data0x(127 DOWNTO 0);
+	sub_wire5    <= data0x(127 DOWNTO 0);
 	result    <= sub_wire0(127 DOWNTO 0);
-	sub_wire1    <= data1x(127 DOWNTO 0);
+	sub_wire1    <= sel;
-	sub_wire2(1, 0)    <= sub_wire1(0);
+	sub_wire2(0)    <= sub_wire1;
-	sub_wire2(1, 1)    <= sub_wire1(1);
+	sub_wire3    <= data1x(127 DOWNTO 0);
-	sub_wire2(1, 2)    <= sub_wire1(2);
+	sub_wire4(1, 0)    <= sub_wire3(0);
-	sub_wire2(1, 3)    <= sub_wire1(3);
+	sub_wire4(1, 1)    <= sub_wire3(1);
-	sub_wire2(1, 4)    <= sub_wire1(4);
+	sub_wire4(1, 2)    <= sub_wire3(2);
-	sub_wire2(1, 5)    <= sub_wire1(5);
+	sub_wire4(1, 3)    <= sub_wire3(3);
-	sub_wire2(1, 6)    <= sub_wire1(6);
+	sub_wire4(1, 4)    <= sub_wire3(4);
-	sub_wire2(1, 7)    <= sub_wire1(7);
+	sub_wire4(1, 5)    <= sub_wire3(5);
-	sub_wire2(1, 8)    <= sub_wire1(8);
+	sub_wire4(1, 6)    <= sub_wire3(6);
-	sub_wire2(1, 9)    <= sub_wire1(9);
+	sub_wire4(1, 7)    <= sub_wire3(7);
-	sub_wire2(1, 10)    <= sub_wire1(10);
+	sub_wire4(1, 8)    <= sub_wire3(8);
-	sub_wire2(1, 11)    <= sub_wire1(11);
+	sub_wire4(1, 9)    <= sub_wire3(9);
-	sub_wire2(1, 12)    <= sub_wire1(12);
+	sub_wire4(1, 10)    <= sub_wire3(10);
-	sub_wire2(1, 13)    <= sub_wire1(13);
+	sub_wire4(1, 11)    <= sub_wire3(11);
-	sub_wire2(1, 14)    <= sub_wire1(14);
+	sub_wire4(1, 12)    <= sub_wire3(12);
-	sub_wire2(1, 15)    <= sub_wire1(15);
+	sub_wire4(1, 13)    <= sub_wire3(13);
-	sub_wire2(1, 16)    <= sub_wire1(16);
+	sub_wire4(1, 14)    <= sub_wire3(14);
-	sub_wire2(1, 17)    <= sub_wire1(17);
+	sub_wire4(1, 15)    <= sub_wire3(15);
-	sub_wire2(1, 18)    <= sub_wire1(18);
+	sub_wire4(1, 16)    <= sub_wire3(16);
-	sub_wire2(1, 19)    <= sub_wire1(19);
+	sub_wire4(1, 17)    <= sub_wire3(17);
-	sub_wire2(1, 20)    <= sub_wire1(20);
+	sub_wire4(1, 18)    <= sub_wire3(18);
-	sub_wire2(1, 21)    <= sub_wire1(21);
+	sub_wire4(1, 19)    <= sub_wire3(19);
-	sub_wire2(1, 22)    <= sub_wire1(22);
+	sub_wire4(1, 20)    <= sub_wire3(20);
-	sub_wire2(1, 23)    <= sub_wire1(23);
+	sub_wire4(1, 21)    <= sub_wire3(21);
-	sub_wire2(1, 24)    <= sub_wire1(24);
+	sub_wire4(1, 22)    <= sub_wire3(22);
-	sub_wire2(1, 25)    <= sub_wire1(25);
+	sub_wire4(1, 23)    <= sub_wire3(23);
-	sub_wire2(1, 26)    <= sub_wire1(26);
+	sub_wire4(1, 24)    <= sub_wire3(24);
-	sub_wire2(1, 27)    <= sub_wire1(27);
+	sub_wire4(1, 25)    <= sub_wire3(25);
-	sub_wire2(1, 28)    <= sub_wire1(28);
+	sub_wire4(1, 26)    <= sub_wire3(26);
-	sub_wire2(1, 29)    <= sub_wire1(29);
+	sub_wire4(1, 27)    <= sub_wire3(27);
-	sub_wire2(1, 30)    <= sub_wire1(30);
+	sub_wire4(1, 28)    <= sub_wire3(28);
-	sub_wire2(1, 31)    <= sub_wire1(31);
+	sub_wire4(1, 29)    <= sub_wire3(29);
-	sub_wire2(1, 32)    <= sub_wire1(32);
+	sub_wire4(1, 30)    <= sub_wire3(30);
-	sub_wire2(1, 33)    <= sub_wire1(33);
+	sub_wire4(1, 31)    <= sub_wire3(31);
-	sub_wire2(1, 34)    <= sub_wire1(34);
+	sub_wire4(1, 32)    <= sub_wire3(32);
-	sub_wire2(1, 35)    <= sub_wire1(35);
+	sub_wire4(1, 33)    <= sub_wire3(33);
-	sub_wire2(1, 36)    <= sub_wire1(36);
+	sub_wire4(1, 34)    <= sub_wire3(34);
-	sub_wire2(1, 37)    <= sub_wire1(37);
+	sub_wire4(1, 35)    <= sub_wire3(35);
-	sub_wire2(1, 38)    <= sub_wire1(38);
+	sub_wire4(1, 36)    <= sub_wire3(36);
-	sub_wire2(1, 39)    <= sub_wire1(39);
+	sub_wire4(1, 37)    <= sub_wire3(37);
-	sub_wire2(1, 40)    <= sub_wire1(40);
+	sub_wire4(1, 38)    <= sub_wire3(38);
-	sub_wire2(1, 41)    <= sub_wire1(41);
+	sub_wire4(1, 39)    <= sub_wire3(39);
-	sub_wire2(1, 42)    <= sub_wire1(42);
+	sub_wire4(1, 40)    <= sub_wire3(40);
-	sub_wire2(1, 43)    <= sub_wire1(43);
+	sub_wire4(1, 41)    <= sub_wire3(41);
-	sub_wire2(1, 44)    <= sub_wire1(44);
+	sub_wire4(1, 42)    <= sub_wire3(42);
-	sub_wire2(1, 45)    <= sub_wire1(45);
+	sub_wire4(1, 43)    <= sub_wire3(43);
-	sub_wire2(1, 46)    <= sub_wire1(46);
+	sub_wire4(1, 44)    <= sub_wire3(44);
-	sub_wire2(1, 47)    <= sub_wire1(47);
+	sub_wire4(1, 45)    <= sub_wire3(45);
-	sub_wire2(1, 48)    <= sub_wire1(48);
+	sub_wire4(1, 46)    <= sub_wire3(46);
-	sub_wire2(1, 49)    <= sub_wire1(49);
+	sub_wire4(1, 47)    <= sub_wire3(47);
-	sub_wire2(1, 50)    <= sub_wire1(50);
+	sub_wire4(1, 48)    <= sub_wire3(48);
-	sub_wire2(1, 51)    <= sub_wire1(51);
+	sub_wire4(1, 49)    <= sub_wire3(49);
-	sub_wire2(1, 52)    <= sub_wire1(52);
+	sub_wire4(1, 50)    <= sub_wire3(50);
-	sub_wire2(1, 53)    <= sub_wire1(53);
+	sub_wire4(1, 51)    <= sub_wire3(51);
-	sub_wire2(1, 54)    <= sub_wire1(54);
+	sub_wire4(1, 52)    <= sub_wire3(52);
-	sub_wire2(1, 55)    <= sub_wire1(55);
+	sub_wire4(1, 53)    <= sub_wire3(53);
-	sub_wire2(1, 56)    <= sub_wire1(56);
+	sub_wire4(1, 54)    <= sub_wire3(54);
-	sub_wire2(1, 57)    <= sub_wire1(57);
+	sub_wire4(1, 55)    <= sub_wire3(55);
-	sub_wire2(1, 58)    <= sub_wire1(58);
+	sub_wire4(1, 56)    <= sub_wire3(56);
-	sub_wire2(1, 59)    <= sub_wire1(59);
+	sub_wire4(1, 57)    <= sub_wire3(57);
-	sub_wire2(1, 60)    <= sub_wire1(60);
+	sub_wire4(1, 58)    <= sub_wire3(58);
-	sub_wire2(1, 61)    <= sub_wire1(61);
+	sub_wire4(1, 59)    <= sub_wire3(59);
-	sub_wire2(1, 62)    <= sub_wire1(62);
+	sub_wire4(1, 60)    <= sub_wire3(60);
-	sub_wire2(1, 63)    <= sub_wire1(63);
+	sub_wire4(1, 61)    <= sub_wire3(61);
-	sub_wire2(1, 64)    <= sub_wire1(64);
+	sub_wire4(1, 62)    <= sub_wire3(62);
-	sub_wire2(1, 65)    <= sub_wire1(65);
+	sub_wire4(1, 63)    <= sub_wire3(63);
-	sub_wire2(1, 66)    <= sub_wire1(66);
+	sub_wire4(1, 64)    <= sub_wire3(64);
-	sub_wire2(1, 67)    <= sub_wire1(67);
+	sub_wire4(1, 65)    <= sub_wire3(65);
-	sub_wire2(1, 68)    <= sub_wire1(68);
+	sub_wire4(1, 66)    <= sub_wire3(66);
-	sub_wire2(1, 69)    <= sub_wire1(69);
+	sub_wire4(1, 67)    <= sub_wire3(67);
-	sub_wire2(1, 70)    <= sub_wire1(70);
+	sub_wire4(1, 68)    <= sub_wire3(68);
-	sub_wire2(1, 71)    <= sub_wire1(71);
+	sub_wire4(1, 69)    <= sub_wire3(69);
-	sub_wire2(1, 72)    <= sub_wire1(72);
+	sub_wire4(1, 70)    <= sub_wire3(70);
-	sub_wire2(1, 73)    <= sub_wire1(73);
+	sub_wire4(1, 71)    <= sub_wire3(71);
-	sub_wire2(1, 74)    <= sub_wire1(74);
+	sub_wire4(1, 72)    <= sub_wire3(72);
-	sub_wire2(1, 75)    <= sub_wire1(75);
+	sub_wire4(1, 73)    <= sub_wire3(73);
-	sub_wire2(1, 76)    <= sub_wire1(76);
+	sub_wire4(1, 74)    <= sub_wire3(74);
-	sub_wire2(1, 77)    <= sub_wire1(77);
+	sub_wire4(1, 75)    <= sub_wire3(75);
-	sub_wire2(1, 78)    <= sub_wire1(78);
+	sub_wire4(1, 76)    <= sub_wire3(76);
-	sub_wire2(1, 79)    <= sub_wire1(79);
+	sub_wire4(1, 77)    <= sub_wire3(77);
-	sub_wire2(1, 80)    <= sub_wire1(80);
+	sub_wire4(1, 78)    <= sub_wire3(78);
-	sub_wire2(1, 81)    <= sub_wire1(81);
+	sub_wire4(1, 79)    <= sub_wire3(79);
-	sub_wire2(1, 82)    <= sub_wire1(82);
+	sub_wire4(1, 80)    <= sub_wire3(80);
-	sub_wire2(1, 83)    <= sub_wire1(83);
+	sub_wire4(1, 81)    <= sub_wire3(81);
-	sub_wire2(1, 84)    <= sub_wire1(84);
+	sub_wire4(1, 82)    <= sub_wire3(82);
-	sub_wire2(1, 85)    <= sub_wire1(85);
+	sub_wire4(1, 83)    <= sub_wire3(83);
-	sub_wire2(1, 86)    <= sub_wire1(86);
+	sub_wire4(1, 84)    <= sub_wire3(84);
-	sub_wire2(1, 87)    <= sub_wire1(87);
+	sub_wire4(1, 85)    <= sub_wire3(85);
-	sub_wire2(1, 88)    <= sub_wire1(88);
+	sub_wire4(1, 86)    <= sub_wire3(86);
-	sub_wire2(1, 89)    <= sub_wire1(89);
+	sub_wire4(1, 87)    <= sub_wire3(87);
-	sub_wire2(1, 90)    <= sub_wire1(90);
+	sub_wire4(1, 88)    <= sub_wire3(88);
-	sub_wire2(1, 91)    <= sub_wire1(91);
+	sub_wire4(1, 89)    <= sub_wire3(89);
-	sub_wire2(1, 92)    <= sub_wire1(92);
+	sub_wire4(1, 90)    <= sub_wire3(90);
-	sub_wire2(1, 93)    <= sub_wire1(93);
+	sub_wire4(1, 91)    <= sub_wire3(91);
-	sub_wire2(1, 94)    <= sub_wire1(94);
+	sub_wire4(1, 92)    <= sub_wire3(92);
-	sub_wire2(1, 95)    <= sub_wire1(95);
+	sub_wire4(1, 93)    <= sub_wire3(93);
-	sub_wire2(1, 96)    <= sub_wire1(96);
+	sub_wire4(1, 94)    <= sub_wire3(94);
-	sub_wire2(1, 97)    <= sub_wire1(97);
+	sub_wire4(1, 95)    <= sub_wire3(95);
-	sub_wire2(1, 98)    <= sub_wire1(98);
+	sub_wire4(1, 96)    <= sub_wire3(96);
-	sub_wire2(1, 99)    <= sub_wire1(99);
+	sub_wire4(1, 97)    <= sub_wire3(97);
-	sub_wire2(1, 100)    <= sub_wire1(100);
+	sub_wire4(1, 98)    <= sub_wire3(98);
-	sub_wire2(1, 101)    <= sub_wire1(101);
+	sub_wire4(1, 99)    <= sub_wire3(99);
-	sub_wire2(1, 102)    <= sub_wire1(102);
+	sub_wire4(1, 100)    <= sub_wire3(100);
-	sub_wire2(1, 103)    <= sub_wire1(103);
+	sub_wire4(1, 101)    <= sub_wire3(101);
-	sub_wire2(1, 104)    <= sub_wire1(104);
+	sub_wire4(1, 102)    <= sub_wire3(102);
-	sub_wire2(1, 105)    <= sub_wire1(105);
+	sub_wire4(1, 103)    <= sub_wire3(103);
-	sub_wire2(1, 106)    <= sub_wire1(106);
+	sub_wire4(1, 104)    <= sub_wire3(104);
-	sub_wire2(1, 107)    <= sub_wire1(107);
+	sub_wire4(1, 105)    <= sub_wire3(105);
-	sub_wire2(1, 108)    <= sub_wire1(108);
+	sub_wire4(1, 106)    <= sub_wire3(106);
-	sub_wire2(1, 109)    <= sub_wire1(109);
+	sub_wire4(1, 107)    <= sub_wire3(107);
-	sub_wire2(1, 110)    <= sub_wire1(110);
+	sub_wire4(1, 108)    <= sub_wire3(108);
-	sub_wire2(1, 111)    <= sub_wire1(111);
+	sub_wire4(1, 109)    <= sub_wire3(109);
-	sub_wire2(1, 112)    <= sub_wire1(112);
+	sub_wire4(1, 110)    <= sub_wire3(110);
-	sub_wire2(1, 113)    <= sub_wire1(113);
+	sub_wire4(1, 111)    <= sub_wire3(111);
-	sub_wire2(1, 114)    <= sub_wire1(114);
+	sub_wire4(1, 112)    <= sub_wire3(112);
-	sub_wire2(1, 115)    <= sub_wire1(115);
+	sub_wire4(1, 113)    <= sub_wire3(113);
-	sub_wire2(1, 116)    <= sub_wire1(116);
+	sub_wire4(1, 114)    <= sub_wire3(114);
-	sub_wire2(1, 117)    <= sub_wire1(117);
+	sub_wire4(1, 115)    <= sub_wire3(115);
-	sub_wire2(1, 118)    <= sub_wire1(118);
+	sub_wire4(1, 116)    <= sub_wire3(116);
-	sub_wire2(1, 119)    <= sub_wire1(119);
+	sub_wire4(1, 117)    <= sub_wire3(117);
-	sub_wire2(1, 120)    <= sub_wire1(120);
+	sub_wire4(1, 118)    <= sub_wire3(118);
-	sub_wire2(1, 121)    <= sub_wire1(121);
+	sub_wire4(1, 119)    <= sub_wire3(119);
-	sub_wire2(1, 122)    <= sub_wire1(122);
+	sub_wire4(1, 120)    <= sub_wire3(120);
-	sub_wire2(1, 123)    <= sub_wire1(123);
+	sub_wire4(1, 121)    <= sub_wire3(121);
-	sub_wire2(1, 124)    <= sub_wire1(124);
+	sub_wire4(1, 122)    <= sub_wire3(122);
-	sub_wire2(1, 125)    <= sub_wire1(125);
+	sub_wire4(1, 123)    <= sub_wire3(123);
-	sub_wire2(1, 126)    <= sub_wire1(126);
+	sub_wire4(1, 124)    <= sub_wire3(124);
-	sub_wire2(1, 127)    <= sub_wire1(127);
+	sub_wire4(1, 125)    <= sub_wire3(125);
-	sub_wire2(0, 0)    <= sub_wire3(0);
+	sub_wire4(1, 126)    <= sub_wire3(126);
-	sub_wire2(0, 1)    <= sub_wire3(1);
+	sub_wire4(1, 127)    <= sub_wire3(127);
-	sub_wire2(0, 2)    <= sub_wire3(2);
+	sub_wire4(0, 0)    <= sub_wire5(0);
-	sub_wire2(0, 3)    <= sub_wire3(3);
+	sub_wire4(0, 1)    <= sub_wire5(1);
-	sub_wire2(0, 4)    <= sub_wire3(4);
+	sub_wire4(0, 2)    <= sub_wire5(2);
-	sub_wire2(0, 5)    <= sub_wire3(5);
+	sub_wire4(0, 3)    <= sub_wire5(3);
-	sub_wire2(0, 6)    <= sub_wire3(6);
+	sub_wire4(0, 4)    <= sub_wire5(4);
-	sub_wire2(0, 7)    <= sub_wire3(7);
+	sub_wire4(0, 5)    <= sub_wire5(5);
-	sub_wire2(0, 8)    <= sub_wire3(8);
+	sub_wire4(0, 6)    <= sub_wire5(6);
-	sub_wire2(0, 9)    <= sub_wire3(9);
+	sub_wire4(0, 7)    <= sub_wire5(7);
-	sub_wire2(0, 10)    <= sub_wire3(10);
+	sub_wire4(0, 8)    <= sub_wire5(8);
-	sub_wire2(0, 11)    <= sub_wire3(11);
+	sub_wire4(0, 9)    <= sub_wire5(9);
-	sub_wire2(0, 12)    <= sub_wire3(12);
+	sub_wire4(0, 10)    <= sub_wire5(10);
-	sub_wire2(0, 13)    <= sub_wire3(13);
+	sub_wire4(0, 11)    <= sub_wire5(11);
-	sub_wire2(0, 14)    <= sub_wire3(14);
+	sub_wire4(0, 12)    <= sub_wire5(12);
-	sub_wire2(0, 15)    <= sub_wire3(15);
+	sub_wire4(0, 13)    <= sub_wire5(13);
-	sub_wire2(0, 16)    <= sub_wire3(16);
+	sub_wire4(0, 14)    <= sub_wire5(14);
-	sub_wire2(0, 17)    <= sub_wire3(17);
+	sub_wire4(0, 15)    <= sub_wire5(15);
-	sub_wire2(0, 18)    <= sub_wire3(18);
+	sub_wire4(0, 16)    <= sub_wire5(16);
-	sub_wire2(0, 19)    <= sub_wire3(19);
+	sub_wire4(0, 17)    <= sub_wire5(17);
-	sub_wire2(0, 20)    <= sub_wire3(20);
+	sub_wire4(0, 18)    <= sub_wire5(18);
-	sub_wire2(0, 21)    <= sub_wire3(21);
+	sub_wire4(0, 19)    <= sub_wire5(19);
-	sub_wire2(0, 22)    <= sub_wire3(22);
+	sub_wire4(0, 20)    <= sub_wire5(20);
-	sub_wire2(0, 23)    <= sub_wire3(23);
+	sub_wire4(0, 21)    <= sub_wire5(21);
-	sub_wire2(0, 24)    <= sub_wire3(24);
+	sub_wire4(0, 22)    <= sub_wire5(22);
-	sub_wire2(0, 25)    <= sub_wire3(25);
+	sub_wire4(0, 23)    <= sub_wire5(23);
-	sub_wire2(0, 26)    <= sub_wire3(26);
+	sub_wire4(0, 24)    <= sub_wire5(24);
-	sub_wire2(0, 27)    <= sub_wire3(27);
+	sub_wire4(0, 25)    <= sub_wire5(25);
-	sub_wire2(0, 28)    <= sub_wire3(28);
+	sub_wire4(0, 26)    <= sub_wire5(26);
-	sub_wire2(0, 29)    <= sub_wire3(29);
+	sub_wire4(0, 27)    <= sub_wire5(27);
-	sub_wire2(0, 30)    <= sub_wire3(30);
+	sub_wire4(0, 28)    <= sub_wire5(28);
-	sub_wire2(0, 31)    <= sub_wire3(31);
+	sub_wire4(0, 29)    <= sub_wire5(29);
-	sub_wire2(0, 32)    <= sub_wire3(32);
+	sub_wire4(0, 30)    <= sub_wire5(30);
-	sub_wire2(0, 33)    <= sub_wire3(33);
+	sub_wire4(0, 31)    <= sub_wire5(31);
-	sub_wire2(0, 34)    <= sub_wire3(34);
+	sub_wire4(0, 32)    <= sub_wire5(32);
-	sub_wire2(0, 35)    <= sub_wire3(35);
+	sub_wire4(0, 33)    <= sub_wire5(33);
-	sub_wire2(0, 36)    <= sub_wire3(36);
+	sub_wire4(0, 34)    <= sub_wire5(34);
-	sub_wire2(0, 37)    <= sub_wire3(37);
+	sub_wire4(0, 35)    <= sub_wire5(35);
-	sub_wire2(0, 38)    <= sub_wire3(38);
+	sub_wire4(0, 36)    <= sub_wire5(36);
-	sub_wire2(0, 39)    <= sub_wire3(39);
+	sub_wire4(0, 37)    <= sub_wire5(37);
-	sub_wire2(0, 40)    <= sub_wire3(40);
+	sub_wire4(0, 38)    <= sub_wire5(38);
-	sub_wire2(0, 41)    <= sub_wire3(41);
+	sub_wire4(0, 39)    <= sub_wire5(39);
-	sub_wire2(0, 42)    <= sub_wire3(42);
+	sub_wire4(0, 40)    <= sub_wire5(40);
-	sub_wire2(0, 43)    <= sub_wire3(43);
+	sub_wire4(0, 41)    <= sub_wire5(41);
-	sub_wire2(0, 44)    <= sub_wire3(44);
+	sub_wire4(0, 42)    <= sub_wire5(42);
-	sub_wire2(0, 45)    <= sub_wire3(45);
+	sub_wire4(0, 43)    <= sub_wire5(43);
-	sub_wire2(0, 46)    <= sub_wire3(46);
+	sub_wire4(0, 44)    <= sub_wire5(44);
-	sub_wire2(0, 47)    <= sub_wire3(47);
+	sub_wire4(0, 45)    <= sub_wire5(45);
-	sub_wire2(0, 48)    <= sub_wire3(48);
+	sub_wire4(0, 46)    <= sub_wire5(46);
-	sub_wire2(0, 49)    <= sub_wire3(49);
+	sub_wire4(0, 47)    <= sub_wire5(47);
-	sub_wire2(0, 50)    <= sub_wire3(50);
+	sub_wire4(0, 48)    <= sub_wire5(48);
-	sub_wire2(0, 51)    <= sub_wire3(51);
+	sub_wire4(0, 49)    <= sub_wire5(49);
-	sub_wire2(0, 52)    <= sub_wire3(52);
+	sub_wire4(0, 50)    <= sub_wire5(50);
-	sub_wire2(0, 53)    <= sub_wire3(53);
+	sub_wire4(0, 51)    <= sub_wire5(51);
-	sub_wire2(0, 54)    <= sub_wire3(54);
+	sub_wire4(0, 52)    <= sub_wire5(52);
-	sub_wire2(0, 55)    <= sub_wire3(55);
+	sub_wire4(0, 53)    <= sub_wire5(53);
-	sub_wire2(0, 56)    <= sub_wire3(56);
+	sub_wire4(0, 54)    <= sub_wire5(54);
-	sub_wire2(0, 57)    <= sub_wire3(57);
+	sub_wire4(0, 55)    <= sub_wire5(55);
-	sub_wire2(0, 58)    <= sub_wire3(58);
+	sub_wire4(0, 56)    <= sub_wire5(56);
-	sub_wire2(0, 59)    <= sub_wire3(59);
+	sub_wire4(0, 57)    <= sub_wire5(57);
-	sub_wire2(0, 60)    <= sub_wire3(60);
+	sub_wire4(0, 58)    <= sub_wire5(58);
-	sub_wire2(0, 61)    <= sub_wire3(61);
+	sub_wire4(0, 59)    <= sub_wire5(59);
-	sub_wire2(0, 62)    <= sub_wire3(62);
+	sub_wire4(0, 60)    <= sub_wire5(60);
-	sub_wire2(0, 63)    <= sub_wire3(63);
+	sub_wire4(0, 61)    <= sub_wire5(61);
-	sub_wire2(0, 64)    <= sub_wire3(64);
+	sub_wire4(0, 62)    <= sub_wire5(62);
-	sub_wire2(0, 65)    <= sub_wire3(65);
+	sub_wire4(0, 63)    <= sub_wire5(63);
-	sub_wire2(0, 66)    <= sub_wire3(66);
+	sub_wire4(0, 64)    <= sub_wire5(64);
-	sub_wire2(0, 67)    <= sub_wire3(67);
+	sub_wire4(0, 65)    <= sub_wire5(65);
-	sub_wire2(0, 68)    <= sub_wire3(68);
+	sub_wire4(0, 66)    <= sub_wire5(66);
-	sub_wire2(0, 69)    <= sub_wire3(69);
+	sub_wire4(0, 67)    <= sub_wire5(67);
-	sub_wire2(0, 70)    <= sub_wire3(70);
+	sub_wire4(0, 68)    <= sub_wire5(68);
-	sub_wire2(0, 71)    <= sub_wire3(71);
+	sub_wire4(0, 69)    <= sub_wire5(69);
-	sub_wire2(0, 72)    <= sub_wire3(72);
+	sub_wire4(0, 70)    <= sub_wire5(70);
-	sub_wire2(0, 73)    <= sub_wire3(73);
+	sub_wire4(0, 71)    <= sub_wire5(71);
-	sub_wire2(0, 74)    <= sub_wire3(74);
+	sub_wire4(0, 72)    <= sub_wire5(72);
-	sub_wire2(0, 75)    <= sub_wire3(75);
+	sub_wire4(0, 73)    <= sub_wire5(73);
-	sub_wire2(0, 76)    <= sub_wire3(76);
+	sub_wire4(0, 74)    <= sub_wire5(74);
-	sub_wire2(0, 77)    <= sub_wire3(77);
+	sub_wire4(0, 75)    <= sub_wire5(75);
-	sub_wire2(0, 78)    <= sub_wire3(78);
+	sub_wire4(0, 76)    <= sub_wire5(76);
-	sub_wire2(0, 79)    <= sub_wire3(79);
+	sub_wire4(0, 77)    <= sub_wire5(77);
-	sub_wire2(0, 80)    <= sub_wire3(80);
+	sub_wire4(0, 78)    <= sub_wire5(78);
-	sub_wire2(0, 81)    <= sub_wire3(81);
+	sub_wire4(0, 79)    <= sub_wire5(79);
-	sub_wire2(0, 82)    <= sub_wire3(82);
+	sub_wire4(0, 80)    <= sub_wire5(80);
-	sub_wire2(0, 83)    <= sub_wire3(83);
+	sub_wire4(0, 81)    <= sub_wire5(81);
-	sub_wire2(0, 84)    <= sub_wire3(84);
+	sub_wire4(0, 82)    <= sub_wire5(82);
-	sub_wire2(0, 85)    <= sub_wire3(85);
+	sub_wire4(0, 83)    <= sub_wire5(83);
-	sub_wire2(0, 86)    <= sub_wire3(86);
+	sub_wire4(0, 84)    <= sub_wire5(84);
-	sub_wire2(0, 87)    <= sub_wire3(87);
+	sub_wire4(0, 85)    <= sub_wire5(85);
-	sub_wire2(0, 88)    <= sub_wire3(88);
+	sub_wire4(0, 86)    <= sub_wire5(86);
-	sub_wire2(0, 89)    <= sub_wire3(89);
+	sub_wire4(0, 87)    <= sub_wire5(87);
-	sub_wire2(0, 90)    <= sub_wire3(90);
+	sub_wire4(0, 88)    <= sub_wire5(88);
-	sub_wire2(0, 91)    <= sub_wire3(91);
+	sub_wire4(0, 89)    <= sub_wire5(89);
-	sub_wire2(0, 92)    <= sub_wire3(92);
+	sub_wire4(0, 90)    <= sub_wire5(90);
-	sub_wire2(0, 93)    <= sub_wire3(93);
+	sub_wire4(0, 91)    <= sub_wire5(91);
-	sub_wire2(0, 94)    <= sub_wire3(94);
+	sub_wire4(0, 92)    <= sub_wire5(92);
-	sub_wire2(0, 95)    <= sub_wire3(95);
+	sub_wire4(0, 93)    <= sub_wire5(93);
-	sub_wire2(0, 96)    <= sub_wire3(96);
+	sub_wire4(0, 94)    <= sub_wire5(94);
-	sub_wire2(0, 97)    <= sub_wire3(97);
+	sub_wire4(0, 95)    <= sub_wire5(95);
-	sub_wire2(0, 98)    <= sub_wire3(98);
+	sub_wire4(0, 96)    <= sub_wire5(96);
-	sub_wire2(0, 99)    <= sub_wire3(99);
+	sub_wire4(0, 97)    <= sub_wire5(97);
-	sub_wire2(0, 100)    <= sub_wire3(100);
+	sub_wire4(0, 98)    <= sub_wire5(98);
-	sub_wire2(0, 101)    <= sub_wire3(101);
+	sub_wire4(0, 99)    <= sub_wire5(99);
-	sub_wire2(0, 102)    <= sub_wire3(102);
+	sub_wire4(0, 100)    <= sub_wire5(100);
-	sub_wire2(0, 103)    <= sub_wire3(103);
+	sub_wire4(0, 101)    <= sub_wire5(101);
-	sub_wire2(0, 104)    <= sub_wire3(104);
+	sub_wire4(0, 102)    <= sub_wire5(102);
-	sub_wire2(0, 105)    <= sub_wire3(105);
+	sub_wire4(0, 103)    <= sub_wire5(103);
-	sub_wire2(0, 106)    <= sub_wire3(106);
+	sub_wire4(0, 104)    <= sub_wire5(104);
-	sub_wire2(0, 107)    <= sub_wire3(107);
+	sub_wire4(0, 105)    <= sub_wire5(105);
-	sub_wire2(0, 108)    <= sub_wire3(108);
+	sub_wire4(0, 106)    <= sub_wire5(106);
-	sub_wire2(0, 109)    <= sub_wire3(109);
+	sub_wire4(0, 107)    <= sub_wire5(107);
-	sub_wire2(0, 110)    <= sub_wire3(110);
+	sub_wire4(0, 108)    <= sub_wire5(108);
-	sub_wire2(0, 111)    <= sub_wire3(111);
+	sub_wire4(0, 109)    <= sub_wire5(109);
-	sub_wire2(0, 112)    <= sub_wire3(112);
+	sub_wire4(0, 110)    <= sub_wire5(110);
-	sub_wire2(0, 113)    <= sub_wire3(113);
+	sub_wire4(0, 111)    <= sub_wire5(111);
-	sub_wire2(0, 114)    <= sub_wire3(114);
+	sub_wire4(0, 112)    <= sub_wire5(112);
-	sub_wire2(0, 115)    <= sub_wire3(115);
+	sub_wire4(0, 113)    <= sub_wire5(113);
-	sub_wire2(0, 116)    <= sub_wire3(116);
+	sub_wire4(0, 114)    <= sub_wire5(114);
-	sub_wire2(0, 117)    <= sub_wire3(117);
+	sub_wire4(0, 115)    <= sub_wire5(115);
-	sub_wire2(0, 118)    <= sub_wire3(118);
+	sub_wire4(0, 116)    <= sub_wire5(116);
-	sub_wire2(0, 119)    <= sub_wire3(119);
+	sub_wire4(0, 117)    <= sub_wire5(117);
-	sub_wire2(0, 120)    <= sub_wire3(120);
+	sub_wire4(0, 118)    <= sub_wire5(118);
-	sub_wire2(0, 121)    <= sub_wire3(121);
+	sub_wire4(0, 119)    <= sub_wire5(119);
-	sub_wire2(0, 122)    <= sub_wire3(122);
+	sub_wire4(0, 120)    <= sub_wire5(120);
-	sub_wire2(0, 123)    <= sub_wire3(123);
+	sub_wire4(0, 121)    <= sub_wire5(121);
-	sub_wire2(0, 124)    <= sub_wire3(124);
+	sub_wire4(0, 122)    <= sub_wire5(122);
-	sub_wire2(0, 125)    <= sub_wire3(125);
+	sub_wire4(0, 123)    <= sub_wire5(123);
-	sub_wire2(0, 126)    <= sub_wire3(126);
+	sub_wire4(0, 124)    <= sub_wire5(124);
-	sub_wire2(0, 127)    <= sub_wire3(127);
+	sub_wire4(0, 125)    <= sub_wire5(125);
-	sub_wire4    <= sel;
+	sub_wire4(0, 126)    <= sub_wire5(126);
-	sub_wire5(0)    <= sub_wire4;
+	sub_wire4(0, 127)    <= sub_wire5(127);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_pipeline => 1,
 		lpm_size => 2,
@@ -335,10 +335,10 @@ BEGIN
 		lpm_widths => 1
 	)
 	PORT MAP (
-		clock => clock,
+		sel => sub_wire2,
-		data => sub_wire2,
-		sel => sub_wire5,
 		clken => clken,
+		clock => clock,
+		data => sub_wire4,
 		result => sub_wire0
 	);
 
@@ -351,28 +351,27 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
--- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
+-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
--- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
--- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
--- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
--- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
--- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
--- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
 -- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_muxVDM.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2009 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,149 +18,141 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 144 304)
+	(rect 0 0 168 304)
-	(text "lpm_muxVDM" (rect 31 0 131 16)(font "Arial" (font_size 10)))
+	(text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 289 26 300)(font "Arial" ))
+	(text "inst" (rect 8 288 25 300)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data15x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
-		(text "data15x[127..0]" (rect 4 27 79 39)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 80 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data14x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
-		(text "data14x[127..0]" (rect 4 43 79 55)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 80 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data13x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
-		(text "data13x[127..0]" (rect 4 59 79 71)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 3))
+		(line (pt 0 72)(pt 80 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data12x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
-		(text "data12x[127..0]" (rect 4 75 79 87)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 64 88)(line_width 3))
+		(line (pt 0 88)(pt 80 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data11x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
-		(text "data11x[127..0]" (rect 4 91 79 103)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 64 104)(line_width 3))
+		(line (pt 0 104)(pt 80 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data10x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
-		(text "data10x[127..0]" (rect 4 107 79 119)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 4 107 78 120)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 64 120)(line_width 3))
+		(line (pt 0 120)(pt 80 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data9x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data9x[127..0]" (rect 4 123 73 135)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8)))
-		(line (pt 0 136)(pt 64 136)(line_width 3))
+		(line (pt 0 136)(pt 80 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data8x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data8x[127..0]" (rect 4 139 73 151)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 64 152)(line_width 3))
+		(line (pt 0 152)(pt 80 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "data7x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data7x[127..0]" (rect 4 155 73 167)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 64 168)(line_width 3))
+		(line (pt 0 168)(pt 80 168)(line_width 3))
 	)
 	(port
 		(pt 0 184)
 		(input)
-		(text "data6x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data6x[127..0]" (rect 4 171 73 183)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8)))
-		(line (pt 0 184)(pt 64 184)(line_width 3))
+		(line (pt 0 184)(pt 80 184)(line_width 3))
 	)
 	(port
 		(pt 0 200)
 		(input)
-		(text "data5x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data5x[127..0]" (rect 4 187 73 199)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8)))
-		(line (pt 0 200)(pt 64 200)(line_width 3))
+		(line (pt 0 200)(pt 80 200)(line_width 3))
 	)
 	(port
 		(pt 0 216)
 		(input)
-		(text "data4x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data4x[127..0]" (rect 4 203 73 215)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8)))
-		(line (pt 0 216)(pt 64 216)(line_width 3))
+		(line (pt 0 216)(pt 80 216)(line_width 3))
 	)
 	(port
 		(pt 0 232)
 		(input)
-		(text "data3x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data3x[127..0]" (rect 4 219 73 231)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8)))
-		(line (pt 0 232)(pt 64 232)(line_width 3))
+		(line (pt 0 232)(pt 80 232)(line_width 3))
 	)
 	(port
 		(pt 0 248)
 		(input)
-		(text "data2x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data2x[127..0]" (rect 4 235 73 247)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 4 235 72 248)(font "Arial" (font_size 8)))
-		(line (pt 0 248)(pt 64 248)(line_width 3))
+		(line (pt 0 248)(pt 80 248)(line_width 3))
 	)
 	(port
 		(pt 0 264)
 		(input)
-		(text "data1x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data1x[127..0]" (rect 4 251 73 263)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8)))
-		(line (pt 0 264)(pt 64 264)(line_width 3))
+		(line (pt 0 264)(pt 80 264)(line_width 3))
 	)
 	(port
 		(pt 0 280)
 		(input)
-		(text "data0x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
-		(text "data0x[127..0]" (rect 4 267 73 279)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8)))
-		(line (pt 0 280)(pt 64 280)(line_width 3))
+		(line (pt 0 280)(pt 80 280)(line_width 3))
 	)
 	(port
-		(pt 72 304)
+		(pt 88 304)
 		(input)
-		(text "sel[3..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
-		(text "sel[3..0]" (rect 66 249 78 287)(font "Arial" (font_size 8))(vertical))
+		(text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8)))
-		(line (pt 72 304)(pt 72 292)(line_width 3))
+		(line (pt 88 304)(pt 88 292)(line_width 3))
 	)
 	(port
-		(pt 144 160)
+		(pt 168 160)
 		(output)
-		(text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
-		(text "result[127..0]" (rect 79 147 142 159)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8)))
-		(line (pt 144 160)(pt 80 160)(line_width 3))
+		(line (pt 168 160)(pt 96 160)(line_width 3))
 	)
 	(drawing
-		(line (pt 64 24)(pt 64 296))
+		(line (pt 80 24)(pt 80 296)(line_width 1))
-		(line (pt 64 24)(pt 80 32))
+		(line (pt 96 32)(pt 96 288)(line_width 1))
-		(line (pt 64 296)(pt 80 288))
+		(line (pt 80 24)(pt 96 32)(line_width 1))
-		(line (pt 80 32)(pt 80 288))
+		(line (pt 80 296)(pt 96 288)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
-		(line (pt 146 0)(pt 146 306))
-		(line (pt 0 306)(pt 146 306))
-		(line (pt 0 0)(pt 0 306))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_muxVDM.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2009 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_muxVDM.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"]

Video/lpm_muxVDM.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_MUX%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_MUX 
+-- MODULE: lpm_mux 
 
 -- ============================================================
 -- File Name: lpm_muxVDM.vhd
 -- Megafunction Name(s):
--- 			LPM_MUX
+-- 			lpm_mux
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2009 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -2154,7 +2154,7 @@ BEGIN
 	sub_wire2(0, 126)    <= sub_wire17(126);
 	sub_wire2(0, 127)    <= sub_wire17(127);
 
-	LPM_MUX_component : LPM_MUX
+	lpm_mux_component : lpm_mux
 	GENERIC MAP (
 		lpm_size => 16,
 		lpm_type => "LPM_MUX",
@@ -2162,8 +2162,8 @@ BEGIN
 		lpm_widths => 4
 	)
 	PORT MAP (
-		data => sub_wire2,
 		sel => sel,
+		data => sub_wire2,
 		result => sub_wire0
 	);
 
@@ -2176,51 +2176,50 @@ END SYN;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
 -- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
--- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
--- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL "data10x[127..0]"
+-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0]
--- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL "data11x[127..0]"
+-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0]
--- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL "data12x[127..0]"
+-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0]
--- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL "data13x[127..0]"
+-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0]
--- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL "data14x[127..0]"
+-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0]
--- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL "data15x[127..0]"
+-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0]
--- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
--- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL "data2x[127..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0]
--- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL "data3x[127..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0]
--- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL "data4x[127..0]"
+-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0]
--- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL "data5x[127..0]"
+-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0]
--- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL "data6x[127..0]"
+-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0]
--- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL "data7x[127..0]"
+-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0]
--- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL "data8x[127..0]"
+-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0]
--- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL "data9x[127..0]"
+-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0]
--- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
--- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
+-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
--- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
--- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
--- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
 -- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_shiftreg0.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,61 +18,53 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 144 128)
-	(text "lpm_shiftreg0" (rect 33 0 128 16)(font "Arial" (font_size 10)))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 113 26 124)(font "Arial" ))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 25 13)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 41 38)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 41 39)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 61 13)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 72 54)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 51 86)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8)))
-		(line (pt 0 80)(pt 16 80))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 48 102)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 16 96))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
-		(pt 144 64)
+		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 91 58 126 70)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8)))
-		(line (pt 144 64)(pt 128 64))
+		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 96 18 227 46)(font "Arial" ))
+		(text "left shift" (rect 92 17 128 29)(font "Arial" ))
-		(line (pt 16 16)(pt 16 112))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
-		(line (pt 16 16)(pt 128 16))
+		(line (pt 128 16)(pt 128 112)(line_width 1))
-		(line (pt 16 112)(pt 128 112))
+		(line (pt 128 112)(pt 16 112)(line_width 1))
-		(line (pt 128 16)(pt 128 112))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 16 74)(pt 22 80)(line_width 1))
-		(line (pt 146 0)(pt 146 130))
+		(line (pt 22 80)(pt 16 86)(line_width 1))
-		(line (pt 0 130)(pt 146 130))
-		(line (pt 0 0)(pt 0 130))
-		(line (pt 16 74)(pt 22 80))
-		(line (pt 22 80)(pt 16 86))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_shiftreg0.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_shiftreg0.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_shiftreg0.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]

Video/lpm_shiftreg0.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_SHIFTREG%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_SHIFTREG 
+-- MODULE: lpm_shiftreg 
 
 -- ============================================================
 -- File Name: lpm_shiftreg0.vhd
 -- Megafunction Name(s):
--- 			LPM_SHIFTREG
+-- 			lpm_shiftreg
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -64,9 +64,9 @@ ARCHITECTURE SYN OF lpm_shiftreg0 IS
 		lpm_width		: NATURAL
 	);
 	PORT (
+			load	: IN STD_LOGIC ;
 			clock	: IN STD_LOGIC ;
 			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-			load	: IN STD_LOGIC ;
 			shiftout	: OUT STD_LOGIC ;
 			shiftin	: IN STD_LOGIC 
 	);
@@ -75,16 +75,16 @@ ARCHITECTURE SYN OF lpm_shiftreg0 IS
 BEGIN
 	shiftout    <= sub_wire0;
 
-	LPM_SHIFTREG_component : LPM_SHIFTREG
+	lpm_shiftreg_component : lpm_shiftreg
 	GENERIC MAP (
 		lpm_direction => "LEFT",
 		lpm_type => "LPM_SHIFTREG",
 		lpm_width => 16
 	)
 	PORT MAP (
+		load => load,
 		clock => clock,
 		data => data,
-		load => load,
 		shiftin => shiftin,
 		shiftout => sub_wire0
 	);
@@ -113,24 +113,23 @@ END SYN;
 -- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
 -- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
 -- Retrieval info: PRIVATE: nBit NUMERIC "16"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
--- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL "load"
+-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
--- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
--- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
--- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
 -- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
 -- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_shiftreg4.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,47 +18,39 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 144 80)
-	(text "lpm_shiftreg4" (rect 33 0 129 16)(font "Arial" (font_size 10)))
+	(text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 65 26 76)(font "Arial" ))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 16 48))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 91 42 126 54)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
-		(line (pt 144 48)(pt 128 48))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
 	)
 	(drawing
-		(text "right shift" (rect 90 18 220 46)(font "Arial" ))
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
-		(line (pt 16 16)(pt 16 64))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
-		(line (pt 16 16)(pt 128 16))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
-		(line (pt 16 64)(pt 128 64))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
-		(line (pt 128 16)(pt 128 64))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
-		(line (pt 146 0)(pt 146 82))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
-		(line (pt 0 82)(pt 146 82))
-		(line (pt 0 0)(pt 0 82))
-		(line (pt 16 26)(pt 22 32))
-		(line (pt 22 32)(pt 16 38))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_shiftreg4.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_shiftreg4.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_shiftreg4.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"]

Video/lpm_shiftreg4.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_SHIFTREG%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_SHIFTREG 
+-- MODULE: lpm_shiftreg 
 
 -- ============================================================
 -- File Name: lpm_shiftreg4.vhd
 -- Megafunction Name(s):
--- 			LPM_SHIFTREG
+-- 			lpm_shiftreg
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -63,15 +63,15 @@ ARCHITECTURE SYN OF lpm_shiftreg4 IS
 	);
 	PORT (
 			clock	: IN STD_LOGIC ;
-			shiftin	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
-			shiftout	: OUT STD_LOGIC 
+			shiftin	: IN STD_LOGIC 
 	);
 	END COMPONENT;
 
 BEGIN
 	shiftout    <= sub_wire0;
 
-	LPM_SHIFTREG_component : LPM_SHIFTREG
+	lpm_shiftreg_component : lpm_shiftreg
 	GENERIC MAP (
 		lpm_direction => "RIGHT",
 		lpm_type => "LPM_SHIFTREG",
@@ -107,20 +107,19 @@ END SYN;
 -- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
 -- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
 -- Retrieval info: PRIVATE: nBit NUMERIC "5"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
--- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
 -- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
 -- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

Video/lpm_shiftreg6.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,47 +18,39 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 144 80)
-	(text "lpm_shiftreg6" (rect 33 0 128 16)(font "Arial" (font_size 10)))
+	(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 65 26 76)(font "Arial" ))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 16 48))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[4..0]" (rect 0 0 36 13)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
-		(text "q[4..0]" (rect 95 42 126 54)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "right shift" (rect 90 18 220 46)(font "Arial" ))
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
-		(line (pt 16 16)(pt 16 64))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
-		(line (pt 16 16)(pt 128 16))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
-		(line (pt 16 64)(pt 128 64))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
-		(line (pt 128 16)(pt 128 64))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
-		(line (pt 0 0)(pt 146 0))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
-		(line (pt 146 0)(pt 146 82))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
-		(line (pt 0 82)(pt 146 82))
-		(line (pt 0 0)(pt 0 82))
-		(line (pt 16 26)(pt 22 32))
-		(line (pt 22 32)(pt 16 38))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
-		(line (pt 0 0)(pt 0 0))
 	)
 )

Video/lpm_shiftreg6.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_shiftreg6.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

Video/lpm_shiftreg6.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"]

Video/lpm_shiftreg6.vhd

@@ -1,12 +1,12 @@
 -- megafunction wizard: %LPM_SHIFTREG%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
--- MODULE: LPM_SHIFTREG 
+-- MODULE: lpm_shiftreg 
 
 -- ============================================================
 -- File Name: lpm_shiftreg6.vhd
 -- Megafunction Name(s):
--- 			LPM_SHIFTREG
+-- 			lpm_shiftreg
 --
 -- Simulation Library Files(s):
 -- 			lpm
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2008 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -71,7 +71,7 @@ ARCHITECTURE SYN OF lpm_shiftreg6 IS
 BEGIN
 	q    <= sub_wire0(4 DOWNTO 0);
 
-	LPM_SHIFTREG_component : LPM_SHIFTREG
+	lpm_shiftreg_component : lpm_shiftreg
 	GENERIC MAP (
 		lpm_direction => "RIGHT",
 		lpm_type => "LPM_SHIFTREG",
@@ -107,20 +107,19 @@ END SYN;
 -- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
 -- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
 -- Retrieval info: PRIVATE: nBit NUMERIC "5"
--- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
--- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
+-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
--- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
 -- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: lpm

altddio_out3.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2013 Altera Corporation
+Copyright (C) 1991-2008 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,47 +18,47 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 192 112)
+	(rect 0 0 232 120)
-	(text "altddio_out3" (rect 57 0 156 17)(font "Dialog" (font_size 10)))
+	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 97 26 108)(font "Arial" ))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
 	(port
-		(pt 0 48)
+		(pt 0 24)
 		(input)
-		(text "datain_h[0]" (rect 0 0 73 13)(font "Dialog" (font_size 8)))
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
-		(text "datain_h[0]" (rect 4 35 67 47)(font "Dialog" (font_size 8)))
+		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 64 48)(line_width 3))
+		(line (pt 0 24)(pt 88 24)(line_width 1))
 	)
 	(port
-		(pt 0 64)
+		(pt 0 40)
 		(input)
-		(text "datain_l[0]" (rect 0 0 69 13)(font "Dialog" (font_size 8)))
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
-		(text "datain_l[0]" (rect 4 51 63 63)(font "Dialog" (font_size 8)))
+		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 64 64)(line_width 3))
+		(line (pt 0 40)(pt 88 40)(line_width 1))
 	)
 	(port
-		(pt 0 80)
+		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
-		(line (pt 0 80)(pt 64 80))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
-		(pt 192 48)
+		(pt 232 24)
 		(output)
-		(text "dataout[0]" (rect 0 0 68 13)(font "Dialog" (font_size 8)))
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
-		(text "dataout[0]" (rect 131 35 190 47)(font "Dialog" (font_size 8)))
+		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
-		(line (pt 192 48)(pt 128 48)(line_width 3))
+		(line (pt 232 24)(pt 152 24)(line_width 1))
 	)
 	(drawing
-		(line (pt 64 32)(pt 128 32))
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
-		(line (pt 128 32)(pt 128 96))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
-		(line (pt 64 96)(pt 128 96))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
-		(line (pt 64 32)(pt 64 96))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
-		(line (pt 0 0)(pt 192 0))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
-		(line (pt 192 0)(pt 192 112))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
-		(line (pt 0 112)(pt 192 112))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
-		(line (pt 0 0)(pt 0 112))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
 	)
 )