diff --git a/DSP/DSP.vhd b/DSP/DSP.vhd index 26f8e2e..22ae2ee 100644 --- a/DSP/DSP.vhd +++ b/DSP/DSP.vhd @@ -1,18 +1,18 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text +-- WARNING: Do NOT edit the input AND output ports in this file in a text -- editor if you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2008 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any +-- AND other software AND tools, AND its AMPP partner logic +-- functions, AND any output files from any of the foregoing +-- (including device programming or simulation files), AND any -- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License +-- to the terms AND conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by +-- programming logic devices manufactured by Altera AND sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. @@ -21,59 +21,57 @@ -- Created on Tue Sep 08 16:24:57 2009 LIBRARY ieee; -USE ieee.std_logic_1164.all; + USE ieee.std_logic_1164.all; -- Entity Declaration -ENTITY DSP IS +ENTITY dsp IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nRSTO : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nSRCS : INOUT STD_LOGIC; - nSRBLE : OUT STD_LOGIC; - nSRBHE : OUT STD_LOGIC; - nSRWE : OUT STD_LOGIC; - nSROE : OUT STD_LOGIC; - DSP_INT : OUT STD_LOGIC; - DSP_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - IO : INOUT STD_LOGIC_VECTOR(17 downto 0); - SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_OE : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + nRSTO : IN std_logic; + nFB_CS3 : IN std_logic; + nSRCS : INOUT std_logic; + nSRBLE : OUT std_logic; + nSRBHE : OUT std_logic; + nSRWE : OUT std_logic; + nSROE : OUT std_logic; + DSP_INT : OUT std_logic; + DSP_TA : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + IO : INOUT std_logic_vector(17 DOWNTO 0); + SRD : INOUT std_logic_vector(15 DOWNTO 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -END DSP; +END dsp; -- Architecture Body -ARCHITECTURE DSP_architecture OF DSP IS +ARCHITECTURE rtl OF dsp IS BEGIN - nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; - nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; - nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; - nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; - nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; + nSRCS <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1'; --nFB_CS3; + nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1'; + nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; + nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1'; + nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1'; DSP_INT <= '0'; DSP_TA <= '0'; - IO(17 downto 0) <= FB_ADR(18 downto 1); - SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - - -END DSP_architecture; + IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1); + SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; +END rtl; diff --git a/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index 1cfbdbe..b994a78 100644 --- a/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -1,995 +1,1024 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:20 2009 - -library work; -use work.FalconIO_SDCard_IDE_CF_pkg.all; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - --- Entity Declaration - - --- Entity Declaration - -ENTITY FalconIO_SDCard_IDE_CF IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT - ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - CLK2M : IN STD_LOGIC; - CLK500k : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - LP_BUSY : IN STD_LOGIC; - nACSI_DRQ : IN STD_LOGIC; - nACSI_INT : IN STD_LOGIC; - nSCSI_DRQ : IN STD_LOGIC; - nSCSI_MSG : IN STD_LOGIC; - MIDI_IN : IN STD_LOGIC; - RxD : IN STD_LOGIC; - CTS : IN STD_LOGIC; - RI : IN STD_LOGIC; - DCD : IN STD_LOGIC; - AMKB_RX : IN STD_LOGIC; - PIC_AMKB_RX : IN STD_LOGIC; - IDE_RDY : IN STD_LOGIC; - IDE_INT : IN STD_LOGIC; - WP_CS_CARD : IN STD_LOGIC; - nINDEX : IN STD_LOGIC; - TRACK00 : IN STD_LOGIC; - nRD_DATA : IN STD_LOGIC; - nDCHG : IN STD_LOGIC; - SD_DATA0 : IN STD_LOGIC; - SD_DATA1 : IN STD_LOGIC; - SD_DATA2 : IN STD_LOGIC; - SD_CARD_DEDECT : IN STD_LOGIC; - SD_WP : IN STD_LOGIC; - nDACK0 : IN STD_LOGIC; - nFB_WR : INOUT STD_LOGIC; - WP_CF_CARD : IN STD_LOGIC; - nWP : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - HD_DD : IN STD_LOGIC; - nSCSI_C_D : IN STD_LOGIC; - nSCSI_I_O : IN STD_LOGIC; - CLK2M4576 : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - VSYNC : IN STD_LOGIC; - HSYNC : IN STD_LOGIC; - DSP_INT : IN STD_LOGIC; - nBLANK : IN STD_LOGIC; - FDC_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); - nIDE_CS1 : OUT STD_LOGIC; - nIDE_CS0 : OUT STD_LOGIC; - LP_STR : OUT STD_LOGIC; - LP_DIR : OUT STD_LOGIC; - nACSI_ACK : OUT STD_LOGIC; - nACSI_RESET : OUT STD_LOGIC; - nACSI_CS : OUT STD_LOGIC; - ACSI_DIR : OUT STD_LOGIC; - ACSI_A1 : OUT STD_LOGIC; - nSCSI_ACK : OUT STD_LOGIC; - nSCSI_ATN : OUT STD_LOGIC; - SCSI_DIR : OUT STD_LOGIC; - SD_CLK : OUT STD_LOGIC; - YM_QA : OUT STD_LOGIC; - YM_QC : OUT STD_LOGIC; - YM_QB : OUT STD_LOGIC; - nSDSEL : OUT STD_LOGIC; - STEP : OUT STD_LOGIC; - MOT_ON : OUT STD_LOGIC; - nRP_LDS : OUT STD_LOGIC; - nRP_UDS : OUT STD_LOGIC; - nROM4 : OUT STD_LOGIC; - nROM3 : OUT STD_LOGIC; - nCF_CS1 : OUT STD_LOGIC; - nCF_CS0 : OUT STD_LOGIC; - nIDE_RD : INOUT STD_LOGIC; - nIDE_WR : INOUT STD_LOGIC; - AMKB_TX : OUT STD_LOGIC; - IDE_RES : OUT STD_LOGIC; - DTR : OUT STD_LOGIC; - RTS : OUT STD_LOGIC; - TxD : OUT STD_LOGIC; - MIDI_OLR : OUT STD_LOGIC; - MIDI_TLR : OUT STD_LOGIC; - nDREQ0 : OUT STD_LOGIC; - DSA_D : OUT STD_LOGIC; - nMFP_INT : OUT STD_LOGIC; - FALCON_IO_TA : OUT STD_LOGIC; - STEP_DIR : OUT STD_LOGIC; - WR_DATA : OUT STD_LOGIC; - WR_GATE : OUT STD_LOGIC; - DMA_DRQ : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_PAR : INOUT STD_LOGIC; - nSCSI_SEL : INOUT STD_LOGIC; - nSCSI_BUSY : INOUT STD_LOGIC; - nSCSI_RST : INOUT STD_LOGIC; - SD_CD_DATA3 : INOUT STD_LOGIC; - SD_CDM_D1 : INOUT STD_LOGIC - ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END FalconIO_SDCard_IDE_CF; - - --- Architecture Body - -ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS --- system -signal SYS_CLK : STD_LOGIC; -signal RESETn : STD_LOGIC; -signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS -signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS -signal BYT : STD_LOGIC; -- WENN BYT -> 1 -signal LONG : STD_LOGIC; -- WENN -> 1 --- KEYBOARD MIDI -signal ACIA_CS_I : STD_LOGIC; -signal IRQ_KEYBDn : STD_LOGIC; -signal IRQ_MIDIn : STD_LOGIC; -signal KEYB_RxD : STD_LOGIC; -signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); -signal MIDI_OUT : STD_LOGIC; -signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); -signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); --- MFP -signal MFP_CS : STD_LOGIC; -signal MFP_INTACK : STD_LOGIC; -signal LDS : STD_LOGIC; -signal DTACK_OUT_MFPn : STD_LOGIC; -signal IRQ_ACIAn : STD_LOGIC; -signal DINTn : STD_LOGIC; -signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); -signal TDO : STD_LOGIC; --- SOUND -signal SNDCS : STD_LOGIC; -signal SNDCS_I : STD_LOGIC; -signal SNDIR_I : STD_LOGIC; -signal LP_DIR_X : STD_LOGIC; -signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); -signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); --- DIV -signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE -signal ROM_CS : STD_LOGIC; --- DMA UND FLOPPY -signal DMA_DATEN_CS : STD_LOGIC; -signal DMA_MODUS_CS : STD_LOGIC; -signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); -signal WDC_BSL_CS : STD_LOGIC; -signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); -signal HD_DD_OUT : STD_LOGIC; -signal FDCS_In : STD_LOGIC; -signal CA0 : STD_LOGIC; -signal CA1 : STD_LOGIC; -signal CA2 : STD_LOGIC; -signal FDINT : STD_LOGIC; -signal FDRQ : STD_LOGIC; -signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_TOP_CS : STD_LOGIC; -signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_HIGH_CS : STD_LOGIC; -signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_MID_CS : STD_LOGIC; -signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_LOW_CS : STD_LOGIC; -signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_DIRM_CS : STD_LOGIC; -signal DMA_ADR_CS : STD_LOGIC; -signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); -signal DMA_DIR_OLD : STD_LOGIC; -signal DMA_BYT_CNT_CS : STD_LOGIC; -signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); -signal CLR_FIFO : STD_LOGIC; -signal DMA_DRQ_I : STD_LOGIC; -signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); -signal DMA_DRQQ : STD_LOGIC; -signal DMA_DRQ_Q : STD_LOGIC; -signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); -signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal RDF_RDE : STD_LOGIC; -signal RDF_WRE : STD_LOGIC; -signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal WRF_RDE : STD_LOGIC; -signal WRF_WRE : STD_LOGIC; -signal nFDC_WR : STD_LOGIC; -type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); -signal FCF_STATE : FCF_STATES; -signal NEXT_FCF_STATE : FCF_STATES; -signal DMA_REQ : STD_LOGIC; -signal FDC_CS : STD_LOGIC; -signal FCF_CS : STD_LOGIC; -signal FCF_APH : STD_LOGIC; -signal DMA_AZ_CS : STD_LOGIC; -signal DMA_ACTIV : STD_LOGIC; -signal DMA_ACTIV_NEW : STD_LOGIC; -signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); --- SCSI -signal SCSI_CS : STD_LOGIC; -signal SCSI_CSn : STD_LOGIC; -signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal nSCSI_DACK : STD_LOGIC; -signal SCSI_DRQ : STD_LOGIC; -signal SCSI_INT : STD_LOGIC; -signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); -signal DB_EN : STD_LOGIC; -signal DBP_OUTn : STD_LOGIC; -signal DBP_EN : STD_LOGIC; -signal RST_OUTn : STD_LOGIC; -signal RST_EN : STD_LOGIC; -signal BSY_OUTn : STD_LOGIC; -signal BSY_EN : STD_LOGIC; -signal SEL_OUTn : STD_LOGIC; -signal SEL_EN : STD_LOGIC; --- IDE -signal nnIDE_RES : STD_LOGIC; -signal IDE_CF_CS : STD_LOGIC; -signal IDE_CF_TA : STD_LOGIC; -signal NEXT_nIDE_RD : STD_LOGIC; -signal NEXT_nIDE_WR : STD_LOGIC; -type CMD_STATES is( IDLE, T1, T6, T7); -signal CMD_STATE : CMD_STATES; -signal NEXT_CMD_STATE : CMD_STATES; -SIGNAL data : std_logic_vector(31 DOWNTO 0); -SIGNAL adr : std_logic_vector(2 DOWNTO 0); -SIGNAL wr_n : std_logic; -SIGNAL rd_n : std_logic; -SIGNAL ds_n : std_logic; -SIGNAL cs_n : std_logic; -SIGNAL gpip_in_7 : std_logic; -SIGNAL gpip_in_6 : std_logic; -SIGNAL gpip_in_2 : std_logic; -SIGNAL gpip_in_1 : std_logic; -SIGNAL iack_n : std_logic; -SIGNAL dummy : std_logic; -SIGNAL io_b_en : std_logic; -BEGIN -LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; -BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; -FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; -FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; - -FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' - or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; -SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE - '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE - '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; -nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; -nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; -nDREQ0 <= '0'; ----------------------------------------------------------------------------- --- SD ----------------------------------------------------------------------------- -SD_CLK <= 'Z'; -SD_CD_DATA3 <= 'Z'; -SD_CDM_D1 <= 'Z'; ----------------------------------------------------------------------------- --- IDE ----------------------------------------------------------------------------- -CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) - begin - if nRSTO = '0' then - CMD_STATE <= IDLE; - elsif rising_edge(MAIN_CLK) then - CMD_STATE <= NEXT_CMD_STATE; -- go to next - nIDE_RD <= NEXT_nIDE_RD; -- go to next - nIDE_WR <= NEXT_nIDE_WR; -- go to next - else - CMD_STATE <= CMD_STATE; -- halten - nIDE_RD <= nIDE_RD; -- halten - nIDE_WR <= nIDE_WR; -- halten - end if; - end process CMD_REG; - - CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) - begin - case CMD_STATE is - when IDLE => - IDE_CF_TA <= '0'; - if IDE_CF_CS = '1' then - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T1; - else - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= IDLE; - end if; - when T1 => - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T6; - when T6 => - IF IDE_RDY = '1' then - IDE_CF_TA <= '1'; - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= T7; - else - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T6; - end if; - when T7 => - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= IDLE; - end case; - end process CMD_DECODER; - -IDE_RES <= not nnIDE_RES and nRSTO; -IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 -nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F -nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F -nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F -nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F ------------------------------------------------------------------------------------------------------------------------------------------ --- ACSI, SCSI UND FLOPPY WD1772 -------------------------------------------------------------------------------------------------------------------------------------------- --- daten read fifo - RDF: dcfifo0 - port map( - aclr => CLR_FIFO, - data => RDF_DIN, - rdclk => MAIN_CLK, - rdreq => RDF_RDE, - wrclk => FDC_CLK, - wrreq => RDF_WRE, - q => RDF_DOUT, - wrusedw => RDF_AZ - ); -FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY -FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY -RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE -FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; --- daten write fifo -data <= FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24); - - WRF: dcfifo1 - port map( - aclr => CLR_FIFO, - data => data, - rdclk => FDC_CLK, - rdreq => WRF_RDE, - wrclk => MAIN_CLK, - wrreq => WRF_WRE, - q => WRF_DOUT, - rdusedw => WRF_AZ - ); -CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB -DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG -FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- - process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) - begin - if nRSTO = '0' THEN - WRF_WRE <= '0'; - elsif rising_edge(MAIN_CLK) then - IF FCF_APH = '1' and nFB_WR = '0' then - WRF_WRE <= '1'; - else - WRF_WRE <= '0'; - end if; - else - WRF_WRE <= WRF_WRE; - end if; - END PROCESS; - -FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) - begin - if nRSTO = '0' then - FCF_STATE <= FCF_IDLE; - DMA_ACTIV <= '0'; - elsif rising_edge(FDC_CLK) then - FCF_STATE <= NEXT_FCF_STATE; -- go to next - DMA_ACTIV <= DMA_ACTIV_NEW; - else - FCF_STATE <= FCF_STATE; -- halten - DMA_ACTIV <= DMA_ACTIV; - end if; - end process FCF_REG; - -FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) - begin - if nRSTO = '0' then - FDC_OUT <= x"00"; - elsif rising_edge(FDC_CLK) and FDCS_In = '0' then - FDC_OUT <= CD_OUT_FDC; -- set - else - FDC_OUT <= FDC_OUT; -- halten - end if; - end process FDC_REG; - -DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; -FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; -SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; - - FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) - begin - case FCF_STATE is - when FCF_IDLE => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - WRF_RDE <= '0'; - nSCSI_DACK <= '1'; - if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then - DMA_ACTIV_NEW <= DMA_REQ; - NEXT_FCF_STATE <= FCF_T0; - else - DMA_ACTIV_NEW <= '0'; - NEXT_FCF_STATE <= FCF_IDLE; - end if; - when FCF_T0 => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - nSCSI_DACK <= '1'; - DMA_ACTIV_NEW <= DMA_REQ; - WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO - if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? - NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start - else - NEXT_FCF_STATE <= FCF_T1; - end if; - when FCF_T1 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T2; - when FCF_T2 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T3; - when FCF_T3 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T6; - when FCF_T6 => - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO - NEXT_FCF_STATE <= FCF_T7; - when FCF_T7 => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - WRF_RDE <= '0'; - nSCSI_DACK <= '1'; - DMA_ACTIV_NEW <= '0'; - if FDC_CS = '1' and DMA_REQ = '0' then - NEXT_FCF_STATE <= FCF_T7; - else - NEXT_FCF_STATE <= FCF_IDLE; - end if; - end case; - end process FCF_DECODER; - - I_FDC: WF1772IP_TOP_SOC - port map( - CLK => FDC_CLK, - RESETn => nRSTO, - CSn => FDCS_In, - RWn => nFDC_WR, - A1 => CA2, - A0 => CA1, - DATA_IN => CD_IN_FDC, - DATA_OUT => CD_OUT_FDC, --- DATA_EN => CD_EN_FDC, - RDn => nRD_DATA, - TR00n => TRACK00, - IPn => nINDEX, - WPRTn => nWP, - DDEn => '0', -- Fixed to MFM. - HDTYPE => HD_DD_OUT, - MO => MOT_ON, - WG => WR_GATE, - WD => WR_DATA, - STEP => STEP, - DIRC => STEP_DIR, - DRQ => DMA_DRQ_I, - INTRQ => FDINT - ); -DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 -DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 -WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 -HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); -nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; -CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); -CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); -CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); -FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else - SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else - DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ---- WDC BSL REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN - WDC_BSL <= "00"; - elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then - IF FB_B0 = '1' THEN - WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); - else - WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); - end if; - end if; - END PROCESS; ---- DMA MODUS REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN - DMA_MODUS <= x"0000"; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then - IF FB_B0 = '1' THEN - DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); - else - DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); - end if; - IF FB_B1 = '1' THEN - DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); - else - DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); - end if; - else - DMA_MODUS <= DMA_MODUS; - end if; - END PROCESS; --- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) - begin - if nRSTO = '0' or CLR_FIFO = '1' THEN - DMA_BYT_CNT <= x"00000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then - DMA_BYT_CNT(31 downto 17) <= "000000000000000"; - DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); - DMA_BYT_CNT(8 downto 0) <= "000000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then - DMA_BYT_CNT <= FB_AD; - else - DMA_BYT_CNT <= DMA_BYT_CNT; - end if; - END PROCESS; --------------------------------------------------------------------- -FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -DMA_STATUS(0) <= '1'; -- DMA OK -DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS -DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; -DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else - '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; -DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ - process(FDC_CLK, nRSTO, DMA_DRQ_REG) - begin - if nRSTO = '0' THEN - DMA_DRQ_REG <= "00"; - elsif rising_edge(FDC_CLK) then - DMA_DRQ_REG(0) <= DMA_DRQQ; - DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; - else - DMA_DRQ_REG <= DMA_DRQ_REG; - end if; - END PROCESS; --- DMA ADRESSE ------------------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN - DMA_TOP <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then - DMA_TOP <= FB_AD(31 downto 24); - else - DMA_TOP <= DMA_TOP; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN - DMA_HIGH <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then - DMA_HIGH <= FB_AD(23 downto 16); - else - DMA_HIGH <= DMA_HIGH; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) - begin - DMA_MID <= DMA_MID; - if nRSTO = '0' THEN - DMA_MID <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_MID_CS = '1' then - DMA_MID <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_MID <= FB_AD(15 downto 8); - end if; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) - begin - DMA_LOW <= DMA_LOW; - if nRSTO = '0' THEN - DMA_LOW <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_LOW_CS = '1'then - DMA_LOW <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_LOW <= FB_AD(7 downto 0); - end if; - end if; - END PROCESS; --------------------------------------------------------------------------------------------- -DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 -DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 -DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 -DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 -FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- DIRECTZUGRIFF -DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD -DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG -DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG -FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; --- DMA RW TOGGLE ------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) - begin - if nRSTO = '0' THEN - DMA_DIR_OLD <= '0'; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then - DMA_DIR_OLD <= DMA_MODUS(8); - else - DMA_DIR_OLD <= DMA_DIR_OLD; - end if; - END PROCESS; -CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; -adr <= ca2 & ca1 & ca0; -rd_n <= (NOT nFDC_WR) OR (NOT scsi_cs); -wr_n <= nFDC_WR OR (NOT scsi_cs); --- SCSI ---------------------------------------------------------------------------------- - I_SCSI: WF5380_TOP_SOC - port map( - CLK => FDC_CLK, - RESETn => nRSTO, - ADR => adr, - DATA_IN => CD_IN_FDC, - DATA_OUT => SCSI_DOUT, - --DATA_EN : out bit; - -- Bus and DMA controls: - CSn => '1', --SCSI_CSn, ABGESCHALTET - RDn => rd_n, - WRn => wr_n, - EOPn => '1', - DACKn => nSCSI_DACK, - DRQ => SCSI_DRQ, - INT => SCSI_INT, --- READY => - -- SCSI bus: - DB_INn => SCSI_D, - DB_OUTn => DB_OUTn, - DB_EN => DB_EN, - DBP_INn => SCSI_PAR, - DBP_OUTn => DBP_OUTn, - DBP_EN => DBP_EN, -- wenn 1 dann output - RST_INn => nSCSI_RST, - RST_OUTn => RST_OUTn, - RST_EN => RST_EN, - BSY_INn => nSCSI_BUSY, - BSY_OUTn => BSY_OUTn, - BSY_EN => BSY_EN, - SEL_INn => nSCSI_SEL, - SEL_OUTn => SEL_OUTn, - SEL_EN => SEL_EN, - ACK_INn => '1', - ACK_OUTn => nSCSI_ACK, --- ACK_EN => ACK_EN, - ATN_INn => '1', - ATN_OUTn => nSCSI_ATN, --- ATN_EN => ATN_EN, - REQ_INn => nSCSI_DRQ, --- REQ_OUTn => REQ_OUTn, --- REQ_EN => REQ_EN, - IOn_IN => nSCSI_I_O, --- IOn_OUT => IOn_OUT, --- IO_EN => IO_EN, - CDn_IN => nSCSI_C_D, --- CDn_OUT => CDn_OUT, --- CD_EN => CD_EN, - MSG_INn => nSCSI_MSG --- MSG_OUTn => MSG_OUTn, --- MSG_EN => MSG_EN - ); --- SCSI ACSI --------------------------------------------------------------- -SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; -SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET -SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; -nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; -nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; -nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; -ACSI_DIR <= '0'; -ACSI_D <= "ZZZZZZZZ"; -nACSI_CS <= '1'; -ACSI_A1 <= CA1; -nACSI_RESET <= nRSTO; -nACSI_ACK <= '1'; ----------------------------------------------------------------------------- --- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns ----------------------------------------------------------------------------- -ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 -nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; -nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; ----------------------------------------------------------------------------- --- ACIA KEYBOARD ----------------------------------------------------------------------------- - I_ACIA_KEYBOARD: WF6850IP_TOP_SOC - port map( - CLK => MAIN_CLK, - RESETn => nRSTO, - - CS2n => FB_ADR(2), - CS1 => '1', - CS0 => ACIA_CS_I, - E => ACIA_CS_I, - RWn => nFB_WR, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_I, --- DATA_EN => DATA_EN_ACIA_I, - - TXCLK => CLK500k, - RXCLK => CLK500k, - RXDATA => KEYB_RxD, - - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_KEYBDn, - TXDATA => AMKB_TX - --RTSn => -- Not used. - ); -ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 -KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL -FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; --- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ - process(CLK2M, AMKB_RX, AMKB_REG) - begin - if rising_edge(CLK2M) then - IF AMKB_RX = '0' THEN - IF AMKB_REG < 16 THEN - AMKB_REG <= "00000"; - ELSE - AMKB_REG <= AMKB_REG - 1; - END IF; - ELSE - IF AMKB_REG > 15 THEN - AMKB_REG <= "11111"; - ELSE - AMKB_REG <= AMKB_REG + 1; - END IF; - END IF; - ELSE - AMKB_REG <= AMKB_REG; - end if; - END PROCESS; ----------------------------------------------------------------------------- --- ACIA MIDI ----------------------------------------------------------------------------- - I_ACIA_MIDI: WF6850IP_TOP_SOC - port map( - CLK => MAIN_CLK, - RESETn => nRSTO, - - CS2n => '0', - CS1 => FB_ADR(2), - CS0 => ACIA_CS_I, - E => ACIA_CS_I, - RWn => nFB_WR, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_II, --- DATA_EN => DATA_EN_ACIA_II, - - TXCLK => CLK500k, - RXCLK => CLK500k, - RXDATA => MIDI_IN, - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_MIDIn, - TXDATA => MIDI_OUT - --RTSn => -- Not used. - ); -MIDI_TLR <= MIDI_OUT; -MIDI_OLR <= MIDI_OUT; -FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -ds_n <= NOT lds; -cs_n <= NOT mfp_cs; -gpip_in_7 <= NOT dma_drq_q; -gpip_in_6 <= NOT ri; -gpip_in_2 <= NOT cts; -gpip_in_1 <= NOT dcd; -iack_n <= NOT mfp_intack; ----------------------------------------------------------------------------- --- MFP ----------------------------------------------------------------------------- - I_MFP: WF68901IP_TOP_SOC - port map( - -- System control: - CLK => MAIN_CLK, - RESETn => nRSTO, - -- Asynchronous bus control: - DSn => ds_n, - CSn => cs_n, - RWn => nFB_WR, - DTACKn => DTACK_OUT_MFPn, - -- Data and Adresses: - RS => FB_ADR(5 downto 1), - DATA_IN => FB_AD(23 downto 16), - DATA_OUT => DATA_OUT_MFP, --- DATA_EN => DATA_EN_MFP, - GPIP_IN(7) => gpip_in_7, - GPIP_IN(6) => gpip_in_6, - GPIP_IN(5) => DINTn, - GPIP_IN(4) => IRQ_ACIAn, - GPIP_IN(3) => DSP_INT, - GPIP_IN(2) => gpip_in_2, - GPIP_IN(1) => gpip_in_1, - GPIP_IN(0) => LP_BUSY, - -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. - -- GPIP_EN =>, -- Not used; all GPIPs are direction input. - -- Interrupt control: - IACKn => iack_n, - IEIn => '0', - -- IEOn =>, -- Not used. - IRQn => nMFP_INT, - -- Timers and timer control: - XTAL1 => CLK2M4576, - TAI => '0', - TBI => nBLANK, - -- TAO =>, - -- TBO =>, - -- TCO =>, - TDO => TDO, - -- Serial I/O control: - RC => TDO, - TC => TDO, - SI => RxD, - SO => TxD - -- SO_EN => MFP_SO_EN - -- DMA control: - -- RRn =>, - -- TRn => - ); - -MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 -MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 -LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; -FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; -DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else - '0' when FDINT = '1' else - '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1'; --- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ - process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) - begin - if nRSTO = '0' THEN - IRQ_ACIAn <= '1'; - elsif rising_edge(MAIN_CLK) then - IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; - else - IRQ_ACIAn <= IRQ_ACIAn; - end if; - END PROCESS; ----------------------------------------------------------------------------- --- Sound ----------------------------------------------------------------------------- - I_SOUND: WF2149IP_TOP_SOC - port map( - SYS_CLK => MAIN_CLK, - RESETn => nRSTO, - - WAV_CLK => CLK2M, - SELn => '1', - - BDIR => SNDIR_I, - BC2 => '1', - BC1 => SNDCS_I, - - A9n => '0', - A8 => '1', - DA_IN => FB_AD(31 downto 24), - DA_OUT => DA_OUT_X, - - IO_A_IN => x"00", -- All port pins are dedicated outputs. - IO_A_OUT(7) => nnIDE_RES, - IO_A_OUT(6) => LP_DIR_X, - IO_A_OUT(5) => LP_STR, - IO_A_OUT(4) => DTR, - IO_A_OUT(3) => RTS, --- IO_A_OUT(2) => FDD_D1SEL, - IO_A_OUT(2) => dummy, - IO_A_OUT(1) => DSA_D, - IO_A_OUT(0) => nSDSEL, --- IO_A_EN =>, -- Not required. - IO_B_IN => LP_D, - IO_B_OUT => LP_D_X, - IO_B_EN => IO_B_EN, - - OUT_A => YM_QA, - OUT_B => YM_QB, - OUT_C => YM_QC - ); - -SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 -SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; -SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; -FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; -LP_DIR <= LP_DIR_X; - -END FalconIO_SDCard_IDE_CF_architecture; +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor IF you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:20 2009 + +LIBRARY work; + USE work.FalconIO_SDCard_IDE_CF_pkg.ALL; + +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.std_logic_unsigned.ALL; + + +-- Entity Declaration + + +-- Entity Declaration + +ENTITY falconio_sdcard_ide_cf IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + CLK2M : IN std_logic; + CLK500k : IN std_logic; + nFB_CS1 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + LP_BUSY : IN std_logic; + nACSI_DRQ : IN std_logic; + nACSI_INT : IN std_logic; + nSCSI_DRQ : IN std_logic; + nSCSI_MSG : IN std_logic; + MIDI_IN : IN std_logic; + RxD : IN std_logic; + CTS : IN std_logic; + RI : IN std_logic; + DCD : IN std_logic; + AMKB_RX : IN std_logic; + PIC_AMKB_RX : IN std_logic; + IDE_RDY : IN std_logic; + IDE_INT : IN std_logic; + WP_CS_CARD : IN std_logic; + nINDEX : IN std_logic; + TRACK00 : IN std_logic; + nRD_DATA : IN std_logic; + nDCHG : IN std_logic; + SD_DATA0 : IN std_logic; + SD_DATA1 : IN std_logic; + SD_DATA2 : IN std_logic; + SD_CARD_DEDECT : IN std_logic; + SD_WP : IN std_logic; + nDACK0 : IN std_logic; + nFB_WR : INOUT std_logic; + WP_CF_CARD : IN std_logic; + nWP : IN std_logic; + nFB_CS2 : IN std_logic; + nRSTO : IN std_logic; + HD_DD : IN std_logic; + nSCSI_C_D : IN std_logic; + nSCSI_I_O : IN std_logic; + CLK2M4576 : IN std_logic; + nFB_OE : IN std_logic; + VSYNC : IN std_logic; + HSYNC : IN std_logic; + DSP_INT : IN std_logic; + nBLANK : IN std_logic; + FDC_CLK : IN std_logic; + FB_ALE : IN std_logic; + ACP_CONF : IN std_logic_vector(31 DOWNTO 24); + nIDE_CS1 : OUT std_logic; + nIDE_CS0 : OUT std_logic; + LP_STR : OUT std_logic; + LP_DIR : OUT std_logic; + nACSI_ACK : OUT std_logic; + nACSI_RESET : OUT std_logic; + nACSI_CS : OUT std_logic; + ACSI_DIR : OUT std_logic; + ACSI_A1 : OUT std_logic; + nSCSI_ACK : OUT std_logic; + nSCSI_ATN : OUT std_logic; + SCSI_DIR : OUT std_logic; + SD_CLK : OUT std_logic; + YM_QA : OUT std_logic; + YM_QC : OUT std_logic; + YM_QB : OUT std_logic; + nSDSEL : OUT std_logic; + STEP : OUT std_logic; + MOT_ON : OUT std_logic; + nRP_LDS : OUT std_logic; + nRP_UDS : OUT std_logic; + nROM4 : OUT std_logic; + nROM3 : OUT std_logic; + nCF_CS1 : OUT std_logic; + nCF_CS0 : OUT std_logic; + nIDE_RD : INOUT std_logic; + nIDE_WR : INOUT std_logic; + AMKB_TX : OUT std_logic; + IDE_RES : OUT std_logic; + DTR : OUT std_logic; + RTS : OUT std_logic; + TxD : OUT std_logic; + MIDI_OLR : OUT std_logic; + MIDI_TLR : OUT std_logic; + nDREQ0 : OUT std_logic; + DSA_D : OUT std_logic; + nMFP_INT : OUT std_logic; + FALCON_IO_TA : OUT std_logic; + STEP_DIR : OUT std_logic; + WR_DATA : OUT std_logic; + WR_GATE : OUT std_logic; + DMA_DRQ : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + LP_D : INOUT std_logic_vector(7 DOWNTO 0); + ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_PAR : INOUT std_logic; + nSCSI_SEL : INOUT std_logic; + nSCSI_BUSY : INOUT std_logic; + nSCSI_RST : INOUT std_logic; + SD_CD_DATA3 : INOUT std_logic; + SD_CDM_D1 : INOUT std_logic + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END falconio_sdcard_ide_cf; + + +-- Architecture Body + +ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS + -- system + SIGNAL SYS_CLK : std_logic; + SIGNAL RESETn : std_logic; + SIGNAL FB_B0 : std_logic; -- UPPER BYT BEI 16BIT BUS + SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS + SIGNAL BYT : std_logic; -- WENN BYT -> 1 + SIGNAL LONG : std_logic; -- WENN -> 1 + -- KEYBOARD MIDI + SIGNAL ACIA_CS_I : std_logic; + SIGNAL IRQ_KEYBDn : std_logic; + SIGNAL IRQ_MIDIn : std_logic; + SIGNAL KEYB_RxD : std_logic; + SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); + SIGNAL MIDI_OUT : std_logic; + SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); + SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); + -- MFP + SIGNAL MFP_CS : std_logic; + SIGNAL MFP_INTACK : std_logic; + SIGNAL LDS : std_logic; + SIGNAL DTACK_OUT_MFPn : std_logic; + SIGNAL IRQ_ACIAn : std_logic; + SIGNAL DINTn : std_logic; + SIGNAL DATA_OUT_MFP : std_logic_vector(7 DOWNTO 0); + SIGNAL TDO : std_logic; + -- SOUND + SIGNAL SNDCS : std_logic; + SIGNAL SNDCS_I : std_logic; + SIGNAL SNDIR_I : std_logic; + SIGNAL LP_DIR_X : std_logic; + SIGNAL DA_OUT_X : std_logic_vector(7 DOWNTO 0); + SIGNAL LP_D_X : std_logic_vector(7 DOWNTO 0); + -- DIV + SIGNAL SUB_BUS : std_logic; -- SUB BUS MIT ROM-PORT, CF UND IDE + SIGNAL ROM_CS : std_logic; + -- DMA UND FLOPPY + SIGNAL DMA_DATEN_CS : std_logic; + SIGNAL DMA_MODUS_CS : std_logic; + SIGNAL DMA_MODUS : std_logic_vector(15 DOWNTO 0); + SIGNAL WDC_BSL_CS : std_logic; + SIGNAL WDC_BSL : std_logic_vector(1 DOWNTO 0); + SIGNAL HD_DD_OUT : std_logic; + SIGNAL FDCS_In : std_logic; + SIGNAL CA0 : std_logic; + SIGNAL CA1 : std_logic; + SIGNAL CA2 : std_logic; + SIGNAL FDINT : std_logic; + SIGNAL FDRQ : std_logic; + SIGNAL CD_OUT_FDC : std_logic_vector(7 DOWNTO 0); + SIGNAL CD_IN_FDC : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_TOP_CS : std_logic; + SIGNAL DMA_TOP : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_HIGH_CS : std_logic; + SIGNAL DMA_HIGH : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_MID_CS : std_logic; + SIGNAL DMA_MID : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_LOW_CS : std_logic; + SIGNAL DMA_LOW : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_DIRM_CS : std_logic; + SIGNAL DMA_ADR_CS : std_logic; + SIGNAL DMA_STATUS : std_logic_vector(2 DOWNTO 0); + SIGNAL DMA_DIR_OLD : std_logic; + SIGNAL DMA_BYT_CNT_CS : std_logic; + SIGNAL DMA_BYT_CNT : std_logic_vector(31 DOWNTO 0); + SIGNAL CLR_FIFO : std_logic; + SIGNAL DMA_DRQ_I : std_logic; + SIGNAL DMA_DRQ_REG : std_logic_vector(1 DOWNTO 0); + SIGNAL DMA_DRQQ : std_logic; + SIGNAL DMA_DRQ_Q : std_logic; + SIGNAL RDF_DOUT : std_logic_vector(31 DOWNTO 0); + SIGNAL RDF_AZ : std_logic_vector(9 DOWNTO 0); + SIGNAL RDF_RDE : std_logic; + SIGNAL RDF_WRE : std_logic; + SIGNAL RDF_DIN : std_logic_vector(7 DOWNTO 0); + SIGNAL WRF_DOUT : std_logic_vector(7 DOWNTO 0); + SIGNAL WRF_AZ : std_logic_vector(9 DOWNTO 0); + SIGNAL WRF_RDE : std_logic; + SIGNAL WRF_WRE : std_logic; + SIGNAL nFDC_WR : std_logic; + + TYPE FCF_STATES IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); + + SIGNAL FCF_STATE : FCF_STATES; + SIGNAL NEXT_FCF_STATE : FCF_STATES; + SIGNAL DMA_REQ : std_logic; + SIGNAL FDC_CS : std_logic; + SIGNAL FCF_CS : std_logic; + SIGNAL FCF_APH : std_logic; + SIGNAL DMA_AZ_CS : std_logic; + SIGNAL DMA_ACTIV : std_logic; + SIGNAL DMA_ACTIV_NEW : std_logic; + SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0); + + -- SCSI + SIGNAL SCSI_CS : std_logic; + SIGNAL SCSI_CSn : std_logic; + SIGNAL SCSI_DOUT : std_logic_vector(7 DOWNTO 0); + SIGNAL nSCSI_DACK : std_logic; + SIGNAL SCSI_DRQ : std_logic; + SIGNAL SCSI_INT : std_logic; + SIGNAL DB_OUTn : std_logic_vector(7 DOWNTO 0); + SIGNAL DB_EN : std_logic; + SIGNAL DBP_OUTn : std_logic; + SIGNAL DBP_EN : std_logic; + SIGNAL RST_OUTn : std_logic; + SIGNAL RST_EN : std_logic; + SIGNAL BSY_OUTn : std_logic; + SIGNAL BSY_EN : std_logic; + SIGNAL SEL_OUTn : std_logic; + SIGNAL SEL_EN : std_logic; + + -- IDE + SIGNAL nnIDE_RES : std_logic; + SIGNAL IDE_CF_CS : std_logic; + SIGNAL IDE_CF_TA : std_logic; + SIGNAL NEXT_nIDE_RD : std_logic; + SIGNAL NEXT_nIDE_WR : std_logic; + type CMD_STATES is( IDLE, T1, T6, T7); + SIGNAL CMD_STATE : CMD_STATES; + SIGNAL NEXT_CMD_STATE : CMD_STATES; + + +BEGIN + LONG <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '0' ELSE '0'; + BYT <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; + FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYT = '0' ELSE '0'; + FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYT = '0' ELSE '0'; + + FALCON_IO_TA <= '1' WHEN SNDCS = '1' OR DTACK_OUT_MFPn = '0' OR ACIA_CS_I = '1' OR DMA_MODUS_CS ='1' + OR DMA_ADR_CS = '1' OR DMA_DIRM_CS = '1' OR DMA_BYT_CNT_CS = '1' OR FCF_CS = '1' OR IDE_CF_TA = '1' ELSE '0'; + + SUB_BUS <= '1' WHEN nFB_WR = '1' AND ROM_CS = '1' ELSE + '1' WHEN nFB_WR = '1' AND IDE_CF_CS = '1' ELSE + '1' WHEN nFB_WR = '0' AND nIDE_WR = '0' ELSE '0'; + nRP_UDS <= '0' WHEN SUB_BUS = '1' AND FB_B0 = '1' ELSE '1'; + nRP_LDS <= '0' WHEN SUB_BUS = '1' AND FB_B1 = '1' ELSE '1'; + nDREQ0 <= '0'; + + ---------------------------------------------------------------------------- + -- SD + ---------------------------------------------------------------------------- + SD_CLK <= 'Z'; + SD_CD_DATA3 <= 'Z'; + SD_CDM_D1 <= 'Z'; + + ---------------------------------------------------------------------------- + -- IDE + ---------------------------------------------------------------------------- + CMD_REG: PROCESS(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) + BEGIN + IF nRSTO = '0' THEN + CMD_STATE <= IDLE; + ELSIF rising_edge(MAIN_CLK) THEN + CMD_STATE <= NEXT_CMD_STATE; -- go to next + nIDE_RD <= NEXT_nIDE_RD; -- go to next + nIDE_WR <= NEXT_nIDE_WR; -- go to next + ELSE + CMD_STATE <= CMD_STATE; -- halten + nIDE_RD <= nIDE_RD; -- halten + nIDE_WR <= nIDE_WR; -- halten + END IF; + END PROCESS CMD_REG; + + CMD_DECODER: PROCESS(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) + BEGIN + case CMD_STATE is + WHEN IDLE => + IDE_CF_TA <= '0'; + IF IDE_CF_CS = '1' THEN + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T1; + ELSE + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + END IF; + WHEN T1 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + WHEN T6 => + IF IDE_RDY = '1' THEN + IDE_CF_TA <= '1'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= T7; + ELSE + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + END IF; + WHEN T7 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + END CASE; + END PROCESS CMD_DECODER; + + IDE_RES <= NOT nnIDE_RES AND nRSTO; + IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80 + + nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F + '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F + + nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F + '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F + + nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F + '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F + + nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F + '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F + + ----------------------------------------------------------------------------------------------------------------------------------------- + -- ACSI, SCSI UND FLOPPY WD1772 + ------------------------------------------------------------------------------------------------------------------------------------------- + -- daten read fifo + i_data_read_fifo: dcfifo0 + PORT MAP( + aclr => CLR_FIFO, + data => RDF_DIN, + rdclk => MAIN_CLK, + rdreq => RDF_RDE, + wrclk => FDC_CLK, + wrreq => RDF_WRE, + q => RDF_DOUT, + wrusedw => RDF_AZ + ); + + FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY + FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY + RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE + + FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; + + -- daten write fifo + i_data_write_fifo: dcfifo1 + PORT MAP( + aclr => CLR_FIFO, + data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), + rdclk => FDC_CLK, + rdreq => WRF_RDE, + wrclk => MAIN_CLK, + wrreq => WRF_WRE, + q => WRF_DOUT, + rdusedw => WRF_AZ + ); + + CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' AND DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB + DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG + FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; + + -- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + BEGIN + IF nRSTO = '0' THEN + WRF_WRE <= '0'; + ELSIF rising_edge(MAIN_CLK) THEN + IF FCF_APH = '1' AND nFB_WR = '0' THEN + WRF_WRE <= '1'; + ELSE + WRF_WRE <= '0'; + END IF; + ELSE + WRF_WRE <= WRF_WRE; + END IF; + END PROCESS; + + FCF_REG: PROCESS(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) + BEGIN + IF nRSTO = '0' THEN + FCF_STATE <= FCF_IDLE; + DMA_ACTIV <= '0'; + ELSIF rising_edge(FDC_CLK) THEN + FCF_STATE <= NEXT_FCF_STATE; -- go to next + DMA_ACTIV <= DMA_ACTIV_NEW; + ELSE + FCF_STATE <= FCF_STATE; -- halten + DMA_ACTIV <= DMA_ACTIV; + END IF; + END PROCESS FCF_REG; + + FDC_REG: PROCESS(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) + BEGIN + IF nRSTO = '0' THEN + FDC_OUT <= x"00"; + ELSIF rising_edge(FDC_CLK) AND FDCS_In = '0' THEN + FDC_OUT <= CD_OUT_FDC; -- set + ELSE + FDC_OUT <= FDC_OUT; -- halten + END IF; + END PROCESS FDC_REG; + + DMA_REQ <= '1' WHEN ((DMA_DRQ_I = '1' AND DMA_MODUS(7) = '1') OR (SCSI_DRQ = '1' AND DMA_MODUS(7) = '0')) AND DMA_STATUS(1) = '1' AND DMA_MODUS(6) = '0' AND CLR_FIFO = '0' ELSE '0'; + FDC_CS <= '1' WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND FB_B1 = '1' ELSE '0'; + SCSI_CS <= '1' WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND FB_B1 = '1' ELSE '0'; + + FCF_DECODER: PROCESS(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) + BEGIN + CASE FCF_STATE IS + WHEN FCF_IDLE => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + IF DMA_REQ = '1' OR FDC_CS = '1' OR SCSI_CS = '1' THEN + DMA_ACTIV_NEW <= DMA_REQ; + NEXT_FCF_STATE <= FCF_T0; + ELSE + DMA_ACTIV_NEW <= '0'; + NEXT_FCF_STATE <= FCF_IDLE; + END IF; + WHEN FCF_T0 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= DMA_REQ; + WRF_RDE <= DMA_MODUS(8) AND DMA_REQ; -- WRITE -> READ FROM FIFO + IF DMA_REQ = '0' AND DMA_ACTIV = '1' THEN -- spike? + NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start + ELSE + NEXT_FCF_STATE <= FCF_T1; + END IF; + WHEN FCF_T1 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T2; + WHEN FCF_T2 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T3; + WHEN FCF_T3 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T6; + WHEN FCF_T6 => + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; + RDF_WRE <= NOT DMA_MODUS(8) AND DMA_ACTIV; -- READ -> WRITE IN FIFO + NEXT_FCF_STATE <= FCF_T7; + WHEN FCF_T7 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= '0'; + IF FDC_CS = '1' AND DMA_REQ = '0' THEN + NEXT_FCF_STATE <= FCF_T7; + ELSE + NEXT_FCF_STATE <= FCF_IDLE; + END IF; + END CASE; + END PROCESS FCF_DECODER; + + i_fdc : WF1772IP_TOP_SOC + PORT MAP( + CLK => FDC_CLK, + RESETn => nRSTO, + CSn => FDCS_In, + RWn => nFDC_WR, + A1 => CA2, + A0 => CA1, + DATA_IN => CD_IN_FDC, + DATA_OUT => CD_OUT_FDC, +-- DATA_EN => CD_EN_FDC, + RDn => nRD_DATA, + TR00n => TRACK00, + IPn => nINDEX, + WPRTn => nWP, + DDEn => '0', -- Fixed to MFM. + HDTYPE => HD_DD_OUT, + MO => MOT_ON, + WG => WR_GATE, + WD => WR_DATA, + STEP => STEP, + DIRC => STEP_DIR, + DRQ => DMA_DRQ_I, + INTRQ => FDINT + ); + + DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2 + DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2 + WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2 + + HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); + nFDC_WR <= NOT DMA_MODUS(8) WHEN DMA_ACTIV = '1' ELSE nFB_WR; + + CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0); + CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); + CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); + + FB_AD(23 DOWNTO 16) <= "0000" & (NOT DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE + SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE + DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + + --- WDC BSL REGISTER ------------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) + BEGIN + IF nRSTO = '0' THEN + WDC_BSL <= "00"; + ELSIF rising_edge(MAIN_CLK) AND WDC_BSL_CS = '1' AND nFB_WR = '0' THEN + IF FB_B0 = '1' THEN + WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); + ELSE + WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); + END IF; + END IF; + END PROCESS; + +--- DMA MODUS REGISTER ------------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) + BEGIN + IF nRSTO = '0' THEN + DMA_MODUS <= x"0000"; + ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '1' AND nFB_WR = '0' THEN + IF FB_B0 = '1' THEN + DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24); + ELSE + DMA_MODUS(15 DOWNTO 8) <= DMA_MODUS(15 DOWNTO 8); + END IF; + IF FB_B1 = '1' THEN + DMA_MODUS(7 DOWNTO 0) <= FB_AD(23 DOWNTO 16); + ELSE + DMA_MODUS(7 DOWNTO 0) <= DMA_MODUS(7 DOWNTO 0); + END IF; + ELSE + DMA_MODUS <= DMA_MODUS; + END IF; + END PROCESS; + + -- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) + BEGIN + IF nRSTO = '0' OR CLR_FIFO = '1' THEN + DMA_BYT_CNT <= x"00000000"; + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN + DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z'); + DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); + DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z'); + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN + DMA_BYT_CNT <= FB_AD; + ELSE + DMA_BYT_CNT <= DMA_BYT_CNT; + END IF; + END PROCESS; + -------------------------------------------------------------------- + FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + + DMA_STATUS(0) <= '1'; -- DMA OK + DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS + DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0'; + DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '0' AND RDF_AZ > 15 AND DMA_MODUS(6) = '0' ELSE + '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '1' AND WRF_AZ < 512 AND DMA_MODUS(6) = '0' ELSE '0'; + DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" AND DMA_MODUS(6) = '0' ELSE '0'; + + -- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG) + BEGIN + IF nRSTO = '0' THEN + DMA_DRQ_REG <= "00"; + ELSIF rising_edge(FDC_CLK) THEN + DMA_DRQ_REG(0) <= DMA_DRQQ; + DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; + ELSE + DMA_DRQ_REG <= DMA_DRQ_REG; + END IF; + END PROCESS; + + -- DMA ADRESSE ------------------------------------------------------ + PROCESS(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) + BEGIN + IF nRSTO = '0' THEN + DMA_TOP <= x"00"; + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_TOP_CS = '1' OR DMA_ADR_CS = '1') THEN + DMA_TOP <= FB_AD(31 DOWNTO 24); + ELSE + DMA_TOP <= DMA_TOP; + END IF; + END PROCESS; + + PROCESS(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) + BEGIN + IF nRSTO = '0' THEN + DMA_HIGH <= x"00"; + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_HIGH_CS = '1' OR DMA_ADR_CS = '1') THEN + DMA_HIGH <= FB_AD(23 DOWNTO 16); + ELSE + DMA_HIGH <= DMA_HIGH; + END IF; + END PROCESS; + + PROCESS(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) + BEGIN + DMA_MID <= DMA_MID; + IF nRSTO = '0' THEN + DMA_MID <= x"00"; + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN + IF DMA_MID_CS = '1' THEN + DMA_MID <= FB_AD(23 DOWNTO 16); + ELSIF DMA_ADR_CS = '1' THEN + DMA_MID <= FB_AD(15 DOWNTO 8); + END IF; + END IF; + END PROCESS; + + PROCESS(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) + BEGIN + DMA_LOW <= DMA_LOW; + IF nRSTO = '0' THEN + DMA_LOW <= x"00"; + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN + IF DMA_LOW_CS = '1'THEN + DMA_LOW <= FB_AD(23 DOWNTO 16); + ELSIF DMA_ADR_CS = '1' THEN + DMA_LOW <= FB_AD(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; + + -------------------------------------------------------------------------------------------- + DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2 + DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2 + DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 + DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 + + FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + -- DIRECTZUGRIFF + DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD + DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG + DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG + + FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + + -- DMA RW TOGGLE ------------------------------------------ + + PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) + BEGIN + IF nRSTO = '0' THEN + DMA_DIR_OLD <= '0'; + ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '0' THEN + DMA_DIR_OLD <= DMA_MODUS(8); + ELSE + DMA_DIR_OLD <= DMA_DIR_OLD; + END IF; + END PROCESS; + + CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD; + + -- SCSI ---------------------------------------------------------------------------------- + i_scsi : WF5380_TOP_SOC + PORT MAP( + CLK => FDC_CLK, + RESETn => nRSTO, + ADR => CA2 & CA1 & CA0, + DATA_IN => CD_IN_FDC, + DATA_OUT => SCSI_DOUT, + --DATA_EN : out bit; + -- Bus and DMA controls: + CSn => '1', --SCSI_CSn, ABGESCHALTET + RDn => (not nFDC_WR) or (not SCSI_CS), + WRn => nFDC_WR or (not SCSI_CS), + EOPn => '1', + DACKn => nSCSI_DACK, + DRQ => SCSI_DRQ, + INT => SCSI_INT, +-- READY => + -- SCSI bus: + DB_INn => SCSI_D, + DB_OUTn => DB_OUTn, + DB_EN => DB_EN, + DBP_INn => SCSI_PAR, + DBP_OUTn => DBP_OUTn, + DBP_EN => DBP_EN, -- wenn 1 dann output + RST_INn => nSCSI_RST, + RST_OUTn => RST_OUTn, + RST_EN => RST_EN, + BSY_INn => nSCSI_BUSY, + BSY_OUTn => BSY_OUTn, + BSY_EN => BSY_EN, + SEL_INn => nSCSI_SEL, + SEL_OUTn => SEL_OUTn, + SEL_EN => SEL_EN, + ACK_INn => '1', + ACK_OUTn => nSCSI_ACK, +-- ACK_EN => ACK_EN, + ATN_INn => '1', + ATN_OUTn => nSCSI_ATN, +-- ATN_EN => ATN_EN, + REQ_INn => nSCSI_DRQ, +-- REQ_OUTn => REQ_OUTn, +-- REQ_EN => REQ_EN, + IOn_IN => nSCSI_I_O, +-- IOn_OUT => IOn_OUT, +-- IO_EN => IO_EN, + CDn_IN => nSCSI_C_D, +-- CDn_OUT => CDn_OUT, +-- CD_EN => CD_EN, + MSG_INn => nSCSI_MSG +-- MSG_OUTn => MSG_OUTn, +-- MSG_EN => MSG_EN + ); + + -- SCSI ACSI --------------------------------------------------------------- + SCSI_D <= DB_OUTn WHEN DB_EN = '1' ELSE (OTHERS => 'Z'); + SCSI_DIR <= '1'; --'0' WHEN DB_EN = '1' ELSE '1'; --ABGESCHALTET + SCSI_PAR <= DBP_OUTn WHEN DBP_EN = '1' ELSE 'Z'; + nSCSI_RST <= RST_OUTn WHEN RST_EN = '1' ELSE 'Z'; + nSCSI_BUSY <= BSY_OUTn WHEN BSY_EN = '1' ELSE 'Z'; + nSCSI_SEL <= SEL_OUTn WHEN SEL_EN = '1' ELSE 'Z'; + ACSI_DIR <= '0'; + ACSI_D <= (OTHERS => 'Z'); + nACSI_CS <= '1'; + ACSI_A1 <= CA1; + nACSI_RESET <= nRSTO; + nACSI_ACK <= '1'; + + + ---------------------------------------------------------------------------- + -- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns + ---------------------------------------------------------------------------- + ROM_CS <= '1' WHEN nFB_CS1 = '0' AND nFB_WR = '1' AND FB_ADR(19 DOWNTO 17) = x"5" ELSE '0'; -- FFF A'0000/2'0000 + nROM4 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '0' ELSE '1'; + nROM3 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '1' ELSE '1'; + + + ---------------------------------------------------------------------------- + -- ACIA KEYBOARD + ---------------------------------------------------------------------------- + i_acia_keyboard : WF6850IP_TOP_SOC + PORT MAP( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => FB_ADR(2), + CS1 => '1', + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 DOWNTO 24), + DATA_OUT => DATA_OUT_ACIA_I, +-- DATA_EN => DATA_EN_ACIA_I, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => KEYB_RxD, + + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_KEYBDn, + TXDATA => AMKB_TX + --RTSn => -- Not used. + ); + + ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8 + KEYB_RxD <= '1' WHEN AMKB_REG(3) = '1' OR PIC_AMKB_RX = '0' ELSE '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '0' AND nFB_OE = '0' ELSE "ZZZZZZZZ"; + + -- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(CLK2M, AMKB_RX, AMKB_REG) + BEGIN + IF rising_edge(CLK2M) THEN + IF AMKB_RX = '0' THEN + IF AMKB_REG < 16 THEN + AMKB_REG <= "00000"; + ELSE + AMKB_REG <= AMKB_REG - 1; + END IF; + ELSE + IF AMKB_REG > 15 THEN + AMKB_REG <= "11111"; + ELSE + AMKB_REG <= AMKB_REG + 1; + END IF; + END IF; + ELSE + AMKB_REG <= AMKB_REG; + END IF; + END PROCESS; + + ---------------------------------------------------------------------------- + -- ACIA MIDI + ---------------------------------------------------------------------------- + i_acia_midi : WF6850IP_TOP_SOC + PORT MAP( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => '0', + CS1 => FB_ADR(2), + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 DOWNTO 24), + DATA_OUT => DATA_OUT_ACIA_II, +-- DATA_EN => DATA_EN_ACIA_II, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => MIDI_IN, + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_MIDIn, + TXDATA => MIDI_OUT + --RTSn => -- Not used. + ); + + MIDI_TLR <= MIDI_OUT; + MIDI_OLR <= MIDI_OUT; + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + ---------------------------------------------------------------------------- + -- MFP + ---------------------------------------------------------------------------- + i_mfp : WF68901IP_TOP_SOC + PORT MAP( + -- System control: + CLK => MAIN_CLK, + RESETn => nRSTO, + -- Asynchronous bus control: + DSn => NOT LDS, + CSn => NOT MFP_CS, + RWn => nFB_WR, + DTACKn => DTACK_OUT_MFPn, + -- Data and Adresses: + RS => FB_ADR(5 DOWNTO 1), + DATA_IN => FB_AD(23 DOWNTO 16), + DATA_OUT => DATA_OUT_MFP, +-- DATA_EN => DATA_EN_MFP, + GPIP_IN(7) => NOT DMA_DRQ_Q, + GPIP_IN(6) => NOT RI, + GPIP_IN(5) => DINTn, + GPIP_IN(4) => IRQ_ACIAn, + GPIP_IN(3) => DSP_INT, + GPIP_IN(2) => NOT CTS, + GPIP_IN(1) => NOT DCD, + GPIP_IN(0) => LP_BUSY, + -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. + -- GPIP_EN =>, -- Not used; all GPIPs are direction input. + -- Interrupt control: + IACKn => NOT MFP_INTACK, + IEIn => '0', + -- IEOn =>, -- Not used. + IRQn => nMFP_INT, + -- Timers and timer control: + XTAL1 => CLK2M4576, + TAI => '0', + TBI => nBLANK, + -- TAO =>, + -- TBO =>, + -- TCO =>, + TDO => TDO, + -- Serial I/O control: + RC => TDO, + TC => TDO, + SI => RxD, + SO => TxD + -- SO_EN => MFP_SO_EN + -- DMA control: + -- RRn =>, + -- TRn => + ); + + MFP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 6) = x"3FE8" ELSE '0'; -- FFA00/40 + MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 + LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0'; + + FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 10) <= (OTHERS => '0') WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z') ; + FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ"; + + DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE + '0' WHEN FDINT = '1' ELSE + '0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1'; + + -- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(MAIN_CLK, nRSTO, IRQ_ACIAn, IRQ_KEYBDn, IRQ_MIDIn) + BEGIN + IF nRSTO = '0' THEN + IRQ_ACIAn <= '1'; + ELSIF rising_edge(MAIN_CLK) THEN + IRQ_ACIAn <= IRQ_KEYBDn AND IRQ_MIDIn; + ELSE + IRQ_ACIAn <= IRQ_ACIAn; + END IF; + END PROCESS; + + ---------------------------------------------------------------------------- + -- Sound + ---------------------------------------------------------------------------- + i_sound : WF2149IP_TOP_SOC + PORT MAP( + SYS_CLK => MAIN_CLK, + RESETn => nRSTO, + + WAV_CLK => CLK2M, + SELn => '1', + + BDIR => SNDIR_I, + BC2 => '1', + BC1 => SNDCS_I, + + A9n => '0', + A8 => '1', + DA_IN => FB_AD(31 DOWNTO 24), + DA_OUT => DA_OUT_X, + + IO_A_IN => x"00", -- All port pins are dedicated outputs. + IO_A_OUT(7) => nnIDE_RES, + IO_A_OUT(6) => LP_DIR_X, + IO_A_OUT(5) => LP_STR, + IO_A_OUT(4) => DTR, + IO_A_OUT(3) => RTS, +-- IO_A_OUT(2) => FDD_D1SEL, + IO_A_OUT(1) => DSA_D, + IO_A_OUT(0) => nSDSEL, +-- IO_A_EN =>, -- Not required. + IO_B_IN => LP_D, + IO_B_OUT => LP_D_X, +-- IO_B_EN => IO_B_EN, + + OUT_A => YM_QA, + OUT_B => YM_QB, + OUT_C => YM_QC + ); + + SNDCS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4 + SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; + SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0'; + FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z'); + LP_DIR <= LP_DIR_X; +END rtl; diff --git a/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd index 9d048de..a140e29 100644 --- a/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +++ b/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd @@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS); component WF2149IP_WAVE port( RESETn : in bit; - SYS_CLK : in bit; + SYS_CLK : in std_logic; WAV_STRB : in bit; diff --git a/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd index 2835438..060058c 100644 --- a/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +++ b/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd @@ -72,134 +72,134 @@ -- Revision 2K6B 2006/11/07 WF -- Modified Source to compile with the Xilinx ISE. -- Top level file provided for SOC (systems on programmable chips). --- Revision 2K8A 2008/07/14 WF --- Minor changes. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. -- -library ieee; -use ieee.std_logic_1164.all; -use work.wf2149ip_pkg.all; +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE work.wf2149ip_pkg.ALL; -entity WF2149IP_TOP_SOC is - port( +ENTITY WF2149IP_TOP_SOC IS + PORT( - SYS_CLK : in bit; -- Read the inforation in the header! - RESETn : in bit; + SYS_CLK : IN std_logic; -- Read the inforation in the header! + RESETn : IN bit; - WAV_CLK : in bit; -- Read the inforation in the header! - SELn : in bit; + WAV_CLK : IN bit; -- Read the inforation in the header! + SELn : IN bit; - BDIR : in bit; - BC2, BC1 : in bit; + BDIR : IN bit; + BC2, BC1 : IN bit; - A9n, A8 : in bit; - DA_IN : in std_logic_vector(7 downto 0); - DA_OUT : out std_logic_vector(7 downto 0); - DA_EN : out bit; + A9n, A8 : IN bit; + DA_IN : IN std_logic_vector(7 DOWNTO 0); + DA_OUT : OUT std_logic_vector(7 DOWNTO 0); + DA_EN : OUT bit; - IO_A_IN : in bit_vector(7 downto 0); - IO_A_OUT : out bit_vector(7 downto 0); - IO_A_EN : out bit; - IO_B_IN : in bit_vector(7 downto 0); - IO_B_OUT : out bit_vector(7 downto 0); - IO_B_EN : out bit; + IO_A_IN : IN bit_vector(7 DOWNTO 0); + IO_A_OUT : OUT bit_vector(7 DOWNTO 0); + IO_A_EN : OUT bit; + IO_B_IN : IN bit_vector(7 DOWNTO 0); + IO_B_OUT : OUT bit_vector(7 DOWNTO 0); + IO_B_EN : OUT bit; - OUT_A : out bit; -- Analog (PWM) outputs. - OUT_B : out bit; - OUT_C : out bit + OUT_A : OUT bit; -- Analog (PWM) outputs. + OUT_B : OUT bit; + OUT_C : OUT bit ); -end WF2149IP_TOP_SOC; +END WF2149IP_TOP_SOC; -architecture STRUCTURE of WF2149IP_TOP_SOC is -signal BUSCYCLE : BUSCYCLES; -signal DATA_OUT_I : std_logic_vector(7 downto 0); -signal DATA_EN_I : bit; -signal WAV_STRB : bit; -signal ADR_I : bit_vector(3 downto 0); -signal CTRL_REG : bit_vector(7 downto 0); -signal PORT_A : bit_vector(7 downto 0); -signal PORT_B : bit_vector(7 downto 0); - SIGNAL bsel : bit_vector(2 DOWNTO 0); -begin - P_WAVSTRB: process(RESETn, SYS_CLK) - variable LOCK : boolean; - variable TMP : bit; - begin - if RESETn = '0' then +ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS + SIGNAL BUSCYCLE : BUSCYCLES; + SIGNAL DATA_OUT_I : std_logic_vector(7 DOWNTO 0); + SIGNAL DATA_EN_I : bit; + SIGNAL WAV_STRB : bit; + SIGNAL ADR_I : bit_vector(3 DOWNTO 0); + SIGNAL CTRL_REG : bit_vector(7 DOWNTO 0); + SIGNAL PORT_A : bit_vector(7 DOWNTO 0); + SIGNAL PORT_B : bit_vector(7 DOWNTO 0); +BEGIN + P_WAVSTRB: PROCESS(RESETn, SYS_CLK) + VARIABLE LOCK : boolean; + VARIABLE TMP : bit; + BEGIN + IF RESETn = '0' THEN LOCK := false; TMP := '0'; - elsif SYS_CLK = '1' and SYS_CLK' event then - if WAV_CLK = '1' and LOCK = false then + ELSIF rising_edge(SYS_CLK) THEN + IF WAV_CLK = '1' and LOCK = false THEN LOCK := true; TMP := not TMP; -- Divider by 2. - case SELn is - when '1' => WAV_STRB <= '1'; - when others => WAV_STRB <= TMP; - end case; - elsif WAV_CLK = '0' then + + CASE SELn IS + WHEN '1' => WAV_STRB <= '1'; + WHEN OTHERS => WAV_STRB <= TMP; + END CASE; + ELSIF WAV_CLK = '0' THEN LOCK := false; WAV_STRB <= '0'; - else + ELSE WAV_STRB <= '0'; - end if; - end if; - end process P_WAVSTRB; - bsel <= bdir & bc2 & bc1; - with bsel select - BUSCYCLE <= INACTIVE when "000" | "010" | "101", - ADDRESS when "001" | "100" | "111", - R_READ when "011", - R_WRITE when "110"; + END IF; + END IF; + END PROCESS P_WAVSTRB; - ADDRESSLATCH: process(RESETn, SYS_CLK) + WITH BDIR & BC2 & BC1 SELECT + BUSCYCLE <= INACTIVE WHEN "000" | "010" | "101", + ADDRESS WHEN "001" | "100" | "111", + R_READ WHEN "011", + R_WRITE WHEN "110"; + + ADDRESSLATCH: PROCESS(RESETn, SYS_CLK) -- This process is responsible to store the desired register -- address. The default (after reset) is channel A fine tone -- adjustment. - begin - if RESETn = '0' then - ADR_I <= (others => '0'); - elsif SYS_CLK = '1' and SYS_CLK' event then - if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then - ADR_I <= To_BitVector(DA_IN(3 downto 0)); - end if; - end if; - end process ADDRESSLATCH; + BEGIN + IF RESETn = '0' THEN + ADR_I <= (OTHERS => '0'); + ELSIF rising_edge(SYS_CLK) THEN + IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN + ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0)); + END IF; + END IF; + END PROCESS ADDRESSLATCH; - P_CTRL_REG: process(RESETn, SYS_CLK) + P_CTRL_REG: PROCESS(RESETn, SYS_CLK) -- THIS is the Control register for the mixer and for the I/O ports. - begin - if RESETn = '0' then + BEGIN + IF RESETn = '0' THEN CTRL_REG <= x"00"; - elsif SYS_CLK = '1' and SYS_CLK' event then - if BUSCYCLE = R_WRITE and ADR_I = x"7" then + ELSIF rising_edge(SYS_CLK) THEN + IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN CTRL_REG <= To_BitVector(DA_IN); - end if; - end if; - end process P_CTRL_REG; + END IF; + END IF; + END PROCESS P_CTRL_REG; - DIG_PORTS: process(RESETn, SYS_CLK) - begin - if RESETn = '0' then + DIG_PORTS: PROCESS(RESETn, SYS_CLK) + BEGIN + IF RESETn = '0' THEN PORT_A <= x"00"; PORT_B <= x"00"; - elsif SYS_CLK = '1' and SYS_CLK' event then - if BUSCYCLE = R_WRITE and ADR_I = x"E" then + ELSIF rising_edge(SYS_CLK) THEN + IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN PORT_A <= To_BitVector(DA_IN); - elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then + ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN PORT_B <= To_BitVector(DA_IN); - end if; - end if; - end process DIG_PORTS; + END IF; + END IF; + END PROCESS DIG_PORTS; -- Set port direction to input or to output: - IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0'; - IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0'; + IO_A_EN <= '1' WHEN CTRL_REG(6) = '1' ELSE '0'; + IO_B_EN <= '1' WHEN CTRL_REG(7) = '1' ELSE '0'; IO_A_OUT <= PORT_A; IO_B_OUT <= PORT_B; I_PSG_WAVE: WF2149IP_WAVE - port map( + PORT MAP( RESETn => RESETn, - SYS_CLK => SYS_CLK, + SYS_CLK => SYS_CLK, WAV_STRB => WAV_STRB, @@ -209,7 +209,7 @@ begin DATA_EN => DATA_EN_I, BUSCYCLE => BUSCYCLE, - CTRL_REG => CTRL_REG(5 downto 0), + CTRL_REG => CTRL_REG(5 DOWNTO 0), OUT_A => OUT_A, OUT_B => OUT_B, @@ -217,14 +217,14 @@ begin ); -- Read the ports and registers: - DA_EN <= '1' when DATA_EN_I = '1' else - '1' when BUSCYCLE = R_READ and ADR_I = x"7" else - '1' when BUSCYCLE = R_READ and ADR_I = x"E" else - '1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0'; + DA_EN <= '1' WHEN DATA_EN_I = '1' ELSE + '1' WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE + '1' WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE + '1' WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE '0'; - DA_OUT <= DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff. - To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else - To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else - To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0'); + DA_OUT <= DATA_OUT_I WHEN DATA_EN_I = '1' ELSE -- WAV stuff. + To_StdLogicVector(IO_A_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE + To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE + To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0'); -end STRUCTURE; +END rtl; diff --git a/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd index d829f9b..8744213 100644 --- a/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +++ b/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd @@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all; entity WF2149IP_WAVE is port( RESETn : in bit; - SYS_CLK : in bit; + SYS_CLK : in std_logic; WAV_STRB : in bit; diff --git a/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd index cbca6bd..bb806d6 100644 --- a/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +++ b/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -60,8 +60,8 @@ -- library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; entity WF6850IP_TOP_SOC is port ( diff --git a/Interrupt_Handler/interrupt_handler.tdf b/Interrupt_Handler/interrupt_handler.tdf index a455469..b569002 100644 --- a/Interrupt_Handler/interrupt_handler.tdf +++ b/Interrupt_Handler/interrupt_handler.tdf @@ -17,64 +17,64 @@ INCLUDE "lpm_bustri_BYT.inc"; SUBDESIGN interrupt_handler ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - MAIN_CLK : INPUT; - nFB_WR : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - FB_ADR[31..0] : INPUT; - PIC_INT : INPUT; - E0_INT : INPUT; - DVI_INT : INPUT; - nPCI_INTA : INPUT; - nPCI_INTB : INPUT; - nPCI_INTC : INPUT; - nPCI_INTD : INPUT; - nMFP_INT : INPUT; - nFB_OE : INPUT; - DSP_INT : INPUT; - VSYNC : INPUT; - HSYNC : INPUT; - DMA_DRQ : INPUT; - nIRQ[7..2] : OUTPUT; - INT_HANDLER_TA : OUTPUT; - ACP_CONF[31..0] : OUTPUT; - TIN0 : OUTPUT; - FB_AD[31..0] : BIDIR; + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) VARIABLE - FB_B[3..0] :NODE; - INT_CTR[31..0] :DFFE; - INT_CTR_CS :NODE; - INT_LATCH[31..0] :DFF; - INT_LATCH_CS :NODE; - INT_CLEAR[31..0] :DFF; - INT_CLEAR_CS :NODE; - INT_IN[31..0] :NODE; - INT_ENA[31..0] :DFFE; - INT_ENA_CS :NODE; - ACP_CONF[31..0] :DFFE; - ACP_CONF_CS :NODE; - PSEUDO_BUS_ERROR :NODE; - UHR_AS :NODE; - UHR_DS :NODE; - RTC_ADR[5..0] :DFFE; - ACHTELSEKUNDEN[2..0] :DFFE; - WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 - PIC_INT_SYNC[2..0] :DFF; - INC_SEC :NODE; - INC_MIN :NODE; - INC_STD :NODE; - INC_TAG :NODE; + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; ANZAHL_TAGE_DES_MONATS[7..0]:NODE; - WINTERZEIT :NODE; - SOMMERZEIT :NODE; - INC_MONAT :NODE; - INC_JAHR :NODE; - UPDATE_ON :NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; BEGIN -- BYT SELECT @@ -91,7 +91,7 @@ BEGIN # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE --- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL�SEN, 1=INT7 AUSL�SEN INT_CTR[].CLK = MAIN_CLK; INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 INT_CTR[] = FB_AD[]; @@ -99,6 +99,7 @@ BEGIN INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; + -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 INT_ENA[].CLK = MAIN_CLK; INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 @@ -107,6 +108,7 @@ BEGIN INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; + -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR INT_CLEAR[].CLK = MAIN_CLK; INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 @@ -114,8 +116,10 @@ BEGIN INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; + -- INTERRUPT LATCH REGISTER READ ONLY INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 + -- INTERRUPT !nIRQ2 = HSYNC & INT_ENA[26]; !nIRQ3 = INT_CTR0 & INT_ENA[27]; @@ -139,6 +143,7 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC # FB_ADR[19..4]==H"F890" -- DMA SOUND # FB_ADR[19..4]==H"F891" -- DMA SOUND # FB_ADR[19..4]==H"F892"); -- DMA SOUND + -- IF VIDEO ADR CHANGE TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 @@ -176,6 +181,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H INT_IN29 = INT_LATCH[]!=H"00000000"; INT_IN30 = !nMFP_INT; INT_IN31 = DMA_DRQ; + --*************************************************************************************** -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE ACP_CONF[].CLK = MAIN_CLK; @@ -324,9 +330,12 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; - PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; + + PIC_INT_SYNC[].CLK = MAIN_CLK; + PIC_INT_SYNC[0] = PIC_INT; PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; + UPDATE_ON = !WERTE[7][11]; WERTE[6][10].CLRN = GND; -- KEIN UIP UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF @@ -334,48 +343,57 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[7][13] = VCC; -- IMMER RICHTIG --- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) + +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL WERTE[0][13] = SOMMERZEIT; WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER + -- ACHTELSEKUNDEN ACHTELSEKUNDEN[].CLK = MAIN_CLK; ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; + -- SEKUNDEN INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; - WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z�HLEN BIS 59 WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); + -- MINUTEN INC_MIN = INC_SEC & WERTE[][0]==59; -- - WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z�HLEN BIS 59 WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- + -- STUNDEN INC_STD = INC_MIN & WERTE[][2]==59; - WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z�HLEN BIS 23 WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT -- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; - WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z�HLEN BIS 7 # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; - WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z�HLEN BIS MONATSENDE # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- + -- MONATE INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- - WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z�HLEN BIS 12 # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); + -- JAHR INC_JAHR = INC_MONAT & WERTE[][8]==12; -- - WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z�HLEN BIS 99 WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); + -- TRISTATE OUTPUT FB_AD[31..24] = lpm_bustri_BYT( @@ -457,6 +475,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[23..16] # ACP_CONF_CS & ACP_CONF[23..16] ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[15..8] # INT_ENA_CS & INT_ENA[15..8] @@ -464,6 +483,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[15..8] # ACP_CONF_CS & ACP_CONF[15..8] ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[7..0] # INT_ENA_CS & INT_ENA[7..0] diff --git a/Video/BLITTER/BLITTER.vhd b/Video/BLITTER/BLITTER.vhd index e09ed0b..63cc93f 100644 --- a/Video/BLITTER/BLITTER.vhd +++ b/Video/BLITTER/BLITTER.vhd @@ -26,7 +26,7 @@ USE ieee.std_logic_1164.all; -- Entity Declaration -ENTITY BLITTER IS +ENTITY blitter IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( @@ -61,7 +61,7 @@ END BLITTER; -- Architecture Body -ARCHITECTURE BLITTER_architecture OF BLITTER IS +ARCHITECTURE BLITTER_architecture OF blitter IS BEGIN diff --git a/Video/DDR_CTR.tdf b/Video/DDR_CTR.tdf index d5b5ec2..d22c642 100644 --- a/Video/DDR_CTR.tdf +++ b/Video/DDR_CTR.tdf @@ -58,9 +58,9 @@ SUBDESIGN DDR_CTR ) VARIABLE - FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); - DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) - DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG + FB_REGDDR :MACHINE WITH STATES(FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) + DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG DS_T4R,DS_T5R, -- READ CPU UND BLITTER, DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO @@ -129,7 +129,8 @@ VARIABLE BEGIN LINE = FB_SIZE0 & FB_SIZE1; --- BYT SELECT + + -- BYT SELECT FB_B0 = FB_ADR[1..0]==0 -- ADR==0 # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE FB_B1 = FB_ADR[1..0]==1 -- ADR==1 @@ -140,7 +141,8 @@ BEGIN FB_B3 = FB_ADR[1..0]==3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + + -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- FB_REGDDR.CLK = MAIN_CLK; CASE FB_REGDDR IS WHEN FR_WAIT => @@ -198,7 +200,8 @@ BEGIN FB_REGDDR = FR_WAIT; END IF; END CASE; --- DDR STEUERUNG ----------------------------------------------------- + + -- DDR STEUERUNG ----------------------------------------------------- -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; VCKE = VIDEO_RAM_CTR0; nVCS = !VIDEO_RAM_CTR1; @@ -220,34 +223,39 @@ BEGIN FIFO_AC.CLK = DDRCLK0; BLITTER_AC.CLK = DDRCLK0; DDRWR_D_SEL1 = BLITTER_AC; --- SELECT LOGIC + + -- SELECT LOGIC DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; DDR_CS.CLK = MAIN_CLK; DDR_CS.ENA = FB_ALE; DDR_CS = DDR_SEL; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + + -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP�TER CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS - # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP�TER CPU_REQ.CLK = DDR_SYNC_66M; CPU_REQ = CPU_SIG # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG BUS_CYC.CLK = DDRCLK0; BUS_CYC = BUS_CYC & !BUS_CYC_END; + -- STATE MACHINE SYNCHRONISIEREN ----------------- MCS[].CLK = DDRCLK0; MCS0 = MAIN_CLK; MCS1 = MCS0; CPU_DDR_SYNC.CLK = DDRCLK0; CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN - --------------------------------------------------- + + --------------------------------------------------- VA_S[].CLK = DDRCLK0; BA_S[].CLK = DDRCLK0; VA[] = VA_S[]; BA[] = BA_S[]; VA_P[].CLK = DDRCLK0; BA_P[].CLK = DDRCLK0; --- DDR STATE MACHINE ----------------------------------------------- + + -- DDR STATE MACHINE ----------------------------------------------- DDR_SM.CLK = DDRCLK0; CASE DDR_SM IS WHEN DS_T1 => @@ -336,12 +344,13 @@ BEGIN END IF; END IF; END IF; --- READ + + -- READ WHEN DS_T4R => CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; VCAS = VCC; - SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU + SR_DDR_FB = CPU_AC; -- READ DATEN F�R CPU SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN DDR_SM = DS_T5R; @@ -357,7 +366,8 @@ BEGIN VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN DDR_SM = DS_CB6; END IF; --- WRITE + + -- WRITE WHEN DS_T4W => CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; @@ -383,7 +393,7 @@ BEGIN VCAS = VCC; VWE = VCC; SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL = VCC; -- 2. H�LFTE WRITE DATEN SELEKTIEREN SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV DDR_SM = DS_T7W; @@ -391,7 +401,7 @@ BEGIN CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL = VCC; -- 2. H�LFTE WRITE DATEN SELEKTIEREN DDR_SM = DS_T8W; WHEN DS_T8W => @@ -407,7 +417,8 @@ BEGIN VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN DDR_SM = DS_CB6; END IF; --- FIFO READ + + -- FIFO READ WHEN DS_T4F => VCAS = VCC; SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO @@ -497,7 +508,8 @@ BEGIN DDR_SM = DS_T7F; END IF; --- CONFIG CYCLUS + + -- CONFIG CYCLUS WHEN DS_C2 => DDR_SM = DS_C3; WHEN DS_C3 => @@ -520,18 +532,20 @@ BEGIN VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE DDR_SM = DS_N8; --- CLOSE FIFO BANK + + -- CLOSE FIFO BANK WHEN DS_CB6 => FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN + VRAS = VCC; -- B�NKE SCHLIESSEN VWE = VCC; DDR_SM = DS_N7; WHEN DS_CB8 => FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN + VRAS = VCC; -- B�NKE SCHLIESSEN VWE = VCC; DDR_SM = DS_T1; --- REFRESH 70NS = 10 ZYCLEN + + -- REFRESH 70NS = 10 ZYCLEN WHEN DS_R2 => IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN VRAS = VCC; -- ALLE BANKS SCHLIESSEN @@ -552,7 +566,8 @@ BEGIN DDR_SM = DS_R6; WHEN DS_R6 => DDR_SM = DS_N5; --- LEERSCHLAUFE + + -- LEERSCHLAUFE WHEN DS_N5 => DDR_SM = DS_N6; WHEN DS_N6 => @@ -584,14 +599,14 @@ BEGIN FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00"); FIFO_BANK_OK.CLK = DDRCLK0; FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK; - -- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- + -- Z�HLER R�CKSETZEN WENN CLR FIFO ---------------- CLR_FIFO_SYNC.CLK =DDRCLK0; CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN CLEAR_FIFO_CNT.CLK = DDRCLK0; CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE; STOP.CLK = DDRCLK0; STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT; - -- ZÄHLEN ----------------------------------------------- + -- Z�HLEN ----------------------------------------------- VIDEO_ADR_CNT[].CLK = DDRCLK0; VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT; VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] @@ -608,12 +623,12 @@ BEGIN -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS ----------------------------------------------------------------------------------------- DDR_REFRESH_CNT[].CLK = CLK33M; - DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z�HLEN 0-2047 REFRESH_TIME.CLK = DDRCLK0; REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC DDR_REFRESH_SIG[].CLK = DDRCLK0; DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; - DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST�CK (8 REFRESH UND 1 ALS VORLAUF) # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT DDR_REFRESH_REQ.CLK = DDRCLK0; DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; diff --git a/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 2c9adcc..f74f1dd 100644 --- a/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -1,4 +1,4 @@ -TITLE "VIDEO MODUSE UND CLUT CONTROL"; +TITLE "VIDEO MODI AND CLUT CONTROL"; -- CREATED BY FREDI ASCHWANDEN @@ -8,58 +8,58 @@ INCLUDE "lpm_bustri_BYT.inc"; -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -SUBDESIGN VIDEO_MOD_MUX_CLUTCTR +SUBDESIGN video_mod_mux_clutctr ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - nRSTO : INPUT; - MAIN_CLK : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_WR : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nFB_BURST : INPUT; - FB_ADR[31..0] : INPUT; - CLK33M : INPUT; - CLK25M : INPUT; - BLITTER_RUN : INPUT; - CLK_VIDEO : INPUT; - VR_D[8..0] : INPUT; - VR_BUSY : INPUT; - COLOR8 : OUTPUT; - ACP_CLUT_RD : OUTPUT; - COLOR1 : OUTPUT; - FALCON_CLUT_RDH : OUTPUT; - FALCON_CLUT_RDL : OUTPUT; - FALCON_CLUT_WR[3..0] : OUTPUT; - ST_CLUT_RD : OUTPUT; - ST_CLUT_WR[1..0] : OUTPUT; - CLUT_MUX_ADR[3..0] : OUTPUT; - HSYNC : OUTPUT; - VSYNC : OUTPUT; - nBLANK : OUTPUT; - nSYNC : OUTPUT; - nPD_VGA : OUTPUT; - FIFO_RDE : OUTPUT; - COLOR2 : OUTPUT; - COLOR4 : OUTPUT; - PIXEL_CLK : OUTPUT; - CLUT_OFF[3..0] : OUTPUT; - BLITTER_ON : OUTPUT; - VIDEO_RAM_CTR[15..0] : OUTPUT; - VIDEO_MOD_TA : OUTPUT; - CCR[23..0] : OUTPUT; - CCSEL[2..0] : OUTPUT; - ACP_CLUT_WR[3..0] : OUTPUT; - INTER_ZEI : OUTPUT; - DOP_FIFO_CLR : OUTPUT; - VIDEO_RECONFIG : OUTPUT; - VR_WR : OUTPUT; - VR_RD : OUTPUT; - CLR_FIFO : OUTPUT; - FB_AD[31..0] : BIDIR; + nRSTO : INPUT; + MAIN_CLK : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_WR : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nFB_BURST : INPUT; + FB_ADR[31..0] : INPUT; + CLK33M : INPUT; + CLK25M : INPUT; + BLITTER_RUN : INPUT; + CLK_VIDEO : INPUT; + VR_D[8..0] : INPUT; + VR_BUSY : INPUT; + COLOR8 : OUTPUT; + ACP_CLUT_RD : OUTPUT; + COLOR1 : OUTPUT; + FALCON_CLUT_RDH : OUTPUT; + FALCON_CLUT_RDL : OUTPUT; + FALCON_CLUT_WR[3..0] : OUTPUT; + ST_CLUT_RD : OUTPUT; + ST_CLUT_WR[1..0] : OUTPUT; + CLUT_MUX_ADR[3..0] : OUTPUT; + HSYNC : OUTPUT; + VSYNC : OUTPUT; + nBLANK : OUTPUT; + nSYNC : OUTPUT; + nPD_VGA : OUTPUT; + FIFO_RDE : OUTPUT; + COLOR2 : OUTPUT; + COLOR4 : OUTPUT; + PIXEL_CLK : OUTPUT; + CLUT_OFF[3..0] : OUTPUT; + BLITTER_ON : OUTPUT; + VIDEO_RAM_CTR[15..0] : OUTPUT; + VIDEO_MOD_TA : OUTPUT; + CCR[23..0] : OUTPUT; + CCSEL[2..0] : OUTPUT; + ACP_CLUT_WR[3..0] : OUTPUT; + INTER_ZEI : OUTPUT; + DOP_FIFO_CLR : OUTPUT; + VIDEO_RECONFIG : OUTPUT; + VR_WR : OUTPUT; + VR_RD : OUTPUT; + CLR_FIFO : OUTPUT; + FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) @@ -98,12 +98,12 @@ VARIABLE VDL_LWD[15..0] :DFFE; VDL_LWD_CS :NODE; -- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT + CLUT_TA :DFF; -- needs one wait state HSYNC :DFF; HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK + HSY_LEN[7..0] :DFF; -- length of hsync pulse in pixel_clk HSYNC_START :DFF; - LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT + LAST :DFF; -- reached last pixel of a line VSYNC :DFF; VSYNC_START :DFFE; VSYNC_I[2..0] :DFFE; @@ -191,60 +191,90 @@ VARIABLE VDL_VCT_CS :NODE; VDL_VMD[3..0] :DFFE; VDL_VMD_CS :NODE; + ACP_VCTR6_DUP : NODE; BEGIN --- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + -- BYT SELECT 32 BIT + FB_B0 = FB_ADR[1..0] == 0; -- ADR==0 + FB_B1 = FB_ADR[1..0] == 1 -- ADR==1 # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + FB_B2 = FB_ADR[1..0] == 2 -- ADR==2 # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + FB_B3 = FB_ADR[1..0] == 3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0]==0; -- ADR==0 - FB_16B1 = FB_ADR[0]==1 -- ADR==1 + + -- BYT SELECT 16 BIT + FB_16B0 = FB_ADR[0] == 0; -- ADR==0 + FB_16B1 = FB_ADR[0] == 1 -- ADR==1 # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT --- ACP CLUT -- - ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 + + -- ACP CLUT -- + ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024 ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; + + CLUT_TA.CLK = MAIN_CLK; CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; ---FALCON CLUT -- - FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 + + + --FALCON CLUT -- + FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400 FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; --- ST CLUT -- - ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 + + + -- ST CLUT -- + ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20 ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; --- ST SHIFT MODE + + + -- ST SHIFT MODE ST_SHIFT_MODE[].CLK = MAIN_CLK; - ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 + ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2 ST_SHIFT_MODE[] = FB_AD[25..24]; ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO - COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN - COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN --- FALCON SHIFT MODE + + COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO + COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN + COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN + + + -- FALCON SHIFT MODE FALCON_SHIFT_MODE[].CLK = MAIN_CLK; - FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 + FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2 FALCON_SHIFT_MODE[] = FB_AD[26..16]; FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; + + CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; + + COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; --- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS + + + -- ACP VIDEO CONTROL + -- BIT 0=ACP VIDEO ON, + -- 1=POWER ON VIDEO DAC, + -- 2=ACP 24BIT, + -- 3=ACP 16BIT, + -- 4=ACP 8BIT, + -- 5=ACP 1BIT, + -- 6=FALCON SHIFT MODE, + -- 7=ST SHIFT MODE, + -- 9..8= VCLK FREQUENZ, + -- 15=-SYNC ALLOWED, + -- 31..16=VIDEO_RAM_CTR, + -- 25=RANDFARBE EINSCHALTEN, + -- 26=STANDARD ATARI SYNCS ACP_VCTR[].CLK = MAIN_CLK; - ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 + ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4 ACP_VCTR[31..8] = FB_AD[31..8]; ACP_VCTR[5..0] = FB_AD[5..0]; ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; @@ -253,9 +283,11 @@ BEGIN ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; - -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG - -- HORIZONTAL TIMING 640x480 + + -- ATARI MODUS + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL�SUNG + + -- HORIZONTAL TIMING 640x480 ATARI_HH[].CLK = MAIN_CLK; ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 ATARI_HH[] = FB_AD[]; @@ -263,7 +295,8 @@ BEGIN ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 640x480 + + -- VERTIKAL TIMING 640x480 ATARI_VH[].CLK = MAIN_CLK; ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 ATARI_VH[] = FB_AD[]; @@ -271,7 +304,8 @@ BEGIN ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - -- HORIZONTAL TIMING 320x240 + + -- HORIZONTAL TIMING 320x240 ATARI_HL[].CLK = MAIN_CLK; ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 ATARI_HL[] = FB_AD[]; @@ -279,7 +313,8 @@ BEGIN ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 320x240 + + -- VERTIKAL TIMING 320x240 ATARI_VL[].CLK = MAIN_CLK; ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 ATARI_VL[] = FB_AD[]; @@ -287,7 +322,9 @@ BEGIN ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; --- VIDEO PLL CONFIG + + + -- VIDEO PLL CONFIG VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY VR_WR.CLK = MAIN_CLK; VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; @@ -298,21 +335,28 @@ BEGIN VR_FRQ[].CLK = MAIN_CLK; VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; VR_FRQ[] = FB_AD[23..16]; --- VIDEO PLL RECONFIG + + -- VIDEO PLL RECONFIG VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 VIDEO_RECONFIG.CLK = MAIN_CLK; VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; ------------------------------------------------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------------------------------------------------ VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; --------------- COLOR MODE IM ACP SETZEN + + -------------- COLOR MODE IM ACP SETZEN COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; --- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + + -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + + -- duplicate ACP_VCTR6 according to TimeQuest recommendations + ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR6 = ACP_VCTR6_DUP; ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; FALCON_VIDEO = ACP_VCTR7; FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; @@ -325,118 +369,140 @@ BEGIN # B"101" & COLOR16 # B"110" & COLOR24 # B"111" & RAND_ON; --- DIVERSE (VIDEO)-REGISTER ---------------------------- --- RANDFARBE + + -- DIVERSE (VIDEO)-REGISTER ---------------------------- + + -- RANDFARBE CCR[].CLK = MAIN_CLK; CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 CCR[] = FB_AD[23..0]; CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; ---SYS CTR + + --SYS CTR SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; BLITTER_ON = !SYS_CTR3; ---VDL_LOF + + --VDL_LOF VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 VDL_LOF[].CLK = MAIN_CLK; VDL_LOF[] = FB_AD[31..16]; VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; ---VDL_LWD + + --VDL_LWD VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 VDL_LWD[].CLK = MAIN_CLK; VDL_LWD[] = FB_AD[31..16]; VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; --- HORIZONTAL --- VDL_HHT + + -- HORIZONTAL + + -- VDL_HHT VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 VDL_HHT[].CLK = MAIN_CLK; VDL_HHT[] = FB_AD[27..16]; VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; --- VDL_HBE + + -- VDL_HBE VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 VDL_HBE[].CLK = MAIN_CLK; VDL_HBE[] = FB_AD[27..16]; VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; --- VDL_HDB + + -- VDL_HDB VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 VDL_HDB[].CLK = MAIN_CLK; VDL_HDB[] = FB_AD[27..16]; VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; --- VDL_HDE + + -- VDL_HDE VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 VDL_HDE[].CLK = MAIN_CLK; VDL_HDE[] = FB_AD[27..16]; VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; --- VDL_HBB + + -- VDL_HBB VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 VDL_HBB[].CLK = MAIN_CLK; VDL_HBB[] = FB_AD[27..16]; VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; --- VDL_HSS + + -- VDL_HSS VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 VDL_HSS[].CLK = MAIN_CLK; VDL_HSS[] = FB_AD[27..16]; VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; --- VERTIKAL --- VDL_VBE + + -- VERTIKAL + + -- VDL_VBE VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 VDL_VBE[].CLK = MAIN_CLK; VDL_VBE[] = FB_AD[26..16]; VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; --- VDL_VDB + + -- VDL_VDB VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 VDL_VDB[].CLK = MAIN_CLK; VDL_VDB[] = FB_AD[26..16]; VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; --- VDL_VDE + + -- VDL_VDE VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 VDL_VDE[].CLK = MAIN_CLK; VDL_VDE[] = FB_AD[26..16]; VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; --- VDL_VBB + + -- VDL_VBB VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 VDL_VBB[].CLK = MAIN_CLK; VDL_VBB[] = FB_AD[26..16]; VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; --- VDL_VSS + + -- VDL_VSS VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 VDL_VSS[].CLK = MAIN_CLK; VDL_VSS[] = FB_AD[26..16]; VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; --- VDL_VFT + + -- VDL_VFT VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 VDL_VFT[].CLK = MAIN_CLK; VDL_VFT[] = FB_AD[26..16]; VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; --- VDL_VCT + + -- VDL_VCT VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 VDL_VCT[].CLK = MAIN_CLK; VDL_VCT[] = FB_AD[24..16]; VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; --- VDL_VMD + + -- VDL_VMD VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 VDL_VMD[].CLK = MAIN_CLK; VDL_VMD[] = FB_AD[19..16]; VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; ---- REGISTER OUT + + --- REGISTER OUT FB_AD[31..16] = lpm_bustri_WORD( ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) @@ -484,8 +550,9 @@ BEGIN # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; --- VIDEO AUSGABE SETZEN - CLK17M.CLK = CLK33M; + + -- VIDEO AUSGABE SETZEN + CLK17M.CLK = MAIN_CLK; CLK17M = !CLK17M; CLK13M.CLK = CLK25M; CLK13M = !CLK13M; @@ -496,9 +563,10 @@ BEGIN # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; --------------------------------------------------------------- --- HORIZONTALE SYNC LÄNGE in PIXEL_CLK ----------------------------------------------------------------- + + -------------------------------------------------------------- + -- HORIZONTALE SYNC L�NGE in PIXEL_CLK + ---------------------------------------------------------------- HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) @@ -517,14 +585,15 @@ BEGIN HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN # 640 & !VDL_VMD2; --- DOPPELZEILENMODUS + + -- DOPPELZEILENMODUS DOP_ZEI.CLK = MAIN_CLK; DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS INTER_ZEI.CLK = PIXEL_CLK; INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L�SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 @@ -566,7 +635,8 @@ BEGIN # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --- ZÄHLER + + -- Z�HLER LAST.CLK = PIXEL_CLK; LAST = VHCNT[]==(H_TOTAL[]-2); VHCNT[].CLK = PIXEL_CLK; @@ -574,10 +644,11 @@ BEGIN VVCNT[].CLK = PIXEL_CLK; VVCNT[].ENA = LAST; VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); --- DISPLAY ON OFF + + -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[] - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/Video/altddio_bidir0.qip b/Video/altddio_bidir0.qip index 0b211a6..3339057 100644 --- a/Video/altddio_bidir0.qip +++ b/Video/altddio_bidir0.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"] diff --git a/Video/altddio_bidir0.vhd b/Video/altddio_bidir0.vhd index b662abe..a0ae0e0 100644 --- a/Video/altddio_bidir0.vhd +++ b/Video/altddio_bidir0.vhd @@ -1,136 +1,172 @@ --- megafunction wizard: %ALTDDIO_BIDIR% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: ALTDDIO_BIDIR - --- ============================================================ --- File Name: altddio_bidir0.vhd --- Megafunction Name(s): --- ALTDDIO_BIDIR --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY altddio_bidir0 IS - PORT - ( - datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - inclock : IN STD_LOGIC ; - oe : IN STD_LOGIC ; - outclock : IN STD_LOGIC ; - combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); - dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); - dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); - padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) - ); -END altddio_bidir0; - - -ARCHITECTURE SYN OF altddio_bidir0 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0); - -BEGIN - combout <= sub_wire0(31 DOWNTO 0); - dataout_h <= sub_wire1(31 DOWNTO 0); - dataout_l <= sub_wire2(31 DOWNTO 0); - - ALTDDIO_BIDIR_component : ALTDDIO_BIDIR - GENERIC MAP ( - extend_oe_disable => "OFF", - implement_input_in_lcell => "ON", - intended_device_family => "Cyclone III", - invert_output => "OFF", - lpm_hint => "UNUSED", - lpm_type => "altddio_bidir", - oe_reg => "UNREGISTERED", - power_up_high => "OFF", - width => 32 - ) - PORT MAP ( - datain_h => datain_h, - datain_l => datain_l, - oe => oe, - outclock => outclock, - inclock => inclock, - combout => sub_wire0, - dataout_h => sub_wire1, - dataout_l => sub_wire2, - padio => padio - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" --- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" --- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" --- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" --- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" --- Retrieval info: CONSTANT: WIDTH NUMERIC "32" --- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL "combout[31..0]" --- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0 --- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL "datain_h[31..0]" --- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0 --- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL "datain_l[31..0]" --- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0 --- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL "dataout_h[31..0]" --- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0 --- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL "dataout_l[31..0]" --- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0 --- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" --- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 --- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" --- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 --- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" --- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 --- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL "padio[31..0]" --- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.qip TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTDDIO_BIDIR% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_bidir + +-- ============================================================ +-- File Name: altddio_bidir0.vhd +-- Megafunction Name(s): +-- altddio_bidir +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_bidir0 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + inclock : IN STD_LOGIC ; + oe : IN STD_LOGIC := '1'; + outclock : IN STD_LOGIC ; + combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END altddio_bidir0; + + +ARCHITECTURE SYN OF altddio_bidir0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT altddio_bidir + GENERIC ( + extend_oe_disable : STRING; + implement_input_in_lcell : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + outclock : IN STD_LOGIC ; + padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); + inclock : IN STD_LOGIC ; + dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + oe : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout_h <= sub_wire0(31 DOWNTO 0); + combout <= sub_wire1(31 DOWNTO 0); + dataout_l <= sub_wire2(31 DOWNTO 0); + + altddio_bidir_component : altddio_bidir + GENERIC MAP ( + extend_oe_disable => "UNUSED", + implement_input_in_lcell => "ON", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_bidir", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 32 + ) + PORT MAP ( + outclock => outclock, + inclock => inclock, + oe => oe, + datain_h => datain_h, + datain_l => datain_l, + dataout_h => sub_wire0, + combout => sub_wire1, + dataout_l => sub_wire2, + padio => padio + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "1" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1" +-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1" +-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0] +-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0] +-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0] +-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0] +-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0] +-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock +-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0] +-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0 +-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0 +-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0 +-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0 +-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Video/altddio_out0.bsf b/Video/altddio_out0.bsf index 6e080ad..6554c2f 100644 --- a/Video/altddio_out0.bsf +++ b/Video/altddio_out0.bsf @@ -1,64 +1,64 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 256 112) - (text "altddio_out0" (rect 89 0 188 17)(font "Dialog" (font_size 10))) - (text "inst" (rect 8 97 26 108)(font "Arial" )) - (port - (pt 0 48) - (input) - (text "datain_h[3..0]" (rect 0 0 89 13)(font "Dialog" (font_size 8))) - (text "datain_h[3..0]" (rect 4 35 80 47)(font "Dialog" (font_size 8))) - (line (pt 0 48)(pt 96 48)(line_width 3)) - ) - (port - (pt 0 64) - (input) - (text "datain_l[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8))) - (text "datain_l[3..0]" (rect 4 51 76 63)(font "Dialog" (font_size 8))) - (line (pt 0 64)(pt 96 64)(line_width 3)) - ) - (port - (pt 0 80) - (input) - (text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8))) - (text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8))) - (line (pt 0 80)(pt 96 80)) - ) - (port - (pt 256 48) - (output) - (text "dataout[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8))) - (text "dataout[3..0]" (rect 180 35 252 47)(font "Dialog" (font_size 8))) - (line (pt 256 48)(pt 160 48)(line_width 3)) - ) - (drawing - (line (pt 96 32)(pt 160 32)) - (line (pt 160 32)(pt 160 96)) - (line (pt 96 96)(pt 160 96)) - (line (pt 96 32)(pt 96 96)) - (line (pt 0 0)(pt 256 0)) - (line (pt 256 0)(pt 256 112)) - (line (pt 0 112)(pt 256 112)) - (line (pt 0 0)(pt 0 112)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8))) + (text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 3)) + ) + (port + (pt 0 40) + (input) + (text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8))) + (text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 3)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "high" (rect 92 84 109 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/Video/altddio_out0.cmp b/Video/altddio_out0.cmp index e118a1f..df70a5a 100644 --- a/Video/altddio_out0.cmp +++ b/Video/altddio_out0.cmp @@ -1,24 +1,24 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altddio_out0 - PORT - ( - datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - outclock : IN STD_LOGIC ; - dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out0 + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +end component; diff --git a/Video/altddio_out0.inc b/Video/altddio_out0.inc index 0569f3b..f534925 100644 --- a/Video/altddio_out0.inc +++ b/Video/altddio_out0.inc @@ -1,25 +1,25 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altddio_out0 -( - datain_h[3..0], - datain_l[3..0], - outclock -) - -RETURNS ( - dataout[3..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out0 +( + datain_h[3..0], + datain_l[3..0], + outclock +) + +RETURNS ( + dataout[3..0] +); diff --git a/Video/altddio_out0.ppf b/Video/altddio_out0.ppf index d14dab9..3f3cfb5 100644 --- a/Video/altddio_out0.ppf +++ b/Video/altddio_out0.ppf @@ -1,11 +1,11 @@ - - - - - - - - - - - + + + + + + + + + + + diff --git a/Video/altddio_out0.qip b/Video/altddio_out0.qip index 543aadf..8193856 100644 --- a/Video/altddio_out0.qip +++ b/Video/altddio_out0.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] diff --git a/Video/altddio_out0.vhd b/Video/altddio_out0.vhd index f84eacc..f129798 100644 --- a/Video/altddio_out0.vhd +++ b/Video/altddio_out0.vhd @@ -1,110 +1,136 @@ --- megafunction wizard: %ALTDDIO_OUT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: ALTDDIO_OUT - --- ============================================================ --- File Name: altddio_out0.vhd --- Megafunction Name(s): --- ALTDDIO_OUT --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY altddio_out0 IS - PORT - ( - datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - outclock : IN STD_LOGIC ; - dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) - ); -END altddio_out0; - - -ARCHITECTURE SYN OF altddio_out0 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); - -BEGIN - dataout <= sub_wire0(3 DOWNTO 0); - - ALTDDIO_OUT_component : ALTDDIO_OUT - GENERIC MAP ( - extend_oe_disable => "OFF", - intended_device_family => "Cyclone III", - invert_output => "ON", - lpm_hint => "UNUSED", - lpm_type => "altddio_out", - oe_reg => "UNREGISTERED", - power_up_high => "ON", - width => 4 - ) - PORT MAP ( - datain_h => datain_h, - datain_l => datain_l, - outclock => outclock, - dataout => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON" --- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" --- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" --- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" --- Retrieval info: CONSTANT: WIDTH NUMERIC "4" --- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL "datain_h[3..0]" --- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0 --- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL "datain_l[3..0]" --- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0 --- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]" --- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0 --- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" --- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.qip TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out0.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out0 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END altddio_out0; + + +ARCHITECTURE SYN OF altddio_out0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout <= sub_wire0(3 DOWNTO 0); + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "ON", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "ON", + width => 4 + ) + PORT MAP ( + outclock => outclock, + datain_h => datain_h, + datain_l => datain_l, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "4" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0] +-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0] +-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0] +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0 +-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0 +-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Video/altddio_out2.bsf b/Video/altddio_out2.bsf index f13cbc3..ff039ee 100644 --- a/Video/altddio_out2.bsf +++ b/Video/altddio_out2.bsf @@ -1,64 +1,64 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 256 112) - (text "altddio_out2" (rect 89 0 188 17)(font "Dialog" (font_size 10))) - (text "inst" (rect 8 97 26 108)(font "Arial" )) - (port - (pt 0 48) - (input) - (text "datain_h[23..0]" (rect 0 0 97 13)(font "Dialog" (font_size 8))) - (text "datain_h[23..0]" (rect 4 35 87 47)(font "Dialog" (font_size 8))) - (line (pt 0 48)(pt 96 48)(line_width 3)) - ) - (port - (pt 0 64) - (input) - (text "datain_l[23..0]" (rect 0 0 93 13)(font "Dialog" (font_size 8))) - (text "datain_l[23..0]" (rect 4 51 83 63)(font "Dialog" (font_size 8))) - (line (pt 0 64)(pt 96 64)(line_width 3)) - ) - (port - (pt 0 80) - (input) - (text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8))) - (text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8))) - (line (pt 0 80)(pt 96 80)) - ) - (port - (pt 256 48) - (output) - (text "dataout[23..0]" (rect 0 0 92 13)(font "Dialog" (font_size 8))) - (text "dataout[23..0]" (rect 173 35 252 47)(font "Dialog" (font_size 8))) - (line (pt 256 48)(pt 160 48)(line_width 3)) - ) - (drawing - (line (pt 96 32)(pt 160 32)) - (line (pt 160 32)(pt 160 96)) - (line (pt 96 96)(pt 160 96)) - (line (pt 96 32)(pt 96 96)) - (line (pt 0 0)(pt 256 0)) - (line (pt 256 0)(pt 256 112)) - (line (pt 0 112)(pt 256 112)) - (line (pt 0 0)(pt 0 112)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8))) + (text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 3)) + ) + (port + (pt 0 40) + (input) + (text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8))) + (text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8))) + (text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 3)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/Video/altddio_out2.cmp b/Video/altddio_out2.cmp index 0bbc223..ad8aa55 100644 --- a/Video/altddio_out2.cmp +++ b/Video/altddio_out2.cmp @@ -1,24 +1,24 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altddio_out2 - PORT - ( - datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - outclock : IN STD_LOGIC ; - dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out2 + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/Video/altddio_out2.inc b/Video/altddio_out2.inc index 61b393c..2257c30 100644 --- a/Video/altddio_out2.inc +++ b/Video/altddio_out2.inc @@ -1,25 +1,25 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altddio_out2 -( - datain_h[23..0], - datain_l[23..0], - outclock -) - -RETURNS ( - dataout[23..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out2 +( + datain_h[23..0], + datain_l[23..0], + outclock +) + +RETURNS ( + dataout[23..0] +); diff --git a/Video/altddio_out2.ppf b/Video/altddio_out2.ppf index 46df7ff..93df472 100644 --- a/Video/altddio_out2.ppf +++ b/Video/altddio_out2.ppf @@ -1,11 +1,11 @@ - - - - - - - - - - - + + + + + + + + + + + diff --git a/Video/altddio_out2.qip b/Video/altddio_out2.qip index 0dee468..d72d5ce 100644 --- a/Video/altddio_out2.qip +++ b/Video/altddio_out2.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"] diff --git a/Video/altddio_out2.vhd b/Video/altddio_out2.vhd index ed0ae66..30a8586 100644 --- a/Video/altddio_out2.vhd +++ b/Video/altddio_out2.vhd @@ -1,110 +1,136 @@ --- megafunction wizard: %ALTDDIO_OUT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: ALTDDIO_OUT - --- ============================================================ --- File Name: altddio_out2.vhd --- Megafunction Name(s): --- ALTDDIO_OUT --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY altddio_out2 IS - PORT - ( - datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - outclock : IN STD_LOGIC ; - dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) - ); -END altddio_out2; - - -ARCHITECTURE SYN OF altddio_out2 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); - -BEGIN - dataout <= sub_wire0(23 DOWNTO 0); - - ALTDDIO_OUT_component : ALTDDIO_OUT - GENERIC MAP ( - extend_oe_disable => "OFF", - intended_device_family => "Cyclone III", - invert_output => "OFF", - lpm_hint => "UNUSED", - lpm_type => "altddio_out", - oe_reg => "UNREGISTERED", - power_up_high => "OFF", - width => 24 - ) - PORT MAP ( - datain_h => datain_h, - datain_l => datain_l, - outclock => outclock, - dataout => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" --- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" --- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" --- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" --- Retrieval info: CONSTANT: WIDTH NUMERIC "24" --- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL "datain_h[23..0]" --- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0 --- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL "datain_l[23..0]" --- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0 --- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL "dataout[23..0]" --- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0 --- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" --- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.qip TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out2.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out2 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END altddio_out2; + + +ARCHITECTURE SYN OF altddio_out2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout <= sub_wire0(23 DOWNTO 0); + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 24 + ) + PORT MAP ( + outclock => outclock, + datain_h => datain_h, + datain_l => datain_l, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "24" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0] +-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0] +-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0] +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0 +-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0 +-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Video/lpm_constant0.bsf b/Video/lpm_constant0.bsf index f2188cc..684bbae 100644 --- a/Video/lpm_constant0.bsf +++ b/Video/lpm_constant0.bsf @@ -1,49 +1,42 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 112 48) - (text "lpm_constant0" (rect 14 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 33 26 44)(font "Arial" )) - (port - (pt 112 24) - (output) - (text "result[4..0]" (rect 0 0 60 13)(font "Arial" (font_size 8))) - (text "0" (rect 87 18 94 30)(font "Arial" (font_size 8))) - (line (pt 112 24)(pt 96 24)(line_width 3)) - ) - (drawing - (text "5" (rect 99 27 204 64)(font "Arial" )) - (line (pt 106 20)(pt 98 28)) - (line (pt 16 16)(pt 16 32)) - (line (pt 16 16)(pt 96 16)) - (line (pt 16 32)(pt 96 32)) - (line (pt 96 16)(pt 96 32)) - (line (pt 0 0)(pt 114 0)) - (line (pt 114 0)(pt 114 50)) - (line (pt 0 50)(pt 114 50)) - (line (pt 0 0)(pt 0 50)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "5" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/Video/lpm_constant0.cmp b/Video/lpm_constant0.cmp index 36b4cd6..7143429 100644 --- a/Video/lpm_constant0.cmp +++ b/Video/lpm_constant0.cmp @@ -1,21 +1,21 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_constant0 - PORT - ( - result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant0 + PORT + ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_constant0.qip b/Video/lpm_constant0.qip index bf6dc5d..bb19c49 100644 --- a/Video/lpm_constant0.qip +++ b/Video/lpm_constant0.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"] diff --git a/Video/lpm_constant0.vhd b/Video/lpm_constant0.vhd index c9b9c7a..63631cc 100644 --- a/Video/lpm_constant0.vhd +++ b/Video/lpm_constant0.vhd @@ -1,109 +1,108 @@ --- megafunction wizard: %LPM_CONSTANT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_CONSTANT - --- ============================================================ --- File Name: lpm_constant0.vhd --- Megafunction Name(s): --- LPM_CONSTANT --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_constant0 IS - PORT - ( - result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); -END lpm_constant0; - - -ARCHITECTURE SYN OF lpm_constant0 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - - - - COMPONENT lpm_constant - GENERIC ( - lpm_cvalue : NATURAL; - lpm_hint : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - result <= sub_wire0(4 DOWNTO 0); - - LPM_CONSTANT_component : LPM_CONSTANT - GENERIC MAP ( - lpm_cvalue => 0, - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "LPM_CONSTANT", - lpm_width => 5 - ) - PORT MAP ( - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: Radix NUMERIC "2" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: Value NUMERIC "0" --- Retrieval info: PRIVATE: nBit NUMERIC "5" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" --- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL "result[4..0]" --- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant0.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant0 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_constant0; + + +ARCHITECTURE SYN OF lpm_constant0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(4 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 5 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0] +-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_constant1.bsf b/Video/lpm_constant1.bsf index 515002e..01fdb2b 100644 --- a/Video/lpm_constant1.bsf +++ b/Video/lpm_constant1.bsf @@ -1,49 +1,42 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 112 48) - (text "lpm_constant1" (rect 14 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 33 26 44)(font "Arial" )) - (port - (pt 112 24) - (output) - (text "result[1..0]" (rect 0 0 60 13)(font "Arial" (font_size 8))) - (text "0" (rect 87 18 94 30)(font "Arial" (font_size 8))) - (line (pt 112 24)(pt 96 24)(line_width 3)) - ) - (drawing - (text "2" (rect 99 27 204 64)(font "Arial" )) - (line (pt 106 20)(pt 98 28)) - (line (pt 16 16)(pt 16 32)) - (line (pt 16 16)(pt 96 16)) - (line (pt 16 32)(pt 96 32)) - (line (pt 96 16)(pt 96 32)) - (line (pt 0 0)(pt 114 0)) - (line (pt 114 0)(pt 114 50)) - (line (pt 0 50)(pt 114 50)) - (line (pt 0 0)(pt 0 50)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "2" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/Video/lpm_constant1.cmp b/Video/lpm_constant1.cmp index 6af1a7c..a7e275c 100644 --- a/Video/lpm_constant1.cmp +++ b/Video/lpm_constant1.cmp @@ -1,21 +1,21 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_constant1 - PORT - ( - result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant1 + PORT + ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_constant1.inc b/Video/lpm_constant1.inc index 945d114..9b556e7 100644 --- a/Video/lpm_constant1.inc +++ b/Video/lpm_constant1.inc @@ -1,23 +1,23 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_constant1 -( - -) - -RETURNS ( - result[1..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_constant1 +( + +) + +RETURNS ( + result[1..0] +); diff --git a/Video/lpm_constant1.qip b/Video/lpm_constant1.qip index b0bd0cd..2bc12e7 100644 --- a/Video/lpm_constant1.qip +++ b/Video/lpm_constant1.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"] diff --git a/Video/lpm_constant1.vhd b/Video/lpm_constant1.vhd index 5c437f5..afa67ba 100644 --- a/Video/lpm_constant1.vhd +++ b/Video/lpm_constant1.vhd @@ -1,109 +1,108 @@ --- megafunction wizard: %LPM_CONSTANT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_CONSTANT - --- ============================================================ --- File Name: lpm_constant1.vhd --- Megafunction Name(s): --- LPM_CONSTANT --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_constant1 IS - PORT - ( - result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END lpm_constant1; - - -ARCHITECTURE SYN OF lpm_constant1 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); - - - - COMPONENT lpm_constant - GENERIC ( - lpm_cvalue : NATURAL; - lpm_hint : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - result <= sub_wire0(1 DOWNTO 0); - - LPM_CONSTANT_component : LPM_CONSTANT - GENERIC MAP ( - lpm_cvalue => 0, - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "LPM_CONSTANT", - lpm_width => 2 - ) - PORT MAP ( - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: Radix NUMERIC "2" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: Value NUMERIC "0" --- Retrieval info: PRIVATE: nBit NUMERIC "2" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" --- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL "result[1..0]" --- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant1.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant1 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END lpm_constant1; + + +ARCHITECTURE SYN OF lpm_constant1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(1 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 2 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" +-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0] +-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_constant2.bsf b/Video/lpm_constant2.bsf index 7ea4a33..a4b7697 100644 --- a/Video/lpm_constant2.bsf +++ b/Video/lpm_constant2.bsf @@ -1,49 +1,42 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 112 48) - (text "lpm_constant2" (rect 14 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 33 26 44)(font "Arial" )) - (port - (pt 112 24) - (output) - (text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8))) - (text "0" (rect 87 18 94 30)(font "Arial" (font_size 8))) - (line (pt 112 24)(pt 96 24)(line_width 3)) - ) - (drawing - (text "8" (rect 99 27 204 64)(font "Arial" )) - (line (pt 106 20)(pt 98 28)) - (line (pt 16 16)(pt 16 32)) - (line (pt 16 16)(pt 96 16)) - (line (pt 16 32)(pt 96 32)) - (line (pt 96 16)(pt 96 32)) - (line (pt 0 0)(pt 114 0)) - (line (pt 114 0)(pt 114 50)) - (line (pt 0 50)(pt 114 50)) - (line (pt 0 0)(pt 0 50)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "8" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/Video/lpm_constant2.cmp b/Video/lpm_constant2.cmp index b6b1a2f..63cc406 100644 --- a/Video/lpm_constant2.cmp +++ b/Video/lpm_constant2.cmp @@ -1,21 +1,21 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_constant2 - PORT - ( - result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant2 + PORT + ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_constant2.qip b/Video/lpm_constant2.qip index 02c8f72..ad38485 100644 --- a/Video/lpm_constant2.qip +++ b/Video/lpm_constant2.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"] diff --git a/Video/lpm_constant2.vhd b/Video/lpm_constant2.vhd index cffe365..f25e68f 100644 --- a/Video/lpm_constant2.vhd +++ b/Video/lpm_constant2.vhd @@ -1,109 +1,108 @@ --- megafunction wizard: %LPM_CONSTANT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_CONSTANT - --- ============================================================ --- File Name: lpm_constant2.vhd --- Megafunction Name(s): --- LPM_CONSTANT --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_constant2 IS - PORT - ( - result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -END lpm_constant2; - - -ARCHITECTURE SYN OF lpm_constant2 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); - - - - COMPONENT lpm_constant - GENERIC ( - lpm_cvalue : NATURAL; - lpm_hint : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - result <= sub_wire0(7 DOWNTO 0); - - LPM_CONSTANT_component : LPM_CONSTANT - GENERIC MAP ( - lpm_cvalue => 0, - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "LPM_CONSTANT", - lpm_width => 8 - ) - PORT MAP ( - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: Radix NUMERIC "2" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: Value NUMERIC "0" --- Retrieval info: PRIVATE: nBit NUMERIC "8" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" --- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]" --- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant2.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant2 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_constant2; + + +ARCHITECTURE SYN OF lpm_constant2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(7 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 8 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_constant3.bsf b/Video/lpm_constant3.bsf index 29284ad..7616869 100644 --- a/Video/lpm_constant3.bsf +++ b/Video/lpm_constant3.bsf @@ -1,49 +1,42 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 112 48) - (text "lpm_constant3" (rect 14 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 33 26 44)(font "Arial" )) - (port - (pt 112 24) - (output) - (text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8))) - (text "0" (rect 87 18 94 30)(font "Arial" (font_size 8))) - (line (pt 112 24)(pt 96 24)(line_width 3)) - ) - (drawing - (text "7" (rect 99 27 204 64)(font "Arial" )) - (line (pt 106 20)(pt 98 28)) - (line (pt 16 16)(pt 16 32)) - (line (pt 16 16)(pt 96 16)) - (line (pt 16 32)(pt 96 32)) - (line (pt 96 16)(pt 96 32)) - (line (pt 0 0)(pt 114 0)) - (line (pt 114 0)(pt 114 50)) - (line (pt 0 50)(pt 114 50)) - (line (pt 0 0)(pt 0 50)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "7" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/Video/lpm_constant3.cmp b/Video/lpm_constant3.cmp index f91faf3..0e2f877 100644 --- a/Video/lpm_constant3.cmp +++ b/Video/lpm_constant3.cmp @@ -1,21 +1,21 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_constant3 - PORT - ( - result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant3 + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_constant3.qip b/Video/lpm_constant3.qip index e679bb1..615a781 100644 --- a/Video/lpm_constant3.qip +++ b/Video/lpm_constant3.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"] diff --git a/Video/lpm_constant3.vhd b/Video/lpm_constant3.vhd index 8605ae4..5d47d8e 100644 --- a/Video/lpm_constant3.vhd +++ b/Video/lpm_constant3.vhd @@ -1,109 +1,108 @@ --- megafunction wizard: %LPM_CONSTANT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_CONSTANT - --- ============================================================ --- File Name: lpm_constant3.vhd --- Megafunction Name(s): --- LPM_CONSTANT --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_constant3 IS - PORT - ( - result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) - ); -END lpm_constant3; - - -ARCHITECTURE SYN OF lpm_constant3 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); - - - - COMPONENT lpm_constant - GENERIC ( - lpm_cvalue : NATURAL; - lpm_hint : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - result <= sub_wire0(6 DOWNTO 0); - - LPM_CONSTANT_component : LPM_CONSTANT - GENERIC MAP ( - lpm_cvalue => 0, - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "LPM_CONSTANT", - lpm_width => 7 - ) - PORT MAP ( - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: Radix NUMERIC "2" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: Value NUMERIC "0" --- Retrieval info: PRIVATE: nBit NUMERIC "7" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" --- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]" --- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant3.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant3 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_constant3; + + +ARCHITECTURE SYN OF lpm_constant3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(6 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 7 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "7" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0] +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_mux0.bsf b/Video/lpm_mux0.bsf index e028c90..ce1e27e 100644 --- a/Video/lpm_mux0.bsf +++ b/Video/lpm_mux0.bsf @@ -1,91 +1,83 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 128) - (text "lpm_mux0" (rect 43 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 113 26 124)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data3x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data3x[31..0]" (rect 4 27 67 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data2x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data2x[31..0]" (rect 4 43 67 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data1x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data1x[31..0]" (rect 4 59 67 71)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data0x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data0x[31..0]" (rect 4 75 67 87)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 4 91 29 103)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 64 104)) - ) - (port - (pt 72 128) - (input) - (text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical)) - (text "sel[1..0]" (rect 66 73 78 111)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 128)(pt 72 116)(line_width 3)) - ) - (port - (pt 144 72) - (output) - (text "result[31..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "result[31..0]" (rect 85 59 142 71)(font "Arial" (font_size 8))) - (line (pt 144 72)(pt 80 72)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 120)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 120)(pt 80 112)) - (line (pt 80 32)(pt 80 112)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 130)) - (line (pt 0 130)(pt 146 130)) - (line (pt 0 0)(pt 0 130)) - (line (pt 64 98)(pt 70 104)) - (line (pt 70 104)(pt 64 110)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 128) + (text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 1)) + ) + (port + (pt 80 128) + (input) + (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8))) + (line (pt 80 128)(pt 80 116)(line_width 3)) + ) + (port + (pt 152 72) + (output) + (text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8))) + (line (pt 152 72)(pt 88 72)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 120)(line_width 1)) + (line (pt 88 32)(pt 88 112)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 120)(pt 88 112)(line_width 1)) + (line (pt 72 98)(pt 78 104)(line_width 1)) + (line (pt 78 104)(pt 72 110)(line_width 1)) + ) +) diff --git a/Video/lpm_mux0.cmp b/Video/lpm_mux0.cmp index 5f233c1..7b6c18f 100644 --- a/Video/lpm_mux0.cmp +++ b/Video/lpm_mux0.cmp @@ -1,27 +1,27 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_mux0 - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux0 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_mux0.inc b/Video/lpm_mux0.inc index a925772..b0bc2be 100644 --- a/Video/lpm_mux0.inc +++ b/Video/lpm_mux0.inc @@ -1,28 +1,28 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_mux0 -( - clock, - data0x[31..0], - data1x[31..0], - data2x[31..0], - data3x[31..0], - sel[1..0] -) - -RETURNS ( - result[31..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux0 +( + clock, + data0x[31..0], + data1x[31..0], + data2x[31..0], + data3x[31..0], + sel[1..0] +) + +RETURNS ( + result[31..0] +); diff --git a/Video/lpm_mux0.qip b/Video/lpm_mux0.qip index 0b82f34..5e8e2b6 100644 --- a/Video/lpm_mux0.qip +++ b/Video/lpm_mux0.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] diff --git a/Video/lpm_mux0.vhd b/Video/lpm_mux0.vhd index 02ed2fd..9d641a4 100644 --- a/Video/lpm_mux0.vhd +++ b/Video/lpm_mux0.vhd @@ -1,252 +1,251 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_mux0.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_mux0 IS - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) - ); -END lpm_mux0; - - -ARCHITECTURE SYN OF lpm_mux0 IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (31 DOWNTO 0); - -BEGIN - sub_wire5 <= data0x(31 DOWNTO 0); - sub_wire4 <= data1x(31 DOWNTO 0); - sub_wire3 <= data2x(31 DOWNTO 0); - result <= sub_wire0(31 DOWNTO 0); - sub_wire1 <= data3x(31 DOWNTO 0); - sub_wire2(3, 0) <= sub_wire1(0); - sub_wire2(3, 1) <= sub_wire1(1); - sub_wire2(3, 2) <= sub_wire1(2); - sub_wire2(3, 3) <= sub_wire1(3); - sub_wire2(3, 4) <= sub_wire1(4); - sub_wire2(3, 5) <= sub_wire1(5); - sub_wire2(3, 6) <= sub_wire1(6); - sub_wire2(3, 7) <= sub_wire1(7); - sub_wire2(3, 8) <= sub_wire1(8); - sub_wire2(3, 9) <= sub_wire1(9); - sub_wire2(3, 10) <= sub_wire1(10); - sub_wire2(3, 11) <= sub_wire1(11); - sub_wire2(3, 12) <= sub_wire1(12); - sub_wire2(3, 13) <= sub_wire1(13); - sub_wire2(3, 14) <= sub_wire1(14); - sub_wire2(3, 15) <= sub_wire1(15); - sub_wire2(3, 16) <= sub_wire1(16); - sub_wire2(3, 17) <= sub_wire1(17); - sub_wire2(3, 18) <= sub_wire1(18); - sub_wire2(3, 19) <= sub_wire1(19); - sub_wire2(3, 20) <= sub_wire1(20); - sub_wire2(3, 21) <= sub_wire1(21); - sub_wire2(3, 22) <= sub_wire1(22); - sub_wire2(3, 23) <= sub_wire1(23); - sub_wire2(3, 24) <= sub_wire1(24); - sub_wire2(3, 25) <= sub_wire1(25); - sub_wire2(3, 26) <= sub_wire1(26); - sub_wire2(3, 27) <= sub_wire1(27); - sub_wire2(3, 28) <= sub_wire1(28); - sub_wire2(3, 29) <= sub_wire1(29); - sub_wire2(3, 30) <= sub_wire1(30); - sub_wire2(3, 31) <= sub_wire1(31); - sub_wire2(2, 0) <= sub_wire3(0); - sub_wire2(2, 1) <= sub_wire3(1); - sub_wire2(2, 2) <= sub_wire3(2); - sub_wire2(2, 3) <= sub_wire3(3); - sub_wire2(2, 4) <= sub_wire3(4); - sub_wire2(2, 5) <= sub_wire3(5); - sub_wire2(2, 6) <= sub_wire3(6); - sub_wire2(2, 7) <= sub_wire3(7); - sub_wire2(2, 8) <= sub_wire3(8); - sub_wire2(2, 9) <= sub_wire3(9); - sub_wire2(2, 10) <= sub_wire3(10); - sub_wire2(2, 11) <= sub_wire3(11); - sub_wire2(2, 12) <= sub_wire3(12); - sub_wire2(2, 13) <= sub_wire3(13); - sub_wire2(2, 14) <= sub_wire3(14); - sub_wire2(2, 15) <= sub_wire3(15); - sub_wire2(2, 16) <= sub_wire3(16); - sub_wire2(2, 17) <= sub_wire3(17); - sub_wire2(2, 18) <= sub_wire3(18); - sub_wire2(2, 19) <= sub_wire3(19); - sub_wire2(2, 20) <= sub_wire3(20); - sub_wire2(2, 21) <= sub_wire3(21); - sub_wire2(2, 22) <= sub_wire3(22); - sub_wire2(2, 23) <= sub_wire3(23); - sub_wire2(2, 24) <= sub_wire3(24); - sub_wire2(2, 25) <= sub_wire3(25); - sub_wire2(2, 26) <= sub_wire3(26); - sub_wire2(2, 27) <= sub_wire3(27); - sub_wire2(2, 28) <= sub_wire3(28); - sub_wire2(2, 29) <= sub_wire3(29); - sub_wire2(2, 30) <= sub_wire3(30); - sub_wire2(2, 31) <= sub_wire3(31); - sub_wire2(1, 0) <= sub_wire4(0); - sub_wire2(1, 1) <= sub_wire4(1); - sub_wire2(1, 2) <= sub_wire4(2); - sub_wire2(1, 3) <= sub_wire4(3); - sub_wire2(1, 4) <= sub_wire4(4); - sub_wire2(1, 5) <= sub_wire4(5); - sub_wire2(1, 6) <= sub_wire4(6); - sub_wire2(1, 7) <= sub_wire4(7); - sub_wire2(1, 8) <= sub_wire4(8); - sub_wire2(1, 9) <= sub_wire4(9); - sub_wire2(1, 10) <= sub_wire4(10); - sub_wire2(1, 11) <= sub_wire4(11); - sub_wire2(1, 12) <= sub_wire4(12); - sub_wire2(1, 13) <= sub_wire4(13); - sub_wire2(1, 14) <= sub_wire4(14); - sub_wire2(1, 15) <= sub_wire4(15); - sub_wire2(1, 16) <= sub_wire4(16); - sub_wire2(1, 17) <= sub_wire4(17); - sub_wire2(1, 18) <= sub_wire4(18); - sub_wire2(1, 19) <= sub_wire4(19); - sub_wire2(1, 20) <= sub_wire4(20); - sub_wire2(1, 21) <= sub_wire4(21); - sub_wire2(1, 22) <= sub_wire4(22); - sub_wire2(1, 23) <= sub_wire4(23); - sub_wire2(1, 24) <= sub_wire4(24); - sub_wire2(1, 25) <= sub_wire4(25); - sub_wire2(1, 26) <= sub_wire4(26); - sub_wire2(1, 27) <= sub_wire4(27); - sub_wire2(1, 28) <= sub_wire4(28); - sub_wire2(1, 29) <= sub_wire4(29); - sub_wire2(1, 30) <= sub_wire4(30); - sub_wire2(1, 31) <= sub_wire4(31); - sub_wire2(0, 0) <= sub_wire5(0); - sub_wire2(0, 1) <= sub_wire5(1); - sub_wire2(0, 2) <= sub_wire5(2); - sub_wire2(0, 3) <= sub_wire5(3); - sub_wire2(0, 4) <= sub_wire5(4); - sub_wire2(0, 5) <= sub_wire5(5); - sub_wire2(0, 6) <= sub_wire5(6); - sub_wire2(0, 7) <= sub_wire5(7); - sub_wire2(0, 8) <= sub_wire5(8); - sub_wire2(0, 9) <= sub_wire5(9); - sub_wire2(0, 10) <= sub_wire5(10); - sub_wire2(0, 11) <= sub_wire5(11); - sub_wire2(0, 12) <= sub_wire5(12); - sub_wire2(0, 13) <= sub_wire5(13); - sub_wire2(0, 14) <= sub_wire5(14); - sub_wire2(0, 15) <= sub_wire5(15); - sub_wire2(0, 16) <= sub_wire5(16); - sub_wire2(0, 17) <= sub_wire5(17); - sub_wire2(0, 18) <= sub_wire5(18); - sub_wire2(0, 19) <= sub_wire5(19); - sub_wire2(0, 20) <= sub_wire5(20); - sub_wire2(0, 21) <= sub_wire5(21); - sub_wire2(0, 22) <= sub_wire5(22); - sub_wire2(0, 23) <= sub_wire5(23); - sub_wire2(0, 24) <= sub_wire5(24); - sub_wire2(0, 25) <= sub_wire5(25); - sub_wire2(0, 26) <= sub_wire5(26); - sub_wire2(0, 27) <= sub_wire5(27); - sub_wire2(0, 28) <= sub_wire5(28); - sub_wire2(0, 29) <= sub_wire5(29); - sub_wire2(0, 30) <= sub_wire5(30); - sub_wire2(0, 31) <= sub_wire5(31); - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_pipeline => 4, - lpm_size => 4, - lpm_type => "LPM_MUX", - lpm_width => 32, - lpm_widths => 2 - ) - PORT MAP ( - clock => clock, - data => sub_wire2, - sel => sel, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL "data0x[31..0]" --- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL "data1x[31..0]" --- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL "data2x[31..0]" --- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL "data3x[31..0]" --- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]" --- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0 --- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0 --- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0 --- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0 --- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 --- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux0.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux0 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_mux0; + + +ARCHITECTURE SYN OF lpm_mux0 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (31 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(31 DOWNTO 0); + sub_wire4 <= data1x(31 DOWNTO 0); + sub_wire3 <= data2x(31 DOWNTO 0); + result <= sub_wire0(31 DOWNTO 0); + sub_wire1 <= data3x(31 DOWNTO 0); + sub_wire2(3, 0) <= sub_wire1(0); + sub_wire2(3, 1) <= sub_wire1(1); + sub_wire2(3, 2) <= sub_wire1(2); + sub_wire2(3, 3) <= sub_wire1(3); + sub_wire2(3, 4) <= sub_wire1(4); + sub_wire2(3, 5) <= sub_wire1(5); + sub_wire2(3, 6) <= sub_wire1(6); + sub_wire2(3, 7) <= sub_wire1(7); + sub_wire2(3, 8) <= sub_wire1(8); + sub_wire2(3, 9) <= sub_wire1(9); + sub_wire2(3, 10) <= sub_wire1(10); + sub_wire2(3, 11) <= sub_wire1(11); + sub_wire2(3, 12) <= sub_wire1(12); + sub_wire2(3, 13) <= sub_wire1(13); + sub_wire2(3, 14) <= sub_wire1(14); + sub_wire2(3, 15) <= sub_wire1(15); + sub_wire2(3, 16) <= sub_wire1(16); + sub_wire2(3, 17) <= sub_wire1(17); + sub_wire2(3, 18) <= sub_wire1(18); + sub_wire2(3, 19) <= sub_wire1(19); + sub_wire2(3, 20) <= sub_wire1(20); + sub_wire2(3, 21) <= sub_wire1(21); + sub_wire2(3, 22) <= sub_wire1(22); + sub_wire2(3, 23) <= sub_wire1(23); + sub_wire2(3, 24) <= sub_wire1(24); + sub_wire2(3, 25) <= sub_wire1(25); + sub_wire2(3, 26) <= sub_wire1(26); + sub_wire2(3, 27) <= sub_wire1(27); + sub_wire2(3, 28) <= sub_wire1(28); + sub_wire2(3, 29) <= sub_wire1(29); + sub_wire2(3, 30) <= sub_wire1(30); + sub_wire2(3, 31) <= sub_wire1(31); + sub_wire2(2, 0) <= sub_wire3(0); + sub_wire2(2, 1) <= sub_wire3(1); + sub_wire2(2, 2) <= sub_wire3(2); + sub_wire2(2, 3) <= sub_wire3(3); + sub_wire2(2, 4) <= sub_wire3(4); + sub_wire2(2, 5) <= sub_wire3(5); + sub_wire2(2, 6) <= sub_wire3(6); + sub_wire2(2, 7) <= sub_wire3(7); + sub_wire2(2, 8) <= sub_wire3(8); + sub_wire2(2, 9) <= sub_wire3(9); + sub_wire2(2, 10) <= sub_wire3(10); + sub_wire2(2, 11) <= sub_wire3(11); + sub_wire2(2, 12) <= sub_wire3(12); + sub_wire2(2, 13) <= sub_wire3(13); + sub_wire2(2, 14) <= sub_wire3(14); + sub_wire2(2, 15) <= sub_wire3(15); + sub_wire2(2, 16) <= sub_wire3(16); + sub_wire2(2, 17) <= sub_wire3(17); + sub_wire2(2, 18) <= sub_wire3(18); + sub_wire2(2, 19) <= sub_wire3(19); + sub_wire2(2, 20) <= sub_wire3(20); + sub_wire2(2, 21) <= sub_wire3(21); + sub_wire2(2, 22) <= sub_wire3(22); + sub_wire2(2, 23) <= sub_wire3(23); + sub_wire2(2, 24) <= sub_wire3(24); + sub_wire2(2, 25) <= sub_wire3(25); + sub_wire2(2, 26) <= sub_wire3(26); + sub_wire2(2, 27) <= sub_wire3(27); + sub_wire2(2, 28) <= sub_wire3(28); + sub_wire2(2, 29) <= sub_wire3(29); + sub_wire2(2, 30) <= sub_wire3(30); + sub_wire2(2, 31) <= sub_wire3(31); + sub_wire2(1, 0) <= sub_wire4(0); + sub_wire2(1, 1) <= sub_wire4(1); + sub_wire2(1, 2) <= sub_wire4(2); + sub_wire2(1, 3) <= sub_wire4(3); + sub_wire2(1, 4) <= sub_wire4(4); + sub_wire2(1, 5) <= sub_wire4(5); + sub_wire2(1, 6) <= sub_wire4(6); + sub_wire2(1, 7) <= sub_wire4(7); + sub_wire2(1, 8) <= sub_wire4(8); + sub_wire2(1, 9) <= sub_wire4(9); + sub_wire2(1, 10) <= sub_wire4(10); + sub_wire2(1, 11) <= sub_wire4(11); + sub_wire2(1, 12) <= sub_wire4(12); + sub_wire2(1, 13) <= sub_wire4(13); + sub_wire2(1, 14) <= sub_wire4(14); + sub_wire2(1, 15) <= sub_wire4(15); + sub_wire2(1, 16) <= sub_wire4(16); + sub_wire2(1, 17) <= sub_wire4(17); + sub_wire2(1, 18) <= sub_wire4(18); + sub_wire2(1, 19) <= sub_wire4(19); + sub_wire2(1, 20) <= sub_wire4(20); + sub_wire2(1, 21) <= sub_wire4(21); + sub_wire2(1, 22) <= sub_wire4(22); + sub_wire2(1, 23) <= sub_wire4(23); + sub_wire2(1, 24) <= sub_wire4(24); + sub_wire2(1, 25) <= sub_wire4(25); + sub_wire2(1, 26) <= sub_wire4(26); + sub_wire2(1, 27) <= sub_wire4(27); + sub_wire2(1, 28) <= sub_wire4(28); + sub_wire2(1, 29) <= sub_wire4(29); + sub_wire2(1, 30) <= sub_wire4(30); + sub_wire2(1, 31) <= sub_wire4(31); + sub_wire2(0, 0) <= sub_wire5(0); + sub_wire2(0, 1) <= sub_wire5(1); + sub_wire2(0, 2) <= sub_wire5(2); + sub_wire2(0, 3) <= sub_wire5(3); + sub_wire2(0, 4) <= sub_wire5(4); + sub_wire2(0, 5) <= sub_wire5(5); + sub_wire2(0, 6) <= sub_wire5(6); + sub_wire2(0, 7) <= sub_wire5(7); + sub_wire2(0, 8) <= sub_wire5(8); + sub_wire2(0, 9) <= sub_wire5(9); + sub_wire2(0, 10) <= sub_wire5(10); + sub_wire2(0, 11) <= sub_wire5(11); + sub_wire2(0, 12) <= sub_wire5(12); + sub_wire2(0, 13) <= sub_wire5(13); + sub_wire2(0, 14) <= sub_wire5(14); + sub_wire2(0, 15) <= sub_wire5(15); + sub_wire2(0, 16) <= sub_wire5(16); + sub_wire2(0, 17) <= sub_wire5(17); + sub_wire2(0, 18) <= sub_wire5(18); + sub_wire2(0, 19) <= sub_wire5(19); + sub_wire2(0, 20) <= sub_wire5(20); + sub_wire2(0, 21) <= sub_wire5(21); + sub_wire2(0, 22) <= sub_wire5(22); + sub_wire2(0, 23) <= sub_wire5(23); + sub_wire2(0, 24) <= sub_wire5(24); + sub_wire2(0, 25) <= sub_wire5(25); + sub_wire2(0, 26) <= sub_wire5(26); + sub_wire2(0, 27) <= sub_wire5(27); + sub_wire2(0, 28) <= sub_wire5(28); + sub_wire2(0, 29) <= sub_wire5(29); + sub_wire2(0, 30) <= sub_wire5(30); + sub_wire2(0, 31) <= sub_wire5(31); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 4, + lpm_size => 4, + lpm_type => "LPM_MUX", + lpm_width => 32, + lpm_widths => 2 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0] +-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0] +-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0] +-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0] +-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] +-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0 +-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_mux1.bsf b/Video/lpm_mux1.bsf index f82aeec..24ee953 100644 --- a/Video/lpm_mux1.bsf +++ b/Video/lpm_mux1.bsf @@ -1,119 +1,111 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 192) - (text "lpm_mux1" (rect 43 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 177 26 188)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data7x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data7x[15..0]" (rect 4 27 67 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data6x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data6x[15..0]" (rect 4 43 67 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data5x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data5x[15..0]" (rect 4 59 67 71)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data4x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data4x[15..0]" (rect 4 75 67 87)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "data3x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data3x[15..0]" (rect 4 91 67 103)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 64 104)(line_width 3)) - ) - (port - (pt 0 120) - (input) - (text "data2x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data2x[15..0]" (rect 4 107 67 119)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 64 120)(line_width 3)) - ) - (port - (pt 0 136) - (input) - (text "data1x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data1x[15..0]" (rect 4 123 67 135)(font "Arial" (font_size 8))) - (line (pt 0 136)(pt 64 136)(line_width 3)) - ) - (port - (pt 0 152) - (input) - (text "data0x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data0x[15..0]" (rect 4 139 67 151)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 64 152)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 4 155 29 167)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 64 168)) - ) - (port - (pt 72 192) - (input) - (text "sel[2..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical)) - (text "sel[2..0]" (rect 66 137 78 175)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 192)(pt 72 180)(line_width 3)) - ) - (port - (pt 144 104) - (output) - (text "result[15..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "result[15..0]" (rect 85 91 142 103)(font "Arial" (font_size 8))) - (line (pt 144 104)(pt 80 104)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 184)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 184)(pt 80 176)) - (line (pt 80 32)(pt 80 176)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 194)) - (line (pt 0 194)(pt 146 194)) - (line (pt 0 0)(pt 0 194)) - (line (pt 64 162)(pt 70 168)) - (line (pt 70 168)(pt 64 174)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 192) + (text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 176 25 188)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 1)) + ) + (port + (pt 80 192) + (input) + (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) + (line (pt 80 192)(pt 80 180)(line_width 3)) + ) + (port + (pt 152 104) + (output) + (text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) + (line (pt 152 104)(pt 88 104)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 184)(line_width 1)) + (line (pt 88 32)(pt 88 176)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 184)(pt 88 176)(line_width 1)) + (line (pt 72 162)(pt 78 168)(line_width 1)) + (line (pt 78 168)(pt 72 174)(line_width 1)) + ) +) diff --git a/Video/lpm_mux1.cmp b/Video/lpm_mux1.cmp index 0597488..cfc222a 100644 --- a/Video/lpm_mux1.cmp +++ b/Video/lpm_mux1.cmp @@ -1,31 +1,31 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_mux1 - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux1 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_mux1.inc b/Video/lpm_mux1.inc index 09507c3..e2f94a4 100644 --- a/Video/lpm_mux1.inc +++ b/Video/lpm_mux1.inc @@ -1,32 +1,32 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_mux1 -( - clock, - data0x[15..0], - data1x[15..0], - data2x[15..0], - data3x[15..0], - data4x[15..0], - data5x[15..0], - data6x[15..0], - data7x[15..0], - sel[2..0] -) - -RETURNS ( - result[15..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux1 +( + clock, + data0x[15..0], + data1x[15..0], + data2x[15..0], + data3x[15..0], + data4x[15..0], + data5x[15..0], + data6x[15..0], + data7x[15..0], + sel[2..0] +) + +RETURNS ( + result[15..0] +); diff --git a/Video/lpm_mux1.qip b/Video/lpm_mux1.qip index 3803bf9..8a445b2 100644 --- a/Video/lpm_mux1.qip +++ b/Video/lpm_mux1.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"] diff --git a/Video/lpm_mux1.vhd b/Video/lpm_mux1.vhd index cdff3df..a9ad991 100644 --- a/Video/lpm_mux1.vhd +++ b/Video/lpm_mux1.vhd @@ -1,272 +1,271 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_mux1.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_mux1 IS - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) - ); -END lpm_mux1; - - -ARCHITECTURE SYN OF lpm_mux1 IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0); - -BEGIN - sub_wire9 <= data0x(15 DOWNTO 0); - sub_wire8 <= data1x(15 DOWNTO 0); - sub_wire7 <= data2x(15 DOWNTO 0); - sub_wire6 <= data3x(15 DOWNTO 0); - sub_wire5 <= data4x(15 DOWNTO 0); - sub_wire4 <= data5x(15 DOWNTO 0); - sub_wire3 <= data6x(15 DOWNTO 0); - result <= sub_wire0(15 DOWNTO 0); - sub_wire1 <= data7x(15 DOWNTO 0); - sub_wire2(7, 0) <= sub_wire1(0); - sub_wire2(7, 1) <= sub_wire1(1); - sub_wire2(7, 2) <= sub_wire1(2); - sub_wire2(7, 3) <= sub_wire1(3); - sub_wire2(7, 4) <= sub_wire1(4); - sub_wire2(7, 5) <= sub_wire1(5); - sub_wire2(7, 6) <= sub_wire1(6); - sub_wire2(7, 7) <= sub_wire1(7); - sub_wire2(7, 8) <= sub_wire1(8); - sub_wire2(7, 9) <= sub_wire1(9); - sub_wire2(7, 10) <= sub_wire1(10); - sub_wire2(7, 11) <= sub_wire1(11); - sub_wire2(7, 12) <= sub_wire1(12); - sub_wire2(7, 13) <= sub_wire1(13); - sub_wire2(7, 14) <= sub_wire1(14); - sub_wire2(7, 15) <= sub_wire1(15); - sub_wire2(6, 0) <= sub_wire3(0); - sub_wire2(6, 1) <= sub_wire3(1); - sub_wire2(6, 2) <= sub_wire3(2); - sub_wire2(6, 3) <= sub_wire3(3); - sub_wire2(6, 4) <= sub_wire3(4); - sub_wire2(6, 5) <= sub_wire3(5); - sub_wire2(6, 6) <= sub_wire3(6); - sub_wire2(6, 7) <= sub_wire3(7); - sub_wire2(6, 8) <= sub_wire3(8); - sub_wire2(6, 9) <= sub_wire3(9); - sub_wire2(6, 10) <= sub_wire3(10); - sub_wire2(6, 11) <= sub_wire3(11); - sub_wire2(6, 12) <= sub_wire3(12); - sub_wire2(6, 13) <= sub_wire3(13); - sub_wire2(6, 14) <= sub_wire3(14); - sub_wire2(6, 15) <= sub_wire3(15); - sub_wire2(5, 0) <= sub_wire4(0); - sub_wire2(5, 1) <= sub_wire4(1); - sub_wire2(5, 2) <= sub_wire4(2); - sub_wire2(5, 3) <= sub_wire4(3); - sub_wire2(5, 4) <= sub_wire4(4); - sub_wire2(5, 5) <= sub_wire4(5); - sub_wire2(5, 6) <= sub_wire4(6); - sub_wire2(5, 7) <= sub_wire4(7); - sub_wire2(5, 8) <= sub_wire4(8); - sub_wire2(5, 9) <= sub_wire4(9); - sub_wire2(5, 10) <= sub_wire4(10); - sub_wire2(5, 11) <= sub_wire4(11); - sub_wire2(5, 12) <= sub_wire4(12); - sub_wire2(5, 13) <= sub_wire4(13); - sub_wire2(5, 14) <= sub_wire4(14); - sub_wire2(5, 15) <= sub_wire4(15); - sub_wire2(4, 0) <= sub_wire5(0); - sub_wire2(4, 1) <= sub_wire5(1); - sub_wire2(4, 2) <= sub_wire5(2); - sub_wire2(4, 3) <= sub_wire5(3); - sub_wire2(4, 4) <= sub_wire5(4); - sub_wire2(4, 5) <= sub_wire5(5); - sub_wire2(4, 6) <= sub_wire5(6); - sub_wire2(4, 7) <= sub_wire5(7); - sub_wire2(4, 8) <= sub_wire5(8); - sub_wire2(4, 9) <= sub_wire5(9); - sub_wire2(4, 10) <= sub_wire5(10); - sub_wire2(4, 11) <= sub_wire5(11); - sub_wire2(4, 12) <= sub_wire5(12); - sub_wire2(4, 13) <= sub_wire5(13); - sub_wire2(4, 14) <= sub_wire5(14); - sub_wire2(4, 15) <= sub_wire5(15); - sub_wire2(3, 0) <= sub_wire6(0); - sub_wire2(3, 1) <= sub_wire6(1); - sub_wire2(3, 2) <= sub_wire6(2); - sub_wire2(3, 3) <= sub_wire6(3); - sub_wire2(3, 4) <= sub_wire6(4); - sub_wire2(3, 5) <= sub_wire6(5); - sub_wire2(3, 6) <= sub_wire6(6); - sub_wire2(3, 7) <= sub_wire6(7); - sub_wire2(3, 8) <= sub_wire6(8); - sub_wire2(3, 9) <= sub_wire6(9); - sub_wire2(3, 10) <= sub_wire6(10); - sub_wire2(3, 11) <= sub_wire6(11); - sub_wire2(3, 12) <= sub_wire6(12); - sub_wire2(3, 13) <= sub_wire6(13); - sub_wire2(3, 14) <= sub_wire6(14); - sub_wire2(3, 15) <= sub_wire6(15); - sub_wire2(2, 0) <= sub_wire7(0); - sub_wire2(2, 1) <= sub_wire7(1); - sub_wire2(2, 2) <= sub_wire7(2); - sub_wire2(2, 3) <= sub_wire7(3); - sub_wire2(2, 4) <= sub_wire7(4); - sub_wire2(2, 5) <= sub_wire7(5); - sub_wire2(2, 6) <= sub_wire7(6); - sub_wire2(2, 7) <= sub_wire7(7); - sub_wire2(2, 8) <= sub_wire7(8); - sub_wire2(2, 9) <= sub_wire7(9); - sub_wire2(2, 10) <= sub_wire7(10); - sub_wire2(2, 11) <= sub_wire7(11); - sub_wire2(2, 12) <= sub_wire7(12); - sub_wire2(2, 13) <= sub_wire7(13); - sub_wire2(2, 14) <= sub_wire7(14); - sub_wire2(2, 15) <= sub_wire7(15); - sub_wire2(1, 0) <= sub_wire8(0); - sub_wire2(1, 1) <= sub_wire8(1); - sub_wire2(1, 2) <= sub_wire8(2); - sub_wire2(1, 3) <= sub_wire8(3); - sub_wire2(1, 4) <= sub_wire8(4); - sub_wire2(1, 5) <= sub_wire8(5); - sub_wire2(1, 6) <= sub_wire8(6); - sub_wire2(1, 7) <= sub_wire8(7); - sub_wire2(1, 8) <= sub_wire8(8); - sub_wire2(1, 9) <= sub_wire8(9); - sub_wire2(1, 10) <= sub_wire8(10); - sub_wire2(1, 11) <= sub_wire8(11); - sub_wire2(1, 12) <= sub_wire8(12); - sub_wire2(1, 13) <= sub_wire8(13); - sub_wire2(1, 14) <= sub_wire8(14); - sub_wire2(1, 15) <= sub_wire8(15); - sub_wire2(0, 0) <= sub_wire9(0); - sub_wire2(0, 1) <= sub_wire9(1); - sub_wire2(0, 2) <= sub_wire9(2); - sub_wire2(0, 3) <= sub_wire9(3); - sub_wire2(0, 4) <= sub_wire9(4); - sub_wire2(0, 5) <= sub_wire9(5); - sub_wire2(0, 6) <= sub_wire9(6); - sub_wire2(0, 7) <= sub_wire9(7); - sub_wire2(0, 8) <= sub_wire9(8); - sub_wire2(0, 9) <= sub_wire9(9); - sub_wire2(0, 10) <= sub_wire9(10); - sub_wire2(0, 11) <= sub_wire9(11); - sub_wire2(0, 12) <= sub_wire9(12); - sub_wire2(0, 13) <= sub_wire9(13); - sub_wire2(0, 14) <= sub_wire9(14); - sub_wire2(0, 15) <= sub_wire9(15); - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_pipeline => 4, - lpm_size => 8, - lpm_type => "LPM_MUX", - lpm_width => 16, - lpm_widths => 3 - ) - PORT MAP ( - clock => clock, - data => sub_wire2, - sel => sel, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]" --- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]" --- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]" --- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]" --- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]" --- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]" --- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]" --- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]" --- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]" --- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0 --- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0 --- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0 --- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0 --- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0 --- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0 --- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0 --- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0 --- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 --- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux1.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux1 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END lpm_mux1; + + +ARCHITECTURE SYN OF lpm_mux1 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +BEGIN + sub_wire9 <= data0x(15 DOWNTO 0); + sub_wire8 <= data1x(15 DOWNTO 0); + sub_wire7 <= data2x(15 DOWNTO 0); + sub_wire6 <= data3x(15 DOWNTO 0); + sub_wire5 <= data4x(15 DOWNTO 0); + sub_wire4 <= data5x(15 DOWNTO 0); + sub_wire3 <= data6x(15 DOWNTO 0); + result <= sub_wire0(15 DOWNTO 0); + sub_wire1 <= data7x(15 DOWNTO 0); + sub_wire2(7, 0) <= sub_wire1(0); + sub_wire2(7, 1) <= sub_wire1(1); + sub_wire2(7, 2) <= sub_wire1(2); + sub_wire2(7, 3) <= sub_wire1(3); + sub_wire2(7, 4) <= sub_wire1(4); + sub_wire2(7, 5) <= sub_wire1(5); + sub_wire2(7, 6) <= sub_wire1(6); + sub_wire2(7, 7) <= sub_wire1(7); + sub_wire2(7, 8) <= sub_wire1(8); + sub_wire2(7, 9) <= sub_wire1(9); + sub_wire2(7, 10) <= sub_wire1(10); + sub_wire2(7, 11) <= sub_wire1(11); + sub_wire2(7, 12) <= sub_wire1(12); + sub_wire2(7, 13) <= sub_wire1(13); + sub_wire2(7, 14) <= sub_wire1(14); + sub_wire2(7, 15) <= sub_wire1(15); + sub_wire2(6, 0) <= sub_wire3(0); + sub_wire2(6, 1) <= sub_wire3(1); + sub_wire2(6, 2) <= sub_wire3(2); + sub_wire2(6, 3) <= sub_wire3(3); + sub_wire2(6, 4) <= sub_wire3(4); + sub_wire2(6, 5) <= sub_wire3(5); + sub_wire2(6, 6) <= sub_wire3(6); + sub_wire2(6, 7) <= sub_wire3(7); + sub_wire2(6, 8) <= sub_wire3(8); + sub_wire2(6, 9) <= sub_wire3(9); + sub_wire2(6, 10) <= sub_wire3(10); + sub_wire2(6, 11) <= sub_wire3(11); + sub_wire2(6, 12) <= sub_wire3(12); + sub_wire2(6, 13) <= sub_wire3(13); + sub_wire2(6, 14) <= sub_wire3(14); + sub_wire2(6, 15) <= sub_wire3(15); + sub_wire2(5, 0) <= sub_wire4(0); + sub_wire2(5, 1) <= sub_wire4(1); + sub_wire2(5, 2) <= sub_wire4(2); + sub_wire2(5, 3) <= sub_wire4(3); + sub_wire2(5, 4) <= sub_wire4(4); + sub_wire2(5, 5) <= sub_wire4(5); + sub_wire2(5, 6) <= sub_wire4(6); + sub_wire2(5, 7) <= sub_wire4(7); + sub_wire2(5, 8) <= sub_wire4(8); + sub_wire2(5, 9) <= sub_wire4(9); + sub_wire2(5, 10) <= sub_wire4(10); + sub_wire2(5, 11) <= sub_wire4(11); + sub_wire2(5, 12) <= sub_wire4(12); + sub_wire2(5, 13) <= sub_wire4(13); + sub_wire2(5, 14) <= sub_wire4(14); + sub_wire2(5, 15) <= sub_wire4(15); + sub_wire2(4, 0) <= sub_wire5(0); + sub_wire2(4, 1) <= sub_wire5(1); + sub_wire2(4, 2) <= sub_wire5(2); + sub_wire2(4, 3) <= sub_wire5(3); + sub_wire2(4, 4) <= sub_wire5(4); + sub_wire2(4, 5) <= sub_wire5(5); + sub_wire2(4, 6) <= sub_wire5(6); + sub_wire2(4, 7) <= sub_wire5(7); + sub_wire2(4, 8) <= sub_wire5(8); + sub_wire2(4, 9) <= sub_wire5(9); + sub_wire2(4, 10) <= sub_wire5(10); + sub_wire2(4, 11) <= sub_wire5(11); + sub_wire2(4, 12) <= sub_wire5(12); + sub_wire2(4, 13) <= sub_wire5(13); + sub_wire2(4, 14) <= sub_wire5(14); + sub_wire2(4, 15) <= sub_wire5(15); + sub_wire2(3, 0) <= sub_wire6(0); + sub_wire2(3, 1) <= sub_wire6(1); + sub_wire2(3, 2) <= sub_wire6(2); + sub_wire2(3, 3) <= sub_wire6(3); + sub_wire2(3, 4) <= sub_wire6(4); + sub_wire2(3, 5) <= sub_wire6(5); + sub_wire2(3, 6) <= sub_wire6(6); + sub_wire2(3, 7) <= sub_wire6(7); + sub_wire2(3, 8) <= sub_wire6(8); + sub_wire2(3, 9) <= sub_wire6(9); + sub_wire2(3, 10) <= sub_wire6(10); + sub_wire2(3, 11) <= sub_wire6(11); + sub_wire2(3, 12) <= sub_wire6(12); + sub_wire2(3, 13) <= sub_wire6(13); + sub_wire2(3, 14) <= sub_wire6(14); + sub_wire2(3, 15) <= sub_wire6(15); + sub_wire2(2, 0) <= sub_wire7(0); + sub_wire2(2, 1) <= sub_wire7(1); + sub_wire2(2, 2) <= sub_wire7(2); + sub_wire2(2, 3) <= sub_wire7(3); + sub_wire2(2, 4) <= sub_wire7(4); + sub_wire2(2, 5) <= sub_wire7(5); + sub_wire2(2, 6) <= sub_wire7(6); + sub_wire2(2, 7) <= sub_wire7(7); + sub_wire2(2, 8) <= sub_wire7(8); + sub_wire2(2, 9) <= sub_wire7(9); + sub_wire2(2, 10) <= sub_wire7(10); + sub_wire2(2, 11) <= sub_wire7(11); + sub_wire2(2, 12) <= sub_wire7(12); + sub_wire2(2, 13) <= sub_wire7(13); + sub_wire2(2, 14) <= sub_wire7(14); + sub_wire2(2, 15) <= sub_wire7(15); + sub_wire2(1, 0) <= sub_wire8(0); + sub_wire2(1, 1) <= sub_wire8(1); + sub_wire2(1, 2) <= sub_wire8(2); + sub_wire2(1, 3) <= sub_wire8(3); + sub_wire2(1, 4) <= sub_wire8(4); + sub_wire2(1, 5) <= sub_wire8(5); + sub_wire2(1, 6) <= sub_wire8(6); + sub_wire2(1, 7) <= sub_wire8(7); + sub_wire2(1, 8) <= sub_wire8(8); + sub_wire2(1, 9) <= sub_wire8(9); + sub_wire2(1, 10) <= sub_wire8(10); + sub_wire2(1, 11) <= sub_wire8(11); + sub_wire2(1, 12) <= sub_wire8(12); + sub_wire2(1, 13) <= sub_wire8(13); + sub_wire2(1, 14) <= sub_wire8(14); + sub_wire2(1, 15) <= sub_wire8(15); + sub_wire2(0, 0) <= sub_wire9(0); + sub_wire2(0, 1) <= sub_wire9(1); + sub_wire2(0, 2) <= sub_wire9(2); + sub_wire2(0, 3) <= sub_wire9(3); + sub_wire2(0, 4) <= sub_wire9(4); + sub_wire2(0, 5) <= sub_wire9(5); + sub_wire2(0, 6) <= sub_wire9(6); + sub_wire2(0, 7) <= sub_wire9(7); + sub_wire2(0, 8) <= sub_wire9(8); + sub_wire2(0, 9) <= sub_wire9(9); + sub_wire2(0, 10) <= sub_wire9(10); + sub_wire2(0, 11) <= sub_wire9(11); + sub_wire2(0, 12) <= sub_wire9(12); + sub_wire2(0, 13) <= sub_wire9(13); + sub_wire2(0, 14) <= sub_wire9(14); + sub_wire2(0, 15) <= sub_wire9(15); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 4, + lpm_size => 8, + lpm_type => "LPM_MUX", + lpm_width => 16, + lpm_widths => 3 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0] +-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0] +-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0] +-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0] +-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0] +-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0] +-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0] +-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0] +-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] +-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0 +-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_mux2.bsf b/Video/lpm_mux2.bsf index 6edef16..b37c425 100644 --- a/Video/lpm_mux2.bsf +++ b/Video/lpm_mux2.bsf @@ -1,175 +1,167 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 320) - (text "lpm_mux2" (rect 43 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 305 26 316)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data15x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data15x[7..0]" (rect 4 27 67 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data14x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data14x[7..0]" (rect 4 43 67 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data13x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data13x[7..0]" (rect 4 59 67 71)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data12x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data12x[7..0]" (rect 4 75 67 87)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "data11x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data11x[7..0]" (rect 4 91 67 103)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 64 104)(line_width 3)) - ) - (port - (pt 0 120) - (input) - (text "data10x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data10x[7..0]" (rect 4 107 67 119)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 64 120)(line_width 3)) - ) - (port - (pt 0 136) - (input) - (text "data9x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data9x[7..0]" (rect 4 123 61 135)(font "Arial" (font_size 8))) - (line (pt 0 136)(pt 64 136)(line_width 3)) - ) - (port - (pt 0 152) - (input) - (text "data8x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data8x[7..0]" (rect 4 139 61 151)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 64 152)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "data7x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data7x[7..0]" (rect 4 155 61 167)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 64 168)(line_width 3)) - ) - (port - (pt 0 184) - (input) - (text "data6x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data6x[7..0]" (rect 4 171 61 183)(font "Arial" (font_size 8))) - (line (pt 0 184)(pt 64 184)(line_width 3)) - ) - (port - (pt 0 200) - (input) - (text "data5x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data5x[7..0]" (rect 4 187 61 199)(font "Arial" (font_size 8))) - (line (pt 0 200)(pt 64 200)(line_width 3)) - ) - (port - (pt 0 216) - (input) - (text "data4x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data4x[7..0]" (rect 4 203 61 215)(font "Arial" (font_size 8))) - (line (pt 0 216)(pt 64 216)(line_width 3)) - ) - (port - (pt 0 232) - (input) - (text "data3x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data3x[7..0]" (rect 4 219 61 231)(font "Arial" (font_size 8))) - (line (pt 0 232)(pt 64 232)(line_width 3)) - ) - (port - (pt 0 248) - (input) - (text "data2x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data2x[7..0]" (rect 4 235 61 247)(font "Arial" (font_size 8))) - (line (pt 0 248)(pt 64 248)(line_width 3)) - ) - (port - (pt 0 264) - (input) - (text "data1x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data1x[7..0]" (rect 4 251 61 263)(font "Arial" (font_size 8))) - (line (pt 0 264)(pt 64 264)(line_width 3)) - ) - (port - (pt 0 280) - (input) - (text "data0x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data0x[7..0]" (rect 4 267 61 279)(font "Arial" (font_size 8))) - (line (pt 0 280)(pt 64 280)(line_width 3)) - ) - (port - (pt 0 296) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 4 283 29 295)(font "Arial" (font_size 8))) - (line (pt 0 296)(pt 64 296)) - ) - (port - (pt 72 320) - (input) - (text "sel[3..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical)) - (text "sel[3..0]" (rect 66 265 78 303)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 320)(pt 72 308)(line_width 3)) - ) - (port - (pt 144 168) - (output) - (text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8))) - (text "result[7..0]" (rect 91 155 142 167)(font "Arial" (font_size 8))) - (line (pt 144 168)(pt 80 168)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 312)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 312)(pt 80 304)) - (line (pt 80 32)(pt 80 304)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 322)) - (line (pt 0 322)(pt 146 322)) - (line (pt 0 0)(pt 0 322)) - (line (pt 64 290)(pt 70 296)) - (line (pt 70 296)(pt 64 302)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 320) + (text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 304 25 316)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data9x[7..0]" (rect 4 123 60 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data8x[7..0]" (rect 4 139 60 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "data7x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data7x[7..0]" (rect 4 155 60 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 3)) + ) + (port + (pt 0 184) + (input) + (text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data6x[7..0]" (rect 4 171 60 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 72 184)(line_width 3)) + ) + (port + (pt 0 200) + (input) + (text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data5x[7..0]" (rect 4 187 60 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 72 200)(line_width 3)) + ) + (port + (pt 0 216) + (input) + (text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data4x[7..0]" (rect 4 203 60 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 72 216)(line_width 3)) + ) + (port + (pt 0 232) + (input) + (text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data3x[7..0]" (rect 4 219 60 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 72 232)(line_width 3)) + ) + (port + (pt 0 248) + (input) + (text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data2x[7..0]" (rect 4 235 60 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 72 248)(line_width 3)) + ) + (port + (pt 0 264) + (input) + (text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[7..0]" (rect 4 251 60 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 72 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 72 280)(line_width 3)) + ) + (port + (pt 0 296) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8))) + (line (pt 0 296)(pt 72 296)(line_width 1)) + ) + (port + (pt 80 320) + (input) + (text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8))) + (line (pt 80 320)(pt 80 308)(line_width 3)) + ) + (port + (pt 144 168) + (output) + (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8))) + (line (pt 144 168)(pt 88 168)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 312)(line_width 1)) + (line (pt 88 32)(pt 88 304)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 312)(pt 88 304)(line_width 1)) + (line (pt 72 290)(pt 78 296)(line_width 1)) + (line (pt 78 296)(pt 72 302)(line_width 1)) + ) +) diff --git a/Video/lpm_mux2.cmp b/Video/lpm_mux2.cmp index 9fb6bc9..d94260c 100644 --- a/Video/lpm_mux2.cmp +++ b/Video/lpm_mux2.cmp @@ -1,39 +1,39 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_mux2 - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux2 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_mux2.inc b/Video/lpm_mux2.inc index a0c2a29..2334c7e 100644 --- a/Video/lpm_mux2.inc +++ b/Video/lpm_mux2.inc @@ -1,40 +1,40 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_mux2 -( - clock, - data0x[7..0], - data10x[7..0], - data11x[7..0], - data12x[7..0], - data13x[7..0], - data14x[7..0], - data15x[7..0], - data1x[7..0], - data2x[7..0], - data3x[7..0], - data4x[7..0], - data5x[7..0], - data6x[7..0], - data7x[7..0], - data8x[7..0], - data9x[7..0], - sel[3..0] -) - -RETURNS ( - result[7..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux2 +( + clock, + data0x[7..0], + data10x[7..0], + data11x[7..0], + data12x[7..0], + data13x[7..0], + data14x[7..0], + data15x[7..0], + data1x[7..0], + data2x[7..0], + data3x[7..0], + data4x[7..0], + data5x[7..0], + data6x[7..0], + data7x[7..0], + data8x[7..0], + data9x[7..0], + sel[3..0] +) + +RETURNS ( + result[7..0] +); diff --git a/Video/lpm_mux2.qip b/Video/lpm_mux2.qip index 136e747..7b5db74 100644 --- a/Video/lpm_mux2.qip +++ b/Video/lpm_mux2.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"] diff --git a/Video/lpm_mux2.vhd b/Video/lpm_mux2.vhd index 62bfd1e..cfece2e 100644 --- a/Video/lpm_mux2.vhd +++ b/Video/lpm_mux2.vhd @@ -1,312 +1,311 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_mux2.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_mux2 IS - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -END lpm_mux2; - - -ARCHITECTURE SYN OF lpm_mux2 IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire9 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire10 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire11 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire12 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire13 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire14 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire15 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire16 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire17 : STD_LOGIC_VECTOR (7 DOWNTO 0); - -BEGIN - sub_wire17 <= data0x(7 DOWNTO 0); - sub_wire16 <= data1x(7 DOWNTO 0); - sub_wire15 <= data2x(7 DOWNTO 0); - sub_wire14 <= data3x(7 DOWNTO 0); - sub_wire13 <= data4x(7 DOWNTO 0); - sub_wire12 <= data5x(7 DOWNTO 0); - sub_wire11 <= data6x(7 DOWNTO 0); - sub_wire10 <= data7x(7 DOWNTO 0); - sub_wire9 <= data8x(7 DOWNTO 0); - sub_wire8 <= data9x(7 DOWNTO 0); - sub_wire7 <= data10x(7 DOWNTO 0); - sub_wire6 <= data11x(7 DOWNTO 0); - sub_wire5 <= data12x(7 DOWNTO 0); - sub_wire4 <= data13x(7 DOWNTO 0); - sub_wire3 <= data14x(7 DOWNTO 0); - result <= sub_wire0(7 DOWNTO 0); - sub_wire1 <= data15x(7 DOWNTO 0); - sub_wire2(15, 0) <= sub_wire1(0); - sub_wire2(15, 1) <= sub_wire1(1); - sub_wire2(15, 2) <= sub_wire1(2); - sub_wire2(15, 3) <= sub_wire1(3); - sub_wire2(15, 4) <= sub_wire1(4); - sub_wire2(15, 5) <= sub_wire1(5); - sub_wire2(15, 6) <= sub_wire1(6); - sub_wire2(15, 7) <= sub_wire1(7); - sub_wire2(14, 0) <= sub_wire3(0); - sub_wire2(14, 1) <= sub_wire3(1); - sub_wire2(14, 2) <= sub_wire3(2); - sub_wire2(14, 3) <= sub_wire3(3); - sub_wire2(14, 4) <= sub_wire3(4); - sub_wire2(14, 5) <= sub_wire3(5); - sub_wire2(14, 6) <= sub_wire3(6); - sub_wire2(14, 7) <= sub_wire3(7); - sub_wire2(13, 0) <= sub_wire4(0); - sub_wire2(13, 1) <= sub_wire4(1); - sub_wire2(13, 2) <= sub_wire4(2); - sub_wire2(13, 3) <= sub_wire4(3); - sub_wire2(13, 4) <= sub_wire4(4); - sub_wire2(13, 5) <= sub_wire4(5); - sub_wire2(13, 6) <= sub_wire4(6); - sub_wire2(13, 7) <= sub_wire4(7); - sub_wire2(12, 0) <= sub_wire5(0); - sub_wire2(12, 1) <= sub_wire5(1); - sub_wire2(12, 2) <= sub_wire5(2); - sub_wire2(12, 3) <= sub_wire5(3); - sub_wire2(12, 4) <= sub_wire5(4); - sub_wire2(12, 5) <= sub_wire5(5); - sub_wire2(12, 6) <= sub_wire5(6); - sub_wire2(12, 7) <= sub_wire5(7); - sub_wire2(11, 0) <= sub_wire6(0); - sub_wire2(11, 1) <= sub_wire6(1); - sub_wire2(11, 2) <= sub_wire6(2); - sub_wire2(11, 3) <= sub_wire6(3); - sub_wire2(11, 4) <= sub_wire6(4); - sub_wire2(11, 5) <= sub_wire6(5); - sub_wire2(11, 6) <= sub_wire6(6); - sub_wire2(11, 7) <= sub_wire6(7); - sub_wire2(10, 0) <= sub_wire7(0); - sub_wire2(10, 1) <= sub_wire7(1); - sub_wire2(10, 2) <= sub_wire7(2); - sub_wire2(10, 3) <= sub_wire7(3); - sub_wire2(10, 4) <= sub_wire7(4); - sub_wire2(10, 5) <= sub_wire7(5); - sub_wire2(10, 6) <= sub_wire7(6); - sub_wire2(10, 7) <= sub_wire7(7); - sub_wire2(9, 0) <= sub_wire8(0); - sub_wire2(9, 1) <= sub_wire8(1); - sub_wire2(9, 2) <= sub_wire8(2); - sub_wire2(9, 3) <= sub_wire8(3); - sub_wire2(9, 4) <= sub_wire8(4); - sub_wire2(9, 5) <= sub_wire8(5); - sub_wire2(9, 6) <= sub_wire8(6); - sub_wire2(9, 7) <= sub_wire8(7); - sub_wire2(8, 0) <= sub_wire9(0); - sub_wire2(8, 1) <= sub_wire9(1); - sub_wire2(8, 2) <= sub_wire9(2); - sub_wire2(8, 3) <= sub_wire9(3); - sub_wire2(8, 4) <= sub_wire9(4); - sub_wire2(8, 5) <= sub_wire9(5); - sub_wire2(8, 6) <= sub_wire9(6); - sub_wire2(8, 7) <= sub_wire9(7); - sub_wire2(7, 0) <= sub_wire10(0); - sub_wire2(7, 1) <= sub_wire10(1); - sub_wire2(7, 2) <= sub_wire10(2); - sub_wire2(7, 3) <= sub_wire10(3); - sub_wire2(7, 4) <= sub_wire10(4); - sub_wire2(7, 5) <= sub_wire10(5); - sub_wire2(7, 6) <= sub_wire10(6); - sub_wire2(7, 7) <= sub_wire10(7); - sub_wire2(6, 0) <= sub_wire11(0); - sub_wire2(6, 1) <= sub_wire11(1); - sub_wire2(6, 2) <= sub_wire11(2); - sub_wire2(6, 3) <= sub_wire11(3); - sub_wire2(6, 4) <= sub_wire11(4); - sub_wire2(6, 5) <= sub_wire11(5); - sub_wire2(6, 6) <= sub_wire11(6); - sub_wire2(6, 7) <= sub_wire11(7); - sub_wire2(5, 0) <= sub_wire12(0); - sub_wire2(5, 1) <= sub_wire12(1); - sub_wire2(5, 2) <= sub_wire12(2); - sub_wire2(5, 3) <= sub_wire12(3); - sub_wire2(5, 4) <= sub_wire12(4); - sub_wire2(5, 5) <= sub_wire12(5); - sub_wire2(5, 6) <= sub_wire12(6); - sub_wire2(5, 7) <= sub_wire12(7); - sub_wire2(4, 0) <= sub_wire13(0); - sub_wire2(4, 1) <= sub_wire13(1); - sub_wire2(4, 2) <= sub_wire13(2); - sub_wire2(4, 3) <= sub_wire13(3); - sub_wire2(4, 4) <= sub_wire13(4); - sub_wire2(4, 5) <= sub_wire13(5); - sub_wire2(4, 6) <= sub_wire13(6); - sub_wire2(4, 7) <= sub_wire13(7); - sub_wire2(3, 0) <= sub_wire14(0); - sub_wire2(3, 1) <= sub_wire14(1); - sub_wire2(3, 2) <= sub_wire14(2); - sub_wire2(3, 3) <= sub_wire14(3); - sub_wire2(3, 4) <= sub_wire14(4); - sub_wire2(3, 5) <= sub_wire14(5); - sub_wire2(3, 6) <= sub_wire14(6); - sub_wire2(3, 7) <= sub_wire14(7); - sub_wire2(2, 0) <= sub_wire15(0); - sub_wire2(2, 1) <= sub_wire15(1); - sub_wire2(2, 2) <= sub_wire15(2); - sub_wire2(2, 3) <= sub_wire15(3); - sub_wire2(2, 4) <= sub_wire15(4); - sub_wire2(2, 5) <= sub_wire15(5); - sub_wire2(2, 6) <= sub_wire15(6); - sub_wire2(2, 7) <= sub_wire15(7); - sub_wire2(1, 0) <= sub_wire16(0); - sub_wire2(1, 1) <= sub_wire16(1); - sub_wire2(1, 2) <= sub_wire16(2); - sub_wire2(1, 3) <= sub_wire16(3); - sub_wire2(1, 4) <= sub_wire16(4); - sub_wire2(1, 5) <= sub_wire16(5); - sub_wire2(1, 6) <= sub_wire16(6); - sub_wire2(1, 7) <= sub_wire16(7); - sub_wire2(0, 0) <= sub_wire17(0); - sub_wire2(0, 1) <= sub_wire17(1); - sub_wire2(0, 2) <= sub_wire17(2); - sub_wire2(0, 3) <= sub_wire17(3); - sub_wire2(0, 4) <= sub_wire17(4); - sub_wire2(0, 5) <= sub_wire17(5); - sub_wire2(0, 6) <= sub_wire17(6); - sub_wire2(0, 7) <= sub_wire17(7); - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_pipeline => 2, - lpm_size => 16, - lpm_type => "LPM_MUX", - lpm_width => 8, - lpm_widths => 4 - ) - PORT MAP ( - clock => clock, - data => sub_wire2, - sel => sel, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]" --- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL "data10x[7..0]" --- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL "data11x[7..0]" --- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL "data12x[7..0]" --- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL "data13x[7..0]" --- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL "data14x[7..0]" --- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL "data15x[7..0]" --- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]" --- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]" --- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]" --- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL "data4x[7..0]" --- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL "data5x[7..0]" --- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL "data6x[7..0]" --- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL "data7x[7..0]" --- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL "data8x[7..0]" --- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL "data9x[7..0]" --- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]" --- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0 --- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0 --- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 --- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux2.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux2 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_mux2; + + +ARCHITECTURE SYN OF lpm_mux2 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire10 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire11 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire12 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire13 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire14 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire15 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire16 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire17 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + sub_wire17 <= data0x(7 DOWNTO 0); + sub_wire16 <= data1x(7 DOWNTO 0); + sub_wire15 <= data2x(7 DOWNTO 0); + sub_wire14 <= data3x(7 DOWNTO 0); + sub_wire13 <= data4x(7 DOWNTO 0); + sub_wire12 <= data5x(7 DOWNTO 0); + sub_wire11 <= data6x(7 DOWNTO 0); + sub_wire10 <= data7x(7 DOWNTO 0); + sub_wire9 <= data8x(7 DOWNTO 0); + sub_wire8 <= data9x(7 DOWNTO 0); + sub_wire7 <= data10x(7 DOWNTO 0); + sub_wire6 <= data11x(7 DOWNTO 0); + sub_wire5 <= data12x(7 DOWNTO 0); + sub_wire4 <= data13x(7 DOWNTO 0); + sub_wire3 <= data14x(7 DOWNTO 0); + result <= sub_wire0(7 DOWNTO 0); + sub_wire1 <= data15x(7 DOWNTO 0); + sub_wire2(15, 0) <= sub_wire1(0); + sub_wire2(15, 1) <= sub_wire1(1); + sub_wire2(15, 2) <= sub_wire1(2); + sub_wire2(15, 3) <= sub_wire1(3); + sub_wire2(15, 4) <= sub_wire1(4); + sub_wire2(15, 5) <= sub_wire1(5); + sub_wire2(15, 6) <= sub_wire1(6); + sub_wire2(15, 7) <= sub_wire1(7); + sub_wire2(14, 0) <= sub_wire3(0); + sub_wire2(14, 1) <= sub_wire3(1); + sub_wire2(14, 2) <= sub_wire3(2); + sub_wire2(14, 3) <= sub_wire3(3); + sub_wire2(14, 4) <= sub_wire3(4); + sub_wire2(14, 5) <= sub_wire3(5); + sub_wire2(14, 6) <= sub_wire3(6); + sub_wire2(14, 7) <= sub_wire3(7); + sub_wire2(13, 0) <= sub_wire4(0); + sub_wire2(13, 1) <= sub_wire4(1); + sub_wire2(13, 2) <= sub_wire4(2); + sub_wire2(13, 3) <= sub_wire4(3); + sub_wire2(13, 4) <= sub_wire4(4); + sub_wire2(13, 5) <= sub_wire4(5); + sub_wire2(13, 6) <= sub_wire4(6); + sub_wire2(13, 7) <= sub_wire4(7); + sub_wire2(12, 0) <= sub_wire5(0); + sub_wire2(12, 1) <= sub_wire5(1); + sub_wire2(12, 2) <= sub_wire5(2); + sub_wire2(12, 3) <= sub_wire5(3); + sub_wire2(12, 4) <= sub_wire5(4); + sub_wire2(12, 5) <= sub_wire5(5); + sub_wire2(12, 6) <= sub_wire5(6); + sub_wire2(12, 7) <= sub_wire5(7); + sub_wire2(11, 0) <= sub_wire6(0); + sub_wire2(11, 1) <= sub_wire6(1); + sub_wire2(11, 2) <= sub_wire6(2); + sub_wire2(11, 3) <= sub_wire6(3); + sub_wire2(11, 4) <= sub_wire6(4); + sub_wire2(11, 5) <= sub_wire6(5); + sub_wire2(11, 6) <= sub_wire6(6); + sub_wire2(11, 7) <= sub_wire6(7); + sub_wire2(10, 0) <= sub_wire7(0); + sub_wire2(10, 1) <= sub_wire7(1); + sub_wire2(10, 2) <= sub_wire7(2); + sub_wire2(10, 3) <= sub_wire7(3); + sub_wire2(10, 4) <= sub_wire7(4); + sub_wire2(10, 5) <= sub_wire7(5); + sub_wire2(10, 6) <= sub_wire7(6); + sub_wire2(10, 7) <= sub_wire7(7); + sub_wire2(9, 0) <= sub_wire8(0); + sub_wire2(9, 1) <= sub_wire8(1); + sub_wire2(9, 2) <= sub_wire8(2); + sub_wire2(9, 3) <= sub_wire8(3); + sub_wire2(9, 4) <= sub_wire8(4); + sub_wire2(9, 5) <= sub_wire8(5); + sub_wire2(9, 6) <= sub_wire8(6); + sub_wire2(9, 7) <= sub_wire8(7); + sub_wire2(8, 0) <= sub_wire9(0); + sub_wire2(8, 1) <= sub_wire9(1); + sub_wire2(8, 2) <= sub_wire9(2); + sub_wire2(8, 3) <= sub_wire9(3); + sub_wire2(8, 4) <= sub_wire9(4); + sub_wire2(8, 5) <= sub_wire9(5); + sub_wire2(8, 6) <= sub_wire9(6); + sub_wire2(8, 7) <= sub_wire9(7); + sub_wire2(7, 0) <= sub_wire10(0); + sub_wire2(7, 1) <= sub_wire10(1); + sub_wire2(7, 2) <= sub_wire10(2); + sub_wire2(7, 3) <= sub_wire10(3); + sub_wire2(7, 4) <= sub_wire10(4); + sub_wire2(7, 5) <= sub_wire10(5); + sub_wire2(7, 6) <= sub_wire10(6); + sub_wire2(7, 7) <= sub_wire10(7); + sub_wire2(6, 0) <= sub_wire11(0); + sub_wire2(6, 1) <= sub_wire11(1); + sub_wire2(6, 2) <= sub_wire11(2); + sub_wire2(6, 3) <= sub_wire11(3); + sub_wire2(6, 4) <= sub_wire11(4); + sub_wire2(6, 5) <= sub_wire11(5); + sub_wire2(6, 6) <= sub_wire11(6); + sub_wire2(6, 7) <= sub_wire11(7); + sub_wire2(5, 0) <= sub_wire12(0); + sub_wire2(5, 1) <= sub_wire12(1); + sub_wire2(5, 2) <= sub_wire12(2); + sub_wire2(5, 3) <= sub_wire12(3); + sub_wire2(5, 4) <= sub_wire12(4); + sub_wire2(5, 5) <= sub_wire12(5); + sub_wire2(5, 6) <= sub_wire12(6); + sub_wire2(5, 7) <= sub_wire12(7); + sub_wire2(4, 0) <= sub_wire13(0); + sub_wire2(4, 1) <= sub_wire13(1); + sub_wire2(4, 2) <= sub_wire13(2); + sub_wire2(4, 3) <= sub_wire13(3); + sub_wire2(4, 4) <= sub_wire13(4); + sub_wire2(4, 5) <= sub_wire13(5); + sub_wire2(4, 6) <= sub_wire13(6); + sub_wire2(4, 7) <= sub_wire13(7); + sub_wire2(3, 0) <= sub_wire14(0); + sub_wire2(3, 1) <= sub_wire14(1); + sub_wire2(3, 2) <= sub_wire14(2); + sub_wire2(3, 3) <= sub_wire14(3); + sub_wire2(3, 4) <= sub_wire14(4); + sub_wire2(3, 5) <= sub_wire14(5); + sub_wire2(3, 6) <= sub_wire14(6); + sub_wire2(3, 7) <= sub_wire14(7); + sub_wire2(2, 0) <= sub_wire15(0); + sub_wire2(2, 1) <= sub_wire15(1); + sub_wire2(2, 2) <= sub_wire15(2); + sub_wire2(2, 3) <= sub_wire15(3); + sub_wire2(2, 4) <= sub_wire15(4); + sub_wire2(2, 5) <= sub_wire15(5); + sub_wire2(2, 6) <= sub_wire15(6); + sub_wire2(2, 7) <= sub_wire15(7); + sub_wire2(1, 0) <= sub_wire16(0); + sub_wire2(1, 1) <= sub_wire16(1); + sub_wire2(1, 2) <= sub_wire16(2); + sub_wire2(1, 3) <= sub_wire16(3); + sub_wire2(1, 4) <= sub_wire16(4); + sub_wire2(1, 5) <= sub_wire16(5); + sub_wire2(1, 6) <= sub_wire16(6); + sub_wire2(1, 7) <= sub_wire16(7); + sub_wire2(0, 0) <= sub_wire17(0); + sub_wire2(0, 1) <= sub_wire17(1); + sub_wire2(0, 2) <= sub_wire17(2); + sub_wire2(0, 3) <= sub_wire17(3); + sub_wire2(0, 4) <= sub_wire17(4); + sub_wire2(0, 5) <= sub_wire17(5); + sub_wire2(0, 6) <= sub_wire17(6); + sub_wire2(0, 7) <= sub_wire17(7); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 2, + lpm_size => 16, + lpm_type => "LPM_MUX", + lpm_width => 8, + lpm_widths => 4 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0] +-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0] +-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0] +-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0] +-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0] +-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0] +-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0] +-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0] +-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0] +-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0] +-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0] +-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0] +-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0] +-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0] +-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0] +-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0] +-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0 +-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_mux3.bsf b/Video/lpm_mux3.bsf index cb3de81..c389543 100644 --- a/Video/lpm_mux3.bsf +++ b/Video/lpm_mux3.bsf @@ -1,68 +1,60 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 80 80) - (text "lpm_mux3" (rect 11 0 85 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 65 26 76)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data1" (rect 0 0 33 13)(font "Arial" (font_size 8))) - (text "data1" (rect 4 27 32 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 32 40)) - ) - (port - (pt 0 56) - (input) - (text "data0" (rect 0 0 33 13)(font "Arial" (font_size 8))) - (text "data0" (rect 4 43 32 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 32 56)) - ) - (port - (pt 40 80) - (input) - (text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical)) - (text "sel" (rect 34 49 46 63)(font "Arial" (font_size 8))(vertical)) - (line (pt 40 80)(pt 40 68)) - ) - (port - (pt 80 48) - (output) - (text "result" (rect 0 0 33 13)(font "Arial" (font_size 8))) - (text "result" (rect 51 35 78 47)(font "Arial" (font_size 8))) - (line (pt 80 48)(pt 48 48)) - ) - (drawing - (line (pt 32 24)(pt 32 72)) - (line (pt 32 24)(pt 48 32)) - (line (pt 32 72)(pt 48 64)) - (line (pt 48 32)(pt 48 64)) - (line (pt 0 0)(pt 82 0)) - (line (pt 82 0)(pt 82 82)) - (line (pt 0 82)(pt 82 82)) - (line (pt 0 0)(pt 0 82)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 80) + (text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 32 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 32 56)(line_width 1)) + ) + (port + (pt 40 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8))) + (line (pt 40 80)(pt 40 68)(line_width 1)) + ) + (port + (pt 80 48) + (output) + (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "result" (rect 50 35 75 48)(font "Arial" (font_size 8))) + (line (pt 80 48)(pt 48 48)(line_width 1)) + ) + (drawing + (line (pt 32 24)(pt 32 72)(line_width 1)) + (line (pt 48 32)(pt 48 64)(line_width 1)) + (line (pt 32 24)(pt 48 32)(line_width 1)) + (line (pt 32 72)(pt 48 64)(line_width 1)) + ) +) diff --git a/Video/lpm_mux3.cmp b/Video/lpm_mux3.cmp index 9f99918..48f730d 100644 --- a/Video/lpm_mux3.cmp +++ b/Video/lpm_mux3.cmp @@ -1,24 +1,24 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_mux3 - PORT - ( - data0 : IN STD_LOGIC ; - data1 : IN STD_LOGIC ; - sel : IN STD_LOGIC ; - result : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux3 + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +end component; diff --git a/Video/lpm_mux3.qip b/Video/lpm_mux3.qip index b2d0a0c..ca1e672 100644 --- a/Video/lpm_mux3.qip +++ b/Video/lpm_mux3.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"] diff --git a/Video/lpm_mux3.vhd b/Video/lpm_mux3.vhd index 8f9e3aa..b975686 100644 --- a/Video/lpm_mux3.vhd +++ b/Video/lpm_mux3.vhd @@ -1,116 +1,115 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_mux3.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_mux3 IS - PORT - ( - data0 : IN STD_LOGIC ; - data1 : IN STD_LOGIC ; - sel : IN STD_LOGIC ; - result : OUT STD_LOGIC - ); -END lpm_mux3; - - -ARCHITECTURE SYN OF lpm_mux3 IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); - -BEGIN - sub_wire4 <= data0; - sub_wire1 <= sub_wire0(0); - result <= sub_wire1; - sub_wire2 <= data1; - sub_wire3(1, 0) <= sub_wire2; - sub_wire3(0, 0) <= sub_wire4; - sub_wire5 <= sel; - sub_wire6(0) <= sub_wire5; - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_size => 2, - lpm_type => "LPM_MUX", - lpm_width => 1, - lpm_widths => 1 - ) - PORT MAP ( - data => sub_wire3, - sel => sub_wire6, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" --- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0" --- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1" --- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result" --- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel" --- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 --- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 --- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 --- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux3.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux3 IS + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +END lpm_mux3; + + +ARCHITECTURE SYN OF lpm_mux3 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + +BEGIN + sub_wire6 <= data0; + sub_wire1 <= sub_wire0(0); + result <= sub_wire1; + sub_wire2 <= sel; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= data1; + sub_wire5(1, 0) <= sub_wire4; + sub_wire5(0, 0) <= sub_wire6; + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 1, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire3, + data => sub_wire5, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0 +-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1 +-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 +-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 +-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_mux4.bsf b/Video/lpm_mux4.bsf index 8c0f941..a1c9ca0 100644 --- a/Video/lpm_mux4.bsf +++ b/Video/lpm_mux4.bsf @@ -1,68 +1,60 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 80) - (text "lpm_mux4" (rect 43 0 118 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 65 26 76)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data1x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data1x[6..0]" (rect 4 27 61 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data0x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "data0x[6..0]" (rect 4 43 61 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 72 80) - (input) - (text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical)) - (text "sel" (rect 66 49 78 63)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 80)(pt 72 68)) - ) - (port - (pt 144 48) - (output) - (text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8))) - (text "result[6..0]" (rect 91 35 142 47)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 80 48)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 72)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 72)(pt 80 64)) - (line (pt 80 32)(pt 80 64)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 82)) - (line (pt 0 82)(pt 146 82)) - (line (pt 0 0)(pt 0 82)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 136 80) + (text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 72 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8))) + (line (pt 72 80)(pt 72 68)(line_width 1)) + ) + (port + (pt 136 48) + (output) + (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8))) + (line (pt 136 48)(pt 80 48)(line_width 3)) + ) + (drawing + (line (pt 64 24)(pt 64 72)(line_width 1)) + (line (pt 80 32)(pt 80 64)(line_width 1)) + (line (pt 64 24)(pt 80 32)(line_width 1)) + (line (pt 64 72)(pt 80 64)(line_width 1)) + ) +) diff --git a/Video/lpm_mux4.cmp b/Video/lpm_mux4.cmp index 527c71c..05e7a07 100644 --- a/Video/lpm_mux4.cmp +++ b/Video/lpm_mux4.cmp @@ -1,24 +1,24 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_mux4 - PORT - ( - data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); - sel : IN STD_LOGIC ; - result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux4 + PORT + ( + data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_mux4.qip b/Video/lpm_mux4.qip index ec17308..7712e39 100644 --- a/Video/lpm_mux4.qip +++ b/Video/lpm_mux4.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"] diff --git a/Video/lpm_mux4.vhd b/Video/lpm_mux4.vhd index 43ff8df..854a491 100644 --- a/Video/lpm_mux4.vhd +++ b/Video/lpm_mux4.vhd @@ -1,126 +1,125 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_mux4.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_mux4 IS - PORT - ( - data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); - sel : IN STD_LOGIC ; - result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) - ); -END lpm_mux4; - - -ARCHITECTURE SYN OF lpm_mux4 IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (6 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (6 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - -BEGIN - sub_wire3 <= data0x(6 DOWNTO 0); - result <= sub_wire0(6 DOWNTO 0); - sub_wire1 <= data1x(6 DOWNTO 0); - sub_wire2(1, 0) <= sub_wire1(0); - sub_wire2(1, 1) <= sub_wire1(1); - sub_wire2(1, 2) <= sub_wire1(2); - sub_wire2(1, 3) <= sub_wire1(3); - sub_wire2(1, 4) <= sub_wire1(4); - sub_wire2(1, 5) <= sub_wire1(5); - sub_wire2(1, 6) <= sub_wire1(6); - sub_wire2(0, 0) <= sub_wire3(0); - sub_wire2(0, 1) <= sub_wire3(1); - sub_wire2(0, 2) <= sub_wire3(2); - sub_wire2(0, 3) <= sub_wire3(3); - sub_wire2(0, 4) <= sub_wire3(4); - sub_wire2(0, 5) <= sub_wire3(5); - sub_wire2(0, 6) <= sub_wire3(6); - sub_wire4 <= sel; - sub_wire5(0) <= sub_wire4; - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_size => 2, - lpm_type => "LPM_MUX", - lpm_width => 7, - lpm_widths => 1 - ) - PORT MAP ( - data => sub_wire2, - sel => sub_wire5, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" --- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL "data0x[6..0]" --- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL "data1x[6..0]" --- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]" --- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel" --- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0 --- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0 --- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 --- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux4.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux4 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_mux4; + + +ARCHITECTURE SYN OF lpm_mux4 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (6 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(6 DOWNTO 0); + result <= sub_wire0(6 DOWNTO 0); + sub_wire1 <= sel; + sub_wire2(0) <= sub_wire1; + sub_wire3 <= data1x(6 DOWNTO 0); + sub_wire4(1, 0) <= sub_wire3(0); + sub_wire4(1, 1) <= sub_wire3(1); + sub_wire4(1, 2) <= sub_wire3(2); + sub_wire4(1, 3) <= sub_wire3(3); + sub_wire4(1, 4) <= sub_wire3(4); + sub_wire4(1, 5) <= sub_wire3(5); + sub_wire4(1, 6) <= sub_wire3(6); + sub_wire4(0, 0) <= sub_wire5(0); + sub_wire4(0, 1) <= sub_wire5(1); + sub_wire4(0, 2) <= sub_wire5(2); + sub_wire4(0, 3) <= sub_wire5(3); + sub_wire4(0, 4) <= sub_wire5(4); + sub_wire4(0, 5) <= sub_wire5(5); + sub_wire4(0, 6) <= sub_wire5(6); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 7, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire2, + data => sub_wire4, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0] +-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0] +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0] +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_mux5.bsf b/Video/lpm_mux5.bsf index 69a6c35..e63ce50 100644 --- a/Video/lpm_mux5.bsf +++ b/Video/lpm_mux5.bsf @@ -1,82 +1,74 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 112) - (text "lpm_mux5" (rect 43 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 97 26 108)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data3x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data3x[63..0]" (rect 4 27 67 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data2x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data2x[63..0]" (rect 4 43 67 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data1x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data1x[63..0]" (rect 4 59 67 71)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data0x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data0x[63..0]" (rect 4 75 67 87)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 72 112) - (input) - (text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical)) - (text "sel[1..0]" (rect 66 57 78 95)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 112)(pt 72 100)(line_width 3)) - ) - (port - (pt 144 64) - (output) - (text "result[63..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "result[63..0]" (rect 85 51 142 63)(font "Arial" (font_size 8))) - (line (pt 144 64)(pt 80 64)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 104)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 104)(pt 80 96)) - (line (pt 80 32)(pt 80 96)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 114)) - (line (pt 0 114)(pt 146 114)) - (line (pt 0 0)(pt 0 114)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 112) + (text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 80 112) + (input) + (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8))) + (line (pt 80 112)(pt 80 100)(line_width 3)) + ) + (port + (pt 152 64) + (output) + (text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8))) + (line (pt 152 64)(pt 88 64)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 104)(line_width 1)) + (line (pt 88 32)(pt 88 96)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 104)(pt 88 96)(line_width 1)) + ) +) diff --git a/Video/lpm_mux5.cmp b/Video/lpm_mux5.cmp index 7a19761..efc712a 100644 --- a/Video/lpm_mux5.cmp +++ b/Video/lpm_mux5.cmp @@ -1,26 +1,26 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_mux5 - PORT - ( - data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux5 + PORT + ( + data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_mux5.inc b/Video/lpm_mux5.inc index 46e1ac5..a063f55 100644 --- a/Video/lpm_mux5.inc +++ b/Video/lpm_mux5.inc @@ -1,27 +1,27 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_mux5 -( - data0x[63..0], - data1x[63..0], - data2x[63..0], - data3x[63..0], - sel[1..0] -) - -RETURNS ( - result[63..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux5 +( + data0x[63..0], + data1x[63..0], + data2x[63..0], + data3x[63..0], + sel[1..0] +) + +RETURNS ( + result[63..0] +); diff --git a/Video/lpm_mux5.qip b/Video/lpm_mux5.qip index 5d5aeab..08b2e74 100644 --- a/Video/lpm_mux5.qip +++ b/Video/lpm_mux5.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"] diff --git a/Video/lpm_mux5.vhd b/Video/lpm_mux5.vhd index 269376a..1d35347 100644 --- a/Video/lpm_mux5.vhd +++ b/Video/lpm_mux5.vhd @@ -1,374 +1,373 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_mux5.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_mux5 IS - PORT - ( - data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) - ); -END lpm_mux5; - - -ARCHITECTURE SYN OF lpm_mux5 IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (63 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (63 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (63 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (63 DOWNTO 0); - -BEGIN - sub_wire5 <= data0x(63 DOWNTO 0); - sub_wire4 <= data1x(63 DOWNTO 0); - sub_wire3 <= data2x(63 DOWNTO 0); - result <= sub_wire0(63 DOWNTO 0); - sub_wire1 <= data3x(63 DOWNTO 0); - sub_wire2(3, 0) <= sub_wire1(0); - sub_wire2(3, 1) <= sub_wire1(1); - sub_wire2(3, 2) <= sub_wire1(2); - sub_wire2(3, 3) <= sub_wire1(3); - sub_wire2(3, 4) <= sub_wire1(4); - sub_wire2(3, 5) <= sub_wire1(5); - sub_wire2(3, 6) <= sub_wire1(6); - sub_wire2(3, 7) <= sub_wire1(7); - sub_wire2(3, 8) <= sub_wire1(8); - sub_wire2(3, 9) <= sub_wire1(9); - sub_wire2(3, 10) <= sub_wire1(10); - sub_wire2(3, 11) <= sub_wire1(11); - sub_wire2(3, 12) <= sub_wire1(12); - sub_wire2(3, 13) <= sub_wire1(13); - sub_wire2(3, 14) <= sub_wire1(14); - sub_wire2(3, 15) <= sub_wire1(15); - sub_wire2(3, 16) <= sub_wire1(16); - sub_wire2(3, 17) <= sub_wire1(17); - sub_wire2(3, 18) <= sub_wire1(18); - sub_wire2(3, 19) <= sub_wire1(19); - sub_wire2(3, 20) <= sub_wire1(20); - sub_wire2(3, 21) <= sub_wire1(21); - sub_wire2(3, 22) <= sub_wire1(22); - sub_wire2(3, 23) <= sub_wire1(23); - sub_wire2(3, 24) <= sub_wire1(24); - sub_wire2(3, 25) <= sub_wire1(25); - sub_wire2(3, 26) <= sub_wire1(26); - sub_wire2(3, 27) <= sub_wire1(27); - sub_wire2(3, 28) <= sub_wire1(28); - sub_wire2(3, 29) <= sub_wire1(29); - sub_wire2(3, 30) <= sub_wire1(30); - sub_wire2(3, 31) <= sub_wire1(31); - sub_wire2(3, 32) <= sub_wire1(32); - sub_wire2(3, 33) <= sub_wire1(33); - sub_wire2(3, 34) <= sub_wire1(34); - sub_wire2(3, 35) <= sub_wire1(35); - sub_wire2(3, 36) <= sub_wire1(36); - sub_wire2(3, 37) <= sub_wire1(37); - sub_wire2(3, 38) <= sub_wire1(38); - sub_wire2(3, 39) <= sub_wire1(39); - sub_wire2(3, 40) <= sub_wire1(40); - sub_wire2(3, 41) <= sub_wire1(41); - sub_wire2(3, 42) <= sub_wire1(42); - sub_wire2(3, 43) <= sub_wire1(43); - sub_wire2(3, 44) <= sub_wire1(44); - sub_wire2(3, 45) <= sub_wire1(45); - sub_wire2(3, 46) <= sub_wire1(46); - sub_wire2(3, 47) <= sub_wire1(47); - sub_wire2(3, 48) <= sub_wire1(48); - sub_wire2(3, 49) <= sub_wire1(49); - sub_wire2(3, 50) <= sub_wire1(50); - sub_wire2(3, 51) <= sub_wire1(51); - sub_wire2(3, 52) <= sub_wire1(52); - sub_wire2(3, 53) <= sub_wire1(53); - sub_wire2(3, 54) <= sub_wire1(54); - sub_wire2(3, 55) <= sub_wire1(55); - sub_wire2(3, 56) <= sub_wire1(56); - sub_wire2(3, 57) <= sub_wire1(57); - sub_wire2(3, 58) <= sub_wire1(58); - sub_wire2(3, 59) <= sub_wire1(59); - sub_wire2(3, 60) <= sub_wire1(60); - sub_wire2(3, 61) <= sub_wire1(61); - sub_wire2(3, 62) <= sub_wire1(62); - sub_wire2(3, 63) <= sub_wire1(63); - sub_wire2(2, 0) <= sub_wire3(0); - sub_wire2(2, 1) <= sub_wire3(1); - sub_wire2(2, 2) <= sub_wire3(2); - sub_wire2(2, 3) <= sub_wire3(3); - sub_wire2(2, 4) <= sub_wire3(4); - sub_wire2(2, 5) <= sub_wire3(5); - sub_wire2(2, 6) <= sub_wire3(6); - sub_wire2(2, 7) <= sub_wire3(7); - sub_wire2(2, 8) <= sub_wire3(8); - sub_wire2(2, 9) <= sub_wire3(9); - sub_wire2(2, 10) <= sub_wire3(10); - sub_wire2(2, 11) <= sub_wire3(11); - sub_wire2(2, 12) <= sub_wire3(12); - sub_wire2(2, 13) <= sub_wire3(13); - sub_wire2(2, 14) <= sub_wire3(14); - sub_wire2(2, 15) <= sub_wire3(15); - sub_wire2(2, 16) <= sub_wire3(16); - sub_wire2(2, 17) <= sub_wire3(17); - sub_wire2(2, 18) <= sub_wire3(18); - sub_wire2(2, 19) <= sub_wire3(19); - sub_wire2(2, 20) <= sub_wire3(20); - sub_wire2(2, 21) <= sub_wire3(21); - sub_wire2(2, 22) <= sub_wire3(22); - sub_wire2(2, 23) <= sub_wire3(23); - sub_wire2(2, 24) <= sub_wire3(24); - sub_wire2(2, 25) <= sub_wire3(25); - sub_wire2(2, 26) <= sub_wire3(26); - sub_wire2(2, 27) <= sub_wire3(27); - sub_wire2(2, 28) <= sub_wire3(28); - sub_wire2(2, 29) <= sub_wire3(29); - sub_wire2(2, 30) <= sub_wire3(30); - sub_wire2(2, 31) <= sub_wire3(31); - sub_wire2(2, 32) <= sub_wire3(32); - sub_wire2(2, 33) <= sub_wire3(33); - sub_wire2(2, 34) <= sub_wire3(34); - sub_wire2(2, 35) <= sub_wire3(35); - sub_wire2(2, 36) <= sub_wire3(36); - sub_wire2(2, 37) <= sub_wire3(37); - sub_wire2(2, 38) <= sub_wire3(38); - sub_wire2(2, 39) <= sub_wire3(39); - sub_wire2(2, 40) <= sub_wire3(40); - sub_wire2(2, 41) <= sub_wire3(41); - sub_wire2(2, 42) <= sub_wire3(42); - sub_wire2(2, 43) <= sub_wire3(43); - sub_wire2(2, 44) <= sub_wire3(44); - sub_wire2(2, 45) <= sub_wire3(45); - sub_wire2(2, 46) <= sub_wire3(46); - sub_wire2(2, 47) <= sub_wire3(47); - sub_wire2(2, 48) <= sub_wire3(48); - sub_wire2(2, 49) <= sub_wire3(49); - sub_wire2(2, 50) <= sub_wire3(50); - sub_wire2(2, 51) <= sub_wire3(51); - sub_wire2(2, 52) <= sub_wire3(52); - sub_wire2(2, 53) <= sub_wire3(53); - sub_wire2(2, 54) <= sub_wire3(54); - sub_wire2(2, 55) <= sub_wire3(55); - sub_wire2(2, 56) <= sub_wire3(56); - sub_wire2(2, 57) <= sub_wire3(57); - sub_wire2(2, 58) <= sub_wire3(58); - sub_wire2(2, 59) <= sub_wire3(59); - sub_wire2(2, 60) <= sub_wire3(60); - sub_wire2(2, 61) <= sub_wire3(61); - sub_wire2(2, 62) <= sub_wire3(62); - sub_wire2(2, 63) <= sub_wire3(63); - sub_wire2(1, 0) <= sub_wire4(0); - sub_wire2(1, 1) <= sub_wire4(1); - sub_wire2(1, 2) <= sub_wire4(2); - sub_wire2(1, 3) <= sub_wire4(3); - sub_wire2(1, 4) <= sub_wire4(4); - sub_wire2(1, 5) <= sub_wire4(5); - sub_wire2(1, 6) <= sub_wire4(6); - sub_wire2(1, 7) <= sub_wire4(7); - sub_wire2(1, 8) <= sub_wire4(8); - sub_wire2(1, 9) <= sub_wire4(9); - sub_wire2(1, 10) <= sub_wire4(10); - sub_wire2(1, 11) <= sub_wire4(11); - sub_wire2(1, 12) <= sub_wire4(12); - sub_wire2(1, 13) <= sub_wire4(13); - sub_wire2(1, 14) <= sub_wire4(14); - sub_wire2(1, 15) <= sub_wire4(15); - sub_wire2(1, 16) <= sub_wire4(16); - sub_wire2(1, 17) <= sub_wire4(17); - sub_wire2(1, 18) <= sub_wire4(18); - sub_wire2(1, 19) <= sub_wire4(19); - sub_wire2(1, 20) <= sub_wire4(20); - sub_wire2(1, 21) <= sub_wire4(21); - sub_wire2(1, 22) <= sub_wire4(22); - sub_wire2(1, 23) <= sub_wire4(23); - sub_wire2(1, 24) <= sub_wire4(24); - sub_wire2(1, 25) <= sub_wire4(25); - sub_wire2(1, 26) <= sub_wire4(26); - sub_wire2(1, 27) <= sub_wire4(27); - sub_wire2(1, 28) <= sub_wire4(28); - sub_wire2(1, 29) <= sub_wire4(29); - sub_wire2(1, 30) <= sub_wire4(30); - sub_wire2(1, 31) <= sub_wire4(31); - sub_wire2(1, 32) <= sub_wire4(32); - sub_wire2(1, 33) <= sub_wire4(33); - sub_wire2(1, 34) <= sub_wire4(34); - sub_wire2(1, 35) <= sub_wire4(35); - sub_wire2(1, 36) <= sub_wire4(36); - sub_wire2(1, 37) <= sub_wire4(37); - sub_wire2(1, 38) <= sub_wire4(38); - sub_wire2(1, 39) <= sub_wire4(39); - sub_wire2(1, 40) <= sub_wire4(40); - sub_wire2(1, 41) <= sub_wire4(41); - sub_wire2(1, 42) <= sub_wire4(42); - sub_wire2(1, 43) <= sub_wire4(43); - sub_wire2(1, 44) <= sub_wire4(44); - sub_wire2(1, 45) <= sub_wire4(45); - sub_wire2(1, 46) <= sub_wire4(46); - sub_wire2(1, 47) <= sub_wire4(47); - sub_wire2(1, 48) <= sub_wire4(48); - sub_wire2(1, 49) <= sub_wire4(49); - sub_wire2(1, 50) <= sub_wire4(50); - sub_wire2(1, 51) <= sub_wire4(51); - sub_wire2(1, 52) <= sub_wire4(52); - sub_wire2(1, 53) <= sub_wire4(53); - sub_wire2(1, 54) <= sub_wire4(54); - sub_wire2(1, 55) <= sub_wire4(55); - sub_wire2(1, 56) <= sub_wire4(56); - sub_wire2(1, 57) <= sub_wire4(57); - sub_wire2(1, 58) <= sub_wire4(58); - sub_wire2(1, 59) <= sub_wire4(59); - sub_wire2(1, 60) <= sub_wire4(60); - sub_wire2(1, 61) <= sub_wire4(61); - sub_wire2(1, 62) <= sub_wire4(62); - sub_wire2(1, 63) <= sub_wire4(63); - sub_wire2(0, 0) <= sub_wire5(0); - sub_wire2(0, 1) <= sub_wire5(1); - sub_wire2(0, 2) <= sub_wire5(2); - sub_wire2(0, 3) <= sub_wire5(3); - sub_wire2(0, 4) <= sub_wire5(4); - sub_wire2(0, 5) <= sub_wire5(5); - sub_wire2(0, 6) <= sub_wire5(6); - sub_wire2(0, 7) <= sub_wire5(7); - sub_wire2(0, 8) <= sub_wire5(8); - sub_wire2(0, 9) <= sub_wire5(9); - sub_wire2(0, 10) <= sub_wire5(10); - sub_wire2(0, 11) <= sub_wire5(11); - sub_wire2(0, 12) <= sub_wire5(12); - sub_wire2(0, 13) <= sub_wire5(13); - sub_wire2(0, 14) <= sub_wire5(14); - sub_wire2(0, 15) <= sub_wire5(15); - sub_wire2(0, 16) <= sub_wire5(16); - sub_wire2(0, 17) <= sub_wire5(17); - sub_wire2(0, 18) <= sub_wire5(18); - sub_wire2(0, 19) <= sub_wire5(19); - sub_wire2(0, 20) <= sub_wire5(20); - sub_wire2(0, 21) <= sub_wire5(21); - sub_wire2(0, 22) <= sub_wire5(22); - sub_wire2(0, 23) <= sub_wire5(23); - sub_wire2(0, 24) <= sub_wire5(24); - sub_wire2(0, 25) <= sub_wire5(25); - sub_wire2(0, 26) <= sub_wire5(26); - sub_wire2(0, 27) <= sub_wire5(27); - sub_wire2(0, 28) <= sub_wire5(28); - sub_wire2(0, 29) <= sub_wire5(29); - sub_wire2(0, 30) <= sub_wire5(30); - sub_wire2(0, 31) <= sub_wire5(31); - sub_wire2(0, 32) <= sub_wire5(32); - sub_wire2(0, 33) <= sub_wire5(33); - sub_wire2(0, 34) <= sub_wire5(34); - sub_wire2(0, 35) <= sub_wire5(35); - sub_wire2(0, 36) <= sub_wire5(36); - sub_wire2(0, 37) <= sub_wire5(37); - sub_wire2(0, 38) <= sub_wire5(38); - sub_wire2(0, 39) <= sub_wire5(39); - sub_wire2(0, 40) <= sub_wire5(40); - sub_wire2(0, 41) <= sub_wire5(41); - sub_wire2(0, 42) <= sub_wire5(42); - sub_wire2(0, 43) <= sub_wire5(43); - sub_wire2(0, 44) <= sub_wire5(44); - sub_wire2(0, 45) <= sub_wire5(45); - sub_wire2(0, 46) <= sub_wire5(46); - sub_wire2(0, 47) <= sub_wire5(47); - sub_wire2(0, 48) <= sub_wire5(48); - sub_wire2(0, 49) <= sub_wire5(49); - sub_wire2(0, 50) <= sub_wire5(50); - sub_wire2(0, 51) <= sub_wire5(51); - sub_wire2(0, 52) <= sub_wire5(52); - sub_wire2(0, 53) <= sub_wire5(53); - sub_wire2(0, 54) <= sub_wire5(54); - sub_wire2(0, 55) <= sub_wire5(55); - sub_wire2(0, 56) <= sub_wire5(56); - sub_wire2(0, 57) <= sub_wire5(57); - sub_wire2(0, 58) <= sub_wire5(58); - sub_wire2(0, 59) <= sub_wire5(59); - sub_wire2(0, 60) <= sub_wire5(60); - sub_wire2(0, 61) <= sub_wire5(61); - sub_wire2(0, 62) <= sub_wire5(62); - sub_wire2(0, 63) <= sub_wire5(63); - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_size => 4, - lpm_type => "LPM_MUX", - lpm_width => 64, - lpm_widths => 2 - ) - PORT MAP ( - data => sub_wire2, - sel => sel, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" --- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL "data0x[63..0]" --- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL "data1x[63..0]" --- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL "data2x[63..0]" --- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL "data3x[63..0]" --- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]" --- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]" --- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0 --- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0 --- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0 --- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0 --- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 --- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux5.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux5 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) + ); +END lpm_mux5; + + +ARCHITECTURE SYN OF lpm_mux5 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (63 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(63 DOWNTO 0); + sub_wire4 <= data1x(63 DOWNTO 0); + sub_wire3 <= data2x(63 DOWNTO 0); + result <= sub_wire0(63 DOWNTO 0); + sub_wire1 <= data3x(63 DOWNTO 0); + sub_wire2(3, 0) <= sub_wire1(0); + sub_wire2(3, 1) <= sub_wire1(1); + sub_wire2(3, 2) <= sub_wire1(2); + sub_wire2(3, 3) <= sub_wire1(3); + sub_wire2(3, 4) <= sub_wire1(4); + sub_wire2(3, 5) <= sub_wire1(5); + sub_wire2(3, 6) <= sub_wire1(6); + sub_wire2(3, 7) <= sub_wire1(7); + sub_wire2(3, 8) <= sub_wire1(8); + sub_wire2(3, 9) <= sub_wire1(9); + sub_wire2(3, 10) <= sub_wire1(10); + sub_wire2(3, 11) <= sub_wire1(11); + sub_wire2(3, 12) <= sub_wire1(12); + sub_wire2(3, 13) <= sub_wire1(13); + sub_wire2(3, 14) <= sub_wire1(14); + sub_wire2(3, 15) <= sub_wire1(15); + sub_wire2(3, 16) <= sub_wire1(16); + sub_wire2(3, 17) <= sub_wire1(17); + sub_wire2(3, 18) <= sub_wire1(18); + sub_wire2(3, 19) <= sub_wire1(19); + sub_wire2(3, 20) <= sub_wire1(20); + sub_wire2(3, 21) <= sub_wire1(21); + sub_wire2(3, 22) <= sub_wire1(22); + sub_wire2(3, 23) <= sub_wire1(23); + sub_wire2(3, 24) <= sub_wire1(24); + sub_wire2(3, 25) <= sub_wire1(25); + sub_wire2(3, 26) <= sub_wire1(26); + sub_wire2(3, 27) <= sub_wire1(27); + sub_wire2(3, 28) <= sub_wire1(28); + sub_wire2(3, 29) <= sub_wire1(29); + sub_wire2(3, 30) <= sub_wire1(30); + sub_wire2(3, 31) <= sub_wire1(31); + sub_wire2(3, 32) <= sub_wire1(32); + sub_wire2(3, 33) <= sub_wire1(33); + sub_wire2(3, 34) <= sub_wire1(34); + sub_wire2(3, 35) <= sub_wire1(35); + sub_wire2(3, 36) <= sub_wire1(36); + sub_wire2(3, 37) <= sub_wire1(37); + sub_wire2(3, 38) <= sub_wire1(38); + sub_wire2(3, 39) <= sub_wire1(39); + sub_wire2(3, 40) <= sub_wire1(40); + sub_wire2(3, 41) <= sub_wire1(41); + sub_wire2(3, 42) <= sub_wire1(42); + sub_wire2(3, 43) <= sub_wire1(43); + sub_wire2(3, 44) <= sub_wire1(44); + sub_wire2(3, 45) <= sub_wire1(45); + sub_wire2(3, 46) <= sub_wire1(46); + sub_wire2(3, 47) <= sub_wire1(47); + sub_wire2(3, 48) <= sub_wire1(48); + sub_wire2(3, 49) <= sub_wire1(49); + sub_wire2(3, 50) <= sub_wire1(50); + sub_wire2(3, 51) <= sub_wire1(51); + sub_wire2(3, 52) <= sub_wire1(52); + sub_wire2(3, 53) <= sub_wire1(53); + sub_wire2(3, 54) <= sub_wire1(54); + sub_wire2(3, 55) <= sub_wire1(55); + sub_wire2(3, 56) <= sub_wire1(56); + sub_wire2(3, 57) <= sub_wire1(57); + sub_wire2(3, 58) <= sub_wire1(58); + sub_wire2(3, 59) <= sub_wire1(59); + sub_wire2(3, 60) <= sub_wire1(60); + sub_wire2(3, 61) <= sub_wire1(61); + sub_wire2(3, 62) <= sub_wire1(62); + sub_wire2(3, 63) <= sub_wire1(63); + sub_wire2(2, 0) <= sub_wire3(0); + sub_wire2(2, 1) <= sub_wire3(1); + sub_wire2(2, 2) <= sub_wire3(2); + sub_wire2(2, 3) <= sub_wire3(3); + sub_wire2(2, 4) <= sub_wire3(4); + sub_wire2(2, 5) <= sub_wire3(5); + sub_wire2(2, 6) <= sub_wire3(6); + sub_wire2(2, 7) <= sub_wire3(7); + sub_wire2(2, 8) <= sub_wire3(8); + sub_wire2(2, 9) <= sub_wire3(9); + sub_wire2(2, 10) <= sub_wire3(10); + sub_wire2(2, 11) <= sub_wire3(11); + sub_wire2(2, 12) <= sub_wire3(12); + sub_wire2(2, 13) <= sub_wire3(13); + sub_wire2(2, 14) <= sub_wire3(14); + sub_wire2(2, 15) <= sub_wire3(15); + sub_wire2(2, 16) <= sub_wire3(16); + sub_wire2(2, 17) <= sub_wire3(17); + sub_wire2(2, 18) <= sub_wire3(18); + sub_wire2(2, 19) <= sub_wire3(19); + sub_wire2(2, 20) <= sub_wire3(20); + sub_wire2(2, 21) <= sub_wire3(21); + sub_wire2(2, 22) <= sub_wire3(22); + sub_wire2(2, 23) <= sub_wire3(23); + sub_wire2(2, 24) <= sub_wire3(24); + sub_wire2(2, 25) <= sub_wire3(25); + sub_wire2(2, 26) <= sub_wire3(26); + sub_wire2(2, 27) <= sub_wire3(27); + sub_wire2(2, 28) <= sub_wire3(28); + sub_wire2(2, 29) <= sub_wire3(29); + sub_wire2(2, 30) <= sub_wire3(30); + sub_wire2(2, 31) <= sub_wire3(31); + sub_wire2(2, 32) <= sub_wire3(32); + sub_wire2(2, 33) <= sub_wire3(33); + sub_wire2(2, 34) <= sub_wire3(34); + sub_wire2(2, 35) <= sub_wire3(35); + sub_wire2(2, 36) <= sub_wire3(36); + sub_wire2(2, 37) <= sub_wire3(37); + sub_wire2(2, 38) <= sub_wire3(38); + sub_wire2(2, 39) <= sub_wire3(39); + sub_wire2(2, 40) <= sub_wire3(40); + sub_wire2(2, 41) <= sub_wire3(41); + sub_wire2(2, 42) <= sub_wire3(42); + sub_wire2(2, 43) <= sub_wire3(43); + sub_wire2(2, 44) <= sub_wire3(44); + sub_wire2(2, 45) <= sub_wire3(45); + sub_wire2(2, 46) <= sub_wire3(46); + sub_wire2(2, 47) <= sub_wire3(47); + sub_wire2(2, 48) <= sub_wire3(48); + sub_wire2(2, 49) <= sub_wire3(49); + sub_wire2(2, 50) <= sub_wire3(50); + sub_wire2(2, 51) <= sub_wire3(51); + sub_wire2(2, 52) <= sub_wire3(52); + sub_wire2(2, 53) <= sub_wire3(53); + sub_wire2(2, 54) <= sub_wire3(54); + sub_wire2(2, 55) <= sub_wire3(55); + sub_wire2(2, 56) <= sub_wire3(56); + sub_wire2(2, 57) <= sub_wire3(57); + sub_wire2(2, 58) <= sub_wire3(58); + sub_wire2(2, 59) <= sub_wire3(59); + sub_wire2(2, 60) <= sub_wire3(60); + sub_wire2(2, 61) <= sub_wire3(61); + sub_wire2(2, 62) <= sub_wire3(62); + sub_wire2(2, 63) <= sub_wire3(63); + sub_wire2(1, 0) <= sub_wire4(0); + sub_wire2(1, 1) <= sub_wire4(1); + sub_wire2(1, 2) <= sub_wire4(2); + sub_wire2(1, 3) <= sub_wire4(3); + sub_wire2(1, 4) <= sub_wire4(4); + sub_wire2(1, 5) <= sub_wire4(5); + sub_wire2(1, 6) <= sub_wire4(6); + sub_wire2(1, 7) <= sub_wire4(7); + sub_wire2(1, 8) <= sub_wire4(8); + sub_wire2(1, 9) <= sub_wire4(9); + sub_wire2(1, 10) <= sub_wire4(10); + sub_wire2(1, 11) <= sub_wire4(11); + sub_wire2(1, 12) <= sub_wire4(12); + sub_wire2(1, 13) <= sub_wire4(13); + sub_wire2(1, 14) <= sub_wire4(14); + sub_wire2(1, 15) <= sub_wire4(15); + sub_wire2(1, 16) <= sub_wire4(16); + sub_wire2(1, 17) <= sub_wire4(17); + sub_wire2(1, 18) <= sub_wire4(18); + sub_wire2(1, 19) <= sub_wire4(19); + sub_wire2(1, 20) <= sub_wire4(20); + sub_wire2(1, 21) <= sub_wire4(21); + sub_wire2(1, 22) <= sub_wire4(22); + sub_wire2(1, 23) <= sub_wire4(23); + sub_wire2(1, 24) <= sub_wire4(24); + sub_wire2(1, 25) <= sub_wire4(25); + sub_wire2(1, 26) <= sub_wire4(26); + sub_wire2(1, 27) <= sub_wire4(27); + sub_wire2(1, 28) <= sub_wire4(28); + sub_wire2(1, 29) <= sub_wire4(29); + sub_wire2(1, 30) <= sub_wire4(30); + sub_wire2(1, 31) <= sub_wire4(31); + sub_wire2(1, 32) <= sub_wire4(32); + sub_wire2(1, 33) <= sub_wire4(33); + sub_wire2(1, 34) <= sub_wire4(34); + sub_wire2(1, 35) <= sub_wire4(35); + sub_wire2(1, 36) <= sub_wire4(36); + sub_wire2(1, 37) <= sub_wire4(37); + sub_wire2(1, 38) <= sub_wire4(38); + sub_wire2(1, 39) <= sub_wire4(39); + sub_wire2(1, 40) <= sub_wire4(40); + sub_wire2(1, 41) <= sub_wire4(41); + sub_wire2(1, 42) <= sub_wire4(42); + sub_wire2(1, 43) <= sub_wire4(43); + sub_wire2(1, 44) <= sub_wire4(44); + sub_wire2(1, 45) <= sub_wire4(45); + sub_wire2(1, 46) <= sub_wire4(46); + sub_wire2(1, 47) <= sub_wire4(47); + sub_wire2(1, 48) <= sub_wire4(48); + sub_wire2(1, 49) <= sub_wire4(49); + sub_wire2(1, 50) <= sub_wire4(50); + sub_wire2(1, 51) <= sub_wire4(51); + sub_wire2(1, 52) <= sub_wire4(52); + sub_wire2(1, 53) <= sub_wire4(53); + sub_wire2(1, 54) <= sub_wire4(54); + sub_wire2(1, 55) <= sub_wire4(55); + sub_wire2(1, 56) <= sub_wire4(56); + sub_wire2(1, 57) <= sub_wire4(57); + sub_wire2(1, 58) <= sub_wire4(58); + sub_wire2(1, 59) <= sub_wire4(59); + sub_wire2(1, 60) <= sub_wire4(60); + sub_wire2(1, 61) <= sub_wire4(61); + sub_wire2(1, 62) <= sub_wire4(62); + sub_wire2(1, 63) <= sub_wire4(63); + sub_wire2(0, 0) <= sub_wire5(0); + sub_wire2(0, 1) <= sub_wire5(1); + sub_wire2(0, 2) <= sub_wire5(2); + sub_wire2(0, 3) <= sub_wire5(3); + sub_wire2(0, 4) <= sub_wire5(4); + sub_wire2(0, 5) <= sub_wire5(5); + sub_wire2(0, 6) <= sub_wire5(6); + sub_wire2(0, 7) <= sub_wire5(7); + sub_wire2(0, 8) <= sub_wire5(8); + sub_wire2(0, 9) <= sub_wire5(9); + sub_wire2(0, 10) <= sub_wire5(10); + sub_wire2(0, 11) <= sub_wire5(11); + sub_wire2(0, 12) <= sub_wire5(12); + sub_wire2(0, 13) <= sub_wire5(13); + sub_wire2(0, 14) <= sub_wire5(14); + sub_wire2(0, 15) <= sub_wire5(15); + sub_wire2(0, 16) <= sub_wire5(16); + sub_wire2(0, 17) <= sub_wire5(17); + sub_wire2(0, 18) <= sub_wire5(18); + sub_wire2(0, 19) <= sub_wire5(19); + sub_wire2(0, 20) <= sub_wire5(20); + sub_wire2(0, 21) <= sub_wire5(21); + sub_wire2(0, 22) <= sub_wire5(22); + sub_wire2(0, 23) <= sub_wire5(23); + sub_wire2(0, 24) <= sub_wire5(24); + sub_wire2(0, 25) <= sub_wire5(25); + sub_wire2(0, 26) <= sub_wire5(26); + sub_wire2(0, 27) <= sub_wire5(27); + sub_wire2(0, 28) <= sub_wire5(28); + sub_wire2(0, 29) <= sub_wire5(29); + sub_wire2(0, 30) <= sub_wire5(30); + sub_wire2(0, 31) <= sub_wire5(31); + sub_wire2(0, 32) <= sub_wire5(32); + sub_wire2(0, 33) <= sub_wire5(33); + sub_wire2(0, 34) <= sub_wire5(34); + sub_wire2(0, 35) <= sub_wire5(35); + sub_wire2(0, 36) <= sub_wire5(36); + sub_wire2(0, 37) <= sub_wire5(37); + sub_wire2(0, 38) <= sub_wire5(38); + sub_wire2(0, 39) <= sub_wire5(39); + sub_wire2(0, 40) <= sub_wire5(40); + sub_wire2(0, 41) <= sub_wire5(41); + sub_wire2(0, 42) <= sub_wire5(42); + sub_wire2(0, 43) <= sub_wire5(43); + sub_wire2(0, 44) <= sub_wire5(44); + sub_wire2(0, 45) <= sub_wire5(45); + sub_wire2(0, 46) <= sub_wire5(46); + sub_wire2(0, 47) <= sub_wire5(47); + sub_wire2(0, 48) <= sub_wire5(48); + sub_wire2(0, 49) <= sub_wire5(49); + sub_wire2(0, 50) <= sub_wire5(50); + sub_wire2(0, 51) <= sub_wire5(51); + sub_wire2(0, 52) <= sub_wire5(52); + sub_wire2(0, 53) <= sub_wire5(53); + sub_wire2(0, 54) <= sub_wire5(54); + sub_wire2(0, 55) <= sub_wire5(55); + sub_wire2(0, 56) <= sub_wire5(56); + sub_wire2(0, 57) <= sub_wire5(57); + sub_wire2(0, 58) <= sub_wire5(58); + sub_wire2(0, 59) <= sub_wire5(59); + sub_wire2(0, 60) <= sub_wire5(60); + sub_wire2(0, 61) <= sub_wire5(61); + sub_wire2(0, 62) <= sub_wire5(62); + sub_wire2(0, 63) <= sub_wire5(63); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 4, + lpm_type => "LPM_MUX", + lpm_width => 64, + lpm_widths => 2 + ) + PORT MAP ( + sel => sel, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" +-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0] +-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0] +-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0] +-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0] +-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0] +-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0] +-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0 +-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_mux6.bsf b/Video/lpm_mux6.bsf index ad0291b..2196842 100644 --- a/Video/lpm_mux6.bsf +++ b/Video/lpm_mux6.bsf @@ -1,119 +1,111 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 192) - (text "lpm_mux6" (rect 43 0 117 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 177 26 188)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data7x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data7x[23..0]" (rect 4 27 67 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data6x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data6x[23..0]" (rect 4 43 67 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data5x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data5x[23..0]" (rect 4 59 67 71)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data4x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data4x[23..0]" (rect 4 75 67 87)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "data3x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data3x[23..0]" (rect 4 91 67 103)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 64 104)(line_width 3)) - ) - (port - (pt 0 120) - (input) - (text "data2x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data2x[23..0]" (rect 4 107 67 119)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 64 120)(line_width 3)) - ) - (port - (pt 0 136) - (input) - (text "data1x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data1x[23..0]" (rect 4 123 67 135)(font "Arial" (font_size 8))) - (line (pt 0 136)(pt 64 136)(line_width 3)) - ) - (port - (pt 0 152) - (input) - (text "data0x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "data0x[23..0]" (rect 4 139 67 151)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 64 152)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 4 155 29 167)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 64 168)) - ) - (port - (pt 72 192) - (input) - (text "sel[2..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical)) - (text "sel[2..0]" (rect 66 137 78 175)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 192)(pt 72 180)(line_width 3)) - ) - (port - (pt 144 104) - (output) - (text "result[23..0]" (rect 0 0 67 13)(font "Arial" (font_size 8))) - (text "result[23..0]" (rect 85 91 142 103)(font "Arial" (font_size 8))) - (line (pt 144 104)(pt 80 104)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 184)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 184)(pt 80 176)) - (line (pt 80 32)(pt 80 176)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 194)) - (line (pt 0 194)(pt 146 194)) - (line (pt 0 0)(pt 0 194)) - (line (pt 64 162)(pt 70 168)) - (line (pt 70 168)(pt 64 174)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 192) + (text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 176 25 188)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 1)) + ) + (port + (pt 80 192) + (input) + (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) + (line (pt 80 192)(pt 80 180)(line_width 3)) + ) + (port + (pt 152 104) + (output) + (text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) + (line (pt 152 104)(pt 88 104)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 184)(line_width 1)) + (line (pt 88 32)(pt 88 176)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 184)(pt 88 176)(line_width 1)) + (line (pt 72 162)(pt 78 168)(line_width 1)) + (line (pt 78 168)(pt 72 174)(line_width 1)) + ) +) diff --git a/Video/lpm_mux6.cmp b/Video/lpm_mux6.cmp index e84abcb..543da1f 100644 --- a/Video/lpm_mux6.cmp +++ b/Video/lpm_mux6.cmp @@ -1,31 +1,31 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_mux6 - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux6 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_mux6.inc b/Video/lpm_mux6.inc index ba93be4..3cf223d 100644 --- a/Video/lpm_mux6.inc +++ b/Video/lpm_mux6.inc @@ -1,32 +1,32 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_mux6 -( - clock, - data0x[23..0], - data1x[23..0], - data2x[23..0], - data3x[23..0], - data4x[23..0], - data5x[23..0], - data6x[23..0], - data7x[23..0], - sel[2..0] -) - -RETURNS ( - result[23..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux6 +( + clock, + data0x[23..0], + data1x[23..0], + data2x[23..0], + data3x[23..0], + data4x[23..0], + data5x[23..0], + data6x[23..0], + data7x[23..0], + sel[2..0] +) + +RETURNS ( + result[23..0] +); diff --git a/Video/lpm_mux6.qip b/Video/lpm_mux6.qip index dc535d9..051a945 100644 --- a/Video/lpm_mux6.qip +++ b/Video/lpm_mux6.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"] diff --git a/Video/lpm_mux6.vhd b/Video/lpm_mux6.vhd index 92e4317..42d5aae 100644 --- a/Video/lpm_mux6.vhd +++ b/Video/lpm_mux6.vhd @@ -1,336 +1,335 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_mux6.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_mux6 IS - PORT - ( - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) - ); -END lpm_mux6; - - -ARCHITECTURE SYN OF lpm_mux6 IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (23 DOWNTO 0); - SIGNAL sub_wire9 : STD_LOGIC_VECTOR (23 DOWNTO 0); - -BEGIN - sub_wire9 <= data0x(23 DOWNTO 0); - sub_wire8 <= data1x(23 DOWNTO 0); - sub_wire7 <= data2x(23 DOWNTO 0); - sub_wire6 <= data3x(23 DOWNTO 0); - sub_wire5 <= data4x(23 DOWNTO 0); - sub_wire4 <= data5x(23 DOWNTO 0); - sub_wire3 <= data6x(23 DOWNTO 0); - result <= sub_wire0(23 DOWNTO 0); - sub_wire1 <= data7x(23 DOWNTO 0); - sub_wire2(7, 0) <= sub_wire1(0); - sub_wire2(7, 1) <= sub_wire1(1); - sub_wire2(7, 2) <= sub_wire1(2); - sub_wire2(7, 3) <= sub_wire1(3); - sub_wire2(7, 4) <= sub_wire1(4); - sub_wire2(7, 5) <= sub_wire1(5); - sub_wire2(7, 6) <= sub_wire1(6); - sub_wire2(7, 7) <= sub_wire1(7); - sub_wire2(7, 8) <= sub_wire1(8); - sub_wire2(7, 9) <= sub_wire1(9); - sub_wire2(7, 10) <= sub_wire1(10); - sub_wire2(7, 11) <= sub_wire1(11); - sub_wire2(7, 12) <= sub_wire1(12); - sub_wire2(7, 13) <= sub_wire1(13); - sub_wire2(7, 14) <= sub_wire1(14); - sub_wire2(7, 15) <= sub_wire1(15); - sub_wire2(7, 16) <= sub_wire1(16); - sub_wire2(7, 17) <= sub_wire1(17); - sub_wire2(7, 18) <= sub_wire1(18); - sub_wire2(7, 19) <= sub_wire1(19); - sub_wire2(7, 20) <= sub_wire1(20); - sub_wire2(7, 21) <= sub_wire1(21); - sub_wire2(7, 22) <= sub_wire1(22); - sub_wire2(7, 23) <= sub_wire1(23); - sub_wire2(6, 0) <= sub_wire3(0); - sub_wire2(6, 1) <= sub_wire3(1); - sub_wire2(6, 2) <= sub_wire3(2); - sub_wire2(6, 3) <= sub_wire3(3); - sub_wire2(6, 4) <= sub_wire3(4); - sub_wire2(6, 5) <= sub_wire3(5); - sub_wire2(6, 6) <= sub_wire3(6); - sub_wire2(6, 7) <= sub_wire3(7); - sub_wire2(6, 8) <= sub_wire3(8); - sub_wire2(6, 9) <= sub_wire3(9); - sub_wire2(6, 10) <= sub_wire3(10); - sub_wire2(6, 11) <= sub_wire3(11); - sub_wire2(6, 12) <= sub_wire3(12); - sub_wire2(6, 13) <= sub_wire3(13); - sub_wire2(6, 14) <= sub_wire3(14); - sub_wire2(6, 15) <= sub_wire3(15); - sub_wire2(6, 16) <= sub_wire3(16); - sub_wire2(6, 17) <= sub_wire3(17); - sub_wire2(6, 18) <= sub_wire3(18); - sub_wire2(6, 19) <= sub_wire3(19); - sub_wire2(6, 20) <= sub_wire3(20); - sub_wire2(6, 21) <= sub_wire3(21); - sub_wire2(6, 22) <= sub_wire3(22); - sub_wire2(6, 23) <= sub_wire3(23); - sub_wire2(5, 0) <= sub_wire4(0); - sub_wire2(5, 1) <= sub_wire4(1); - sub_wire2(5, 2) <= sub_wire4(2); - sub_wire2(5, 3) <= sub_wire4(3); - sub_wire2(5, 4) <= sub_wire4(4); - sub_wire2(5, 5) <= sub_wire4(5); - sub_wire2(5, 6) <= sub_wire4(6); - sub_wire2(5, 7) <= sub_wire4(7); - sub_wire2(5, 8) <= sub_wire4(8); - sub_wire2(5, 9) <= sub_wire4(9); - sub_wire2(5, 10) <= sub_wire4(10); - sub_wire2(5, 11) <= sub_wire4(11); - sub_wire2(5, 12) <= sub_wire4(12); - sub_wire2(5, 13) <= sub_wire4(13); - sub_wire2(5, 14) <= sub_wire4(14); - sub_wire2(5, 15) <= sub_wire4(15); - sub_wire2(5, 16) <= sub_wire4(16); - sub_wire2(5, 17) <= sub_wire4(17); - sub_wire2(5, 18) <= sub_wire4(18); - sub_wire2(5, 19) <= sub_wire4(19); - sub_wire2(5, 20) <= sub_wire4(20); - sub_wire2(5, 21) <= sub_wire4(21); - sub_wire2(5, 22) <= sub_wire4(22); - sub_wire2(5, 23) <= sub_wire4(23); - sub_wire2(4, 0) <= sub_wire5(0); - sub_wire2(4, 1) <= sub_wire5(1); - sub_wire2(4, 2) <= sub_wire5(2); - sub_wire2(4, 3) <= sub_wire5(3); - sub_wire2(4, 4) <= sub_wire5(4); - sub_wire2(4, 5) <= sub_wire5(5); - sub_wire2(4, 6) <= sub_wire5(6); - sub_wire2(4, 7) <= sub_wire5(7); - sub_wire2(4, 8) <= sub_wire5(8); - sub_wire2(4, 9) <= sub_wire5(9); - sub_wire2(4, 10) <= sub_wire5(10); - sub_wire2(4, 11) <= sub_wire5(11); - sub_wire2(4, 12) <= sub_wire5(12); - sub_wire2(4, 13) <= sub_wire5(13); - sub_wire2(4, 14) <= sub_wire5(14); - sub_wire2(4, 15) <= sub_wire5(15); - sub_wire2(4, 16) <= sub_wire5(16); - sub_wire2(4, 17) <= sub_wire5(17); - sub_wire2(4, 18) <= sub_wire5(18); - sub_wire2(4, 19) <= sub_wire5(19); - sub_wire2(4, 20) <= sub_wire5(20); - sub_wire2(4, 21) <= sub_wire5(21); - sub_wire2(4, 22) <= sub_wire5(22); - sub_wire2(4, 23) <= sub_wire5(23); - sub_wire2(3, 0) <= sub_wire6(0); - sub_wire2(3, 1) <= sub_wire6(1); - sub_wire2(3, 2) <= sub_wire6(2); - sub_wire2(3, 3) <= sub_wire6(3); - sub_wire2(3, 4) <= sub_wire6(4); - sub_wire2(3, 5) <= sub_wire6(5); - sub_wire2(3, 6) <= sub_wire6(6); - sub_wire2(3, 7) <= sub_wire6(7); - sub_wire2(3, 8) <= sub_wire6(8); - sub_wire2(3, 9) <= sub_wire6(9); - sub_wire2(3, 10) <= sub_wire6(10); - sub_wire2(3, 11) <= sub_wire6(11); - sub_wire2(3, 12) <= sub_wire6(12); - sub_wire2(3, 13) <= sub_wire6(13); - sub_wire2(3, 14) <= sub_wire6(14); - sub_wire2(3, 15) <= sub_wire6(15); - sub_wire2(3, 16) <= sub_wire6(16); - sub_wire2(3, 17) <= sub_wire6(17); - sub_wire2(3, 18) <= sub_wire6(18); - sub_wire2(3, 19) <= sub_wire6(19); - sub_wire2(3, 20) <= sub_wire6(20); - sub_wire2(3, 21) <= sub_wire6(21); - sub_wire2(3, 22) <= sub_wire6(22); - sub_wire2(3, 23) <= sub_wire6(23); - sub_wire2(2, 0) <= sub_wire7(0); - sub_wire2(2, 1) <= sub_wire7(1); - sub_wire2(2, 2) <= sub_wire7(2); - sub_wire2(2, 3) <= sub_wire7(3); - sub_wire2(2, 4) <= sub_wire7(4); - sub_wire2(2, 5) <= sub_wire7(5); - sub_wire2(2, 6) <= sub_wire7(6); - sub_wire2(2, 7) <= sub_wire7(7); - sub_wire2(2, 8) <= sub_wire7(8); - sub_wire2(2, 9) <= sub_wire7(9); - sub_wire2(2, 10) <= sub_wire7(10); - sub_wire2(2, 11) <= sub_wire7(11); - sub_wire2(2, 12) <= sub_wire7(12); - sub_wire2(2, 13) <= sub_wire7(13); - sub_wire2(2, 14) <= sub_wire7(14); - sub_wire2(2, 15) <= sub_wire7(15); - sub_wire2(2, 16) <= sub_wire7(16); - sub_wire2(2, 17) <= sub_wire7(17); - sub_wire2(2, 18) <= sub_wire7(18); - sub_wire2(2, 19) <= sub_wire7(19); - sub_wire2(2, 20) <= sub_wire7(20); - sub_wire2(2, 21) <= sub_wire7(21); - sub_wire2(2, 22) <= sub_wire7(22); - sub_wire2(2, 23) <= sub_wire7(23); - sub_wire2(1, 0) <= sub_wire8(0); - sub_wire2(1, 1) <= sub_wire8(1); - sub_wire2(1, 2) <= sub_wire8(2); - sub_wire2(1, 3) <= sub_wire8(3); - sub_wire2(1, 4) <= sub_wire8(4); - sub_wire2(1, 5) <= sub_wire8(5); - sub_wire2(1, 6) <= sub_wire8(6); - sub_wire2(1, 7) <= sub_wire8(7); - sub_wire2(1, 8) <= sub_wire8(8); - sub_wire2(1, 9) <= sub_wire8(9); - sub_wire2(1, 10) <= sub_wire8(10); - sub_wire2(1, 11) <= sub_wire8(11); - sub_wire2(1, 12) <= sub_wire8(12); - sub_wire2(1, 13) <= sub_wire8(13); - sub_wire2(1, 14) <= sub_wire8(14); - sub_wire2(1, 15) <= sub_wire8(15); - sub_wire2(1, 16) <= sub_wire8(16); - sub_wire2(1, 17) <= sub_wire8(17); - sub_wire2(1, 18) <= sub_wire8(18); - sub_wire2(1, 19) <= sub_wire8(19); - sub_wire2(1, 20) <= sub_wire8(20); - sub_wire2(1, 21) <= sub_wire8(21); - sub_wire2(1, 22) <= sub_wire8(22); - sub_wire2(1, 23) <= sub_wire8(23); - sub_wire2(0, 0) <= sub_wire9(0); - sub_wire2(0, 1) <= sub_wire9(1); - sub_wire2(0, 2) <= sub_wire9(2); - sub_wire2(0, 3) <= sub_wire9(3); - sub_wire2(0, 4) <= sub_wire9(4); - sub_wire2(0, 5) <= sub_wire9(5); - sub_wire2(0, 6) <= sub_wire9(6); - sub_wire2(0, 7) <= sub_wire9(7); - sub_wire2(0, 8) <= sub_wire9(8); - sub_wire2(0, 9) <= sub_wire9(9); - sub_wire2(0, 10) <= sub_wire9(10); - sub_wire2(0, 11) <= sub_wire9(11); - sub_wire2(0, 12) <= sub_wire9(12); - sub_wire2(0, 13) <= sub_wire9(13); - sub_wire2(0, 14) <= sub_wire9(14); - sub_wire2(0, 15) <= sub_wire9(15); - sub_wire2(0, 16) <= sub_wire9(16); - sub_wire2(0, 17) <= sub_wire9(17); - sub_wire2(0, 18) <= sub_wire9(18); - sub_wire2(0, 19) <= sub_wire9(19); - sub_wire2(0, 20) <= sub_wire9(20); - sub_wire2(0, 21) <= sub_wire9(21); - sub_wire2(0, 22) <= sub_wire9(22); - sub_wire2(0, 23) <= sub_wire9(23); - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_pipeline => 2, - lpm_size => 8, - lpm_type => "LPM_MUX", - lpm_width => 24, - lpm_widths => 3 - ) - PORT MAP ( - clock => clock, - data => sub_wire2, - sel => sel, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL "data0x[23..0]" --- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL "data1x[23..0]" --- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL "data2x[23..0]" --- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL "data3x[23..0]" --- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL "data4x[23..0]" --- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL "data5x[23..0]" --- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL "data6x[23..0]" --- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL "data7x[23..0]" --- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]" --- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0 --- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0 --- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0 --- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0 --- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0 --- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0 --- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0 --- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0 --- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 --- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux6.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux6 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END lpm_mux6; + + +ARCHITECTURE SYN OF lpm_mux6 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (23 DOWNTO 0); + +BEGIN + sub_wire9 <= data0x(23 DOWNTO 0); + sub_wire8 <= data1x(23 DOWNTO 0); + sub_wire7 <= data2x(23 DOWNTO 0); + sub_wire6 <= data3x(23 DOWNTO 0); + sub_wire5 <= data4x(23 DOWNTO 0); + sub_wire4 <= data5x(23 DOWNTO 0); + sub_wire3 <= data6x(23 DOWNTO 0); + result <= sub_wire0(23 DOWNTO 0); + sub_wire1 <= data7x(23 DOWNTO 0); + sub_wire2(7, 0) <= sub_wire1(0); + sub_wire2(7, 1) <= sub_wire1(1); + sub_wire2(7, 2) <= sub_wire1(2); + sub_wire2(7, 3) <= sub_wire1(3); + sub_wire2(7, 4) <= sub_wire1(4); + sub_wire2(7, 5) <= sub_wire1(5); + sub_wire2(7, 6) <= sub_wire1(6); + sub_wire2(7, 7) <= sub_wire1(7); + sub_wire2(7, 8) <= sub_wire1(8); + sub_wire2(7, 9) <= sub_wire1(9); + sub_wire2(7, 10) <= sub_wire1(10); + sub_wire2(7, 11) <= sub_wire1(11); + sub_wire2(7, 12) <= sub_wire1(12); + sub_wire2(7, 13) <= sub_wire1(13); + sub_wire2(7, 14) <= sub_wire1(14); + sub_wire2(7, 15) <= sub_wire1(15); + sub_wire2(7, 16) <= sub_wire1(16); + sub_wire2(7, 17) <= sub_wire1(17); + sub_wire2(7, 18) <= sub_wire1(18); + sub_wire2(7, 19) <= sub_wire1(19); + sub_wire2(7, 20) <= sub_wire1(20); + sub_wire2(7, 21) <= sub_wire1(21); + sub_wire2(7, 22) <= sub_wire1(22); + sub_wire2(7, 23) <= sub_wire1(23); + sub_wire2(6, 0) <= sub_wire3(0); + sub_wire2(6, 1) <= sub_wire3(1); + sub_wire2(6, 2) <= sub_wire3(2); + sub_wire2(6, 3) <= sub_wire3(3); + sub_wire2(6, 4) <= sub_wire3(4); + sub_wire2(6, 5) <= sub_wire3(5); + sub_wire2(6, 6) <= sub_wire3(6); + sub_wire2(6, 7) <= sub_wire3(7); + sub_wire2(6, 8) <= sub_wire3(8); + sub_wire2(6, 9) <= sub_wire3(9); + sub_wire2(6, 10) <= sub_wire3(10); + sub_wire2(6, 11) <= sub_wire3(11); + sub_wire2(6, 12) <= sub_wire3(12); + sub_wire2(6, 13) <= sub_wire3(13); + sub_wire2(6, 14) <= sub_wire3(14); + sub_wire2(6, 15) <= sub_wire3(15); + sub_wire2(6, 16) <= sub_wire3(16); + sub_wire2(6, 17) <= sub_wire3(17); + sub_wire2(6, 18) <= sub_wire3(18); + sub_wire2(6, 19) <= sub_wire3(19); + sub_wire2(6, 20) <= sub_wire3(20); + sub_wire2(6, 21) <= sub_wire3(21); + sub_wire2(6, 22) <= sub_wire3(22); + sub_wire2(6, 23) <= sub_wire3(23); + sub_wire2(5, 0) <= sub_wire4(0); + sub_wire2(5, 1) <= sub_wire4(1); + sub_wire2(5, 2) <= sub_wire4(2); + sub_wire2(5, 3) <= sub_wire4(3); + sub_wire2(5, 4) <= sub_wire4(4); + sub_wire2(5, 5) <= sub_wire4(5); + sub_wire2(5, 6) <= sub_wire4(6); + sub_wire2(5, 7) <= sub_wire4(7); + sub_wire2(5, 8) <= sub_wire4(8); + sub_wire2(5, 9) <= sub_wire4(9); + sub_wire2(5, 10) <= sub_wire4(10); + sub_wire2(5, 11) <= sub_wire4(11); + sub_wire2(5, 12) <= sub_wire4(12); + sub_wire2(5, 13) <= sub_wire4(13); + sub_wire2(5, 14) <= sub_wire4(14); + sub_wire2(5, 15) <= sub_wire4(15); + sub_wire2(5, 16) <= sub_wire4(16); + sub_wire2(5, 17) <= sub_wire4(17); + sub_wire2(5, 18) <= sub_wire4(18); + sub_wire2(5, 19) <= sub_wire4(19); + sub_wire2(5, 20) <= sub_wire4(20); + sub_wire2(5, 21) <= sub_wire4(21); + sub_wire2(5, 22) <= sub_wire4(22); + sub_wire2(5, 23) <= sub_wire4(23); + sub_wire2(4, 0) <= sub_wire5(0); + sub_wire2(4, 1) <= sub_wire5(1); + sub_wire2(4, 2) <= sub_wire5(2); + sub_wire2(4, 3) <= sub_wire5(3); + sub_wire2(4, 4) <= sub_wire5(4); + sub_wire2(4, 5) <= sub_wire5(5); + sub_wire2(4, 6) <= sub_wire5(6); + sub_wire2(4, 7) <= sub_wire5(7); + sub_wire2(4, 8) <= sub_wire5(8); + sub_wire2(4, 9) <= sub_wire5(9); + sub_wire2(4, 10) <= sub_wire5(10); + sub_wire2(4, 11) <= sub_wire5(11); + sub_wire2(4, 12) <= sub_wire5(12); + sub_wire2(4, 13) <= sub_wire5(13); + sub_wire2(4, 14) <= sub_wire5(14); + sub_wire2(4, 15) <= sub_wire5(15); + sub_wire2(4, 16) <= sub_wire5(16); + sub_wire2(4, 17) <= sub_wire5(17); + sub_wire2(4, 18) <= sub_wire5(18); + sub_wire2(4, 19) <= sub_wire5(19); + sub_wire2(4, 20) <= sub_wire5(20); + sub_wire2(4, 21) <= sub_wire5(21); + sub_wire2(4, 22) <= sub_wire5(22); + sub_wire2(4, 23) <= sub_wire5(23); + sub_wire2(3, 0) <= sub_wire6(0); + sub_wire2(3, 1) <= sub_wire6(1); + sub_wire2(3, 2) <= sub_wire6(2); + sub_wire2(3, 3) <= sub_wire6(3); + sub_wire2(3, 4) <= sub_wire6(4); + sub_wire2(3, 5) <= sub_wire6(5); + sub_wire2(3, 6) <= sub_wire6(6); + sub_wire2(3, 7) <= sub_wire6(7); + sub_wire2(3, 8) <= sub_wire6(8); + sub_wire2(3, 9) <= sub_wire6(9); + sub_wire2(3, 10) <= sub_wire6(10); + sub_wire2(3, 11) <= sub_wire6(11); + sub_wire2(3, 12) <= sub_wire6(12); + sub_wire2(3, 13) <= sub_wire6(13); + sub_wire2(3, 14) <= sub_wire6(14); + sub_wire2(3, 15) <= sub_wire6(15); + sub_wire2(3, 16) <= sub_wire6(16); + sub_wire2(3, 17) <= sub_wire6(17); + sub_wire2(3, 18) <= sub_wire6(18); + sub_wire2(3, 19) <= sub_wire6(19); + sub_wire2(3, 20) <= sub_wire6(20); + sub_wire2(3, 21) <= sub_wire6(21); + sub_wire2(3, 22) <= sub_wire6(22); + sub_wire2(3, 23) <= sub_wire6(23); + sub_wire2(2, 0) <= sub_wire7(0); + sub_wire2(2, 1) <= sub_wire7(1); + sub_wire2(2, 2) <= sub_wire7(2); + sub_wire2(2, 3) <= sub_wire7(3); + sub_wire2(2, 4) <= sub_wire7(4); + sub_wire2(2, 5) <= sub_wire7(5); + sub_wire2(2, 6) <= sub_wire7(6); + sub_wire2(2, 7) <= sub_wire7(7); + sub_wire2(2, 8) <= sub_wire7(8); + sub_wire2(2, 9) <= sub_wire7(9); + sub_wire2(2, 10) <= sub_wire7(10); + sub_wire2(2, 11) <= sub_wire7(11); + sub_wire2(2, 12) <= sub_wire7(12); + sub_wire2(2, 13) <= sub_wire7(13); + sub_wire2(2, 14) <= sub_wire7(14); + sub_wire2(2, 15) <= sub_wire7(15); + sub_wire2(2, 16) <= sub_wire7(16); + sub_wire2(2, 17) <= sub_wire7(17); + sub_wire2(2, 18) <= sub_wire7(18); + sub_wire2(2, 19) <= sub_wire7(19); + sub_wire2(2, 20) <= sub_wire7(20); + sub_wire2(2, 21) <= sub_wire7(21); + sub_wire2(2, 22) <= sub_wire7(22); + sub_wire2(2, 23) <= sub_wire7(23); + sub_wire2(1, 0) <= sub_wire8(0); + sub_wire2(1, 1) <= sub_wire8(1); + sub_wire2(1, 2) <= sub_wire8(2); + sub_wire2(1, 3) <= sub_wire8(3); + sub_wire2(1, 4) <= sub_wire8(4); + sub_wire2(1, 5) <= sub_wire8(5); + sub_wire2(1, 6) <= sub_wire8(6); + sub_wire2(1, 7) <= sub_wire8(7); + sub_wire2(1, 8) <= sub_wire8(8); + sub_wire2(1, 9) <= sub_wire8(9); + sub_wire2(1, 10) <= sub_wire8(10); + sub_wire2(1, 11) <= sub_wire8(11); + sub_wire2(1, 12) <= sub_wire8(12); + sub_wire2(1, 13) <= sub_wire8(13); + sub_wire2(1, 14) <= sub_wire8(14); + sub_wire2(1, 15) <= sub_wire8(15); + sub_wire2(1, 16) <= sub_wire8(16); + sub_wire2(1, 17) <= sub_wire8(17); + sub_wire2(1, 18) <= sub_wire8(18); + sub_wire2(1, 19) <= sub_wire8(19); + sub_wire2(1, 20) <= sub_wire8(20); + sub_wire2(1, 21) <= sub_wire8(21); + sub_wire2(1, 22) <= sub_wire8(22); + sub_wire2(1, 23) <= sub_wire8(23); + sub_wire2(0, 0) <= sub_wire9(0); + sub_wire2(0, 1) <= sub_wire9(1); + sub_wire2(0, 2) <= sub_wire9(2); + sub_wire2(0, 3) <= sub_wire9(3); + sub_wire2(0, 4) <= sub_wire9(4); + sub_wire2(0, 5) <= sub_wire9(5); + sub_wire2(0, 6) <= sub_wire9(6); + sub_wire2(0, 7) <= sub_wire9(7); + sub_wire2(0, 8) <= sub_wire9(8); + sub_wire2(0, 9) <= sub_wire9(9); + sub_wire2(0, 10) <= sub_wire9(10); + sub_wire2(0, 11) <= sub_wire9(11); + sub_wire2(0, 12) <= sub_wire9(12); + sub_wire2(0, 13) <= sub_wire9(13); + sub_wire2(0, 14) <= sub_wire9(14); + sub_wire2(0, 15) <= sub_wire9(15); + sub_wire2(0, 16) <= sub_wire9(16); + sub_wire2(0, 17) <= sub_wire9(17); + sub_wire2(0, 18) <= sub_wire9(18); + sub_wire2(0, 19) <= sub_wire9(19); + sub_wire2(0, 20) <= sub_wire9(20); + sub_wire2(0, 21) <= sub_wire9(21); + sub_wire2(0, 22) <= sub_wire9(22); + sub_wire2(0, 23) <= sub_wire9(23); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 2, + lpm_size => 8, + lpm_type => "LPM_MUX", + lpm_width => 24, + lpm_widths => 3 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0] +-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0] +-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0] +-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0] +-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0] +-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0] +-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0] +-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0] +-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0] +-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0 +-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_muxDZ.bsf b/Video/lpm_muxDZ.bsf index ddcbbe3..f4f1c7d 100644 --- a/Video/lpm_muxDZ.bsf +++ b/Video/lpm_muxDZ.bsf @@ -1,84 +1,76 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 112) - (text "lpm_muxDZ" (rect 37 0 123 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 97 26 108)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data1x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data1x[127..0]" (rect 4 27 73 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data0x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data0x[127..0]" (rect 4 43 73 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 4 59 29 71)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)) - ) - (port - (pt 0 88) - (input) - (text "clken" (rect 0 0 30 13)(font "Arial" (font_size 8))) - (text "clken" (rect 4 75 29 87)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)) - ) - (port - (pt 72 112) - (input) - (text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical)) - (text "sel" (rect 66 81 78 95)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 112)(pt 72 100)) - ) - (port - (pt 144 64) - (output) - (text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "result[127..0]" (rect 79 51 142 63)(font "Arial" (font_size 8))) - (line (pt 144 64)(pt 80 64)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 104)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 104)(pt 80 96)) - (line (pt 80 32)(pt 80 96)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 114)) - (line (pt 0 114)(pt 146 114)) - (line (pt 0 0)(pt 0 114)) - (line (pt 64 66)(pt 70 72)) - (line (pt 70 72)(pt 64 78)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 168 112) + (text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 80 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 80 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 80 72)(line_width 1)) + ) + (port + (pt 0 88) + (input) + (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 80 88)(line_width 1)) + ) + (port + (pt 88 112) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8))) + (line (pt 88 112)(pt 88 100)(line_width 1)) + ) + (port + (pt 168 64) + (output) + (text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8))) + (line (pt 168 64)(pt 96 64)(line_width 3)) + ) + (drawing + (line (pt 80 24)(pt 80 104)(line_width 1)) + (line (pt 96 32)(pt 96 96)(line_width 1)) + (line (pt 80 24)(pt 96 32)(line_width 1)) + (line (pt 80 104)(pt 96 96)(line_width 1)) + (line (pt 80 66)(pt 86 72)(line_width 1)) + (line (pt 86 72)(pt 80 78)(line_width 1)) + ) +) diff --git a/Video/lpm_muxDZ.cmp b/Video/lpm_muxDZ.cmp index 7a7102c..f177216 100644 --- a/Video/lpm_muxDZ.cmp +++ b/Video/lpm_muxDZ.cmp @@ -1,26 +1,26 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_muxDZ - PORT - ( - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - sel : IN STD_LOGIC ; - result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxDZ + PORT + ( + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_muxDZ.qip b/Video/lpm_muxDZ.qip index 34db4e2..34ffc75 100644 --- a/Video/lpm_muxDZ.qip +++ b/Video/lpm_muxDZ.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"] diff --git a/Video/lpm_muxDZ.vhd b/Video/lpm_muxDZ.vhd index c63d3a1..e9bd32e 100644 --- a/Video/lpm_muxDZ.vhd +++ b/Video/lpm_muxDZ.vhd @@ -1,378 +1,377 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_muxDZ.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_muxDZ IS - PORT - ( - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC ; - data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - sel : IN STD_LOGIC ; - result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) - ); -END lpm_muxDZ; - - -ARCHITECTURE SYN OF lpm_muxdz IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - -BEGIN - sub_wire3 <= data0x(127 DOWNTO 0); - result <= sub_wire0(127 DOWNTO 0); - sub_wire1 <= data1x(127 DOWNTO 0); - sub_wire2(1, 0) <= sub_wire1(0); - sub_wire2(1, 1) <= sub_wire1(1); - sub_wire2(1, 2) <= sub_wire1(2); - sub_wire2(1, 3) <= sub_wire1(3); - sub_wire2(1, 4) <= sub_wire1(4); - sub_wire2(1, 5) <= sub_wire1(5); - sub_wire2(1, 6) <= sub_wire1(6); - sub_wire2(1, 7) <= sub_wire1(7); - sub_wire2(1, 8) <= sub_wire1(8); - sub_wire2(1, 9) <= sub_wire1(9); - sub_wire2(1, 10) <= sub_wire1(10); - sub_wire2(1, 11) <= sub_wire1(11); - sub_wire2(1, 12) <= sub_wire1(12); - sub_wire2(1, 13) <= sub_wire1(13); - sub_wire2(1, 14) <= sub_wire1(14); - sub_wire2(1, 15) <= sub_wire1(15); - sub_wire2(1, 16) <= sub_wire1(16); - sub_wire2(1, 17) <= sub_wire1(17); - sub_wire2(1, 18) <= sub_wire1(18); - sub_wire2(1, 19) <= sub_wire1(19); - sub_wire2(1, 20) <= sub_wire1(20); - sub_wire2(1, 21) <= sub_wire1(21); - sub_wire2(1, 22) <= sub_wire1(22); - sub_wire2(1, 23) <= sub_wire1(23); - sub_wire2(1, 24) <= sub_wire1(24); - sub_wire2(1, 25) <= sub_wire1(25); - sub_wire2(1, 26) <= sub_wire1(26); - sub_wire2(1, 27) <= sub_wire1(27); - sub_wire2(1, 28) <= sub_wire1(28); - sub_wire2(1, 29) <= sub_wire1(29); - sub_wire2(1, 30) <= sub_wire1(30); - sub_wire2(1, 31) <= sub_wire1(31); - sub_wire2(1, 32) <= sub_wire1(32); - sub_wire2(1, 33) <= sub_wire1(33); - sub_wire2(1, 34) <= sub_wire1(34); - sub_wire2(1, 35) <= sub_wire1(35); - sub_wire2(1, 36) <= sub_wire1(36); - sub_wire2(1, 37) <= sub_wire1(37); - sub_wire2(1, 38) <= sub_wire1(38); - sub_wire2(1, 39) <= sub_wire1(39); - sub_wire2(1, 40) <= sub_wire1(40); - sub_wire2(1, 41) <= sub_wire1(41); - sub_wire2(1, 42) <= sub_wire1(42); - sub_wire2(1, 43) <= sub_wire1(43); - sub_wire2(1, 44) <= sub_wire1(44); - sub_wire2(1, 45) <= sub_wire1(45); - sub_wire2(1, 46) <= sub_wire1(46); - sub_wire2(1, 47) <= sub_wire1(47); - sub_wire2(1, 48) <= sub_wire1(48); - sub_wire2(1, 49) <= sub_wire1(49); - sub_wire2(1, 50) <= sub_wire1(50); - sub_wire2(1, 51) <= sub_wire1(51); - sub_wire2(1, 52) <= sub_wire1(52); - sub_wire2(1, 53) <= sub_wire1(53); - sub_wire2(1, 54) <= sub_wire1(54); - sub_wire2(1, 55) <= sub_wire1(55); - sub_wire2(1, 56) <= sub_wire1(56); - sub_wire2(1, 57) <= sub_wire1(57); - sub_wire2(1, 58) <= sub_wire1(58); - sub_wire2(1, 59) <= sub_wire1(59); - sub_wire2(1, 60) <= sub_wire1(60); - sub_wire2(1, 61) <= sub_wire1(61); - sub_wire2(1, 62) <= sub_wire1(62); - sub_wire2(1, 63) <= sub_wire1(63); - sub_wire2(1, 64) <= sub_wire1(64); - sub_wire2(1, 65) <= sub_wire1(65); - sub_wire2(1, 66) <= sub_wire1(66); - sub_wire2(1, 67) <= sub_wire1(67); - sub_wire2(1, 68) <= sub_wire1(68); - sub_wire2(1, 69) <= sub_wire1(69); - sub_wire2(1, 70) <= sub_wire1(70); - sub_wire2(1, 71) <= sub_wire1(71); - sub_wire2(1, 72) <= sub_wire1(72); - sub_wire2(1, 73) <= sub_wire1(73); - sub_wire2(1, 74) <= sub_wire1(74); - sub_wire2(1, 75) <= sub_wire1(75); - sub_wire2(1, 76) <= sub_wire1(76); - sub_wire2(1, 77) <= sub_wire1(77); - sub_wire2(1, 78) <= sub_wire1(78); - sub_wire2(1, 79) <= sub_wire1(79); - sub_wire2(1, 80) <= sub_wire1(80); - sub_wire2(1, 81) <= sub_wire1(81); - sub_wire2(1, 82) <= sub_wire1(82); - sub_wire2(1, 83) <= sub_wire1(83); - sub_wire2(1, 84) <= sub_wire1(84); - sub_wire2(1, 85) <= sub_wire1(85); - sub_wire2(1, 86) <= sub_wire1(86); - sub_wire2(1, 87) <= sub_wire1(87); - sub_wire2(1, 88) <= sub_wire1(88); - sub_wire2(1, 89) <= sub_wire1(89); - sub_wire2(1, 90) <= sub_wire1(90); - sub_wire2(1, 91) <= sub_wire1(91); - sub_wire2(1, 92) <= sub_wire1(92); - sub_wire2(1, 93) <= sub_wire1(93); - sub_wire2(1, 94) <= sub_wire1(94); - sub_wire2(1, 95) <= sub_wire1(95); - sub_wire2(1, 96) <= sub_wire1(96); - sub_wire2(1, 97) <= sub_wire1(97); - sub_wire2(1, 98) <= sub_wire1(98); - sub_wire2(1, 99) <= sub_wire1(99); - sub_wire2(1, 100) <= sub_wire1(100); - sub_wire2(1, 101) <= sub_wire1(101); - sub_wire2(1, 102) <= sub_wire1(102); - sub_wire2(1, 103) <= sub_wire1(103); - sub_wire2(1, 104) <= sub_wire1(104); - sub_wire2(1, 105) <= sub_wire1(105); - sub_wire2(1, 106) <= sub_wire1(106); - sub_wire2(1, 107) <= sub_wire1(107); - sub_wire2(1, 108) <= sub_wire1(108); - sub_wire2(1, 109) <= sub_wire1(109); - sub_wire2(1, 110) <= sub_wire1(110); - sub_wire2(1, 111) <= sub_wire1(111); - sub_wire2(1, 112) <= sub_wire1(112); - sub_wire2(1, 113) <= sub_wire1(113); - sub_wire2(1, 114) <= sub_wire1(114); - sub_wire2(1, 115) <= sub_wire1(115); - sub_wire2(1, 116) <= sub_wire1(116); - sub_wire2(1, 117) <= sub_wire1(117); - sub_wire2(1, 118) <= sub_wire1(118); - sub_wire2(1, 119) <= sub_wire1(119); - sub_wire2(1, 120) <= sub_wire1(120); - sub_wire2(1, 121) <= sub_wire1(121); - sub_wire2(1, 122) <= sub_wire1(122); - sub_wire2(1, 123) <= sub_wire1(123); - sub_wire2(1, 124) <= sub_wire1(124); - sub_wire2(1, 125) <= sub_wire1(125); - sub_wire2(1, 126) <= sub_wire1(126); - sub_wire2(1, 127) <= sub_wire1(127); - sub_wire2(0, 0) <= sub_wire3(0); - sub_wire2(0, 1) <= sub_wire3(1); - sub_wire2(0, 2) <= sub_wire3(2); - sub_wire2(0, 3) <= sub_wire3(3); - sub_wire2(0, 4) <= sub_wire3(4); - sub_wire2(0, 5) <= sub_wire3(5); - sub_wire2(0, 6) <= sub_wire3(6); - sub_wire2(0, 7) <= sub_wire3(7); - sub_wire2(0, 8) <= sub_wire3(8); - sub_wire2(0, 9) <= sub_wire3(9); - sub_wire2(0, 10) <= sub_wire3(10); - sub_wire2(0, 11) <= sub_wire3(11); - sub_wire2(0, 12) <= sub_wire3(12); - sub_wire2(0, 13) <= sub_wire3(13); - sub_wire2(0, 14) <= sub_wire3(14); - sub_wire2(0, 15) <= sub_wire3(15); - sub_wire2(0, 16) <= sub_wire3(16); - sub_wire2(0, 17) <= sub_wire3(17); - sub_wire2(0, 18) <= sub_wire3(18); - sub_wire2(0, 19) <= sub_wire3(19); - sub_wire2(0, 20) <= sub_wire3(20); - sub_wire2(0, 21) <= sub_wire3(21); - sub_wire2(0, 22) <= sub_wire3(22); - sub_wire2(0, 23) <= sub_wire3(23); - sub_wire2(0, 24) <= sub_wire3(24); - sub_wire2(0, 25) <= sub_wire3(25); - sub_wire2(0, 26) <= sub_wire3(26); - sub_wire2(0, 27) <= sub_wire3(27); - sub_wire2(0, 28) <= sub_wire3(28); - sub_wire2(0, 29) <= sub_wire3(29); - sub_wire2(0, 30) <= sub_wire3(30); - sub_wire2(0, 31) <= sub_wire3(31); - sub_wire2(0, 32) <= sub_wire3(32); - sub_wire2(0, 33) <= sub_wire3(33); - sub_wire2(0, 34) <= sub_wire3(34); - sub_wire2(0, 35) <= sub_wire3(35); - sub_wire2(0, 36) <= sub_wire3(36); - sub_wire2(0, 37) <= sub_wire3(37); - sub_wire2(0, 38) <= sub_wire3(38); - sub_wire2(0, 39) <= sub_wire3(39); - sub_wire2(0, 40) <= sub_wire3(40); - sub_wire2(0, 41) <= sub_wire3(41); - sub_wire2(0, 42) <= sub_wire3(42); - sub_wire2(0, 43) <= sub_wire3(43); - sub_wire2(0, 44) <= sub_wire3(44); - sub_wire2(0, 45) <= sub_wire3(45); - sub_wire2(0, 46) <= sub_wire3(46); - sub_wire2(0, 47) <= sub_wire3(47); - sub_wire2(0, 48) <= sub_wire3(48); - sub_wire2(0, 49) <= sub_wire3(49); - sub_wire2(0, 50) <= sub_wire3(50); - sub_wire2(0, 51) <= sub_wire3(51); - sub_wire2(0, 52) <= sub_wire3(52); - sub_wire2(0, 53) <= sub_wire3(53); - sub_wire2(0, 54) <= sub_wire3(54); - sub_wire2(0, 55) <= sub_wire3(55); - sub_wire2(0, 56) <= sub_wire3(56); - sub_wire2(0, 57) <= sub_wire3(57); - sub_wire2(0, 58) <= sub_wire3(58); - sub_wire2(0, 59) <= sub_wire3(59); - sub_wire2(0, 60) <= sub_wire3(60); - sub_wire2(0, 61) <= sub_wire3(61); - sub_wire2(0, 62) <= sub_wire3(62); - sub_wire2(0, 63) <= sub_wire3(63); - sub_wire2(0, 64) <= sub_wire3(64); - sub_wire2(0, 65) <= sub_wire3(65); - sub_wire2(0, 66) <= sub_wire3(66); - sub_wire2(0, 67) <= sub_wire3(67); - sub_wire2(0, 68) <= sub_wire3(68); - sub_wire2(0, 69) <= sub_wire3(69); - sub_wire2(0, 70) <= sub_wire3(70); - sub_wire2(0, 71) <= sub_wire3(71); - sub_wire2(0, 72) <= sub_wire3(72); - sub_wire2(0, 73) <= sub_wire3(73); - sub_wire2(0, 74) <= sub_wire3(74); - sub_wire2(0, 75) <= sub_wire3(75); - sub_wire2(0, 76) <= sub_wire3(76); - sub_wire2(0, 77) <= sub_wire3(77); - sub_wire2(0, 78) <= sub_wire3(78); - sub_wire2(0, 79) <= sub_wire3(79); - sub_wire2(0, 80) <= sub_wire3(80); - sub_wire2(0, 81) <= sub_wire3(81); - sub_wire2(0, 82) <= sub_wire3(82); - sub_wire2(0, 83) <= sub_wire3(83); - sub_wire2(0, 84) <= sub_wire3(84); - sub_wire2(0, 85) <= sub_wire3(85); - sub_wire2(0, 86) <= sub_wire3(86); - sub_wire2(0, 87) <= sub_wire3(87); - sub_wire2(0, 88) <= sub_wire3(88); - sub_wire2(0, 89) <= sub_wire3(89); - sub_wire2(0, 90) <= sub_wire3(90); - sub_wire2(0, 91) <= sub_wire3(91); - sub_wire2(0, 92) <= sub_wire3(92); - sub_wire2(0, 93) <= sub_wire3(93); - sub_wire2(0, 94) <= sub_wire3(94); - sub_wire2(0, 95) <= sub_wire3(95); - sub_wire2(0, 96) <= sub_wire3(96); - sub_wire2(0, 97) <= sub_wire3(97); - sub_wire2(0, 98) <= sub_wire3(98); - sub_wire2(0, 99) <= sub_wire3(99); - sub_wire2(0, 100) <= sub_wire3(100); - sub_wire2(0, 101) <= sub_wire3(101); - sub_wire2(0, 102) <= sub_wire3(102); - sub_wire2(0, 103) <= sub_wire3(103); - sub_wire2(0, 104) <= sub_wire3(104); - sub_wire2(0, 105) <= sub_wire3(105); - sub_wire2(0, 106) <= sub_wire3(106); - sub_wire2(0, 107) <= sub_wire3(107); - sub_wire2(0, 108) <= sub_wire3(108); - sub_wire2(0, 109) <= sub_wire3(109); - sub_wire2(0, 110) <= sub_wire3(110); - sub_wire2(0, 111) <= sub_wire3(111); - sub_wire2(0, 112) <= sub_wire3(112); - sub_wire2(0, 113) <= sub_wire3(113); - sub_wire2(0, 114) <= sub_wire3(114); - sub_wire2(0, 115) <= sub_wire3(115); - sub_wire2(0, 116) <= sub_wire3(116); - sub_wire2(0, 117) <= sub_wire3(117); - sub_wire2(0, 118) <= sub_wire3(118); - sub_wire2(0, 119) <= sub_wire3(119); - sub_wire2(0, 120) <= sub_wire3(120); - sub_wire2(0, 121) <= sub_wire3(121); - sub_wire2(0, 122) <= sub_wire3(122); - sub_wire2(0, 123) <= sub_wire3(123); - sub_wire2(0, 124) <= sub_wire3(124); - sub_wire2(0, 125) <= sub_wire3(125); - sub_wire2(0, 126) <= sub_wire3(126); - sub_wire2(0, 127) <= sub_wire3(127); - sub_wire4 <= sel; - sub_wire5(0) <= sub_wire4; - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_pipeline => 1, - lpm_size => 2, - lpm_type => "LPM_MUX", - lpm_width => 128, - lpm_widths => 1 - ) - PORT MAP ( - clock => clock, - data => sub_wire2, - sel => sub_wire5, - clken => clken, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" --- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]" --- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]" --- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]" --- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel" --- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 --- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 --- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxDZ.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxDZ IS + PORT + ( + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_muxDZ; + + +ARCHITECTURE SYN OF lpm_muxdz IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(127 DOWNTO 0); + result <= sub_wire0(127 DOWNTO 0); + sub_wire1 <= sel; + sub_wire2(0) <= sub_wire1; + sub_wire3 <= data1x(127 DOWNTO 0); + sub_wire4(1, 0) <= sub_wire3(0); + sub_wire4(1, 1) <= sub_wire3(1); + sub_wire4(1, 2) <= sub_wire3(2); + sub_wire4(1, 3) <= sub_wire3(3); + sub_wire4(1, 4) <= sub_wire3(4); + sub_wire4(1, 5) <= sub_wire3(5); + sub_wire4(1, 6) <= sub_wire3(6); + sub_wire4(1, 7) <= sub_wire3(7); + sub_wire4(1, 8) <= sub_wire3(8); + sub_wire4(1, 9) <= sub_wire3(9); + sub_wire4(1, 10) <= sub_wire3(10); + sub_wire4(1, 11) <= sub_wire3(11); + sub_wire4(1, 12) <= sub_wire3(12); + sub_wire4(1, 13) <= sub_wire3(13); + sub_wire4(1, 14) <= sub_wire3(14); + sub_wire4(1, 15) <= sub_wire3(15); + sub_wire4(1, 16) <= sub_wire3(16); + sub_wire4(1, 17) <= sub_wire3(17); + sub_wire4(1, 18) <= sub_wire3(18); + sub_wire4(1, 19) <= sub_wire3(19); + sub_wire4(1, 20) <= sub_wire3(20); + sub_wire4(1, 21) <= sub_wire3(21); + sub_wire4(1, 22) <= sub_wire3(22); + sub_wire4(1, 23) <= sub_wire3(23); + sub_wire4(1, 24) <= sub_wire3(24); + sub_wire4(1, 25) <= sub_wire3(25); + sub_wire4(1, 26) <= sub_wire3(26); + sub_wire4(1, 27) <= sub_wire3(27); + sub_wire4(1, 28) <= sub_wire3(28); + sub_wire4(1, 29) <= sub_wire3(29); + sub_wire4(1, 30) <= sub_wire3(30); + sub_wire4(1, 31) <= sub_wire3(31); + sub_wire4(1, 32) <= sub_wire3(32); + sub_wire4(1, 33) <= sub_wire3(33); + sub_wire4(1, 34) <= sub_wire3(34); + sub_wire4(1, 35) <= sub_wire3(35); + sub_wire4(1, 36) <= sub_wire3(36); + sub_wire4(1, 37) <= sub_wire3(37); + sub_wire4(1, 38) <= sub_wire3(38); + sub_wire4(1, 39) <= sub_wire3(39); + sub_wire4(1, 40) <= sub_wire3(40); + sub_wire4(1, 41) <= sub_wire3(41); + sub_wire4(1, 42) <= sub_wire3(42); + sub_wire4(1, 43) <= sub_wire3(43); + sub_wire4(1, 44) <= sub_wire3(44); + sub_wire4(1, 45) <= sub_wire3(45); + sub_wire4(1, 46) <= sub_wire3(46); + sub_wire4(1, 47) <= sub_wire3(47); + sub_wire4(1, 48) <= sub_wire3(48); + sub_wire4(1, 49) <= sub_wire3(49); + sub_wire4(1, 50) <= sub_wire3(50); + sub_wire4(1, 51) <= sub_wire3(51); + sub_wire4(1, 52) <= sub_wire3(52); + sub_wire4(1, 53) <= sub_wire3(53); + sub_wire4(1, 54) <= sub_wire3(54); + sub_wire4(1, 55) <= sub_wire3(55); + sub_wire4(1, 56) <= sub_wire3(56); + sub_wire4(1, 57) <= sub_wire3(57); + sub_wire4(1, 58) <= sub_wire3(58); + sub_wire4(1, 59) <= sub_wire3(59); + sub_wire4(1, 60) <= sub_wire3(60); + sub_wire4(1, 61) <= sub_wire3(61); + sub_wire4(1, 62) <= sub_wire3(62); + sub_wire4(1, 63) <= sub_wire3(63); + sub_wire4(1, 64) <= sub_wire3(64); + sub_wire4(1, 65) <= sub_wire3(65); + sub_wire4(1, 66) <= sub_wire3(66); + sub_wire4(1, 67) <= sub_wire3(67); + sub_wire4(1, 68) <= sub_wire3(68); + sub_wire4(1, 69) <= sub_wire3(69); + sub_wire4(1, 70) <= sub_wire3(70); + sub_wire4(1, 71) <= sub_wire3(71); + sub_wire4(1, 72) <= sub_wire3(72); + sub_wire4(1, 73) <= sub_wire3(73); + sub_wire4(1, 74) <= sub_wire3(74); + sub_wire4(1, 75) <= sub_wire3(75); + sub_wire4(1, 76) <= sub_wire3(76); + sub_wire4(1, 77) <= sub_wire3(77); + sub_wire4(1, 78) <= sub_wire3(78); + sub_wire4(1, 79) <= sub_wire3(79); + sub_wire4(1, 80) <= sub_wire3(80); + sub_wire4(1, 81) <= sub_wire3(81); + sub_wire4(1, 82) <= sub_wire3(82); + sub_wire4(1, 83) <= sub_wire3(83); + sub_wire4(1, 84) <= sub_wire3(84); + sub_wire4(1, 85) <= sub_wire3(85); + sub_wire4(1, 86) <= sub_wire3(86); + sub_wire4(1, 87) <= sub_wire3(87); + sub_wire4(1, 88) <= sub_wire3(88); + sub_wire4(1, 89) <= sub_wire3(89); + sub_wire4(1, 90) <= sub_wire3(90); + sub_wire4(1, 91) <= sub_wire3(91); + sub_wire4(1, 92) <= sub_wire3(92); + sub_wire4(1, 93) <= sub_wire3(93); + sub_wire4(1, 94) <= sub_wire3(94); + sub_wire4(1, 95) <= sub_wire3(95); + sub_wire4(1, 96) <= sub_wire3(96); + sub_wire4(1, 97) <= sub_wire3(97); + sub_wire4(1, 98) <= sub_wire3(98); + sub_wire4(1, 99) <= sub_wire3(99); + sub_wire4(1, 100) <= sub_wire3(100); + sub_wire4(1, 101) <= sub_wire3(101); + sub_wire4(1, 102) <= sub_wire3(102); + sub_wire4(1, 103) <= sub_wire3(103); + sub_wire4(1, 104) <= sub_wire3(104); + sub_wire4(1, 105) <= sub_wire3(105); + sub_wire4(1, 106) <= sub_wire3(106); + sub_wire4(1, 107) <= sub_wire3(107); + sub_wire4(1, 108) <= sub_wire3(108); + sub_wire4(1, 109) <= sub_wire3(109); + sub_wire4(1, 110) <= sub_wire3(110); + sub_wire4(1, 111) <= sub_wire3(111); + sub_wire4(1, 112) <= sub_wire3(112); + sub_wire4(1, 113) <= sub_wire3(113); + sub_wire4(1, 114) <= sub_wire3(114); + sub_wire4(1, 115) <= sub_wire3(115); + sub_wire4(1, 116) <= sub_wire3(116); + sub_wire4(1, 117) <= sub_wire3(117); + sub_wire4(1, 118) <= sub_wire3(118); + sub_wire4(1, 119) <= sub_wire3(119); + sub_wire4(1, 120) <= sub_wire3(120); + sub_wire4(1, 121) <= sub_wire3(121); + sub_wire4(1, 122) <= sub_wire3(122); + sub_wire4(1, 123) <= sub_wire3(123); + sub_wire4(1, 124) <= sub_wire3(124); + sub_wire4(1, 125) <= sub_wire3(125); + sub_wire4(1, 126) <= sub_wire3(126); + sub_wire4(1, 127) <= sub_wire3(127); + sub_wire4(0, 0) <= sub_wire5(0); + sub_wire4(0, 1) <= sub_wire5(1); + sub_wire4(0, 2) <= sub_wire5(2); + sub_wire4(0, 3) <= sub_wire5(3); + sub_wire4(0, 4) <= sub_wire5(4); + sub_wire4(0, 5) <= sub_wire5(5); + sub_wire4(0, 6) <= sub_wire5(6); + sub_wire4(0, 7) <= sub_wire5(7); + sub_wire4(0, 8) <= sub_wire5(8); + sub_wire4(0, 9) <= sub_wire5(9); + sub_wire4(0, 10) <= sub_wire5(10); + sub_wire4(0, 11) <= sub_wire5(11); + sub_wire4(0, 12) <= sub_wire5(12); + sub_wire4(0, 13) <= sub_wire5(13); + sub_wire4(0, 14) <= sub_wire5(14); + sub_wire4(0, 15) <= sub_wire5(15); + sub_wire4(0, 16) <= sub_wire5(16); + sub_wire4(0, 17) <= sub_wire5(17); + sub_wire4(0, 18) <= sub_wire5(18); + sub_wire4(0, 19) <= sub_wire5(19); + sub_wire4(0, 20) <= sub_wire5(20); + sub_wire4(0, 21) <= sub_wire5(21); + sub_wire4(0, 22) <= sub_wire5(22); + sub_wire4(0, 23) <= sub_wire5(23); + sub_wire4(0, 24) <= sub_wire5(24); + sub_wire4(0, 25) <= sub_wire5(25); + sub_wire4(0, 26) <= sub_wire5(26); + sub_wire4(0, 27) <= sub_wire5(27); + sub_wire4(0, 28) <= sub_wire5(28); + sub_wire4(0, 29) <= sub_wire5(29); + sub_wire4(0, 30) <= sub_wire5(30); + sub_wire4(0, 31) <= sub_wire5(31); + sub_wire4(0, 32) <= sub_wire5(32); + sub_wire4(0, 33) <= sub_wire5(33); + sub_wire4(0, 34) <= sub_wire5(34); + sub_wire4(0, 35) <= sub_wire5(35); + sub_wire4(0, 36) <= sub_wire5(36); + sub_wire4(0, 37) <= sub_wire5(37); + sub_wire4(0, 38) <= sub_wire5(38); + sub_wire4(0, 39) <= sub_wire5(39); + sub_wire4(0, 40) <= sub_wire5(40); + sub_wire4(0, 41) <= sub_wire5(41); + sub_wire4(0, 42) <= sub_wire5(42); + sub_wire4(0, 43) <= sub_wire5(43); + sub_wire4(0, 44) <= sub_wire5(44); + sub_wire4(0, 45) <= sub_wire5(45); + sub_wire4(0, 46) <= sub_wire5(46); + sub_wire4(0, 47) <= sub_wire5(47); + sub_wire4(0, 48) <= sub_wire5(48); + sub_wire4(0, 49) <= sub_wire5(49); + sub_wire4(0, 50) <= sub_wire5(50); + sub_wire4(0, 51) <= sub_wire5(51); + sub_wire4(0, 52) <= sub_wire5(52); + sub_wire4(0, 53) <= sub_wire5(53); + sub_wire4(0, 54) <= sub_wire5(54); + sub_wire4(0, 55) <= sub_wire5(55); + sub_wire4(0, 56) <= sub_wire5(56); + sub_wire4(0, 57) <= sub_wire5(57); + sub_wire4(0, 58) <= sub_wire5(58); + sub_wire4(0, 59) <= sub_wire5(59); + sub_wire4(0, 60) <= sub_wire5(60); + sub_wire4(0, 61) <= sub_wire5(61); + sub_wire4(0, 62) <= sub_wire5(62); + sub_wire4(0, 63) <= sub_wire5(63); + sub_wire4(0, 64) <= sub_wire5(64); + sub_wire4(0, 65) <= sub_wire5(65); + sub_wire4(0, 66) <= sub_wire5(66); + sub_wire4(0, 67) <= sub_wire5(67); + sub_wire4(0, 68) <= sub_wire5(68); + sub_wire4(0, 69) <= sub_wire5(69); + sub_wire4(0, 70) <= sub_wire5(70); + sub_wire4(0, 71) <= sub_wire5(71); + sub_wire4(0, 72) <= sub_wire5(72); + sub_wire4(0, 73) <= sub_wire5(73); + sub_wire4(0, 74) <= sub_wire5(74); + sub_wire4(0, 75) <= sub_wire5(75); + sub_wire4(0, 76) <= sub_wire5(76); + sub_wire4(0, 77) <= sub_wire5(77); + sub_wire4(0, 78) <= sub_wire5(78); + sub_wire4(0, 79) <= sub_wire5(79); + sub_wire4(0, 80) <= sub_wire5(80); + sub_wire4(0, 81) <= sub_wire5(81); + sub_wire4(0, 82) <= sub_wire5(82); + sub_wire4(0, 83) <= sub_wire5(83); + sub_wire4(0, 84) <= sub_wire5(84); + sub_wire4(0, 85) <= sub_wire5(85); + sub_wire4(0, 86) <= sub_wire5(86); + sub_wire4(0, 87) <= sub_wire5(87); + sub_wire4(0, 88) <= sub_wire5(88); + sub_wire4(0, 89) <= sub_wire5(89); + sub_wire4(0, 90) <= sub_wire5(90); + sub_wire4(0, 91) <= sub_wire5(91); + sub_wire4(0, 92) <= sub_wire5(92); + sub_wire4(0, 93) <= sub_wire5(93); + sub_wire4(0, 94) <= sub_wire5(94); + sub_wire4(0, 95) <= sub_wire5(95); + sub_wire4(0, 96) <= sub_wire5(96); + sub_wire4(0, 97) <= sub_wire5(97); + sub_wire4(0, 98) <= sub_wire5(98); + sub_wire4(0, 99) <= sub_wire5(99); + sub_wire4(0, 100) <= sub_wire5(100); + sub_wire4(0, 101) <= sub_wire5(101); + sub_wire4(0, 102) <= sub_wire5(102); + sub_wire4(0, 103) <= sub_wire5(103); + sub_wire4(0, 104) <= sub_wire5(104); + sub_wire4(0, 105) <= sub_wire5(105); + sub_wire4(0, 106) <= sub_wire5(106); + sub_wire4(0, 107) <= sub_wire5(107); + sub_wire4(0, 108) <= sub_wire5(108); + sub_wire4(0, 109) <= sub_wire5(109); + sub_wire4(0, 110) <= sub_wire5(110); + sub_wire4(0, 111) <= sub_wire5(111); + sub_wire4(0, 112) <= sub_wire5(112); + sub_wire4(0, 113) <= sub_wire5(113); + sub_wire4(0, 114) <= sub_wire5(114); + sub_wire4(0, 115) <= sub_wire5(115); + sub_wire4(0, 116) <= sub_wire5(116); + sub_wire4(0, 117) <= sub_wire5(117); + sub_wire4(0, 118) <= sub_wire5(118); + sub_wire4(0, 119) <= sub_wire5(119); + sub_wire4(0, 120) <= sub_wire5(120); + sub_wire4(0, 121) <= sub_wire5(121); + sub_wire4(0, 122) <= sub_wire5(122); + sub_wire4(0, 123) <= sub_wire5(123); + sub_wire4(0, 124) <= sub_wire5(124); + sub_wire4(0, 125) <= sub_wire5(125); + sub_wire4(0, 126) <= sub_wire5(126); + sub_wire4(0, 127) <= sub_wire5(127); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 1, + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 128, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire2, + clken => clken, + clock => clock, + data => sub_wire4, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0] +-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0] +-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0] +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_muxVDM.bsf b/Video/lpm_muxVDM.bsf index a36fb74..42d235c 100644 --- a/Video/lpm_muxVDM.bsf +++ b/Video/lpm_muxVDM.bsf @@ -1,166 +1,158 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 304) - (text "lpm_muxVDM" (rect 31 0 131 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 289 26 300)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data15x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8))) - (text "data15x[127..0]" (rect 4 27 79 39)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data14x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8))) - (text "data14x[127..0]" (rect 4 43 79 55)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data13x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8))) - (text "data13x[127..0]" (rect 4 59 79 71)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data12x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8))) - (text "data12x[127..0]" (rect 4 75 79 87)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 64 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "data11x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8))) - (text "data11x[127..0]" (rect 4 91 79 103)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 64 104)(line_width 3)) - ) - (port - (pt 0 120) - (input) - (text "data10x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8))) - (text "data10x[127..0]" (rect 4 107 79 119)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 64 120)(line_width 3)) - ) - (port - (pt 0 136) - (input) - (text "data9x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data9x[127..0]" (rect 4 123 73 135)(font "Arial" (font_size 8))) - (line (pt 0 136)(pt 64 136)(line_width 3)) - ) - (port - (pt 0 152) - (input) - (text "data8x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data8x[127..0]" (rect 4 139 73 151)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 64 152)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "data7x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data7x[127..0]" (rect 4 155 73 167)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 64 168)(line_width 3)) - ) - (port - (pt 0 184) - (input) - (text "data6x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data6x[127..0]" (rect 4 171 73 183)(font "Arial" (font_size 8))) - (line (pt 0 184)(pt 64 184)(line_width 3)) - ) - (port - (pt 0 200) - (input) - (text "data5x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data5x[127..0]" (rect 4 187 73 199)(font "Arial" (font_size 8))) - (line (pt 0 200)(pt 64 200)(line_width 3)) - ) - (port - (pt 0 216) - (input) - (text "data4x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data4x[127..0]" (rect 4 203 73 215)(font "Arial" (font_size 8))) - (line (pt 0 216)(pt 64 216)(line_width 3)) - ) - (port - (pt 0 232) - (input) - (text "data3x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data3x[127..0]" (rect 4 219 73 231)(font "Arial" (font_size 8))) - (line (pt 0 232)(pt 64 232)(line_width 3)) - ) - (port - (pt 0 248) - (input) - (text "data2x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data2x[127..0]" (rect 4 235 73 247)(font "Arial" (font_size 8))) - (line (pt 0 248)(pt 64 248)(line_width 3)) - ) - (port - (pt 0 264) - (input) - (text "data1x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data1x[127..0]" (rect 4 251 73 263)(font "Arial" (font_size 8))) - (line (pt 0 264)(pt 64 264)(line_width 3)) - ) - (port - (pt 0 280) - (input) - (text "data0x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8))) - (text "data0x[127..0]" (rect 4 267 73 279)(font "Arial" (font_size 8))) - (line (pt 0 280)(pt 64 280)(line_width 3)) - ) - (port - (pt 72 304) - (input) - (text "sel[3..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical)) - (text "sel[3..0]" (rect 66 249 78 287)(font "Arial" (font_size 8))(vertical)) - (line (pt 72 304)(pt 72 292)(line_width 3)) - ) - (port - (pt 144 160) - (output) - (text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8))) - (text "result[127..0]" (rect 79 147 142 159)(font "Arial" (font_size 8))) - (line (pt 144 160)(pt 80 160)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 296)) - (line (pt 64 24)(pt 80 32)) - (line (pt 64 296)(pt 80 288)) - (line (pt 80 32)(pt 80 288)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 306)) - (line (pt 0 306)(pt 146 306)) - (line (pt 0 0)(pt 0 306)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 168 304) + (text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 288 25 300)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 80 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 80 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 80 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 80 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 80 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data10x[127..0]" (rect 4 107 78 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 80 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 80 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 80 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 80 168)(line_width 3)) + ) + (port + (pt 0 184) + (input) + (text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 80 184)(line_width 3)) + ) + (port + (pt 0 200) + (input) + (text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 80 200)(line_width 3)) + ) + (port + (pt 0 216) + (input) + (text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 80 216)(line_width 3)) + ) + (port + (pt 0 232) + (input) + (text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 80 232)(line_width 3)) + ) + (port + (pt 0 248) + (input) + (text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data2x[127..0]" (rect 4 235 72 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 80 248)(line_width 3)) + ) + (port + (pt 0 264) + (input) + (text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 80 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 80 280)(line_width 3)) + ) + (port + (pt 88 304) + (input) + (text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8))) + (line (pt 88 304)(pt 88 292)(line_width 3)) + ) + (port + (pt 168 160) + (output) + (text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8))) + (line (pt 168 160)(pt 96 160)(line_width 3)) + ) + (drawing + (line (pt 80 24)(pt 80 296)(line_width 1)) + (line (pt 96 32)(pt 96 288)(line_width 1)) + (line (pt 80 24)(pt 96 32)(line_width 1)) + (line (pt 80 296)(pt 96 288)(line_width 1)) + ) +) diff --git a/Video/lpm_muxVDM.cmp b/Video/lpm_muxVDM.cmp index 565ee26..867776d 100644 --- a/Video/lpm_muxVDM.cmp +++ b/Video/lpm_muxVDM.cmp @@ -1,38 +1,38 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_muxVDM - PORT - ( - data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxVDM + PORT + ( + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_muxVDM.qip b/Video/lpm_muxVDM.qip index 09a4b4d..08a824e 100644 --- a/Video/lpm_muxVDM.qip +++ b/Video/lpm_muxVDM.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"] diff --git a/Video/lpm_muxVDM.vhd b/Video/lpm_muxVDM.vhd index d03879d..662c8be 100644 --- a/Video/lpm_muxVDM.vhd +++ b/Video/lpm_muxVDM.vhd @@ -1,2226 +1,2225 @@ --- megafunction wizard: %LPM_MUX% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_MUX - --- ============================================================ --- File Name: lpm_muxVDM.vhd --- Megafunction Name(s): --- LPM_MUX --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.lpm_components.all; - -ENTITY lpm_muxVDM IS - PORT - ( - data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) - ); -END lpm_muxVDM; - - -ARCHITECTURE SYN OF lpm_muxvdm IS - --- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 127 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire9 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire10 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire11 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire12 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire13 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire14 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire15 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire16 : STD_LOGIC_VECTOR (127 DOWNTO 0); - SIGNAL sub_wire17 : STD_LOGIC_VECTOR (127 DOWNTO 0); - -BEGIN - sub_wire17 <= data0x(127 DOWNTO 0); - sub_wire16 <= data1x(127 DOWNTO 0); - sub_wire15 <= data2x(127 DOWNTO 0); - sub_wire14 <= data3x(127 DOWNTO 0); - sub_wire13 <= data4x(127 DOWNTO 0); - sub_wire12 <= data5x(127 DOWNTO 0); - sub_wire11 <= data6x(127 DOWNTO 0); - sub_wire10 <= data7x(127 DOWNTO 0); - sub_wire9 <= data8x(127 DOWNTO 0); - sub_wire8 <= data9x(127 DOWNTO 0); - sub_wire7 <= data10x(127 DOWNTO 0); - sub_wire6 <= data11x(127 DOWNTO 0); - sub_wire5 <= data12x(127 DOWNTO 0); - sub_wire4 <= data13x(127 DOWNTO 0); - sub_wire3 <= data14x(127 DOWNTO 0); - result <= sub_wire0(127 DOWNTO 0); - sub_wire1 <= data15x(127 DOWNTO 0); - sub_wire2(15, 0) <= sub_wire1(0); - sub_wire2(15, 1) <= sub_wire1(1); - sub_wire2(15, 2) <= sub_wire1(2); - sub_wire2(15, 3) <= sub_wire1(3); - sub_wire2(15, 4) <= sub_wire1(4); - sub_wire2(15, 5) <= sub_wire1(5); - sub_wire2(15, 6) <= sub_wire1(6); - sub_wire2(15, 7) <= sub_wire1(7); - sub_wire2(15, 8) <= sub_wire1(8); - sub_wire2(15, 9) <= sub_wire1(9); - sub_wire2(15, 10) <= sub_wire1(10); - sub_wire2(15, 11) <= sub_wire1(11); - sub_wire2(15, 12) <= sub_wire1(12); - sub_wire2(15, 13) <= sub_wire1(13); - sub_wire2(15, 14) <= sub_wire1(14); - sub_wire2(15, 15) <= sub_wire1(15); - sub_wire2(15, 16) <= sub_wire1(16); - sub_wire2(15, 17) <= sub_wire1(17); - sub_wire2(15, 18) <= sub_wire1(18); - sub_wire2(15, 19) <= sub_wire1(19); - sub_wire2(15, 20) <= sub_wire1(20); - sub_wire2(15, 21) <= sub_wire1(21); - sub_wire2(15, 22) <= sub_wire1(22); - sub_wire2(15, 23) <= sub_wire1(23); - sub_wire2(15, 24) <= sub_wire1(24); - sub_wire2(15, 25) <= sub_wire1(25); - sub_wire2(15, 26) <= sub_wire1(26); - sub_wire2(15, 27) <= sub_wire1(27); - sub_wire2(15, 28) <= sub_wire1(28); - sub_wire2(15, 29) <= sub_wire1(29); - sub_wire2(15, 30) <= sub_wire1(30); - sub_wire2(15, 31) <= sub_wire1(31); - sub_wire2(15, 32) <= sub_wire1(32); - sub_wire2(15, 33) <= sub_wire1(33); - sub_wire2(15, 34) <= sub_wire1(34); - sub_wire2(15, 35) <= sub_wire1(35); - sub_wire2(15, 36) <= sub_wire1(36); - sub_wire2(15, 37) <= sub_wire1(37); - sub_wire2(15, 38) <= sub_wire1(38); - sub_wire2(15, 39) <= sub_wire1(39); - sub_wire2(15, 40) <= sub_wire1(40); - sub_wire2(15, 41) <= sub_wire1(41); - sub_wire2(15, 42) <= sub_wire1(42); - sub_wire2(15, 43) <= sub_wire1(43); - sub_wire2(15, 44) <= sub_wire1(44); - sub_wire2(15, 45) <= sub_wire1(45); - sub_wire2(15, 46) <= sub_wire1(46); - sub_wire2(15, 47) <= sub_wire1(47); - sub_wire2(15, 48) <= sub_wire1(48); - sub_wire2(15, 49) <= sub_wire1(49); - sub_wire2(15, 50) <= sub_wire1(50); - sub_wire2(15, 51) <= sub_wire1(51); - sub_wire2(15, 52) <= sub_wire1(52); - sub_wire2(15, 53) <= sub_wire1(53); - sub_wire2(15, 54) <= sub_wire1(54); - sub_wire2(15, 55) <= sub_wire1(55); - sub_wire2(15, 56) <= sub_wire1(56); - sub_wire2(15, 57) <= sub_wire1(57); - sub_wire2(15, 58) <= sub_wire1(58); - sub_wire2(15, 59) <= sub_wire1(59); - sub_wire2(15, 60) <= sub_wire1(60); - sub_wire2(15, 61) <= sub_wire1(61); - sub_wire2(15, 62) <= sub_wire1(62); - sub_wire2(15, 63) <= sub_wire1(63); - sub_wire2(15, 64) <= sub_wire1(64); - sub_wire2(15, 65) <= sub_wire1(65); - sub_wire2(15, 66) <= sub_wire1(66); - sub_wire2(15, 67) <= sub_wire1(67); - sub_wire2(15, 68) <= sub_wire1(68); - sub_wire2(15, 69) <= sub_wire1(69); - sub_wire2(15, 70) <= sub_wire1(70); - sub_wire2(15, 71) <= sub_wire1(71); - sub_wire2(15, 72) <= sub_wire1(72); - sub_wire2(15, 73) <= sub_wire1(73); - sub_wire2(15, 74) <= sub_wire1(74); - sub_wire2(15, 75) <= sub_wire1(75); - sub_wire2(15, 76) <= sub_wire1(76); - sub_wire2(15, 77) <= sub_wire1(77); - sub_wire2(15, 78) <= sub_wire1(78); - sub_wire2(15, 79) <= sub_wire1(79); - sub_wire2(15, 80) <= sub_wire1(80); - sub_wire2(15, 81) <= sub_wire1(81); - sub_wire2(15, 82) <= sub_wire1(82); - sub_wire2(15, 83) <= sub_wire1(83); - sub_wire2(15, 84) <= sub_wire1(84); - sub_wire2(15, 85) <= sub_wire1(85); - sub_wire2(15, 86) <= sub_wire1(86); - sub_wire2(15, 87) <= sub_wire1(87); - sub_wire2(15, 88) <= sub_wire1(88); - sub_wire2(15, 89) <= sub_wire1(89); - sub_wire2(15, 90) <= sub_wire1(90); - sub_wire2(15, 91) <= sub_wire1(91); - sub_wire2(15, 92) <= sub_wire1(92); - sub_wire2(15, 93) <= sub_wire1(93); - sub_wire2(15, 94) <= sub_wire1(94); - sub_wire2(15, 95) <= sub_wire1(95); - sub_wire2(15, 96) <= sub_wire1(96); - sub_wire2(15, 97) <= sub_wire1(97); - sub_wire2(15, 98) <= sub_wire1(98); - sub_wire2(15, 99) <= sub_wire1(99); - sub_wire2(15, 100) <= sub_wire1(100); - sub_wire2(15, 101) <= sub_wire1(101); - sub_wire2(15, 102) <= sub_wire1(102); - sub_wire2(15, 103) <= sub_wire1(103); - sub_wire2(15, 104) <= sub_wire1(104); - sub_wire2(15, 105) <= sub_wire1(105); - sub_wire2(15, 106) <= sub_wire1(106); - sub_wire2(15, 107) <= sub_wire1(107); - sub_wire2(15, 108) <= sub_wire1(108); - sub_wire2(15, 109) <= sub_wire1(109); - sub_wire2(15, 110) <= sub_wire1(110); - sub_wire2(15, 111) <= sub_wire1(111); - sub_wire2(15, 112) <= sub_wire1(112); - sub_wire2(15, 113) <= sub_wire1(113); - sub_wire2(15, 114) <= sub_wire1(114); - sub_wire2(15, 115) <= sub_wire1(115); - sub_wire2(15, 116) <= sub_wire1(116); - sub_wire2(15, 117) <= sub_wire1(117); - sub_wire2(15, 118) <= sub_wire1(118); - sub_wire2(15, 119) <= sub_wire1(119); - sub_wire2(15, 120) <= sub_wire1(120); - sub_wire2(15, 121) <= sub_wire1(121); - sub_wire2(15, 122) <= sub_wire1(122); - sub_wire2(15, 123) <= sub_wire1(123); - sub_wire2(15, 124) <= sub_wire1(124); - sub_wire2(15, 125) <= sub_wire1(125); - sub_wire2(15, 126) <= sub_wire1(126); - sub_wire2(15, 127) <= sub_wire1(127); - sub_wire2(14, 0) <= sub_wire3(0); - sub_wire2(14, 1) <= sub_wire3(1); - sub_wire2(14, 2) <= sub_wire3(2); - sub_wire2(14, 3) <= sub_wire3(3); - sub_wire2(14, 4) <= sub_wire3(4); - sub_wire2(14, 5) <= sub_wire3(5); - sub_wire2(14, 6) <= sub_wire3(6); - sub_wire2(14, 7) <= sub_wire3(7); - sub_wire2(14, 8) <= sub_wire3(8); - sub_wire2(14, 9) <= sub_wire3(9); - sub_wire2(14, 10) <= sub_wire3(10); - sub_wire2(14, 11) <= sub_wire3(11); - sub_wire2(14, 12) <= sub_wire3(12); - sub_wire2(14, 13) <= sub_wire3(13); - sub_wire2(14, 14) <= sub_wire3(14); - sub_wire2(14, 15) <= sub_wire3(15); - sub_wire2(14, 16) <= sub_wire3(16); - sub_wire2(14, 17) <= sub_wire3(17); - sub_wire2(14, 18) <= sub_wire3(18); - sub_wire2(14, 19) <= sub_wire3(19); - sub_wire2(14, 20) <= sub_wire3(20); - sub_wire2(14, 21) <= sub_wire3(21); - sub_wire2(14, 22) <= sub_wire3(22); - sub_wire2(14, 23) <= sub_wire3(23); - sub_wire2(14, 24) <= sub_wire3(24); - sub_wire2(14, 25) <= sub_wire3(25); - sub_wire2(14, 26) <= sub_wire3(26); - sub_wire2(14, 27) <= sub_wire3(27); - sub_wire2(14, 28) <= sub_wire3(28); - sub_wire2(14, 29) <= sub_wire3(29); - sub_wire2(14, 30) <= sub_wire3(30); - sub_wire2(14, 31) <= sub_wire3(31); - sub_wire2(14, 32) <= sub_wire3(32); - sub_wire2(14, 33) <= sub_wire3(33); - sub_wire2(14, 34) <= sub_wire3(34); - sub_wire2(14, 35) <= sub_wire3(35); - sub_wire2(14, 36) <= sub_wire3(36); - sub_wire2(14, 37) <= sub_wire3(37); - sub_wire2(14, 38) <= sub_wire3(38); - sub_wire2(14, 39) <= sub_wire3(39); - sub_wire2(14, 40) <= sub_wire3(40); - sub_wire2(14, 41) <= sub_wire3(41); - sub_wire2(14, 42) <= sub_wire3(42); - sub_wire2(14, 43) <= sub_wire3(43); - sub_wire2(14, 44) <= sub_wire3(44); - sub_wire2(14, 45) <= sub_wire3(45); - sub_wire2(14, 46) <= sub_wire3(46); - sub_wire2(14, 47) <= sub_wire3(47); - sub_wire2(14, 48) <= sub_wire3(48); - sub_wire2(14, 49) <= sub_wire3(49); - sub_wire2(14, 50) <= sub_wire3(50); - sub_wire2(14, 51) <= sub_wire3(51); - sub_wire2(14, 52) <= sub_wire3(52); - sub_wire2(14, 53) <= sub_wire3(53); - sub_wire2(14, 54) <= sub_wire3(54); - sub_wire2(14, 55) <= sub_wire3(55); - sub_wire2(14, 56) <= sub_wire3(56); - sub_wire2(14, 57) <= sub_wire3(57); - sub_wire2(14, 58) <= sub_wire3(58); - sub_wire2(14, 59) <= sub_wire3(59); - sub_wire2(14, 60) <= sub_wire3(60); - sub_wire2(14, 61) <= sub_wire3(61); - sub_wire2(14, 62) <= sub_wire3(62); - sub_wire2(14, 63) <= sub_wire3(63); - sub_wire2(14, 64) <= sub_wire3(64); - sub_wire2(14, 65) <= sub_wire3(65); - sub_wire2(14, 66) <= sub_wire3(66); - sub_wire2(14, 67) <= sub_wire3(67); - sub_wire2(14, 68) <= sub_wire3(68); - sub_wire2(14, 69) <= sub_wire3(69); - sub_wire2(14, 70) <= sub_wire3(70); - sub_wire2(14, 71) <= sub_wire3(71); - sub_wire2(14, 72) <= sub_wire3(72); - sub_wire2(14, 73) <= sub_wire3(73); - sub_wire2(14, 74) <= sub_wire3(74); - sub_wire2(14, 75) <= sub_wire3(75); - sub_wire2(14, 76) <= sub_wire3(76); - sub_wire2(14, 77) <= sub_wire3(77); - sub_wire2(14, 78) <= sub_wire3(78); - sub_wire2(14, 79) <= sub_wire3(79); - sub_wire2(14, 80) <= sub_wire3(80); - sub_wire2(14, 81) <= sub_wire3(81); - sub_wire2(14, 82) <= sub_wire3(82); - sub_wire2(14, 83) <= sub_wire3(83); - sub_wire2(14, 84) <= sub_wire3(84); - sub_wire2(14, 85) <= sub_wire3(85); - sub_wire2(14, 86) <= sub_wire3(86); - sub_wire2(14, 87) <= sub_wire3(87); - sub_wire2(14, 88) <= sub_wire3(88); - sub_wire2(14, 89) <= sub_wire3(89); - sub_wire2(14, 90) <= sub_wire3(90); - sub_wire2(14, 91) <= sub_wire3(91); - sub_wire2(14, 92) <= sub_wire3(92); - sub_wire2(14, 93) <= sub_wire3(93); - sub_wire2(14, 94) <= sub_wire3(94); - sub_wire2(14, 95) <= sub_wire3(95); - sub_wire2(14, 96) <= sub_wire3(96); - sub_wire2(14, 97) <= sub_wire3(97); - sub_wire2(14, 98) <= sub_wire3(98); - sub_wire2(14, 99) <= sub_wire3(99); - sub_wire2(14, 100) <= sub_wire3(100); - sub_wire2(14, 101) <= sub_wire3(101); - sub_wire2(14, 102) <= sub_wire3(102); - sub_wire2(14, 103) <= sub_wire3(103); - sub_wire2(14, 104) <= sub_wire3(104); - sub_wire2(14, 105) <= sub_wire3(105); - sub_wire2(14, 106) <= sub_wire3(106); - sub_wire2(14, 107) <= sub_wire3(107); - sub_wire2(14, 108) <= sub_wire3(108); - sub_wire2(14, 109) <= sub_wire3(109); - sub_wire2(14, 110) <= sub_wire3(110); - sub_wire2(14, 111) <= sub_wire3(111); - sub_wire2(14, 112) <= sub_wire3(112); - sub_wire2(14, 113) <= sub_wire3(113); - sub_wire2(14, 114) <= sub_wire3(114); - sub_wire2(14, 115) <= sub_wire3(115); - sub_wire2(14, 116) <= sub_wire3(116); - sub_wire2(14, 117) <= sub_wire3(117); - sub_wire2(14, 118) <= sub_wire3(118); - sub_wire2(14, 119) <= sub_wire3(119); - sub_wire2(14, 120) <= sub_wire3(120); - sub_wire2(14, 121) <= sub_wire3(121); - sub_wire2(14, 122) <= sub_wire3(122); - sub_wire2(14, 123) <= sub_wire3(123); - sub_wire2(14, 124) <= sub_wire3(124); - sub_wire2(14, 125) <= sub_wire3(125); - sub_wire2(14, 126) <= sub_wire3(126); - sub_wire2(14, 127) <= sub_wire3(127); - sub_wire2(13, 0) <= sub_wire4(0); - sub_wire2(13, 1) <= sub_wire4(1); - sub_wire2(13, 2) <= sub_wire4(2); - sub_wire2(13, 3) <= sub_wire4(3); - sub_wire2(13, 4) <= sub_wire4(4); - sub_wire2(13, 5) <= sub_wire4(5); - sub_wire2(13, 6) <= sub_wire4(6); - sub_wire2(13, 7) <= sub_wire4(7); - sub_wire2(13, 8) <= sub_wire4(8); - sub_wire2(13, 9) <= sub_wire4(9); - sub_wire2(13, 10) <= sub_wire4(10); - sub_wire2(13, 11) <= sub_wire4(11); - sub_wire2(13, 12) <= sub_wire4(12); - sub_wire2(13, 13) <= sub_wire4(13); - sub_wire2(13, 14) <= sub_wire4(14); - sub_wire2(13, 15) <= sub_wire4(15); - sub_wire2(13, 16) <= sub_wire4(16); - sub_wire2(13, 17) <= sub_wire4(17); - sub_wire2(13, 18) <= sub_wire4(18); - sub_wire2(13, 19) <= sub_wire4(19); - sub_wire2(13, 20) <= sub_wire4(20); - sub_wire2(13, 21) <= sub_wire4(21); - sub_wire2(13, 22) <= sub_wire4(22); - sub_wire2(13, 23) <= sub_wire4(23); - sub_wire2(13, 24) <= sub_wire4(24); - sub_wire2(13, 25) <= sub_wire4(25); - sub_wire2(13, 26) <= sub_wire4(26); - sub_wire2(13, 27) <= sub_wire4(27); - sub_wire2(13, 28) <= sub_wire4(28); - sub_wire2(13, 29) <= sub_wire4(29); - sub_wire2(13, 30) <= sub_wire4(30); - sub_wire2(13, 31) <= sub_wire4(31); - sub_wire2(13, 32) <= sub_wire4(32); - sub_wire2(13, 33) <= sub_wire4(33); - sub_wire2(13, 34) <= sub_wire4(34); - sub_wire2(13, 35) <= sub_wire4(35); - sub_wire2(13, 36) <= sub_wire4(36); - sub_wire2(13, 37) <= sub_wire4(37); - sub_wire2(13, 38) <= sub_wire4(38); - sub_wire2(13, 39) <= sub_wire4(39); - sub_wire2(13, 40) <= sub_wire4(40); - sub_wire2(13, 41) <= sub_wire4(41); - sub_wire2(13, 42) <= sub_wire4(42); - sub_wire2(13, 43) <= sub_wire4(43); - sub_wire2(13, 44) <= sub_wire4(44); - sub_wire2(13, 45) <= sub_wire4(45); - sub_wire2(13, 46) <= sub_wire4(46); - sub_wire2(13, 47) <= sub_wire4(47); - sub_wire2(13, 48) <= sub_wire4(48); - sub_wire2(13, 49) <= sub_wire4(49); - sub_wire2(13, 50) <= sub_wire4(50); - sub_wire2(13, 51) <= sub_wire4(51); - sub_wire2(13, 52) <= sub_wire4(52); - sub_wire2(13, 53) <= sub_wire4(53); - sub_wire2(13, 54) <= sub_wire4(54); - sub_wire2(13, 55) <= sub_wire4(55); - sub_wire2(13, 56) <= sub_wire4(56); - sub_wire2(13, 57) <= sub_wire4(57); - sub_wire2(13, 58) <= sub_wire4(58); - sub_wire2(13, 59) <= sub_wire4(59); - sub_wire2(13, 60) <= sub_wire4(60); - sub_wire2(13, 61) <= sub_wire4(61); - sub_wire2(13, 62) <= sub_wire4(62); - sub_wire2(13, 63) <= sub_wire4(63); - sub_wire2(13, 64) <= sub_wire4(64); - sub_wire2(13, 65) <= sub_wire4(65); - sub_wire2(13, 66) <= sub_wire4(66); - sub_wire2(13, 67) <= sub_wire4(67); - sub_wire2(13, 68) <= sub_wire4(68); - sub_wire2(13, 69) <= sub_wire4(69); - sub_wire2(13, 70) <= sub_wire4(70); - sub_wire2(13, 71) <= sub_wire4(71); - sub_wire2(13, 72) <= sub_wire4(72); - sub_wire2(13, 73) <= sub_wire4(73); - sub_wire2(13, 74) <= sub_wire4(74); - sub_wire2(13, 75) <= sub_wire4(75); - sub_wire2(13, 76) <= sub_wire4(76); - sub_wire2(13, 77) <= sub_wire4(77); - sub_wire2(13, 78) <= sub_wire4(78); - sub_wire2(13, 79) <= sub_wire4(79); - sub_wire2(13, 80) <= sub_wire4(80); - sub_wire2(13, 81) <= sub_wire4(81); - sub_wire2(13, 82) <= sub_wire4(82); - sub_wire2(13, 83) <= sub_wire4(83); - sub_wire2(13, 84) <= sub_wire4(84); - sub_wire2(13, 85) <= sub_wire4(85); - sub_wire2(13, 86) <= sub_wire4(86); - sub_wire2(13, 87) <= sub_wire4(87); - sub_wire2(13, 88) <= sub_wire4(88); - sub_wire2(13, 89) <= sub_wire4(89); - sub_wire2(13, 90) <= sub_wire4(90); - sub_wire2(13, 91) <= sub_wire4(91); - sub_wire2(13, 92) <= sub_wire4(92); - sub_wire2(13, 93) <= sub_wire4(93); - sub_wire2(13, 94) <= sub_wire4(94); - sub_wire2(13, 95) <= sub_wire4(95); - sub_wire2(13, 96) <= sub_wire4(96); - sub_wire2(13, 97) <= sub_wire4(97); - sub_wire2(13, 98) <= sub_wire4(98); - sub_wire2(13, 99) <= sub_wire4(99); - sub_wire2(13, 100) <= sub_wire4(100); - sub_wire2(13, 101) <= sub_wire4(101); - sub_wire2(13, 102) <= sub_wire4(102); - sub_wire2(13, 103) <= sub_wire4(103); - sub_wire2(13, 104) <= sub_wire4(104); - sub_wire2(13, 105) <= sub_wire4(105); - sub_wire2(13, 106) <= sub_wire4(106); - sub_wire2(13, 107) <= sub_wire4(107); - sub_wire2(13, 108) <= sub_wire4(108); - sub_wire2(13, 109) <= sub_wire4(109); - sub_wire2(13, 110) <= sub_wire4(110); - sub_wire2(13, 111) <= sub_wire4(111); - sub_wire2(13, 112) <= sub_wire4(112); - sub_wire2(13, 113) <= sub_wire4(113); - sub_wire2(13, 114) <= sub_wire4(114); - sub_wire2(13, 115) <= sub_wire4(115); - sub_wire2(13, 116) <= sub_wire4(116); - sub_wire2(13, 117) <= sub_wire4(117); - sub_wire2(13, 118) <= sub_wire4(118); - sub_wire2(13, 119) <= sub_wire4(119); - sub_wire2(13, 120) <= sub_wire4(120); - sub_wire2(13, 121) <= sub_wire4(121); - sub_wire2(13, 122) <= sub_wire4(122); - sub_wire2(13, 123) <= sub_wire4(123); - sub_wire2(13, 124) <= sub_wire4(124); - sub_wire2(13, 125) <= sub_wire4(125); - sub_wire2(13, 126) <= sub_wire4(126); - sub_wire2(13, 127) <= sub_wire4(127); - sub_wire2(12, 0) <= sub_wire5(0); - sub_wire2(12, 1) <= sub_wire5(1); - sub_wire2(12, 2) <= sub_wire5(2); - sub_wire2(12, 3) <= sub_wire5(3); - sub_wire2(12, 4) <= sub_wire5(4); - sub_wire2(12, 5) <= sub_wire5(5); - sub_wire2(12, 6) <= sub_wire5(6); - sub_wire2(12, 7) <= sub_wire5(7); - sub_wire2(12, 8) <= sub_wire5(8); - sub_wire2(12, 9) <= sub_wire5(9); - sub_wire2(12, 10) <= sub_wire5(10); - sub_wire2(12, 11) <= sub_wire5(11); - sub_wire2(12, 12) <= sub_wire5(12); - sub_wire2(12, 13) <= sub_wire5(13); - sub_wire2(12, 14) <= sub_wire5(14); - sub_wire2(12, 15) <= sub_wire5(15); - sub_wire2(12, 16) <= sub_wire5(16); - sub_wire2(12, 17) <= sub_wire5(17); - sub_wire2(12, 18) <= sub_wire5(18); - sub_wire2(12, 19) <= sub_wire5(19); - sub_wire2(12, 20) <= sub_wire5(20); - sub_wire2(12, 21) <= sub_wire5(21); - sub_wire2(12, 22) <= sub_wire5(22); - sub_wire2(12, 23) <= sub_wire5(23); - sub_wire2(12, 24) <= sub_wire5(24); - sub_wire2(12, 25) <= sub_wire5(25); - sub_wire2(12, 26) <= sub_wire5(26); - sub_wire2(12, 27) <= sub_wire5(27); - sub_wire2(12, 28) <= sub_wire5(28); - sub_wire2(12, 29) <= sub_wire5(29); - sub_wire2(12, 30) <= sub_wire5(30); - sub_wire2(12, 31) <= sub_wire5(31); - sub_wire2(12, 32) <= sub_wire5(32); - sub_wire2(12, 33) <= sub_wire5(33); - sub_wire2(12, 34) <= sub_wire5(34); - sub_wire2(12, 35) <= sub_wire5(35); - sub_wire2(12, 36) <= sub_wire5(36); - sub_wire2(12, 37) <= sub_wire5(37); - sub_wire2(12, 38) <= sub_wire5(38); - sub_wire2(12, 39) <= sub_wire5(39); - sub_wire2(12, 40) <= sub_wire5(40); - sub_wire2(12, 41) <= sub_wire5(41); - sub_wire2(12, 42) <= sub_wire5(42); - sub_wire2(12, 43) <= sub_wire5(43); - sub_wire2(12, 44) <= sub_wire5(44); - sub_wire2(12, 45) <= sub_wire5(45); - sub_wire2(12, 46) <= sub_wire5(46); - sub_wire2(12, 47) <= sub_wire5(47); - sub_wire2(12, 48) <= sub_wire5(48); - sub_wire2(12, 49) <= sub_wire5(49); - sub_wire2(12, 50) <= sub_wire5(50); - sub_wire2(12, 51) <= sub_wire5(51); - sub_wire2(12, 52) <= sub_wire5(52); - sub_wire2(12, 53) <= sub_wire5(53); - sub_wire2(12, 54) <= sub_wire5(54); - sub_wire2(12, 55) <= sub_wire5(55); - sub_wire2(12, 56) <= sub_wire5(56); - sub_wire2(12, 57) <= sub_wire5(57); - sub_wire2(12, 58) <= sub_wire5(58); - sub_wire2(12, 59) <= sub_wire5(59); - sub_wire2(12, 60) <= sub_wire5(60); - sub_wire2(12, 61) <= sub_wire5(61); - sub_wire2(12, 62) <= sub_wire5(62); - sub_wire2(12, 63) <= sub_wire5(63); - sub_wire2(12, 64) <= sub_wire5(64); - sub_wire2(12, 65) <= sub_wire5(65); - sub_wire2(12, 66) <= sub_wire5(66); - sub_wire2(12, 67) <= sub_wire5(67); - sub_wire2(12, 68) <= sub_wire5(68); - sub_wire2(12, 69) <= sub_wire5(69); - sub_wire2(12, 70) <= sub_wire5(70); - sub_wire2(12, 71) <= sub_wire5(71); - sub_wire2(12, 72) <= sub_wire5(72); - sub_wire2(12, 73) <= sub_wire5(73); - sub_wire2(12, 74) <= sub_wire5(74); - sub_wire2(12, 75) <= sub_wire5(75); - sub_wire2(12, 76) <= sub_wire5(76); - sub_wire2(12, 77) <= sub_wire5(77); - sub_wire2(12, 78) <= sub_wire5(78); - sub_wire2(12, 79) <= sub_wire5(79); - sub_wire2(12, 80) <= sub_wire5(80); - sub_wire2(12, 81) <= sub_wire5(81); - sub_wire2(12, 82) <= sub_wire5(82); - sub_wire2(12, 83) <= sub_wire5(83); - sub_wire2(12, 84) <= sub_wire5(84); - sub_wire2(12, 85) <= sub_wire5(85); - sub_wire2(12, 86) <= sub_wire5(86); - sub_wire2(12, 87) <= sub_wire5(87); - sub_wire2(12, 88) <= sub_wire5(88); - sub_wire2(12, 89) <= sub_wire5(89); - sub_wire2(12, 90) <= sub_wire5(90); - sub_wire2(12, 91) <= sub_wire5(91); - sub_wire2(12, 92) <= sub_wire5(92); - sub_wire2(12, 93) <= sub_wire5(93); - sub_wire2(12, 94) <= sub_wire5(94); - sub_wire2(12, 95) <= sub_wire5(95); - sub_wire2(12, 96) <= sub_wire5(96); - sub_wire2(12, 97) <= sub_wire5(97); - sub_wire2(12, 98) <= sub_wire5(98); - sub_wire2(12, 99) <= sub_wire5(99); - sub_wire2(12, 100) <= sub_wire5(100); - sub_wire2(12, 101) <= sub_wire5(101); - sub_wire2(12, 102) <= sub_wire5(102); - sub_wire2(12, 103) <= sub_wire5(103); - sub_wire2(12, 104) <= sub_wire5(104); - sub_wire2(12, 105) <= sub_wire5(105); - sub_wire2(12, 106) <= sub_wire5(106); - sub_wire2(12, 107) <= sub_wire5(107); - sub_wire2(12, 108) <= sub_wire5(108); - sub_wire2(12, 109) <= sub_wire5(109); - sub_wire2(12, 110) <= sub_wire5(110); - sub_wire2(12, 111) <= sub_wire5(111); - sub_wire2(12, 112) <= sub_wire5(112); - sub_wire2(12, 113) <= sub_wire5(113); - sub_wire2(12, 114) <= sub_wire5(114); - sub_wire2(12, 115) <= sub_wire5(115); - sub_wire2(12, 116) <= sub_wire5(116); - sub_wire2(12, 117) <= sub_wire5(117); - sub_wire2(12, 118) <= sub_wire5(118); - sub_wire2(12, 119) <= sub_wire5(119); - sub_wire2(12, 120) <= sub_wire5(120); - sub_wire2(12, 121) <= sub_wire5(121); - sub_wire2(12, 122) <= sub_wire5(122); - sub_wire2(12, 123) <= sub_wire5(123); - sub_wire2(12, 124) <= sub_wire5(124); - sub_wire2(12, 125) <= sub_wire5(125); - sub_wire2(12, 126) <= sub_wire5(126); - sub_wire2(12, 127) <= sub_wire5(127); - sub_wire2(11, 0) <= sub_wire6(0); - sub_wire2(11, 1) <= sub_wire6(1); - sub_wire2(11, 2) <= sub_wire6(2); - sub_wire2(11, 3) <= sub_wire6(3); - sub_wire2(11, 4) <= sub_wire6(4); - sub_wire2(11, 5) <= sub_wire6(5); - sub_wire2(11, 6) <= sub_wire6(6); - sub_wire2(11, 7) <= sub_wire6(7); - sub_wire2(11, 8) <= sub_wire6(8); - sub_wire2(11, 9) <= sub_wire6(9); - sub_wire2(11, 10) <= sub_wire6(10); - sub_wire2(11, 11) <= sub_wire6(11); - sub_wire2(11, 12) <= sub_wire6(12); - sub_wire2(11, 13) <= sub_wire6(13); - sub_wire2(11, 14) <= sub_wire6(14); - sub_wire2(11, 15) <= sub_wire6(15); - sub_wire2(11, 16) <= sub_wire6(16); - sub_wire2(11, 17) <= sub_wire6(17); - sub_wire2(11, 18) <= sub_wire6(18); - sub_wire2(11, 19) <= sub_wire6(19); - sub_wire2(11, 20) <= sub_wire6(20); - sub_wire2(11, 21) <= sub_wire6(21); - sub_wire2(11, 22) <= sub_wire6(22); - sub_wire2(11, 23) <= sub_wire6(23); - sub_wire2(11, 24) <= sub_wire6(24); - sub_wire2(11, 25) <= sub_wire6(25); - sub_wire2(11, 26) <= sub_wire6(26); - sub_wire2(11, 27) <= sub_wire6(27); - sub_wire2(11, 28) <= sub_wire6(28); - sub_wire2(11, 29) <= sub_wire6(29); - sub_wire2(11, 30) <= sub_wire6(30); - sub_wire2(11, 31) <= sub_wire6(31); - sub_wire2(11, 32) <= sub_wire6(32); - sub_wire2(11, 33) <= sub_wire6(33); - sub_wire2(11, 34) <= sub_wire6(34); - sub_wire2(11, 35) <= sub_wire6(35); - sub_wire2(11, 36) <= sub_wire6(36); - sub_wire2(11, 37) <= sub_wire6(37); - sub_wire2(11, 38) <= sub_wire6(38); - sub_wire2(11, 39) <= sub_wire6(39); - sub_wire2(11, 40) <= sub_wire6(40); - sub_wire2(11, 41) <= sub_wire6(41); - sub_wire2(11, 42) <= sub_wire6(42); - sub_wire2(11, 43) <= sub_wire6(43); - sub_wire2(11, 44) <= sub_wire6(44); - sub_wire2(11, 45) <= sub_wire6(45); - sub_wire2(11, 46) <= sub_wire6(46); - sub_wire2(11, 47) <= sub_wire6(47); - sub_wire2(11, 48) <= sub_wire6(48); - sub_wire2(11, 49) <= sub_wire6(49); - sub_wire2(11, 50) <= sub_wire6(50); - sub_wire2(11, 51) <= sub_wire6(51); - sub_wire2(11, 52) <= sub_wire6(52); - sub_wire2(11, 53) <= sub_wire6(53); - sub_wire2(11, 54) <= sub_wire6(54); - sub_wire2(11, 55) <= sub_wire6(55); - sub_wire2(11, 56) <= sub_wire6(56); - sub_wire2(11, 57) <= sub_wire6(57); - sub_wire2(11, 58) <= sub_wire6(58); - sub_wire2(11, 59) <= sub_wire6(59); - sub_wire2(11, 60) <= sub_wire6(60); - sub_wire2(11, 61) <= sub_wire6(61); - sub_wire2(11, 62) <= sub_wire6(62); - sub_wire2(11, 63) <= sub_wire6(63); - sub_wire2(11, 64) <= sub_wire6(64); - sub_wire2(11, 65) <= sub_wire6(65); - sub_wire2(11, 66) <= sub_wire6(66); - sub_wire2(11, 67) <= sub_wire6(67); - sub_wire2(11, 68) <= sub_wire6(68); - sub_wire2(11, 69) <= sub_wire6(69); - sub_wire2(11, 70) <= sub_wire6(70); - sub_wire2(11, 71) <= sub_wire6(71); - sub_wire2(11, 72) <= sub_wire6(72); - sub_wire2(11, 73) <= sub_wire6(73); - sub_wire2(11, 74) <= sub_wire6(74); - sub_wire2(11, 75) <= sub_wire6(75); - sub_wire2(11, 76) <= sub_wire6(76); - sub_wire2(11, 77) <= sub_wire6(77); - sub_wire2(11, 78) <= sub_wire6(78); - sub_wire2(11, 79) <= sub_wire6(79); - sub_wire2(11, 80) <= sub_wire6(80); - sub_wire2(11, 81) <= sub_wire6(81); - sub_wire2(11, 82) <= sub_wire6(82); - sub_wire2(11, 83) <= sub_wire6(83); - sub_wire2(11, 84) <= sub_wire6(84); - sub_wire2(11, 85) <= sub_wire6(85); - sub_wire2(11, 86) <= sub_wire6(86); - sub_wire2(11, 87) <= sub_wire6(87); - sub_wire2(11, 88) <= sub_wire6(88); - sub_wire2(11, 89) <= sub_wire6(89); - sub_wire2(11, 90) <= sub_wire6(90); - sub_wire2(11, 91) <= sub_wire6(91); - sub_wire2(11, 92) <= sub_wire6(92); - sub_wire2(11, 93) <= sub_wire6(93); - sub_wire2(11, 94) <= sub_wire6(94); - sub_wire2(11, 95) <= sub_wire6(95); - sub_wire2(11, 96) <= sub_wire6(96); - sub_wire2(11, 97) <= sub_wire6(97); - sub_wire2(11, 98) <= sub_wire6(98); - sub_wire2(11, 99) <= sub_wire6(99); - sub_wire2(11, 100) <= sub_wire6(100); - sub_wire2(11, 101) <= sub_wire6(101); - sub_wire2(11, 102) <= sub_wire6(102); - sub_wire2(11, 103) <= sub_wire6(103); - sub_wire2(11, 104) <= sub_wire6(104); - sub_wire2(11, 105) <= sub_wire6(105); - sub_wire2(11, 106) <= sub_wire6(106); - sub_wire2(11, 107) <= sub_wire6(107); - sub_wire2(11, 108) <= sub_wire6(108); - sub_wire2(11, 109) <= sub_wire6(109); - sub_wire2(11, 110) <= sub_wire6(110); - sub_wire2(11, 111) <= sub_wire6(111); - sub_wire2(11, 112) <= sub_wire6(112); - sub_wire2(11, 113) <= sub_wire6(113); - sub_wire2(11, 114) <= sub_wire6(114); - sub_wire2(11, 115) <= sub_wire6(115); - sub_wire2(11, 116) <= sub_wire6(116); - sub_wire2(11, 117) <= sub_wire6(117); - sub_wire2(11, 118) <= sub_wire6(118); - sub_wire2(11, 119) <= sub_wire6(119); - sub_wire2(11, 120) <= sub_wire6(120); - sub_wire2(11, 121) <= sub_wire6(121); - sub_wire2(11, 122) <= sub_wire6(122); - sub_wire2(11, 123) <= sub_wire6(123); - sub_wire2(11, 124) <= sub_wire6(124); - sub_wire2(11, 125) <= sub_wire6(125); - sub_wire2(11, 126) <= sub_wire6(126); - sub_wire2(11, 127) <= sub_wire6(127); - sub_wire2(10, 0) <= sub_wire7(0); - sub_wire2(10, 1) <= sub_wire7(1); - sub_wire2(10, 2) <= sub_wire7(2); - sub_wire2(10, 3) <= sub_wire7(3); - sub_wire2(10, 4) <= sub_wire7(4); - sub_wire2(10, 5) <= sub_wire7(5); - sub_wire2(10, 6) <= sub_wire7(6); - sub_wire2(10, 7) <= sub_wire7(7); - sub_wire2(10, 8) <= sub_wire7(8); - sub_wire2(10, 9) <= sub_wire7(9); - sub_wire2(10, 10) <= sub_wire7(10); - sub_wire2(10, 11) <= sub_wire7(11); - sub_wire2(10, 12) <= sub_wire7(12); - sub_wire2(10, 13) <= sub_wire7(13); - sub_wire2(10, 14) <= sub_wire7(14); - sub_wire2(10, 15) <= sub_wire7(15); - sub_wire2(10, 16) <= sub_wire7(16); - sub_wire2(10, 17) <= sub_wire7(17); - sub_wire2(10, 18) <= sub_wire7(18); - sub_wire2(10, 19) <= sub_wire7(19); - sub_wire2(10, 20) <= sub_wire7(20); - sub_wire2(10, 21) <= sub_wire7(21); - sub_wire2(10, 22) <= sub_wire7(22); - sub_wire2(10, 23) <= sub_wire7(23); - sub_wire2(10, 24) <= sub_wire7(24); - sub_wire2(10, 25) <= sub_wire7(25); - sub_wire2(10, 26) <= sub_wire7(26); - sub_wire2(10, 27) <= sub_wire7(27); - sub_wire2(10, 28) <= sub_wire7(28); - sub_wire2(10, 29) <= sub_wire7(29); - sub_wire2(10, 30) <= sub_wire7(30); - sub_wire2(10, 31) <= sub_wire7(31); - sub_wire2(10, 32) <= sub_wire7(32); - sub_wire2(10, 33) <= sub_wire7(33); - sub_wire2(10, 34) <= sub_wire7(34); - sub_wire2(10, 35) <= sub_wire7(35); - sub_wire2(10, 36) <= sub_wire7(36); - sub_wire2(10, 37) <= sub_wire7(37); - sub_wire2(10, 38) <= sub_wire7(38); - sub_wire2(10, 39) <= sub_wire7(39); - sub_wire2(10, 40) <= sub_wire7(40); - sub_wire2(10, 41) <= sub_wire7(41); - sub_wire2(10, 42) <= sub_wire7(42); - sub_wire2(10, 43) <= sub_wire7(43); - sub_wire2(10, 44) <= sub_wire7(44); - sub_wire2(10, 45) <= sub_wire7(45); - sub_wire2(10, 46) <= sub_wire7(46); - sub_wire2(10, 47) <= sub_wire7(47); - sub_wire2(10, 48) <= sub_wire7(48); - sub_wire2(10, 49) <= sub_wire7(49); - sub_wire2(10, 50) <= sub_wire7(50); - sub_wire2(10, 51) <= sub_wire7(51); - sub_wire2(10, 52) <= sub_wire7(52); - sub_wire2(10, 53) <= sub_wire7(53); - sub_wire2(10, 54) <= sub_wire7(54); - sub_wire2(10, 55) <= sub_wire7(55); - sub_wire2(10, 56) <= sub_wire7(56); - sub_wire2(10, 57) <= sub_wire7(57); - sub_wire2(10, 58) <= sub_wire7(58); - sub_wire2(10, 59) <= sub_wire7(59); - sub_wire2(10, 60) <= sub_wire7(60); - sub_wire2(10, 61) <= sub_wire7(61); - sub_wire2(10, 62) <= sub_wire7(62); - sub_wire2(10, 63) <= sub_wire7(63); - sub_wire2(10, 64) <= sub_wire7(64); - sub_wire2(10, 65) <= sub_wire7(65); - sub_wire2(10, 66) <= sub_wire7(66); - sub_wire2(10, 67) <= sub_wire7(67); - sub_wire2(10, 68) <= sub_wire7(68); - sub_wire2(10, 69) <= sub_wire7(69); - sub_wire2(10, 70) <= sub_wire7(70); - sub_wire2(10, 71) <= sub_wire7(71); - sub_wire2(10, 72) <= sub_wire7(72); - sub_wire2(10, 73) <= sub_wire7(73); - sub_wire2(10, 74) <= sub_wire7(74); - sub_wire2(10, 75) <= sub_wire7(75); - sub_wire2(10, 76) <= sub_wire7(76); - sub_wire2(10, 77) <= sub_wire7(77); - sub_wire2(10, 78) <= sub_wire7(78); - sub_wire2(10, 79) <= sub_wire7(79); - sub_wire2(10, 80) <= sub_wire7(80); - sub_wire2(10, 81) <= sub_wire7(81); - sub_wire2(10, 82) <= sub_wire7(82); - sub_wire2(10, 83) <= sub_wire7(83); - sub_wire2(10, 84) <= sub_wire7(84); - sub_wire2(10, 85) <= sub_wire7(85); - sub_wire2(10, 86) <= sub_wire7(86); - sub_wire2(10, 87) <= sub_wire7(87); - sub_wire2(10, 88) <= sub_wire7(88); - sub_wire2(10, 89) <= sub_wire7(89); - sub_wire2(10, 90) <= sub_wire7(90); - sub_wire2(10, 91) <= sub_wire7(91); - sub_wire2(10, 92) <= sub_wire7(92); - sub_wire2(10, 93) <= sub_wire7(93); - sub_wire2(10, 94) <= sub_wire7(94); - sub_wire2(10, 95) <= sub_wire7(95); - sub_wire2(10, 96) <= sub_wire7(96); - sub_wire2(10, 97) <= sub_wire7(97); - sub_wire2(10, 98) <= sub_wire7(98); - sub_wire2(10, 99) <= sub_wire7(99); - sub_wire2(10, 100) <= sub_wire7(100); - sub_wire2(10, 101) <= sub_wire7(101); - sub_wire2(10, 102) <= sub_wire7(102); - sub_wire2(10, 103) <= sub_wire7(103); - sub_wire2(10, 104) <= sub_wire7(104); - sub_wire2(10, 105) <= sub_wire7(105); - sub_wire2(10, 106) <= sub_wire7(106); - sub_wire2(10, 107) <= sub_wire7(107); - sub_wire2(10, 108) <= sub_wire7(108); - sub_wire2(10, 109) <= sub_wire7(109); - sub_wire2(10, 110) <= sub_wire7(110); - sub_wire2(10, 111) <= sub_wire7(111); - sub_wire2(10, 112) <= sub_wire7(112); - sub_wire2(10, 113) <= sub_wire7(113); - sub_wire2(10, 114) <= sub_wire7(114); - sub_wire2(10, 115) <= sub_wire7(115); - sub_wire2(10, 116) <= sub_wire7(116); - sub_wire2(10, 117) <= sub_wire7(117); - sub_wire2(10, 118) <= sub_wire7(118); - sub_wire2(10, 119) <= sub_wire7(119); - sub_wire2(10, 120) <= sub_wire7(120); - sub_wire2(10, 121) <= sub_wire7(121); - sub_wire2(10, 122) <= sub_wire7(122); - sub_wire2(10, 123) <= sub_wire7(123); - sub_wire2(10, 124) <= sub_wire7(124); - sub_wire2(10, 125) <= sub_wire7(125); - sub_wire2(10, 126) <= sub_wire7(126); - sub_wire2(10, 127) <= sub_wire7(127); - sub_wire2(9, 0) <= sub_wire8(0); - sub_wire2(9, 1) <= sub_wire8(1); - sub_wire2(9, 2) <= sub_wire8(2); - sub_wire2(9, 3) <= sub_wire8(3); - sub_wire2(9, 4) <= sub_wire8(4); - sub_wire2(9, 5) <= sub_wire8(5); - sub_wire2(9, 6) <= sub_wire8(6); - sub_wire2(9, 7) <= sub_wire8(7); - sub_wire2(9, 8) <= sub_wire8(8); - sub_wire2(9, 9) <= sub_wire8(9); - sub_wire2(9, 10) <= sub_wire8(10); - sub_wire2(9, 11) <= sub_wire8(11); - sub_wire2(9, 12) <= sub_wire8(12); - sub_wire2(9, 13) <= sub_wire8(13); - sub_wire2(9, 14) <= sub_wire8(14); - sub_wire2(9, 15) <= sub_wire8(15); - sub_wire2(9, 16) <= sub_wire8(16); - sub_wire2(9, 17) <= sub_wire8(17); - sub_wire2(9, 18) <= sub_wire8(18); - sub_wire2(9, 19) <= sub_wire8(19); - sub_wire2(9, 20) <= sub_wire8(20); - sub_wire2(9, 21) <= sub_wire8(21); - sub_wire2(9, 22) <= sub_wire8(22); - sub_wire2(9, 23) <= sub_wire8(23); - sub_wire2(9, 24) <= sub_wire8(24); - sub_wire2(9, 25) <= sub_wire8(25); - sub_wire2(9, 26) <= sub_wire8(26); - sub_wire2(9, 27) <= sub_wire8(27); - sub_wire2(9, 28) <= sub_wire8(28); - sub_wire2(9, 29) <= sub_wire8(29); - sub_wire2(9, 30) <= sub_wire8(30); - sub_wire2(9, 31) <= sub_wire8(31); - sub_wire2(9, 32) <= sub_wire8(32); - sub_wire2(9, 33) <= sub_wire8(33); - sub_wire2(9, 34) <= sub_wire8(34); - sub_wire2(9, 35) <= sub_wire8(35); - sub_wire2(9, 36) <= sub_wire8(36); - sub_wire2(9, 37) <= sub_wire8(37); - sub_wire2(9, 38) <= sub_wire8(38); - sub_wire2(9, 39) <= sub_wire8(39); - sub_wire2(9, 40) <= sub_wire8(40); - sub_wire2(9, 41) <= sub_wire8(41); - sub_wire2(9, 42) <= sub_wire8(42); - sub_wire2(9, 43) <= sub_wire8(43); - sub_wire2(9, 44) <= sub_wire8(44); - sub_wire2(9, 45) <= sub_wire8(45); - sub_wire2(9, 46) <= sub_wire8(46); - sub_wire2(9, 47) <= sub_wire8(47); - sub_wire2(9, 48) <= sub_wire8(48); - sub_wire2(9, 49) <= sub_wire8(49); - sub_wire2(9, 50) <= sub_wire8(50); - sub_wire2(9, 51) <= sub_wire8(51); - sub_wire2(9, 52) <= sub_wire8(52); - sub_wire2(9, 53) <= sub_wire8(53); - sub_wire2(9, 54) <= sub_wire8(54); - sub_wire2(9, 55) <= sub_wire8(55); - sub_wire2(9, 56) <= sub_wire8(56); - sub_wire2(9, 57) <= sub_wire8(57); - sub_wire2(9, 58) <= sub_wire8(58); - sub_wire2(9, 59) <= sub_wire8(59); - sub_wire2(9, 60) <= sub_wire8(60); - sub_wire2(9, 61) <= sub_wire8(61); - sub_wire2(9, 62) <= sub_wire8(62); - sub_wire2(9, 63) <= sub_wire8(63); - sub_wire2(9, 64) <= sub_wire8(64); - sub_wire2(9, 65) <= sub_wire8(65); - sub_wire2(9, 66) <= sub_wire8(66); - sub_wire2(9, 67) <= sub_wire8(67); - sub_wire2(9, 68) <= sub_wire8(68); - sub_wire2(9, 69) <= sub_wire8(69); - sub_wire2(9, 70) <= sub_wire8(70); - sub_wire2(9, 71) <= sub_wire8(71); - sub_wire2(9, 72) <= sub_wire8(72); - sub_wire2(9, 73) <= sub_wire8(73); - sub_wire2(9, 74) <= sub_wire8(74); - sub_wire2(9, 75) <= sub_wire8(75); - sub_wire2(9, 76) <= sub_wire8(76); - sub_wire2(9, 77) <= sub_wire8(77); - sub_wire2(9, 78) <= sub_wire8(78); - sub_wire2(9, 79) <= sub_wire8(79); - sub_wire2(9, 80) <= sub_wire8(80); - sub_wire2(9, 81) <= sub_wire8(81); - sub_wire2(9, 82) <= sub_wire8(82); - sub_wire2(9, 83) <= sub_wire8(83); - sub_wire2(9, 84) <= sub_wire8(84); - sub_wire2(9, 85) <= sub_wire8(85); - sub_wire2(9, 86) <= sub_wire8(86); - sub_wire2(9, 87) <= sub_wire8(87); - sub_wire2(9, 88) <= sub_wire8(88); - sub_wire2(9, 89) <= sub_wire8(89); - sub_wire2(9, 90) <= sub_wire8(90); - sub_wire2(9, 91) <= sub_wire8(91); - sub_wire2(9, 92) <= sub_wire8(92); - sub_wire2(9, 93) <= sub_wire8(93); - sub_wire2(9, 94) <= sub_wire8(94); - sub_wire2(9, 95) <= sub_wire8(95); - sub_wire2(9, 96) <= sub_wire8(96); - sub_wire2(9, 97) <= sub_wire8(97); - sub_wire2(9, 98) <= sub_wire8(98); - sub_wire2(9, 99) <= sub_wire8(99); - sub_wire2(9, 100) <= sub_wire8(100); - sub_wire2(9, 101) <= sub_wire8(101); - sub_wire2(9, 102) <= sub_wire8(102); - sub_wire2(9, 103) <= sub_wire8(103); - sub_wire2(9, 104) <= sub_wire8(104); - sub_wire2(9, 105) <= sub_wire8(105); - sub_wire2(9, 106) <= sub_wire8(106); - sub_wire2(9, 107) <= sub_wire8(107); - sub_wire2(9, 108) <= sub_wire8(108); - sub_wire2(9, 109) <= sub_wire8(109); - sub_wire2(9, 110) <= sub_wire8(110); - sub_wire2(9, 111) <= sub_wire8(111); - sub_wire2(9, 112) <= sub_wire8(112); - sub_wire2(9, 113) <= sub_wire8(113); - sub_wire2(9, 114) <= sub_wire8(114); - sub_wire2(9, 115) <= sub_wire8(115); - sub_wire2(9, 116) <= sub_wire8(116); - sub_wire2(9, 117) <= sub_wire8(117); - sub_wire2(9, 118) <= sub_wire8(118); - sub_wire2(9, 119) <= sub_wire8(119); - sub_wire2(9, 120) <= sub_wire8(120); - sub_wire2(9, 121) <= sub_wire8(121); - sub_wire2(9, 122) <= sub_wire8(122); - sub_wire2(9, 123) <= sub_wire8(123); - sub_wire2(9, 124) <= sub_wire8(124); - sub_wire2(9, 125) <= sub_wire8(125); - sub_wire2(9, 126) <= sub_wire8(126); - sub_wire2(9, 127) <= sub_wire8(127); - sub_wire2(8, 0) <= sub_wire9(0); - sub_wire2(8, 1) <= sub_wire9(1); - sub_wire2(8, 2) <= sub_wire9(2); - sub_wire2(8, 3) <= sub_wire9(3); - sub_wire2(8, 4) <= sub_wire9(4); - sub_wire2(8, 5) <= sub_wire9(5); - sub_wire2(8, 6) <= sub_wire9(6); - sub_wire2(8, 7) <= sub_wire9(7); - sub_wire2(8, 8) <= sub_wire9(8); - sub_wire2(8, 9) <= sub_wire9(9); - sub_wire2(8, 10) <= sub_wire9(10); - sub_wire2(8, 11) <= sub_wire9(11); - sub_wire2(8, 12) <= sub_wire9(12); - sub_wire2(8, 13) <= sub_wire9(13); - sub_wire2(8, 14) <= sub_wire9(14); - sub_wire2(8, 15) <= sub_wire9(15); - sub_wire2(8, 16) <= sub_wire9(16); - sub_wire2(8, 17) <= sub_wire9(17); - sub_wire2(8, 18) <= sub_wire9(18); - sub_wire2(8, 19) <= sub_wire9(19); - sub_wire2(8, 20) <= sub_wire9(20); - sub_wire2(8, 21) <= sub_wire9(21); - sub_wire2(8, 22) <= sub_wire9(22); - sub_wire2(8, 23) <= sub_wire9(23); - sub_wire2(8, 24) <= sub_wire9(24); - sub_wire2(8, 25) <= sub_wire9(25); - sub_wire2(8, 26) <= sub_wire9(26); - sub_wire2(8, 27) <= sub_wire9(27); - sub_wire2(8, 28) <= sub_wire9(28); - sub_wire2(8, 29) <= sub_wire9(29); - sub_wire2(8, 30) <= sub_wire9(30); - sub_wire2(8, 31) <= sub_wire9(31); - sub_wire2(8, 32) <= sub_wire9(32); - sub_wire2(8, 33) <= sub_wire9(33); - sub_wire2(8, 34) <= sub_wire9(34); - sub_wire2(8, 35) <= sub_wire9(35); - sub_wire2(8, 36) <= sub_wire9(36); - sub_wire2(8, 37) <= sub_wire9(37); - sub_wire2(8, 38) <= sub_wire9(38); - sub_wire2(8, 39) <= sub_wire9(39); - sub_wire2(8, 40) <= sub_wire9(40); - sub_wire2(8, 41) <= sub_wire9(41); - sub_wire2(8, 42) <= sub_wire9(42); - sub_wire2(8, 43) <= sub_wire9(43); - sub_wire2(8, 44) <= sub_wire9(44); - sub_wire2(8, 45) <= sub_wire9(45); - sub_wire2(8, 46) <= sub_wire9(46); - sub_wire2(8, 47) <= sub_wire9(47); - sub_wire2(8, 48) <= sub_wire9(48); - sub_wire2(8, 49) <= sub_wire9(49); - sub_wire2(8, 50) <= sub_wire9(50); - sub_wire2(8, 51) <= sub_wire9(51); - sub_wire2(8, 52) <= sub_wire9(52); - sub_wire2(8, 53) <= sub_wire9(53); - sub_wire2(8, 54) <= sub_wire9(54); - sub_wire2(8, 55) <= sub_wire9(55); - sub_wire2(8, 56) <= sub_wire9(56); - sub_wire2(8, 57) <= sub_wire9(57); - sub_wire2(8, 58) <= sub_wire9(58); - sub_wire2(8, 59) <= sub_wire9(59); - sub_wire2(8, 60) <= sub_wire9(60); - sub_wire2(8, 61) <= sub_wire9(61); - sub_wire2(8, 62) <= sub_wire9(62); - sub_wire2(8, 63) <= sub_wire9(63); - sub_wire2(8, 64) <= sub_wire9(64); - sub_wire2(8, 65) <= sub_wire9(65); - sub_wire2(8, 66) <= sub_wire9(66); - sub_wire2(8, 67) <= sub_wire9(67); - sub_wire2(8, 68) <= sub_wire9(68); - sub_wire2(8, 69) <= sub_wire9(69); - sub_wire2(8, 70) <= sub_wire9(70); - sub_wire2(8, 71) <= sub_wire9(71); - sub_wire2(8, 72) <= sub_wire9(72); - sub_wire2(8, 73) <= sub_wire9(73); - sub_wire2(8, 74) <= sub_wire9(74); - sub_wire2(8, 75) <= sub_wire9(75); - sub_wire2(8, 76) <= sub_wire9(76); - sub_wire2(8, 77) <= sub_wire9(77); - sub_wire2(8, 78) <= sub_wire9(78); - sub_wire2(8, 79) <= sub_wire9(79); - sub_wire2(8, 80) <= sub_wire9(80); - sub_wire2(8, 81) <= sub_wire9(81); - sub_wire2(8, 82) <= sub_wire9(82); - sub_wire2(8, 83) <= sub_wire9(83); - sub_wire2(8, 84) <= sub_wire9(84); - sub_wire2(8, 85) <= sub_wire9(85); - sub_wire2(8, 86) <= sub_wire9(86); - sub_wire2(8, 87) <= sub_wire9(87); - sub_wire2(8, 88) <= sub_wire9(88); - sub_wire2(8, 89) <= sub_wire9(89); - sub_wire2(8, 90) <= sub_wire9(90); - sub_wire2(8, 91) <= sub_wire9(91); - sub_wire2(8, 92) <= sub_wire9(92); - sub_wire2(8, 93) <= sub_wire9(93); - sub_wire2(8, 94) <= sub_wire9(94); - sub_wire2(8, 95) <= sub_wire9(95); - sub_wire2(8, 96) <= sub_wire9(96); - sub_wire2(8, 97) <= sub_wire9(97); - sub_wire2(8, 98) <= sub_wire9(98); - sub_wire2(8, 99) <= sub_wire9(99); - sub_wire2(8, 100) <= sub_wire9(100); - sub_wire2(8, 101) <= sub_wire9(101); - sub_wire2(8, 102) <= sub_wire9(102); - sub_wire2(8, 103) <= sub_wire9(103); - sub_wire2(8, 104) <= sub_wire9(104); - sub_wire2(8, 105) <= sub_wire9(105); - sub_wire2(8, 106) <= sub_wire9(106); - sub_wire2(8, 107) <= sub_wire9(107); - sub_wire2(8, 108) <= sub_wire9(108); - sub_wire2(8, 109) <= sub_wire9(109); - sub_wire2(8, 110) <= sub_wire9(110); - sub_wire2(8, 111) <= sub_wire9(111); - sub_wire2(8, 112) <= sub_wire9(112); - sub_wire2(8, 113) <= sub_wire9(113); - sub_wire2(8, 114) <= sub_wire9(114); - sub_wire2(8, 115) <= sub_wire9(115); - sub_wire2(8, 116) <= sub_wire9(116); - sub_wire2(8, 117) <= sub_wire9(117); - sub_wire2(8, 118) <= sub_wire9(118); - sub_wire2(8, 119) <= sub_wire9(119); - sub_wire2(8, 120) <= sub_wire9(120); - sub_wire2(8, 121) <= sub_wire9(121); - sub_wire2(8, 122) <= sub_wire9(122); - sub_wire2(8, 123) <= sub_wire9(123); - sub_wire2(8, 124) <= sub_wire9(124); - sub_wire2(8, 125) <= sub_wire9(125); - sub_wire2(8, 126) <= sub_wire9(126); - sub_wire2(8, 127) <= sub_wire9(127); - sub_wire2(7, 0) <= sub_wire10(0); - sub_wire2(7, 1) <= sub_wire10(1); - sub_wire2(7, 2) <= sub_wire10(2); - sub_wire2(7, 3) <= sub_wire10(3); - sub_wire2(7, 4) <= sub_wire10(4); - sub_wire2(7, 5) <= sub_wire10(5); - sub_wire2(7, 6) <= sub_wire10(6); - sub_wire2(7, 7) <= sub_wire10(7); - sub_wire2(7, 8) <= sub_wire10(8); - sub_wire2(7, 9) <= sub_wire10(9); - sub_wire2(7, 10) <= sub_wire10(10); - sub_wire2(7, 11) <= sub_wire10(11); - sub_wire2(7, 12) <= sub_wire10(12); - sub_wire2(7, 13) <= sub_wire10(13); - sub_wire2(7, 14) <= sub_wire10(14); - sub_wire2(7, 15) <= sub_wire10(15); - sub_wire2(7, 16) <= sub_wire10(16); - sub_wire2(7, 17) <= sub_wire10(17); - sub_wire2(7, 18) <= sub_wire10(18); - sub_wire2(7, 19) <= sub_wire10(19); - sub_wire2(7, 20) <= sub_wire10(20); - sub_wire2(7, 21) <= sub_wire10(21); - sub_wire2(7, 22) <= sub_wire10(22); - sub_wire2(7, 23) <= sub_wire10(23); - sub_wire2(7, 24) <= sub_wire10(24); - sub_wire2(7, 25) <= sub_wire10(25); - sub_wire2(7, 26) <= sub_wire10(26); - sub_wire2(7, 27) <= sub_wire10(27); - sub_wire2(7, 28) <= sub_wire10(28); - sub_wire2(7, 29) <= sub_wire10(29); - sub_wire2(7, 30) <= sub_wire10(30); - sub_wire2(7, 31) <= sub_wire10(31); - sub_wire2(7, 32) <= sub_wire10(32); - sub_wire2(7, 33) <= sub_wire10(33); - sub_wire2(7, 34) <= sub_wire10(34); - sub_wire2(7, 35) <= sub_wire10(35); - sub_wire2(7, 36) <= sub_wire10(36); - sub_wire2(7, 37) <= sub_wire10(37); - sub_wire2(7, 38) <= sub_wire10(38); - sub_wire2(7, 39) <= sub_wire10(39); - sub_wire2(7, 40) <= sub_wire10(40); - sub_wire2(7, 41) <= sub_wire10(41); - sub_wire2(7, 42) <= sub_wire10(42); - sub_wire2(7, 43) <= sub_wire10(43); - sub_wire2(7, 44) <= sub_wire10(44); - sub_wire2(7, 45) <= sub_wire10(45); - sub_wire2(7, 46) <= sub_wire10(46); - sub_wire2(7, 47) <= sub_wire10(47); - sub_wire2(7, 48) <= sub_wire10(48); - sub_wire2(7, 49) <= sub_wire10(49); - sub_wire2(7, 50) <= sub_wire10(50); - sub_wire2(7, 51) <= sub_wire10(51); - sub_wire2(7, 52) <= sub_wire10(52); - sub_wire2(7, 53) <= sub_wire10(53); - sub_wire2(7, 54) <= sub_wire10(54); - sub_wire2(7, 55) <= sub_wire10(55); - sub_wire2(7, 56) <= sub_wire10(56); - sub_wire2(7, 57) <= sub_wire10(57); - sub_wire2(7, 58) <= sub_wire10(58); - sub_wire2(7, 59) <= sub_wire10(59); - sub_wire2(7, 60) <= sub_wire10(60); - sub_wire2(7, 61) <= sub_wire10(61); - sub_wire2(7, 62) <= sub_wire10(62); - sub_wire2(7, 63) <= sub_wire10(63); - sub_wire2(7, 64) <= sub_wire10(64); - sub_wire2(7, 65) <= sub_wire10(65); - sub_wire2(7, 66) <= sub_wire10(66); - sub_wire2(7, 67) <= sub_wire10(67); - sub_wire2(7, 68) <= sub_wire10(68); - sub_wire2(7, 69) <= sub_wire10(69); - sub_wire2(7, 70) <= sub_wire10(70); - sub_wire2(7, 71) <= sub_wire10(71); - sub_wire2(7, 72) <= sub_wire10(72); - sub_wire2(7, 73) <= sub_wire10(73); - sub_wire2(7, 74) <= sub_wire10(74); - sub_wire2(7, 75) <= sub_wire10(75); - sub_wire2(7, 76) <= sub_wire10(76); - sub_wire2(7, 77) <= sub_wire10(77); - sub_wire2(7, 78) <= sub_wire10(78); - sub_wire2(7, 79) <= sub_wire10(79); - sub_wire2(7, 80) <= sub_wire10(80); - sub_wire2(7, 81) <= sub_wire10(81); - sub_wire2(7, 82) <= sub_wire10(82); - sub_wire2(7, 83) <= sub_wire10(83); - sub_wire2(7, 84) <= sub_wire10(84); - sub_wire2(7, 85) <= sub_wire10(85); - sub_wire2(7, 86) <= sub_wire10(86); - sub_wire2(7, 87) <= sub_wire10(87); - sub_wire2(7, 88) <= sub_wire10(88); - sub_wire2(7, 89) <= sub_wire10(89); - sub_wire2(7, 90) <= sub_wire10(90); - sub_wire2(7, 91) <= sub_wire10(91); - sub_wire2(7, 92) <= sub_wire10(92); - sub_wire2(7, 93) <= sub_wire10(93); - sub_wire2(7, 94) <= sub_wire10(94); - sub_wire2(7, 95) <= sub_wire10(95); - sub_wire2(7, 96) <= sub_wire10(96); - sub_wire2(7, 97) <= sub_wire10(97); - sub_wire2(7, 98) <= sub_wire10(98); - sub_wire2(7, 99) <= sub_wire10(99); - sub_wire2(7, 100) <= sub_wire10(100); - sub_wire2(7, 101) <= sub_wire10(101); - sub_wire2(7, 102) <= sub_wire10(102); - sub_wire2(7, 103) <= sub_wire10(103); - sub_wire2(7, 104) <= sub_wire10(104); - sub_wire2(7, 105) <= sub_wire10(105); - sub_wire2(7, 106) <= sub_wire10(106); - sub_wire2(7, 107) <= sub_wire10(107); - sub_wire2(7, 108) <= sub_wire10(108); - sub_wire2(7, 109) <= sub_wire10(109); - sub_wire2(7, 110) <= sub_wire10(110); - sub_wire2(7, 111) <= sub_wire10(111); - sub_wire2(7, 112) <= sub_wire10(112); - sub_wire2(7, 113) <= sub_wire10(113); - sub_wire2(7, 114) <= sub_wire10(114); - sub_wire2(7, 115) <= sub_wire10(115); - sub_wire2(7, 116) <= sub_wire10(116); - sub_wire2(7, 117) <= sub_wire10(117); - sub_wire2(7, 118) <= sub_wire10(118); - sub_wire2(7, 119) <= sub_wire10(119); - sub_wire2(7, 120) <= sub_wire10(120); - sub_wire2(7, 121) <= sub_wire10(121); - sub_wire2(7, 122) <= sub_wire10(122); - sub_wire2(7, 123) <= sub_wire10(123); - sub_wire2(7, 124) <= sub_wire10(124); - sub_wire2(7, 125) <= sub_wire10(125); - sub_wire2(7, 126) <= sub_wire10(126); - sub_wire2(7, 127) <= sub_wire10(127); - sub_wire2(6, 0) <= sub_wire11(0); - sub_wire2(6, 1) <= sub_wire11(1); - sub_wire2(6, 2) <= sub_wire11(2); - sub_wire2(6, 3) <= sub_wire11(3); - sub_wire2(6, 4) <= sub_wire11(4); - sub_wire2(6, 5) <= sub_wire11(5); - sub_wire2(6, 6) <= sub_wire11(6); - sub_wire2(6, 7) <= sub_wire11(7); - sub_wire2(6, 8) <= sub_wire11(8); - sub_wire2(6, 9) <= sub_wire11(9); - sub_wire2(6, 10) <= sub_wire11(10); - sub_wire2(6, 11) <= sub_wire11(11); - sub_wire2(6, 12) <= sub_wire11(12); - sub_wire2(6, 13) <= sub_wire11(13); - sub_wire2(6, 14) <= sub_wire11(14); - sub_wire2(6, 15) <= sub_wire11(15); - sub_wire2(6, 16) <= sub_wire11(16); - sub_wire2(6, 17) <= sub_wire11(17); - sub_wire2(6, 18) <= sub_wire11(18); - sub_wire2(6, 19) <= sub_wire11(19); - sub_wire2(6, 20) <= sub_wire11(20); - sub_wire2(6, 21) <= sub_wire11(21); - sub_wire2(6, 22) <= sub_wire11(22); - sub_wire2(6, 23) <= sub_wire11(23); - sub_wire2(6, 24) <= sub_wire11(24); - sub_wire2(6, 25) <= sub_wire11(25); - sub_wire2(6, 26) <= sub_wire11(26); - sub_wire2(6, 27) <= sub_wire11(27); - sub_wire2(6, 28) <= sub_wire11(28); - sub_wire2(6, 29) <= sub_wire11(29); - sub_wire2(6, 30) <= sub_wire11(30); - sub_wire2(6, 31) <= sub_wire11(31); - sub_wire2(6, 32) <= sub_wire11(32); - sub_wire2(6, 33) <= sub_wire11(33); - sub_wire2(6, 34) <= sub_wire11(34); - sub_wire2(6, 35) <= sub_wire11(35); - sub_wire2(6, 36) <= sub_wire11(36); - sub_wire2(6, 37) <= sub_wire11(37); - sub_wire2(6, 38) <= sub_wire11(38); - sub_wire2(6, 39) <= sub_wire11(39); - sub_wire2(6, 40) <= sub_wire11(40); - sub_wire2(6, 41) <= sub_wire11(41); - sub_wire2(6, 42) <= sub_wire11(42); - sub_wire2(6, 43) <= sub_wire11(43); - sub_wire2(6, 44) <= sub_wire11(44); - sub_wire2(6, 45) <= sub_wire11(45); - sub_wire2(6, 46) <= sub_wire11(46); - sub_wire2(6, 47) <= sub_wire11(47); - sub_wire2(6, 48) <= sub_wire11(48); - sub_wire2(6, 49) <= sub_wire11(49); - sub_wire2(6, 50) <= sub_wire11(50); - sub_wire2(6, 51) <= sub_wire11(51); - sub_wire2(6, 52) <= sub_wire11(52); - sub_wire2(6, 53) <= sub_wire11(53); - sub_wire2(6, 54) <= sub_wire11(54); - sub_wire2(6, 55) <= sub_wire11(55); - sub_wire2(6, 56) <= sub_wire11(56); - sub_wire2(6, 57) <= sub_wire11(57); - sub_wire2(6, 58) <= sub_wire11(58); - sub_wire2(6, 59) <= sub_wire11(59); - sub_wire2(6, 60) <= sub_wire11(60); - sub_wire2(6, 61) <= sub_wire11(61); - sub_wire2(6, 62) <= sub_wire11(62); - sub_wire2(6, 63) <= sub_wire11(63); - sub_wire2(6, 64) <= sub_wire11(64); - sub_wire2(6, 65) <= sub_wire11(65); - sub_wire2(6, 66) <= sub_wire11(66); - sub_wire2(6, 67) <= sub_wire11(67); - sub_wire2(6, 68) <= sub_wire11(68); - sub_wire2(6, 69) <= sub_wire11(69); - sub_wire2(6, 70) <= sub_wire11(70); - sub_wire2(6, 71) <= sub_wire11(71); - sub_wire2(6, 72) <= sub_wire11(72); - sub_wire2(6, 73) <= sub_wire11(73); - sub_wire2(6, 74) <= sub_wire11(74); - sub_wire2(6, 75) <= sub_wire11(75); - sub_wire2(6, 76) <= sub_wire11(76); - sub_wire2(6, 77) <= sub_wire11(77); - sub_wire2(6, 78) <= sub_wire11(78); - sub_wire2(6, 79) <= sub_wire11(79); - sub_wire2(6, 80) <= sub_wire11(80); - sub_wire2(6, 81) <= sub_wire11(81); - sub_wire2(6, 82) <= sub_wire11(82); - sub_wire2(6, 83) <= sub_wire11(83); - sub_wire2(6, 84) <= sub_wire11(84); - sub_wire2(6, 85) <= sub_wire11(85); - sub_wire2(6, 86) <= sub_wire11(86); - sub_wire2(6, 87) <= sub_wire11(87); - sub_wire2(6, 88) <= sub_wire11(88); - sub_wire2(6, 89) <= sub_wire11(89); - sub_wire2(6, 90) <= sub_wire11(90); - sub_wire2(6, 91) <= sub_wire11(91); - sub_wire2(6, 92) <= sub_wire11(92); - sub_wire2(6, 93) <= sub_wire11(93); - sub_wire2(6, 94) <= sub_wire11(94); - sub_wire2(6, 95) <= sub_wire11(95); - sub_wire2(6, 96) <= sub_wire11(96); - sub_wire2(6, 97) <= sub_wire11(97); - sub_wire2(6, 98) <= sub_wire11(98); - sub_wire2(6, 99) <= sub_wire11(99); - sub_wire2(6, 100) <= sub_wire11(100); - sub_wire2(6, 101) <= sub_wire11(101); - sub_wire2(6, 102) <= sub_wire11(102); - sub_wire2(6, 103) <= sub_wire11(103); - sub_wire2(6, 104) <= sub_wire11(104); - sub_wire2(6, 105) <= sub_wire11(105); - sub_wire2(6, 106) <= sub_wire11(106); - sub_wire2(6, 107) <= sub_wire11(107); - sub_wire2(6, 108) <= sub_wire11(108); - sub_wire2(6, 109) <= sub_wire11(109); - sub_wire2(6, 110) <= sub_wire11(110); - sub_wire2(6, 111) <= sub_wire11(111); - sub_wire2(6, 112) <= sub_wire11(112); - sub_wire2(6, 113) <= sub_wire11(113); - sub_wire2(6, 114) <= sub_wire11(114); - sub_wire2(6, 115) <= sub_wire11(115); - sub_wire2(6, 116) <= sub_wire11(116); - sub_wire2(6, 117) <= sub_wire11(117); - sub_wire2(6, 118) <= sub_wire11(118); - sub_wire2(6, 119) <= sub_wire11(119); - sub_wire2(6, 120) <= sub_wire11(120); - sub_wire2(6, 121) <= sub_wire11(121); - sub_wire2(6, 122) <= sub_wire11(122); - sub_wire2(6, 123) <= sub_wire11(123); - sub_wire2(6, 124) <= sub_wire11(124); - sub_wire2(6, 125) <= sub_wire11(125); - sub_wire2(6, 126) <= sub_wire11(126); - sub_wire2(6, 127) <= sub_wire11(127); - sub_wire2(5, 0) <= sub_wire12(0); - sub_wire2(5, 1) <= sub_wire12(1); - sub_wire2(5, 2) <= sub_wire12(2); - sub_wire2(5, 3) <= sub_wire12(3); - sub_wire2(5, 4) <= sub_wire12(4); - sub_wire2(5, 5) <= sub_wire12(5); - sub_wire2(5, 6) <= sub_wire12(6); - sub_wire2(5, 7) <= sub_wire12(7); - sub_wire2(5, 8) <= sub_wire12(8); - sub_wire2(5, 9) <= sub_wire12(9); - sub_wire2(5, 10) <= sub_wire12(10); - sub_wire2(5, 11) <= sub_wire12(11); - sub_wire2(5, 12) <= sub_wire12(12); - sub_wire2(5, 13) <= sub_wire12(13); - sub_wire2(5, 14) <= sub_wire12(14); - sub_wire2(5, 15) <= sub_wire12(15); - sub_wire2(5, 16) <= sub_wire12(16); - sub_wire2(5, 17) <= sub_wire12(17); - sub_wire2(5, 18) <= sub_wire12(18); - sub_wire2(5, 19) <= sub_wire12(19); - sub_wire2(5, 20) <= sub_wire12(20); - sub_wire2(5, 21) <= sub_wire12(21); - sub_wire2(5, 22) <= sub_wire12(22); - sub_wire2(5, 23) <= sub_wire12(23); - sub_wire2(5, 24) <= sub_wire12(24); - sub_wire2(5, 25) <= sub_wire12(25); - sub_wire2(5, 26) <= sub_wire12(26); - sub_wire2(5, 27) <= sub_wire12(27); - sub_wire2(5, 28) <= sub_wire12(28); - sub_wire2(5, 29) <= sub_wire12(29); - sub_wire2(5, 30) <= sub_wire12(30); - sub_wire2(5, 31) <= sub_wire12(31); - sub_wire2(5, 32) <= sub_wire12(32); - sub_wire2(5, 33) <= sub_wire12(33); - sub_wire2(5, 34) <= sub_wire12(34); - sub_wire2(5, 35) <= sub_wire12(35); - sub_wire2(5, 36) <= sub_wire12(36); - sub_wire2(5, 37) <= sub_wire12(37); - sub_wire2(5, 38) <= sub_wire12(38); - sub_wire2(5, 39) <= sub_wire12(39); - sub_wire2(5, 40) <= sub_wire12(40); - sub_wire2(5, 41) <= sub_wire12(41); - sub_wire2(5, 42) <= sub_wire12(42); - sub_wire2(5, 43) <= sub_wire12(43); - sub_wire2(5, 44) <= sub_wire12(44); - sub_wire2(5, 45) <= sub_wire12(45); - sub_wire2(5, 46) <= sub_wire12(46); - sub_wire2(5, 47) <= sub_wire12(47); - sub_wire2(5, 48) <= sub_wire12(48); - sub_wire2(5, 49) <= sub_wire12(49); - sub_wire2(5, 50) <= sub_wire12(50); - sub_wire2(5, 51) <= sub_wire12(51); - sub_wire2(5, 52) <= sub_wire12(52); - sub_wire2(5, 53) <= sub_wire12(53); - sub_wire2(5, 54) <= sub_wire12(54); - sub_wire2(5, 55) <= sub_wire12(55); - sub_wire2(5, 56) <= sub_wire12(56); - sub_wire2(5, 57) <= sub_wire12(57); - sub_wire2(5, 58) <= sub_wire12(58); - sub_wire2(5, 59) <= sub_wire12(59); - sub_wire2(5, 60) <= sub_wire12(60); - sub_wire2(5, 61) <= sub_wire12(61); - sub_wire2(5, 62) <= sub_wire12(62); - sub_wire2(5, 63) <= sub_wire12(63); - sub_wire2(5, 64) <= sub_wire12(64); - sub_wire2(5, 65) <= sub_wire12(65); - sub_wire2(5, 66) <= sub_wire12(66); - sub_wire2(5, 67) <= sub_wire12(67); - sub_wire2(5, 68) <= sub_wire12(68); - sub_wire2(5, 69) <= sub_wire12(69); - sub_wire2(5, 70) <= sub_wire12(70); - sub_wire2(5, 71) <= sub_wire12(71); - sub_wire2(5, 72) <= sub_wire12(72); - sub_wire2(5, 73) <= sub_wire12(73); - sub_wire2(5, 74) <= sub_wire12(74); - sub_wire2(5, 75) <= sub_wire12(75); - sub_wire2(5, 76) <= sub_wire12(76); - sub_wire2(5, 77) <= sub_wire12(77); - sub_wire2(5, 78) <= sub_wire12(78); - sub_wire2(5, 79) <= sub_wire12(79); - sub_wire2(5, 80) <= sub_wire12(80); - sub_wire2(5, 81) <= sub_wire12(81); - sub_wire2(5, 82) <= sub_wire12(82); - sub_wire2(5, 83) <= sub_wire12(83); - sub_wire2(5, 84) <= sub_wire12(84); - sub_wire2(5, 85) <= sub_wire12(85); - sub_wire2(5, 86) <= sub_wire12(86); - sub_wire2(5, 87) <= sub_wire12(87); - sub_wire2(5, 88) <= sub_wire12(88); - sub_wire2(5, 89) <= sub_wire12(89); - sub_wire2(5, 90) <= sub_wire12(90); - sub_wire2(5, 91) <= sub_wire12(91); - sub_wire2(5, 92) <= sub_wire12(92); - sub_wire2(5, 93) <= sub_wire12(93); - sub_wire2(5, 94) <= sub_wire12(94); - sub_wire2(5, 95) <= sub_wire12(95); - sub_wire2(5, 96) <= sub_wire12(96); - sub_wire2(5, 97) <= sub_wire12(97); - sub_wire2(5, 98) <= sub_wire12(98); - sub_wire2(5, 99) <= sub_wire12(99); - sub_wire2(5, 100) <= sub_wire12(100); - sub_wire2(5, 101) <= sub_wire12(101); - sub_wire2(5, 102) <= sub_wire12(102); - sub_wire2(5, 103) <= sub_wire12(103); - sub_wire2(5, 104) <= sub_wire12(104); - sub_wire2(5, 105) <= sub_wire12(105); - sub_wire2(5, 106) <= sub_wire12(106); - sub_wire2(5, 107) <= sub_wire12(107); - sub_wire2(5, 108) <= sub_wire12(108); - sub_wire2(5, 109) <= sub_wire12(109); - sub_wire2(5, 110) <= sub_wire12(110); - sub_wire2(5, 111) <= sub_wire12(111); - sub_wire2(5, 112) <= sub_wire12(112); - sub_wire2(5, 113) <= sub_wire12(113); - sub_wire2(5, 114) <= sub_wire12(114); - sub_wire2(5, 115) <= sub_wire12(115); - sub_wire2(5, 116) <= sub_wire12(116); - sub_wire2(5, 117) <= sub_wire12(117); - sub_wire2(5, 118) <= sub_wire12(118); - sub_wire2(5, 119) <= sub_wire12(119); - sub_wire2(5, 120) <= sub_wire12(120); - sub_wire2(5, 121) <= sub_wire12(121); - sub_wire2(5, 122) <= sub_wire12(122); - sub_wire2(5, 123) <= sub_wire12(123); - sub_wire2(5, 124) <= sub_wire12(124); - sub_wire2(5, 125) <= sub_wire12(125); - sub_wire2(5, 126) <= sub_wire12(126); - sub_wire2(5, 127) <= sub_wire12(127); - sub_wire2(4, 0) <= sub_wire13(0); - sub_wire2(4, 1) <= sub_wire13(1); - sub_wire2(4, 2) <= sub_wire13(2); - sub_wire2(4, 3) <= sub_wire13(3); - sub_wire2(4, 4) <= sub_wire13(4); - sub_wire2(4, 5) <= sub_wire13(5); - sub_wire2(4, 6) <= sub_wire13(6); - sub_wire2(4, 7) <= sub_wire13(7); - sub_wire2(4, 8) <= sub_wire13(8); - sub_wire2(4, 9) <= sub_wire13(9); - sub_wire2(4, 10) <= sub_wire13(10); - sub_wire2(4, 11) <= sub_wire13(11); - sub_wire2(4, 12) <= sub_wire13(12); - sub_wire2(4, 13) <= sub_wire13(13); - sub_wire2(4, 14) <= sub_wire13(14); - sub_wire2(4, 15) <= sub_wire13(15); - sub_wire2(4, 16) <= sub_wire13(16); - sub_wire2(4, 17) <= sub_wire13(17); - sub_wire2(4, 18) <= sub_wire13(18); - sub_wire2(4, 19) <= sub_wire13(19); - sub_wire2(4, 20) <= sub_wire13(20); - sub_wire2(4, 21) <= sub_wire13(21); - sub_wire2(4, 22) <= sub_wire13(22); - sub_wire2(4, 23) <= sub_wire13(23); - sub_wire2(4, 24) <= sub_wire13(24); - sub_wire2(4, 25) <= sub_wire13(25); - sub_wire2(4, 26) <= sub_wire13(26); - sub_wire2(4, 27) <= sub_wire13(27); - sub_wire2(4, 28) <= sub_wire13(28); - sub_wire2(4, 29) <= sub_wire13(29); - sub_wire2(4, 30) <= sub_wire13(30); - sub_wire2(4, 31) <= sub_wire13(31); - sub_wire2(4, 32) <= sub_wire13(32); - sub_wire2(4, 33) <= sub_wire13(33); - sub_wire2(4, 34) <= sub_wire13(34); - sub_wire2(4, 35) <= sub_wire13(35); - sub_wire2(4, 36) <= sub_wire13(36); - sub_wire2(4, 37) <= sub_wire13(37); - sub_wire2(4, 38) <= sub_wire13(38); - sub_wire2(4, 39) <= sub_wire13(39); - sub_wire2(4, 40) <= sub_wire13(40); - sub_wire2(4, 41) <= sub_wire13(41); - sub_wire2(4, 42) <= sub_wire13(42); - sub_wire2(4, 43) <= sub_wire13(43); - sub_wire2(4, 44) <= sub_wire13(44); - sub_wire2(4, 45) <= sub_wire13(45); - sub_wire2(4, 46) <= sub_wire13(46); - sub_wire2(4, 47) <= sub_wire13(47); - sub_wire2(4, 48) <= sub_wire13(48); - sub_wire2(4, 49) <= sub_wire13(49); - sub_wire2(4, 50) <= sub_wire13(50); - sub_wire2(4, 51) <= sub_wire13(51); - sub_wire2(4, 52) <= sub_wire13(52); - sub_wire2(4, 53) <= sub_wire13(53); - sub_wire2(4, 54) <= sub_wire13(54); - sub_wire2(4, 55) <= sub_wire13(55); - sub_wire2(4, 56) <= sub_wire13(56); - sub_wire2(4, 57) <= sub_wire13(57); - sub_wire2(4, 58) <= sub_wire13(58); - sub_wire2(4, 59) <= sub_wire13(59); - sub_wire2(4, 60) <= sub_wire13(60); - sub_wire2(4, 61) <= sub_wire13(61); - sub_wire2(4, 62) <= sub_wire13(62); - sub_wire2(4, 63) <= sub_wire13(63); - sub_wire2(4, 64) <= sub_wire13(64); - sub_wire2(4, 65) <= sub_wire13(65); - sub_wire2(4, 66) <= sub_wire13(66); - sub_wire2(4, 67) <= sub_wire13(67); - sub_wire2(4, 68) <= sub_wire13(68); - sub_wire2(4, 69) <= sub_wire13(69); - sub_wire2(4, 70) <= sub_wire13(70); - sub_wire2(4, 71) <= sub_wire13(71); - sub_wire2(4, 72) <= sub_wire13(72); - sub_wire2(4, 73) <= sub_wire13(73); - sub_wire2(4, 74) <= sub_wire13(74); - sub_wire2(4, 75) <= sub_wire13(75); - sub_wire2(4, 76) <= sub_wire13(76); - sub_wire2(4, 77) <= sub_wire13(77); - sub_wire2(4, 78) <= sub_wire13(78); - sub_wire2(4, 79) <= sub_wire13(79); - sub_wire2(4, 80) <= sub_wire13(80); - sub_wire2(4, 81) <= sub_wire13(81); - sub_wire2(4, 82) <= sub_wire13(82); - sub_wire2(4, 83) <= sub_wire13(83); - sub_wire2(4, 84) <= sub_wire13(84); - sub_wire2(4, 85) <= sub_wire13(85); - sub_wire2(4, 86) <= sub_wire13(86); - sub_wire2(4, 87) <= sub_wire13(87); - sub_wire2(4, 88) <= sub_wire13(88); - sub_wire2(4, 89) <= sub_wire13(89); - sub_wire2(4, 90) <= sub_wire13(90); - sub_wire2(4, 91) <= sub_wire13(91); - sub_wire2(4, 92) <= sub_wire13(92); - sub_wire2(4, 93) <= sub_wire13(93); - sub_wire2(4, 94) <= sub_wire13(94); - sub_wire2(4, 95) <= sub_wire13(95); - sub_wire2(4, 96) <= sub_wire13(96); - sub_wire2(4, 97) <= sub_wire13(97); - sub_wire2(4, 98) <= sub_wire13(98); - sub_wire2(4, 99) <= sub_wire13(99); - sub_wire2(4, 100) <= sub_wire13(100); - sub_wire2(4, 101) <= sub_wire13(101); - sub_wire2(4, 102) <= sub_wire13(102); - sub_wire2(4, 103) <= sub_wire13(103); - sub_wire2(4, 104) <= sub_wire13(104); - sub_wire2(4, 105) <= sub_wire13(105); - sub_wire2(4, 106) <= sub_wire13(106); - sub_wire2(4, 107) <= sub_wire13(107); - sub_wire2(4, 108) <= sub_wire13(108); - sub_wire2(4, 109) <= sub_wire13(109); - sub_wire2(4, 110) <= sub_wire13(110); - sub_wire2(4, 111) <= sub_wire13(111); - sub_wire2(4, 112) <= sub_wire13(112); - sub_wire2(4, 113) <= sub_wire13(113); - sub_wire2(4, 114) <= sub_wire13(114); - sub_wire2(4, 115) <= sub_wire13(115); - sub_wire2(4, 116) <= sub_wire13(116); - sub_wire2(4, 117) <= sub_wire13(117); - sub_wire2(4, 118) <= sub_wire13(118); - sub_wire2(4, 119) <= sub_wire13(119); - sub_wire2(4, 120) <= sub_wire13(120); - sub_wire2(4, 121) <= sub_wire13(121); - sub_wire2(4, 122) <= sub_wire13(122); - sub_wire2(4, 123) <= sub_wire13(123); - sub_wire2(4, 124) <= sub_wire13(124); - sub_wire2(4, 125) <= sub_wire13(125); - sub_wire2(4, 126) <= sub_wire13(126); - sub_wire2(4, 127) <= sub_wire13(127); - sub_wire2(3, 0) <= sub_wire14(0); - sub_wire2(3, 1) <= sub_wire14(1); - sub_wire2(3, 2) <= sub_wire14(2); - sub_wire2(3, 3) <= sub_wire14(3); - sub_wire2(3, 4) <= sub_wire14(4); - sub_wire2(3, 5) <= sub_wire14(5); - sub_wire2(3, 6) <= sub_wire14(6); - sub_wire2(3, 7) <= sub_wire14(7); - sub_wire2(3, 8) <= sub_wire14(8); - sub_wire2(3, 9) <= sub_wire14(9); - sub_wire2(3, 10) <= sub_wire14(10); - sub_wire2(3, 11) <= sub_wire14(11); - sub_wire2(3, 12) <= sub_wire14(12); - sub_wire2(3, 13) <= sub_wire14(13); - sub_wire2(3, 14) <= sub_wire14(14); - sub_wire2(3, 15) <= sub_wire14(15); - sub_wire2(3, 16) <= sub_wire14(16); - sub_wire2(3, 17) <= sub_wire14(17); - sub_wire2(3, 18) <= sub_wire14(18); - sub_wire2(3, 19) <= sub_wire14(19); - sub_wire2(3, 20) <= sub_wire14(20); - sub_wire2(3, 21) <= sub_wire14(21); - sub_wire2(3, 22) <= sub_wire14(22); - sub_wire2(3, 23) <= sub_wire14(23); - sub_wire2(3, 24) <= sub_wire14(24); - sub_wire2(3, 25) <= sub_wire14(25); - sub_wire2(3, 26) <= sub_wire14(26); - sub_wire2(3, 27) <= sub_wire14(27); - sub_wire2(3, 28) <= sub_wire14(28); - sub_wire2(3, 29) <= sub_wire14(29); - sub_wire2(3, 30) <= sub_wire14(30); - sub_wire2(3, 31) <= sub_wire14(31); - sub_wire2(3, 32) <= sub_wire14(32); - sub_wire2(3, 33) <= sub_wire14(33); - sub_wire2(3, 34) <= sub_wire14(34); - sub_wire2(3, 35) <= sub_wire14(35); - sub_wire2(3, 36) <= sub_wire14(36); - sub_wire2(3, 37) <= sub_wire14(37); - sub_wire2(3, 38) <= sub_wire14(38); - sub_wire2(3, 39) <= sub_wire14(39); - sub_wire2(3, 40) <= sub_wire14(40); - sub_wire2(3, 41) <= sub_wire14(41); - sub_wire2(3, 42) <= sub_wire14(42); - sub_wire2(3, 43) <= sub_wire14(43); - sub_wire2(3, 44) <= sub_wire14(44); - sub_wire2(3, 45) <= sub_wire14(45); - sub_wire2(3, 46) <= sub_wire14(46); - sub_wire2(3, 47) <= sub_wire14(47); - sub_wire2(3, 48) <= sub_wire14(48); - sub_wire2(3, 49) <= sub_wire14(49); - sub_wire2(3, 50) <= sub_wire14(50); - sub_wire2(3, 51) <= sub_wire14(51); - sub_wire2(3, 52) <= sub_wire14(52); - sub_wire2(3, 53) <= sub_wire14(53); - sub_wire2(3, 54) <= sub_wire14(54); - sub_wire2(3, 55) <= sub_wire14(55); - sub_wire2(3, 56) <= sub_wire14(56); - sub_wire2(3, 57) <= sub_wire14(57); - sub_wire2(3, 58) <= sub_wire14(58); - sub_wire2(3, 59) <= sub_wire14(59); - sub_wire2(3, 60) <= sub_wire14(60); - sub_wire2(3, 61) <= sub_wire14(61); - sub_wire2(3, 62) <= sub_wire14(62); - sub_wire2(3, 63) <= sub_wire14(63); - sub_wire2(3, 64) <= sub_wire14(64); - sub_wire2(3, 65) <= sub_wire14(65); - sub_wire2(3, 66) <= sub_wire14(66); - sub_wire2(3, 67) <= sub_wire14(67); - sub_wire2(3, 68) <= sub_wire14(68); - sub_wire2(3, 69) <= sub_wire14(69); - sub_wire2(3, 70) <= sub_wire14(70); - sub_wire2(3, 71) <= sub_wire14(71); - sub_wire2(3, 72) <= sub_wire14(72); - sub_wire2(3, 73) <= sub_wire14(73); - sub_wire2(3, 74) <= sub_wire14(74); - sub_wire2(3, 75) <= sub_wire14(75); - sub_wire2(3, 76) <= sub_wire14(76); - sub_wire2(3, 77) <= sub_wire14(77); - sub_wire2(3, 78) <= sub_wire14(78); - sub_wire2(3, 79) <= sub_wire14(79); - sub_wire2(3, 80) <= sub_wire14(80); - sub_wire2(3, 81) <= sub_wire14(81); - sub_wire2(3, 82) <= sub_wire14(82); - sub_wire2(3, 83) <= sub_wire14(83); - sub_wire2(3, 84) <= sub_wire14(84); - sub_wire2(3, 85) <= sub_wire14(85); - sub_wire2(3, 86) <= sub_wire14(86); - sub_wire2(3, 87) <= sub_wire14(87); - sub_wire2(3, 88) <= sub_wire14(88); - sub_wire2(3, 89) <= sub_wire14(89); - sub_wire2(3, 90) <= sub_wire14(90); - sub_wire2(3, 91) <= sub_wire14(91); - sub_wire2(3, 92) <= sub_wire14(92); - sub_wire2(3, 93) <= sub_wire14(93); - sub_wire2(3, 94) <= sub_wire14(94); - sub_wire2(3, 95) <= sub_wire14(95); - sub_wire2(3, 96) <= sub_wire14(96); - sub_wire2(3, 97) <= sub_wire14(97); - sub_wire2(3, 98) <= sub_wire14(98); - sub_wire2(3, 99) <= sub_wire14(99); - sub_wire2(3, 100) <= sub_wire14(100); - sub_wire2(3, 101) <= sub_wire14(101); - sub_wire2(3, 102) <= sub_wire14(102); - sub_wire2(3, 103) <= sub_wire14(103); - sub_wire2(3, 104) <= sub_wire14(104); - sub_wire2(3, 105) <= sub_wire14(105); - sub_wire2(3, 106) <= sub_wire14(106); - sub_wire2(3, 107) <= sub_wire14(107); - sub_wire2(3, 108) <= sub_wire14(108); - sub_wire2(3, 109) <= sub_wire14(109); - sub_wire2(3, 110) <= sub_wire14(110); - sub_wire2(3, 111) <= sub_wire14(111); - sub_wire2(3, 112) <= sub_wire14(112); - sub_wire2(3, 113) <= sub_wire14(113); - sub_wire2(3, 114) <= sub_wire14(114); - sub_wire2(3, 115) <= sub_wire14(115); - sub_wire2(3, 116) <= sub_wire14(116); - sub_wire2(3, 117) <= sub_wire14(117); - sub_wire2(3, 118) <= sub_wire14(118); - sub_wire2(3, 119) <= sub_wire14(119); - sub_wire2(3, 120) <= sub_wire14(120); - sub_wire2(3, 121) <= sub_wire14(121); - sub_wire2(3, 122) <= sub_wire14(122); - sub_wire2(3, 123) <= sub_wire14(123); - sub_wire2(3, 124) <= sub_wire14(124); - sub_wire2(3, 125) <= sub_wire14(125); - sub_wire2(3, 126) <= sub_wire14(126); - sub_wire2(3, 127) <= sub_wire14(127); - sub_wire2(2, 0) <= sub_wire15(0); - sub_wire2(2, 1) <= sub_wire15(1); - sub_wire2(2, 2) <= sub_wire15(2); - sub_wire2(2, 3) <= sub_wire15(3); - sub_wire2(2, 4) <= sub_wire15(4); - sub_wire2(2, 5) <= sub_wire15(5); - sub_wire2(2, 6) <= sub_wire15(6); - sub_wire2(2, 7) <= sub_wire15(7); - sub_wire2(2, 8) <= sub_wire15(8); - sub_wire2(2, 9) <= sub_wire15(9); - sub_wire2(2, 10) <= sub_wire15(10); - sub_wire2(2, 11) <= sub_wire15(11); - sub_wire2(2, 12) <= sub_wire15(12); - sub_wire2(2, 13) <= sub_wire15(13); - sub_wire2(2, 14) <= sub_wire15(14); - sub_wire2(2, 15) <= sub_wire15(15); - sub_wire2(2, 16) <= sub_wire15(16); - sub_wire2(2, 17) <= sub_wire15(17); - sub_wire2(2, 18) <= sub_wire15(18); - sub_wire2(2, 19) <= sub_wire15(19); - sub_wire2(2, 20) <= sub_wire15(20); - sub_wire2(2, 21) <= sub_wire15(21); - sub_wire2(2, 22) <= sub_wire15(22); - sub_wire2(2, 23) <= sub_wire15(23); - sub_wire2(2, 24) <= sub_wire15(24); - sub_wire2(2, 25) <= sub_wire15(25); - sub_wire2(2, 26) <= sub_wire15(26); - sub_wire2(2, 27) <= sub_wire15(27); - sub_wire2(2, 28) <= sub_wire15(28); - sub_wire2(2, 29) <= sub_wire15(29); - sub_wire2(2, 30) <= sub_wire15(30); - sub_wire2(2, 31) <= sub_wire15(31); - sub_wire2(2, 32) <= sub_wire15(32); - sub_wire2(2, 33) <= sub_wire15(33); - sub_wire2(2, 34) <= sub_wire15(34); - sub_wire2(2, 35) <= sub_wire15(35); - sub_wire2(2, 36) <= sub_wire15(36); - sub_wire2(2, 37) <= sub_wire15(37); - sub_wire2(2, 38) <= sub_wire15(38); - sub_wire2(2, 39) <= sub_wire15(39); - sub_wire2(2, 40) <= sub_wire15(40); - sub_wire2(2, 41) <= sub_wire15(41); - sub_wire2(2, 42) <= sub_wire15(42); - sub_wire2(2, 43) <= sub_wire15(43); - sub_wire2(2, 44) <= sub_wire15(44); - sub_wire2(2, 45) <= sub_wire15(45); - sub_wire2(2, 46) <= sub_wire15(46); - sub_wire2(2, 47) <= sub_wire15(47); - sub_wire2(2, 48) <= sub_wire15(48); - sub_wire2(2, 49) <= sub_wire15(49); - sub_wire2(2, 50) <= sub_wire15(50); - sub_wire2(2, 51) <= sub_wire15(51); - sub_wire2(2, 52) <= sub_wire15(52); - sub_wire2(2, 53) <= sub_wire15(53); - sub_wire2(2, 54) <= sub_wire15(54); - sub_wire2(2, 55) <= sub_wire15(55); - sub_wire2(2, 56) <= sub_wire15(56); - sub_wire2(2, 57) <= sub_wire15(57); - sub_wire2(2, 58) <= sub_wire15(58); - sub_wire2(2, 59) <= sub_wire15(59); - sub_wire2(2, 60) <= sub_wire15(60); - sub_wire2(2, 61) <= sub_wire15(61); - sub_wire2(2, 62) <= sub_wire15(62); - sub_wire2(2, 63) <= sub_wire15(63); - sub_wire2(2, 64) <= sub_wire15(64); - sub_wire2(2, 65) <= sub_wire15(65); - sub_wire2(2, 66) <= sub_wire15(66); - sub_wire2(2, 67) <= sub_wire15(67); - sub_wire2(2, 68) <= sub_wire15(68); - sub_wire2(2, 69) <= sub_wire15(69); - sub_wire2(2, 70) <= sub_wire15(70); - sub_wire2(2, 71) <= sub_wire15(71); - sub_wire2(2, 72) <= sub_wire15(72); - sub_wire2(2, 73) <= sub_wire15(73); - sub_wire2(2, 74) <= sub_wire15(74); - sub_wire2(2, 75) <= sub_wire15(75); - sub_wire2(2, 76) <= sub_wire15(76); - sub_wire2(2, 77) <= sub_wire15(77); - sub_wire2(2, 78) <= sub_wire15(78); - sub_wire2(2, 79) <= sub_wire15(79); - sub_wire2(2, 80) <= sub_wire15(80); - sub_wire2(2, 81) <= sub_wire15(81); - sub_wire2(2, 82) <= sub_wire15(82); - sub_wire2(2, 83) <= sub_wire15(83); - sub_wire2(2, 84) <= sub_wire15(84); - sub_wire2(2, 85) <= sub_wire15(85); - sub_wire2(2, 86) <= sub_wire15(86); - sub_wire2(2, 87) <= sub_wire15(87); - sub_wire2(2, 88) <= sub_wire15(88); - sub_wire2(2, 89) <= sub_wire15(89); - sub_wire2(2, 90) <= sub_wire15(90); - sub_wire2(2, 91) <= sub_wire15(91); - sub_wire2(2, 92) <= sub_wire15(92); - sub_wire2(2, 93) <= sub_wire15(93); - sub_wire2(2, 94) <= sub_wire15(94); - sub_wire2(2, 95) <= sub_wire15(95); - sub_wire2(2, 96) <= sub_wire15(96); - sub_wire2(2, 97) <= sub_wire15(97); - sub_wire2(2, 98) <= sub_wire15(98); - sub_wire2(2, 99) <= sub_wire15(99); - sub_wire2(2, 100) <= sub_wire15(100); - sub_wire2(2, 101) <= sub_wire15(101); - sub_wire2(2, 102) <= sub_wire15(102); - sub_wire2(2, 103) <= sub_wire15(103); - sub_wire2(2, 104) <= sub_wire15(104); - sub_wire2(2, 105) <= sub_wire15(105); - sub_wire2(2, 106) <= sub_wire15(106); - sub_wire2(2, 107) <= sub_wire15(107); - sub_wire2(2, 108) <= sub_wire15(108); - sub_wire2(2, 109) <= sub_wire15(109); - sub_wire2(2, 110) <= sub_wire15(110); - sub_wire2(2, 111) <= sub_wire15(111); - sub_wire2(2, 112) <= sub_wire15(112); - sub_wire2(2, 113) <= sub_wire15(113); - sub_wire2(2, 114) <= sub_wire15(114); - sub_wire2(2, 115) <= sub_wire15(115); - sub_wire2(2, 116) <= sub_wire15(116); - sub_wire2(2, 117) <= sub_wire15(117); - sub_wire2(2, 118) <= sub_wire15(118); - sub_wire2(2, 119) <= sub_wire15(119); - sub_wire2(2, 120) <= sub_wire15(120); - sub_wire2(2, 121) <= sub_wire15(121); - sub_wire2(2, 122) <= sub_wire15(122); - sub_wire2(2, 123) <= sub_wire15(123); - sub_wire2(2, 124) <= sub_wire15(124); - sub_wire2(2, 125) <= sub_wire15(125); - sub_wire2(2, 126) <= sub_wire15(126); - sub_wire2(2, 127) <= sub_wire15(127); - sub_wire2(1, 0) <= sub_wire16(0); - sub_wire2(1, 1) <= sub_wire16(1); - sub_wire2(1, 2) <= sub_wire16(2); - sub_wire2(1, 3) <= sub_wire16(3); - sub_wire2(1, 4) <= sub_wire16(4); - sub_wire2(1, 5) <= sub_wire16(5); - sub_wire2(1, 6) <= sub_wire16(6); - sub_wire2(1, 7) <= sub_wire16(7); - sub_wire2(1, 8) <= sub_wire16(8); - sub_wire2(1, 9) <= sub_wire16(9); - sub_wire2(1, 10) <= sub_wire16(10); - sub_wire2(1, 11) <= sub_wire16(11); - sub_wire2(1, 12) <= sub_wire16(12); - sub_wire2(1, 13) <= sub_wire16(13); - sub_wire2(1, 14) <= sub_wire16(14); - sub_wire2(1, 15) <= sub_wire16(15); - sub_wire2(1, 16) <= sub_wire16(16); - sub_wire2(1, 17) <= sub_wire16(17); - sub_wire2(1, 18) <= sub_wire16(18); - sub_wire2(1, 19) <= sub_wire16(19); - sub_wire2(1, 20) <= sub_wire16(20); - sub_wire2(1, 21) <= sub_wire16(21); - sub_wire2(1, 22) <= sub_wire16(22); - sub_wire2(1, 23) <= sub_wire16(23); - sub_wire2(1, 24) <= sub_wire16(24); - sub_wire2(1, 25) <= sub_wire16(25); - sub_wire2(1, 26) <= sub_wire16(26); - sub_wire2(1, 27) <= sub_wire16(27); - sub_wire2(1, 28) <= sub_wire16(28); - sub_wire2(1, 29) <= sub_wire16(29); - sub_wire2(1, 30) <= sub_wire16(30); - sub_wire2(1, 31) <= sub_wire16(31); - sub_wire2(1, 32) <= sub_wire16(32); - sub_wire2(1, 33) <= sub_wire16(33); - sub_wire2(1, 34) <= sub_wire16(34); - sub_wire2(1, 35) <= sub_wire16(35); - sub_wire2(1, 36) <= sub_wire16(36); - sub_wire2(1, 37) <= sub_wire16(37); - sub_wire2(1, 38) <= sub_wire16(38); - sub_wire2(1, 39) <= sub_wire16(39); - sub_wire2(1, 40) <= sub_wire16(40); - sub_wire2(1, 41) <= sub_wire16(41); - sub_wire2(1, 42) <= sub_wire16(42); - sub_wire2(1, 43) <= sub_wire16(43); - sub_wire2(1, 44) <= sub_wire16(44); - sub_wire2(1, 45) <= sub_wire16(45); - sub_wire2(1, 46) <= sub_wire16(46); - sub_wire2(1, 47) <= sub_wire16(47); - sub_wire2(1, 48) <= sub_wire16(48); - sub_wire2(1, 49) <= sub_wire16(49); - sub_wire2(1, 50) <= sub_wire16(50); - sub_wire2(1, 51) <= sub_wire16(51); - sub_wire2(1, 52) <= sub_wire16(52); - sub_wire2(1, 53) <= sub_wire16(53); - sub_wire2(1, 54) <= sub_wire16(54); - sub_wire2(1, 55) <= sub_wire16(55); - sub_wire2(1, 56) <= sub_wire16(56); - sub_wire2(1, 57) <= sub_wire16(57); - sub_wire2(1, 58) <= sub_wire16(58); - sub_wire2(1, 59) <= sub_wire16(59); - sub_wire2(1, 60) <= sub_wire16(60); - sub_wire2(1, 61) <= sub_wire16(61); - sub_wire2(1, 62) <= sub_wire16(62); - sub_wire2(1, 63) <= sub_wire16(63); - sub_wire2(1, 64) <= sub_wire16(64); - sub_wire2(1, 65) <= sub_wire16(65); - sub_wire2(1, 66) <= sub_wire16(66); - sub_wire2(1, 67) <= sub_wire16(67); - sub_wire2(1, 68) <= sub_wire16(68); - sub_wire2(1, 69) <= sub_wire16(69); - sub_wire2(1, 70) <= sub_wire16(70); - sub_wire2(1, 71) <= sub_wire16(71); - sub_wire2(1, 72) <= sub_wire16(72); - sub_wire2(1, 73) <= sub_wire16(73); - sub_wire2(1, 74) <= sub_wire16(74); - sub_wire2(1, 75) <= sub_wire16(75); - sub_wire2(1, 76) <= sub_wire16(76); - sub_wire2(1, 77) <= sub_wire16(77); - sub_wire2(1, 78) <= sub_wire16(78); - sub_wire2(1, 79) <= sub_wire16(79); - sub_wire2(1, 80) <= sub_wire16(80); - sub_wire2(1, 81) <= sub_wire16(81); - sub_wire2(1, 82) <= sub_wire16(82); - sub_wire2(1, 83) <= sub_wire16(83); - sub_wire2(1, 84) <= sub_wire16(84); - sub_wire2(1, 85) <= sub_wire16(85); - sub_wire2(1, 86) <= sub_wire16(86); - sub_wire2(1, 87) <= sub_wire16(87); - sub_wire2(1, 88) <= sub_wire16(88); - sub_wire2(1, 89) <= sub_wire16(89); - sub_wire2(1, 90) <= sub_wire16(90); - sub_wire2(1, 91) <= sub_wire16(91); - sub_wire2(1, 92) <= sub_wire16(92); - sub_wire2(1, 93) <= sub_wire16(93); - sub_wire2(1, 94) <= sub_wire16(94); - sub_wire2(1, 95) <= sub_wire16(95); - sub_wire2(1, 96) <= sub_wire16(96); - sub_wire2(1, 97) <= sub_wire16(97); - sub_wire2(1, 98) <= sub_wire16(98); - sub_wire2(1, 99) <= sub_wire16(99); - sub_wire2(1, 100) <= sub_wire16(100); - sub_wire2(1, 101) <= sub_wire16(101); - sub_wire2(1, 102) <= sub_wire16(102); - sub_wire2(1, 103) <= sub_wire16(103); - sub_wire2(1, 104) <= sub_wire16(104); - sub_wire2(1, 105) <= sub_wire16(105); - sub_wire2(1, 106) <= sub_wire16(106); - sub_wire2(1, 107) <= sub_wire16(107); - sub_wire2(1, 108) <= sub_wire16(108); - sub_wire2(1, 109) <= sub_wire16(109); - sub_wire2(1, 110) <= sub_wire16(110); - sub_wire2(1, 111) <= sub_wire16(111); - sub_wire2(1, 112) <= sub_wire16(112); - sub_wire2(1, 113) <= sub_wire16(113); - sub_wire2(1, 114) <= sub_wire16(114); - sub_wire2(1, 115) <= sub_wire16(115); - sub_wire2(1, 116) <= sub_wire16(116); - sub_wire2(1, 117) <= sub_wire16(117); - sub_wire2(1, 118) <= sub_wire16(118); - sub_wire2(1, 119) <= sub_wire16(119); - sub_wire2(1, 120) <= sub_wire16(120); - sub_wire2(1, 121) <= sub_wire16(121); - sub_wire2(1, 122) <= sub_wire16(122); - sub_wire2(1, 123) <= sub_wire16(123); - sub_wire2(1, 124) <= sub_wire16(124); - sub_wire2(1, 125) <= sub_wire16(125); - sub_wire2(1, 126) <= sub_wire16(126); - sub_wire2(1, 127) <= sub_wire16(127); - sub_wire2(0, 0) <= sub_wire17(0); - sub_wire2(0, 1) <= sub_wire17(1); - sub_wire2(0, 2) <= sub_wire17(2); - sub_wire2(0, 3) <= sub_wire17(3); - sub_wire2(0, 4) <= sub_wire17(4); - sub_wire2(0, 5) <= sub_wire17(5); - sub_wire2(0, 6) <= sub_wire17(6); - sub_wire2(0, 7) <= sub_wire17(7); - sub_wire2(0, 8) <= sub_wire17(8); - sub_wire2(0, 9) <= sub_wire17(9); - sub_wire2(0, 10) <= sub_wire17(10); - sub_wire2(0, 11) <= sub_wire17(11); - sub_wire2(0, 12) <= sub_wire17(12); - sub_wire2(0, 13) <= sub_wire17(13); - sub_wire2(0, 14) <= sub_wire17(14); - sub_wire2(0, 15) <= sub_wire17(15); - sub_wire2(0, 16) <= sub_wire17(16); - sub_wire2(0, 17) <= sub_wire17(17); - sub_wire2(0, 18) <= sub_wire17(18); - sub_wire2(0, 19) <= sub_wire17(19); - sub_wire2(0, 20) <= sub_wire17(20); - sub_wire2(0, 21) <= sub_wire17(21); - sub_wire2(0, 22) <= sub_wire17(22); - sub_wire2(0, 23) <= sub_wire17(23); - sub_wire2(0, 24) <= sub_wire17(24); - sub_wire2(0, 25) <= sub_wire17(25); - sub_wire2(0, 26) <= sub_wire17(26); - sub_wire2(0, 27) <= sub_wire17(27); - sub_wire2(0, 28) <= sub_wire17(28); - sub_wire2(0, 29) <= sub_wire17(29); - sub_wire2(0, 30) <= sub_wire17(30); - sub_wire2(0, 31) <= sub_wire17(31); - sub_wire2(0, 32) <= sub_wire17(32); - sub_wire2(0, 33) <= sub_wire17(33); - sub_wire2(0, 34) <= sub_wire17(34); - sub_wire2(0, 35) <= sub_wire17(35); - sub_wire2(0, 36) <= sub_wire17(36); - sub_wire2(0, 37) <= sub_wire17(37); - sub_wire2(0, 38) <= sub_wire17(38); - sub_wire2(0, 39) <= sub_wire17(39); - sub_wire2(0, 40) <= sub_wire17(40); - sub_wire2(0, 41) <= sub_wire17(41); - sub_wire2(0, 42) <= sub_wire17(42); - sub_wire2(0, 43) <= sub_wire17(43); - sub_wire2(0, 44) <= sub_wire17(44); - sub_wire2(0, 45) <= sub_wire17(45); - sub_wire2(0, 46) <= sub_wire17(46); - sub_wire2(0, 47) <= sub_wire17(47); - sub_wire2(0, 48) <= sub_wire17(48); - sub_wire2(0, 49) <= sub_wire17(49); - sub_wire2(0, 50) <= sub_wire17(50); - sub_wire2(0, 51) <= sub_wire17(51); - sub_wire2(0, 52) <= sub_wire17(52); - sub_wire2(0, 53) <= sub_wire17(53); - sub_wire2(0, 54) <= sub_wire17(54); - sub_wire2(0, 55) <= sub_wire17(55); - sub_wire2(0, 56) <= sub_wire17(56); - sub_wire2(0, 57) <= sub_wire17(57); - sub_wire2(0, 58) <= sub_wire17(58); - sub_wire2(0, 59) <= sub_wire17(59); - sub_wire2(0, 60) <= sub_wire17(60); - sub_wire2(0, 61) <= sub_wire17(61); - sub_wire2(0, 62) <= sub_wire17(62); - sub_wire2(0, 63) <= sub_wire17(63); - sub_wire2(0, 64) <= sub_wire17(64); - sub_wire2(0, 65) <= sub_wire17(65); - sub_wire2(0, 66) <= sub_wire17(66); - sub_wire2(0, 67) <= sub_wire17(67); - sub_wire2(0, 68) <= sub_wire17(68); - sub_wire2(0, 69) <= sub_wire17(69); - sub_wire2(0, 70) <= sub_wire17(70); - sub_wire2(0, 71) <= sub_wire17(71); - sub_wire2(0, 72) <= sub_wire17(72); - sub_wire2(0, 73) <= sub_wire17(73); - sub_wire2(0, 74) <= sub_wire17(74); - sub_wire2(0, 75) <= sub_wire17(75); - sub_wire2(0, 76) <= sub_wire17(76); - sub_wire2(0, 77) <= sub_wire17(77); - sub_wire2(0, 78) <= sub_wire17(78); - sub_wire2(0, 79) <= sub_wire17(79); - sub_wire2(0, 80) <= sub_wire17(80); - sub_wire2(0, 81) <= sub_wire17(81); - sub_wire2(0, 82) <= sub_wire17(82); - sub_wire2(0, 83) <= sub_wire17(83); - sub_wire2(0, 84) <= sub_wire17(84); - sub_wire2(0, 85) <= sub_wire17(85); - sub_wire2(0, 86) <= sub_wire17(86); - sub_wire2(0, 87) <= sub_wire17(87); - sub_wire2(0, 88) <= sub_wire17(88); - sub_wire2(0, 89) <= sub_wire17(89); - sub_wire2(0, 90) <= sub_wire17(90); - sub_wire2(0, 91) <= sub_wire17(91); - sub_wire2(0, 92) <= sub_wire17(92); - sub_wire2(0, 93) <= sub_wire17(93); - sub_wire2(0, 94) <= sub_wire17(94); - sub_wire2(0, 95) <= sub_wire17(95); - sub_wire2(0, 96) <= sub_wire17(96); - sub_wire2(0, 97) <= sub_wire17(97); - sub_wire2(0, 98) <= sub_wire17(98); - sub_wire2(0, 99) <= sub_wire17(99); - sub_wire2(0, 100) <= sub_wire17(100); - sub_wire2(0, 101) <= sub_wire17(101); - sub_wire2(0, 102) <= sub_wire17(102); - sub_wire2(0, 103) <= sub_wire17(103); - sub_wire2(0, 104) <= sub_wire17(104); - sub_wire2(0, 105) <= sub_wire17(105); - sub_wire2(0, 106) <= sub_wire17(106); - sub_wire2(0, 107) <= sub_wire17(107); - sub_wire2(0, 108) <= sub_wire17(108); - sub_wire2(0, 109) <= sub_wire17(109); - sub_wire2(0, 110) <= sub_wire17(110); - sub_wire2(0, 111) <= sub_wire17(111); - sub_wire2(0, 112) <= sub_wire17(112); - sub_wire2(0, 113) <= sub_wire17(113); - sub_wire2(0, 114) <= sub_wire17(114); - sub_wire2(0, 115) <= sub_wire17(115); - sub_wire2(0, 116) <= sub_wire17(116); - sub_wire2(0, 117) <= sub_wire17(117); - sub_wire2(0, 118) <= sub_wire17(118); - sub_wire2(0, 119) <= sub_wire17(119); - sub_wire2(0, 120) <= sub_wire17(120); - sub_wire2(0, 121) <= sub_wire17(121); - sub_wire2(0, 122) <= sub_wire17(122); - sub_wire2(0, 123) <= sub_wire17(123); - sub_wire2(0, 124) <= sub_wire17(124); - sub_wire2(0, 125) <= sub_wire17(125); - sub_wire2(0, 126) <= sub_wire17(126); - sub_wire2(0, 127) <= sub_wire17(127); - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_size => 16, - lpm_type => "LPM_MUX", - lpm_width => 128, - lpm_widths => 4 - ) - PORT MAP ( - data => sub_wire2, - sel => sel, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" --- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]" --- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL "data10x[127..0]" --- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL "data11x[127..0]" --- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL "data12x[127..0]" --- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL "data13x[127..0]" --- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL "data14x[127..0]" --- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL "data15x[127..0]" --- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]" --- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL "data2x[127..0]" --- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL "data3x[127..0]" --- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL "data4x[127..0]" --- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL "data5x[127..0]" --- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL "data6x[127..0]" --- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL "data7x[127..0]" --- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL "data8x[127..0]" --- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL "data9x[127..0]" --- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]" --- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]" --- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0 --- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0 --- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 --- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxVDM.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxVDM IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_muxVDM; + + +ARCHITECTURE SYN OF lpm_muxvdm IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 127 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire10 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire11 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire12 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire13 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire14 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire15 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire16 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire17 : STD_LOGIC_VECTOR (127 DOWNTO 0); + +BEGIN + sub_wire17 <= data0x(127 DOWNTO 0); + sub_wire16 <= data1x(127 DOWNTO 0); + sub_wire15 <= data2x(127 DOWNTO 0); + sub_wire14 <= data3x(127 DOWNTO 0); + sub_wire13 <= data4x(127 DOWNTO 0); + sub_wire12 <= data5x(127 DOWNTO 0); + sub_wire11 <= data6x(127 DOWNTO 0); + sub_wire10 <= data7x(127 DOWNTO 0); + sub_wire9 <= data8x(127 DOWNTO 0); + sub_wire8 <= data9x(127 DOWNTO 0); + sub_wire7 <= data10x(127 DOWNTO 0); + sub_wire6 <= data11x(127 DOWNTO 0); + sub_wire5 <= data12x(127 DOWNTO 0); + sub_wire4 <= data13x(127 DOWNTO 0); + sub_wire3 <= data14x(127 DOWNTO 0); + result <= sub_wire0(127 DOWNTO 0); + sub_wire1 <= data15x(127 DOWNTO 0); + sub_wire2(15, 0) <= sub_wire1(0); + sub_wire2(15, 1) <= sub_wire1(1); + sub_wire2(15, 2) <= sub_wire1(2); + sub_wire2(15, 3) <= sub_wire1(3); + sub_wire2(15, 4) <= sub_wire1(4); + sub_wire2(15, 5) <= sub_wire1(5); + sub_wire2(15, 6) <= sub_wire1(6); + sub_wire2(15, 7) <= sub_wire1(7); + sub_wire2(15, 8) <= sub_wire1(8); + sub_wire2(15, 9) <= sub_wire1(9); + sub_wire2(15, 10) <= sub_wire1(10); + sub_wire2(15, 11) <= sub_wire1(11); + sub_wire2(15, 12) <= sub_wire1(12); + sub_wire2(15, 13) <= sub_wire1(13); + sub_wire2(15, 14) <= sub_wire1(14); + sub_wire2(15, 15) <= sub_wire1(15); + sub_wire2(15, 16) <= sub_wire1(16); + sub_wire2(15, 17) <= sub_wire1(17); + sub_wire2(15, 18) <= sub_wire1(18); + sub_wire2(15, 19) <= sub_wire1(19); + sub_wire2(15, 20) <= sub_wire1(20); + sub_wire2(15, 21) <= sub_wire1(21); + sub_wire2(15, 22) <= sub_wire1(22); + sub_wire2(15, 23) <= sub_wire1(23); + sub_wire2(15, 24) <= sub_wire1(24); + sub_wire2(15, 25) <= sub_wire1(25); + sub_wire2(15, 26) <= sub_wire1(26); + sub_wire2(15, 27) <= sub_wire1(27); + sub_wire2(15, 28) <= sub_wire1(28); + sub_wire2(15, 29) <= sub_wire1(29); + sub_wire2(15, 30) <= sub_wire1(30); + sub_wire2(15, 31) <= sub_wire1(31); + sub_wire2(15, 32) <= sub_wire1(32); + sub_wire2(15, 33) <= sub_wire1(33); + sub_wire2(15, 34) <= sub_wire1(34); + sub_wire2(15, 35) <= sub_wire1(35); + sub_wire2(15, 36) <= sub_wire1(36); + sub_wire2(15, 37) <= sub_wire1(37); + sub_wire2(15, 38) <= sub_wire1(38); + sub_wire2(15, 39) <= sub_wire1(39); + sub_wire2(15, 40) <= sub_wire1(40); + sub_wire2(15, 41) <= sub_wire1(41); + sub_wire2(15, 42) <= sub_wire1(42); + sub_wire2(15, 43) <= sub_wire1(43); + sub_wire2(15, 44) <= sub_wire1(44); + sub_wire2(15, 45) <= sub_wire1(45); + sub_wire2(15, 46) <= sub_wire1(46); + sub_wire2(15, 47) <= sub_wire1(47); + sub_wire2(15, 48) <= sub_wire1(48); + sub_wire2(15, 49) <= sub_wire1(49); + sub_wire2(15, 50) <= sub_wire1(50); + sub_wire2(15, 51) <= sub_wire1(51); + sub_wire2(15, 52) <= sub_wire1(52); + sub_wire2(15, 53) <= sub_wire1(53); + sub_wire2(15, 54) <= sub_wire1(54); + sub_wire2(15, 55) <= sub_wire1(55); + sub_wire2(15, 56) <= sub_wire1(56); + sub_wire2(15, 57) <= sub_wire1(57); + sub_wire2(15, 58) <= sub_wire1(58); + sub_wire2(15, 59) <= sub_wire1(59); + sub_wire2(15, 60) <= sub_wire1(60); + sub_wire2(15, 61) <= sub_wire1(61); + sub_wire2(15, 62) <= sub_wire1(62); + sub_wire2(15, 63) <= sub_wire1(63); + sub_wire2(15, 64) <= sub_wire1(64); + sub_wire2(15, 65) <= sub_wire1(65); + sub_wire2(15, 66) <= sub_wire1(66); + sub_wire2(15, 67) <= sub_wire1(67); + sub_wire2(15, 68) <= sub_wire1(68); + sub_wire2(15, 69) <= sub_wire1(69); + sub_wire2(15, 70) <= sub_wire1(70); + sub_wire2(15, 71) <= sub_wire1(71); + sub_wire2(15, 72) <= sub_wire1(72); + sub_wire2(15, 73) <= sub_wire1(73); + sub_wire2(15, 74) <= sub_wire1(74); + sub_wire2(15, 75) <= sub_wire1(75); + sub_wire2(15, 76) <= sub_wire1(76); + sub_wire2(15, 77) <= sub_wire1(77); + sub_wire2(15, 78) <= sub_wire1(78); + sub_wire2(15, 79) <= sub_wire1(79); + sub_wire2(15, 80) <= sub_wire1(80); + sub_wire2(15, 81) <= sub_wire1(81); + sub_wire2(15, 82) <= sub_wire1(82); + sub_wire2(15, 83) <= sub_wire1(83); + sub_wire2(15, 84) <= sub_wire1(84); + sub_wire2(15, 85) <= sub_wire1(85); + sub_wire2(15, 86) <= sub_wire1(86); + sub_wire2(15, 87) <= sub_wire1(87); + sub_wire2(15, 88) <= sub_wire1(88); + sub_wire2(15, 89) <= sub_wire1(89); + sub_wire2(15, 90) <= sub_wire1(90); + sub_wire2(15, 91) <= sub_wire1(91); + sub_wire2(15, 92) <= sub_wire1(92); + sub_wire2(15, 93) <= sub_wire1(93); + sub_wire2(15, 94) <= sub_wire1(94); + sub_wire2(15, 95) <= sub_wire1(95); + sub_wire2(15, 96) <= sub_wire1(96); + sub_wire2(15, 97) <= sub_wire1(97); + sub_wire2(15, 98) <= sub_wire1(98); + sub_wire2(15, 99) <= sub_wire1(99); + sub_wire2(15, 100) <= sub_wire1(100); + sub_wire2(15, 101) <= sub_wire1(101); + sub_wire2(15, 102) <= sub_wire1(102); + sub_wire2(15, 103) <= sub_wire1(103); + sub_wire2(15, 104) <= sub_wire1(104); + sub_wire2(15, 105) <= sub_wire1(105); + sub_wire2(15, 106) <= sub_wire1(106); + sub_wire2(15, 107) <= sub_wire1(107); + sub_wire2(15, 108) <= sub_wire1(108); + sub_wire2(15, 109) <= sub_wire1(109); + sub_wire2(15, 110) <= sub_wire1(110); + sub_wire2(15, 111) <= sub_wire1(111); + sub_wire2(15, 112) <= sub_wire1(112); + sub_wire2(15, 113) <= sub_wire1(113); + sub_wire2(15, 114) <= sub_wire1(114); + sub_wire2(15, 115) <= sub_wire1(115); + sub_wire2(15, 116) <= sub_wire1(116); + sub_wire2(15, 117) <= sub_wire1(117); + sub_wire2(15, 118) <= sub_wire1(118); + sub_wire2(15, 119) <= sub_wire1(119); + sub_wire2(15, 120) <= sub_wire1(120); + sub_wire2(15, 121) <= sub_wire1(121); + sub_wire2(15, 122) <= sub_wire1(122); + sub_wire2(15, 123) <= sub_wire1(123); + sub_wire2(15, 124) <= sub_wire1(124); + sub_wire2(15, 125) <= sub_wire1(125); + sub_wire2(15, 126) <= sub_wire1(126); + sub_wire2(15, 127) <= sub_wire1(127); + sub_wire2(14, 0) <= sub_wire3(0); + sub_wire2(14, 1) <= sub_wire3(1); + sub_wire2(14, 2) <= sub_wire3(2); + sub_wire2(14, 3) <= sub_wire3(3); + sub_wire2(14, 4) <= sub_wire3(4); + sub_wire2(14, 5) <= sub_wire3(5); + sub_wire2(14, 6) <= sub_wire3(6); + sub_wire2(14, 7) <= sub_wire3(7); + sub_wire2(14, 8) <= sub_wire3(8); + sub_wire2(14, 9) <= sub_wire3(9); + sub_wire2(14, 10) <= sub_wire3(10); + sub_wire2(14, 11) <= sub_wire3(11); + sub_wire2(14, 12) <= sub_wire3(12); + sub_wire2(14, 13) <= sub_wire3(13); + sub_wire2(14, 14) <= sub_wire3(14); + sub_wire2(14, 15) <= sub_wire3(15); + sub_wire2(14, 16) <= sub_wire3(16); + sub_wire2(14, 17) <= sub_wire3(17); + sub_wire2(14, 18) <= sub_wire3(18); + sub_wire2(14, 19) <= sub_wire3(19); + sub_wire2(14, 20) <= sub_wire3(20); + sub_wire2(14, 21) <= sub_wire3(21); + sub_wire2(14, 22) <= sub_wire3(22); + sub_wire2(14, 23) <= sub_wire3(23); + sub_wire2(14, 24) <= sub_wire3(24); + sub_wire2(14, 25) <= sub_wire3(25); + sub_wire2(14, 26) <= sub_wire3(26); + sub_wire2(14, 27) <= sub_wire3(27); + sub_wire2(14, 28) <= sub_wire3(28); + sub_wire2(14, 29) <= sub_wire3(29); + sub_wire2(14, 30) <= sub_wire3(30); + sub_wire2(14, 31) <= sub_wire3(31); + sub_wire2(14, 32) <= sub_wire3(32); + sub_wire2(14, 33) <= sub_wire3(33); + sub_wire2(14, 34) <= sub_wire3(34); + sub_wire2(14, 35) <= sub_wire3(35); + sub_wire2(14, 36) <= sub_wire3(36); + sub_wire2(14, 37) <= sub_wire3(37); + sub_wire2(14, 38) <= sub_wire3(38); + sub_wire2(14, 39) <= sub_wire3(39); + sub_wire2(14, 40) <= sub_wire3(40); + sub_wire2(14, 41) <= sub_wire3(41); + sub_wire2(14, 42) <= sub_wire3(42); + sub_wire2(14, 43) <= sub_wire3(43); + sub_wire2(14, 44) <= sub_wire3(44); + sub_wire2(14, 45) <= sub_wire3(45); + sub_wire2(14, 46) <= sub_wire3(46); + sub_wire2(14, 47) <= sub_wire3(47); + sub_wire2(14, 48) <= sub_wire3(48); + sub_wire2(14, 49) <= sub_wire3(49); + sub_wire2(14, 50) <= sub_wire3(50); + sub_wire2(14, 51) <= sub_wire3(51); + sub_wire2(14, 52) <= sub_wire3(52); + sub_wire2(14, 53) <= sub_wire3(53); + sub_wire2(14, 54) <= sub_wire3(54); + sub_wire2(14, 55) <= sub_wire3(55); + sub_wire2(14, 56) <= sub_wire3(56); + sub_wire2(14, 57) <= sub_wire3(57); + sub_wire2(14, 58) <= sub_wire3(58); + sub_wire2(14, 59) <= sub_wire3(59); + sub_wire2(14, 60) <= sub_wire3(60); + sub_wire2(14, 61) <= sub_wire3(61); + sub_wire2(14, 62) <= sub_wire3(62); + sub_wire2(14, 63) <= sub_wire3(63); + sub_wire2(14, 64) <= sub_wire3(64); + sub_wire2(14, 65) <= sub_wire3(65); + sub_wire2(14, 66) <= sub_wire3(66); + sub_wire2(14, 67) <= sub_wire3(67); + sub_wire2(14, 68) <= sub_wire3(68); + sub_wire2(14, 69) <= sub_wire3(69); + sub_wire2(14, 70) <= sub_wire3(70); + sub_wire2(14, 71) <= sub_wire3(71); + sub_wire2(14, 72) <= sub_wire3(72); + sub_wire2(14, 73) <= sub_wire3(73); + sub_wire2(14, 74) <= sub_wire3(74); + sub_wire2(14, 75) <= sub_wire3(75); + sub_wire2(14, 76) <= sub_wire3(76); + sub_wire2(14, 77) <= sub_wire3(77); + sub_wire2(14, 78) <= sub_wire3(78); + sub_wire2(14, 79) <= sub_wire3(79); + sub_wire2(14, 80) <= sub_wire3(80); + sub_wire2(14, 81) <= sub_wire3(81); + sub_wire2(14, 82) <= sub_wire3(82); + sub_wire2(14, 83) <= sub_wire3(83); + sub_wire2(14, 84) <= sub_wire3(84); + sub_wire2(14, 85) <= sub_wire3(85); + sub_wire2(14, 86) <= sub_wire3(86); + sub_wire2(14, 87) <= sub_wire3(87); + sub_wire2(14, 88) <= sub_wire3(88); + sub_wire2(14, 89) <= sub_wire3(89); + sub_wire2(14, 90) <= sub_wire3(90); + sub_wire2(14, 91) <= sub_wire3(91); + sub_wire2(14, 92) <= sub_wire3(92); + sub_wire2(14, 93) <= sub_wire3(93); + sub_wire2(14, 94) <= sub_wire3(94); + sub_wire2(14, 95) <= sub_wire3(95); + sub_wire2(14, 96) <= sub_wire3(96); + sub_wire2(14, 97) <= sub_wire3(97); + sub_wire2(14, 98) <= sub_wire3(98); + sub_wire2(14, 99) <= sub_wire3(99); + sub_wire2(14, 100) <= sub_wire3(100); + sub_wire2(14, 101) <= sub_wire3(101); + sub_wire2(14, 102) <= sub_wire3(102); + sub_wire2(14, 103) <= sub_wire3(103); + sub_wire2(14, 104) <= sub_wire3(104); + sub_wire2(14, 105) <= sub_wire3(105); + sub_wire2(14, 106) <= sub_wire3(106); + sub_wire2(14, 107) <= sub_wire3(107); + sub_wire2(14, 108) <= sub_wire3(108); + sub_wire2(14, 109) <= sub_wire3(109); + sub_wire2(14, 110) <= sub_wire3(110); + sub_wire2(14, 111) <= sub_wire3(111); + sub_wire2(14, 112) <= sub_wire3(112); + sub_wire2(14, 113) <= sub_wire3(113); + sub_wire2(14, 114) <= sub_wire3(114); + sub_wire2(14, 115) <= sub_wire3(115); + sub_wire2(14, 116) <= sub_wire3(116); + sub_wire2(14, 117) <= sub_wire3(117); + sub_wire2(14, 118) <= sub_wire3(118); + sub_wire2(14, 119) <= sub_wire3(119); + sub_wire2(14, 120) <= sub_wire3(120); + sub_wire2(14, 121) <= sub_wire3(121); + sub_wire2(14, 122) <= sub_wire3(122); + sub_wire2(14, 123) <= sub_wire3(123); + sub_wire2(14, 124) <= sub_wire3(124); + sub_wire2(14, 125) <= sub_wire3(125); + sub_wire2(14, 126) <= sub_wire3(126); + sub_wire2(14, 127) <= sub_wire3(127); + sub_wire2(13, 0) <= sub_wire4(0); + sub_wire2(13, 1) <= sub_wire4(1); + sub_wire2(13, 2) <= sub_wire4(2); + sub_wire2(13, 3) <= sub_wire4(3); + sub_wire2(13, 4) <= sub_wire4(4); + sub_wire2(13, 5) <= sub_wire4(5); + sub_wire2(13, 6) <= sub_wire4(6); + sub_wire2(13, 7) <= sub_wire4(7); + sub_wire2(13, 8) <= sub_wire4(8); + sub_wire2(13, 9) <= sub_wire4(9); + sub_wire2(13, 10) <= sub_wire4(10); + sub_wire2(13, 11) <= sub_wire4(11); + sub_wire2(13, 12) <= sub_wire4(12); + sub_wire2(13, 13) <= sub_wire4(13); + sub_wire2(13, 14) <= sub_wire4(14); + sub_wire2(13, 15) <= sub_wire4(15); + sub_wire2(13, 16) <= sub_wire4(16); + sub_wire2(13, 17) <= sub_wire4(17); + sub_wire2(13, 18) <= sub_wire4(18); + sub_wire2(13, 19) <= sub_wire4(19); + sub_wire2(13, 20) <= sub_wire4(20); + sub_wire2(13, 21) <= sub_wire4(21); + sub_wire2(13, 22) <= sub_wire4(22); + sub_wire2(13, 23) <= sub_wire4(23); + sub_wire2(13, 24) <= sub_wire4(24); + sub_wire2(13, 25) <= sub_wire4(25); + sub_wire2(13, 26) <= sub_wire4(26); + sub_wire2(13, 27) <= sub_wire4(27); + sub_wire2(13, 28) <= sub_wire4(28); + sub_wire2(13, 29) <= sub_wire4(29); + sub_wire2(13, 30) <= sub_wire4(30); + sub_wire2(13, 31) <= sub_wire4(31); + sub_wire2(13, 32) <= sub_wire4(32); + sub_wire2(13, 33) <= sub_wire4(33); + sub_wire2(13, 34) <= sub_wire4(34); + sub_wire2(13, 35) <= sub_wire4(35); + sub_wire2(13, 36) <= sub_wire4(36); + sub_wire2(13, 37) <= sub_wire4(37); + sub_wire2(13, 38) <= sub_wire4(38); + sub_wire2(13, 39) <= sub_wire4(39); + sub_wire2(13, 40) <= sub_wire4(40); + sub_wire2(13, 41) <= sub_wire4(41); + sub_wire2(13, 42) <= sub_wire4(42); + sub_wire2(13, 43) <= sub_wire4(43); + sub_wire2(13, 44) <= sub_wire4(44); + sub_wire2(13, 45) <= sub_wire4(45); + sub_wire2(13, 46) <= sub_wire4(46); + sub_wire2(13, 47) <= sub_wire4(47); + sub_wire2(13, 48) <= sub_wire4(48); + sub_wire2(13, 49) <= sub_wire4(49); + sub_wire2(13, 50) <= sub_wire4(50); + sub_wire2(13, 51) <= sub_wire4(51); + sub_wire2(13, 52) <= sub_wire4(52); + sub_wire2(13, 53) <= sub_wire4(53); + sub_wire2(13, 54) <= sub_wire4(54); + sub_wire2(13, 55) <= sub_wire4(55); + sub_wire2(13, 56) <= sub_wire4(56); + sub_wire2(13, 57) <= sub_wire4(57); + sub_wire2(13, 58) <= sub_wire4(58); + sub_wire2(13, 59) <= sub_wire4(59); + sub_wire2(13, 60) <= sub_wire4(60); + sub_wire2(13, 61) <= sub_wire4(61); + sub_wire2(13, 62) <= sub_wire4(62); + sub_wire2(13, 63) <= sub_wire4(63); + sub_wire2(13, 64) <= sub_wire4(64); + sub_wire2(13, 65) <= sub_wire4(65); + sub_wire2(13, 66) <= sub_wire4(66); + sub_wire2(13, 67) <= sub_wire4(67); + sub_wire2(13, 68) <= sub_wire4(68); + sub_wire2(13, 69) <= sub_wire4(69); + sub_wire2(13, 70) <= sub_wire4(70); + sub_wire2(13, 71) <= sub_wire4(71); + sub_wire2(13, 72) <= sub_wire4(72); + sub_wire2(13, 73) <= sub_wire4(73); + sub_wire2(13, 74) <= sub_wire4(74); + sub_wire2(13, 75) <= sub_wire4(75); + sub_wire2(13, 76) <= sub_wire4(76); + sub_wire2(13, 77) <= sub_wire4(77); + sub_wire2(13, 78) <= sub_wire4(78); + sub_wire2(13, 79) <= sub_wire4(79); + sub_wire2(13, 80) <= sub_wire4(80); + sub_wire2(13, 81) <= sub_wire4(81); + sub_wire2(13, 82) <= sub_wire4(82); + sub_wire2(13, 83) <= sub_wire4(83); + sub_wire2(13, 84) <= sub_wire4(84); + sub_wire2(13, 85) <= sub_wire4(85); + sub_wire2(13, 86) <= sub_wire4(86); + sub_wire2(13, 87) <= sub_wire4(87); + sub_wire2(13, 88) <= sub_wire4(88); + sub_wire2(13, 89) <= sub_wire4(89); + sub_wire2(13, 90) <= sub_wire4(90); + sub_wire2(13, 91) <= sub_wire4(91); + sub_wire2(13, 92) <= sub_wire4(92); + sub_wire2(13, 93) <= sub_wire4(93); + sub_wire2(13, 94) <= sub_wire4(94); + sub_wire2(13, 95) <= sub_wire4(95); + sub_wire2(13, 96) <= sub_wire4(96); + sub_wire2(13, 97) <= sub_wire4(97); + sub_wire2(13, 98) <= sub_wire4(98); + sub_wire2(13, 99) <= sub_wire4(99); + sub_wire2(13, 100) <= sub_wire4(100); + sub_wire2(13, 101) <= sub_wire4(101); + sub_wire2(13, 102) <= sub_wire4(102); + sub_wire2(13, 103) <= sub_wire4(103); + sub_wire2(13, 104) <= sub_wire4(104); + sub_wire2(13, 105) <= sub_wire4(105); + sub_wire2(13, 106) <= sub_wire4(106); + sub_wire2(13, 107) <= sub_wire4(107); + sub_wire2(13, 108) <= sub_wire4(108); + sub_wire2(13, 109) <= sub_wire4(109); + sub_wire2(13, 110) <= sub_wire4(110); + sub_wire2(13, 111) <= sub_wire4(111); + sub_wire2(13, 112) <= sub_wire4(112); + sub_wire2(13, 113) <= sub_wire4(113); + sub_wire2(13, 114) <= sub_wire4(114); + sub_wire2(13, 115) <= sub_wire4(115); + sub_wire2(13, 116) <= sub_wire4(116); + sub_wire2(13, 117) <= sub_wire4(117); + sub_wire2(13, 118) <= sub_wire4(118); + sub_wire2(13, 119) <= sub_wire4(119); + sub_wire2(13, 120) <= sub_wire4(120); + sub_wire2(13, 121) <= sub_wire4(121); + sub_wire2(13, 122) <= sub_wire4(122); + sub_wire2(13, 123) <= sub_wire4(123); + sub_wire2(13, 124) <= sub_wire4(124); + sub_wire2(13, 125) <= sub_wire4(125); + sub_wire2(13, 126) <= sub_wire4(126); + sub_wire2(13, 127) <= sub_wire4(127); + sub_wire2(12, 0) <= sub_wire5(0); + sub_wire2(12, 1) <= sub_wire5(1); + sub_wire2(12, 2) <= sub_wire5(2); + sub_wire2(12, 3) <= sub_wire5(3); + sub_wire2(12, 4) <= sub_wire5(4); + sub_wire2(12, 5) <= sub_wire5(5); + sub_wire2(12, 6) <= sub_wire5(6); + sub_wire2(12, 7) <= sub_wire5(7); + sub_wire2(12, 8) <= sub_wire5(8); + sub_wire2(12, 9) <= sub_wire5(9); + sub_wire2(12, 10) <= sub_wire5(10); + sub_wire2(12, 11) <= sub_wire5(11); + sub_wire2(12, 12) <= sub_wire5(12); + sub_wire2(12, 13) <= sub_wire5(13); + sub_wire2(12, 14) <= sub_wire5(14); + sub_wire2(12, 15) <= sub_wire5(15); + sub_wire2(12, 16) <= sub_wire5(16); + sub_wire2(12, 17) <= sub_wire5(17); + sub_wire2(12, 18) <= sub_wire5(18); + sub_wire2(12, 19) <= sub_wire5(19); + sub_wire2(12, 20) <= sub_wire5(20); + sub_wire2(12, 21) <= sub_wire5(21); + sub_wire2(12, 22) <= sub_wire5(22); + sub_wire2(12, 23) <= sub_wire5(23); + sub_wire2(12, 24) <= sub_wire5(24); + sub_wire2(12, 25) <= sub_wire5(25); + sub_wire2(12, 26) <= sub_wire5(26); + sub_wire2(12, 27) <= sub_wire5(27); + sub_wire2(12, 28) <= sub_wire5(28); + sub_wire2(12, 29) <= sub_wire5(29); + sub_wire2(12, 30) <= sub_wire5(30); + sub_wire2(12, 31) <= sub_wire5(31); + sub_wire2(12, 32) <= sub_wire5(32); + sub_wire2(12, 33) <= sub_wire5(33); + sub_wire2(12, 34) <= sub_wire5(34); + sub_wire2(12, 35) <= sub_wire5(35); + sub_wire2(12, 36) <= sub_wire5(36); + sub_wire2(12, 37) <= sub_wire5(37); + sub_wire2(12, 38) <= sub_wire5(38); + sub_wire2(12, 39) <= sub_wire5(39); + sub_wire2(12, 40) <= sub_wire5(40); + sub_wire2(12, 41) <= sub_wire5(41); + sub_wire2(12, 42) <= sub_wire5(42); + sub_wire2(12, 43) <= sub_wire5(43); + sub_wire2(12, 44) <= sub_wire5(44); + sub_wire2(12, 45) <= sub_wire5(45); + sub_wire2(12, 46) <= sub_wire5(46); + sub_wire2(12, 47) <= sub_wire5(47); + sub_wire2(12, 48) <= sub_wire5(48); + sub_wire2(12, 49) <= sub_wire5(49); + sub_wire2(12, 50) <= sub_wire5(50); + sub_wire2(12, 51) <= sub_wire5(51); + sub_wire2(12, 52) <= sub_wire5(52); + sub_wire2(12, 53) <= sub_wire5(53); + sub_wire2(12, 54) <= sub_wire5(54); + sub_wire2(12, 55) <= sub_wire5(55); + sub_wire2(12, 56) <= sub_wire5(56); + sub_wire2(12, 57) <= sub_wire5(57); + sub_wire2(12, 58) <= sub_wire5(58); + sub_wire2(12, 59) <= sub_wire5(59); + sub_wire2(12, 60) <= sub_wire5(60); + sub_wire2(12, 61) <= sub_wire5(61); + sub_wire2(12, 62) <= sub_wire5(62); + sub_wire2(12, 63) <= sub_wire5(63); + sub_wire2(12, 64) <= sub_wire5(64); + sub_wire2(12, 65) <= sub_wire5(65); + sub_wire2(12, 66) <= sub_wire5(66); + sub_wire2(12, 67) <= sub_wire5(67); + sub_wire2(12, 68) <= sub_wire5(68); + sub_wire2(12, 69) <= sub_wire5(69); + sub_wire2(12, 70) <= sub_wire5(70); + sub_wire2(12, 71) <= sub_wire5(71); + sub_wire2(12, 72) <= sub_wire5(72); + sub_wire2(12, 73) <= sub_wire5(73); + sub_wire2(12, 74) <= sub_wire5(74); + sub_wire2(12, 75) <= sub_wire5(75); + sub_wire2(12, 76) <= sub_wire5(76); + sub_wire2(12, 77) <= sub_wire5(77); + sub_wire2(12, 78) <= sub_wire5(78); + sub_wire2(12, 79) <= sub_wire5(79); + sub_wire2(12, 80) <= sub_wire5(80); + sub_wire2(12, 81) <= sub_wire5(81); + sub_wire2(12, 82) <= sub_wire5(82); + sub_wire2(12, 83) <= sub_wire5(83); + sub_wire2(12, 84) <= sub_wire5(84); + sub_wire2(12, 85) <= sub_wire5(85); + sub_wire2(12, 86) <= sub_wire5(86); + sub_wire2(12, 87) <= sub_wire5(87); + sub_wire2(12, 88) <= sub_wire5(88); + sub_wire2(12, 89) <= sub_wire5(89); + sub_wire2(12, 90) <= sub_wire5(90); + sub_wire2(12, 91) <= sub_wire5(91); + sub_wire2(12, 92) <= sub_wire5(92); + sub_wire2(12, 93) <= sub_wire5(93); + sub_wire2(12, 94) <= sub_wire5(94); + sub_wire2(12, 95) <= sub_wire5(95); + sub_wire2(12, 96) <= sub_wire5(96); + sub_wire2(12, 97) <= sub_wire5(97); + sub_wire2(12, 98) <= sub_wire5(98); + sub_wire2(12, 99) <= sub_wire5(99); + sub_wire2(12, 100) <= sub_wire5(100); + sub_wire2(12, 101) <= sub_wire5(101); + sub_wire2(12, 102) <= sub_wire5(102); + sub_wire2(12, 103) <= sub_wire5(103); + sub_wire2(12, 104) <= sub_wire5(104); + sub_wire2(12, 105) <= sub_wire5(105); + sub_wire2(12, 106) <= sub_wire5(106); + sub_wire2(12, 107) <= sub_wire5(107); + sub_wire2(12, 108) <= sub_wire5(108); + sub_wire2(12, 109) <= sub_wire5(109); + sub_wire2(12, 110) <= sub_wire5(110); + sub_wire2(12, 111) <= sub_wire5(111); + sub_wire2(12, 112) <= sub_wire5(112); + sub_wire2(12, 113) <= sub_wire5(113); + sub_wire2(12, 114) <= sub_wire5(114); + sub_wire2(12, 115) <= sub_wire5(115); + sub_wire2(12, 116) <= sub_wire5(116); + sub_wire2(12, 117) <= sub_wire5(117); + sub_wire2(12, 118) <= sub_wire5(118); + sub_wire2(12, 119) <= sub_wire5(119); + sub_wire2(12, 120) <= sub_wire5(120); + sub_wire2(12, 121) <= sub_wire5(121); + sub_wire2(12, 122) <= sub_wire5(122); + sub_wire2(12, 123) <= sub_wire5(123); + sub_wire2(12, 124) <= sub_wire5(124); + sub_wire2(12, 125) <= sub_wire5(125); + sub_wire2(12, 126) <= sub_wire5(126); + sub_wire2(12, 127) <= sub_wire5(127); + sub_wire2(11, 0) <= sub_wire6(0); + sub_wire2(11, 1) <= sub_wire6(1); + sub_wire2(11, 2) <= sub_wire6(2); + sub_wire2(11, 3) <= sub_wire6(3); + sub_wire2(11, 4) <= sub_wire6(4); + sub_wire2(11, 5) <= sub_wire6(5); + sub_wire2(11, 6) <= sub_wire6(6); + sub_wire2(11, 7) <= sub_wire6(7); + sub_wire2(11, 8) <= sub_wire6(8); + sub_wire2(11, 9) <= sub_wire6(9); + sub_wire2(11, 10) <= sub_wire6(10); + sub_wire2(11, 11) <= sub_wire6(11); + sub_wire2(11, 12) <= sub_wire6(12); + sub_wire2(11, 13) <= sub_wire6(13); + sub_wire2(11, 14) <= sub_wire6(14); + sub_wire2(11, 15) <= sub_wire6(15); + sub_wire2(11, 16) <= sub_wire6(16); + sub_wire2(11, 17) <= sub_wire6(17); + sub_wire2(11, 18) <= sub_wire6(18); + sub_wire2(11, 19) <= sub_wire6(19); + sub_wire2(11, 20) <= sub_wire6(20); + sub_wire2(11, 21) <= sub_wire6(21); + sub_wire2(11, 22) <= sub_wire6(22); + sub_wire2(11, 23) <= sub_wire6(23); + sub_wire2(11, 24) <= sub_wire6(24); + sub_wire2(11, 25) <= sub_wire6(25); + sub_wire2(11, 26) <= sub_wire6(26); + sub_wire2(11, 27) <= sub_wire6(27); + sub_wire2(11, 28) <= sub_wire6(28); + sub_wire2(11, 29) <= sub_wire6(29); + sub_wire2(11, 30) <= sub_wire6(30); + sub_wire2(11, 31) <= sub_wire6(31); + sub_wire2(11, 32) <= sub_wire6(32); + sub_wire2(11, 33) <= sub_wire6(33); + sub_wire2(11, 34) <= sub_wire6(34); + sub_wire2(11, 35) <= sub_wire6(35); + sub_wire2(11, 36) <= sub_wire6(36); + sub_wire2(11, 37) <= sub_wire6(37); + sub_wire2(11, 38) <= sub_wire6(38); + sub_wire2(11, 39) <= sub_wire6(39); + sub_wire2(11, 40) <= sub_wire6(40); + sub_wire2(11, 41) <= sub_wire6(41); + sub_wire2(11, 42) <= sub_wire6(42); + sub_wire2(11, 43) <= sub_wire6(43); + sub_wire2(11, 44) <= sub_wire6(44); + sub_wire2(11, 45) <= sub_wire6(45); + sub_wire2(11, 46) <= sub_wire6(46); + sub_wire2(11, 47) <= sub_wire6(47); + sub_wire2(11, 48) <= sub_wire6(48); + sub_wire2(11, 49) <= sub_wire6(49); + sub_wire2(11, 50) <= sub_wire6(50); + sub_wire2(11, 51) <= sub_wire6(51); + sub_wire2(11, 52) <= sub_wire6(52); + sub_wire2(11, 53) <= sub_wire6(53); + sub_wire2(11, 54) <= sub_wire6(54); + sub_wire2(11, 55) <= sub_wire6(55); + sub_wire2(11, 56) <= sub_wire6(56); + sub_wire2(11, 57) <= sub_wire6(57); + sub_wire2(11, 58) <= sub_wire6(58); + sub_wire2(11, 59) <= sub_wire6(59); + sub_wire2(11, 60) <= sub_wire6(60); + sub_wire2(11, 61) <= sub_wire6(61); + sub_wire2(11, 62) <= sub_wire6(62); + sub_wire2(11, 63) <= sub_wire6(63); + sub_wire2(11, 64) <= sub_wire6(64); + sub_wire2(11, 65) <= sub_wire6(65); + sub_wire2(11, 66) <= sub_wire6(66); + sub_wire2(11, 67) <= sub_wire6(67); + sub_wire2(11, 68) <= sub_wire6(68); + sub_wire2(11, 69) <= sub_wire6(69); + sub_wire2(11, 70) <= sub_wire6(70); + sub_wire2(11, 71) <= sub_wire6(71); + sub_wire2(11, 72) <= sub_wire6(72); + sub_wire2(11, 73) <= sub_wire6(73); + sub_wire2(11, 74) <= sub_wire6(74); + sub_wire2(11, 75) <= sub_wire6(75); + sub_wire2(11, 76) <= sub_wire6(76); + sub_wire2(11, 77) <= sub_wire6(77); + sub_wire2(11, 78) <= sub_wire6(78); + sub_wire2(11, 79) <= sub_wire6(79); + sub_wire2(11, 80) <= sub_wire6(80); + sub_wire2(11, 81) <= sub_wire6(81); + sub_wire2(11, 82) <= sub_wire6(82); + sub_wire2(11, 83) <= sub_wire6(83); + sub_wire2(11, 84) <= sub_wire6(84); + sub_wire2(11, 85) <= sub_wire6(85); + sub_wire2(11, 86) <= sub_wire6(86); + sub_wire2(11, 87) <= sub_wire6(87); + sub_wire2(11, 88) <= sub_wire6(88); + sub_wire2(11, 89) <= sub_wire6(89); + sub_wire2(11, 90) <= sub_wire6(90); + sub_wire2(11, 91) <= sub_wire6(91); + sub_wire2(11, 92) <= sub_wire6(92); + sub_wire2(11, 93) <= sub_wire6(93); + sub_wire2(11, 94) <= sub_wire6(94); + sub_wire2(11, 95) <= sub_wire6(95); + sub_wire2(11, 96) <= sub_wire6(96); + sub_wire2(11, 97) <= sub_wire6(97); + sub_wire2(11, 98) <= sub_wire6(98); + sub_wire2(11, 99) <= sub_wire6(99); + sub_wire2(11, 100) <= sub_wire6(100); + sub_wire2(11, 101) <= sub_wire6(101); + sub_wire2(11, 102) <= sub_wire6(102); + sub_wire2(11, 103) <= sub_wire6(103); + sub_wire2(11, 104) <= sub_wire6(104); + sub_wire2(11, 105) <= sub_wire6(105); + sub_wire2(11, 106) <= sub_wire6(106); + sub_wire2(11, 107) <= sub_wire6(107); + sub_wire2(11, 108) <= sub_wire6(108); + sub_wire2(11, 109) <= sub_wire6(109); + sub_wire2(11, 110) <= sub_wire6(110); + sub_wire2(11, 111) <= sub_wire6(111); + sub_wire2(11, 112) <= sub_wire6(112); + sub_wire2(11, 113) <= sub_wire6(113); + sub_wire2(11, 114) <= sub_wire6(114); + sub_wire2(11, 115) <= sub_wire6(115); + sub_wire2(11, 116) <= sub_wire6(116); + sub_wire2(11, 117) <= sub_wire6(117); + sub_wire2(11, 118) <= sub_wire6(118); + sub_wire2(11, 119) <= sub_wire6(119); + sub_wire2(11, 120) <= sub_wire6(120); + sub_wire2(11, 121) <= sub_wire6(121); + sub_wire2(11, 122) <= sub_wire6(122); + sub_wire2(11, 123) <= sub_wire6(123); + sub_wire2(11, 124) <= sub_wire6(124); + sub_wire2(11, 125) <= sub_wire6(125); + sub_wire2(11, 126) <= sub_wire6(126); + sub_wire2(11, 127) <= sub_wire6(127); + sub_wire2(10, 0) <= sub_wire7(0); + sub_wire2(10, 1) <= sub_wire7(1); + sub_wire2(10, 2) <= sub_wire7(2); + sub_wire2(10, 3) <= sub_wire7(3); + sub_wire2(10, 4) <= sub_wire7(4); + sub_wire2(10, 5) <= sub_wire7(5); + sub_wire2(10, 6) <= sub_wire7(6); + sub_wire2(10, 7) <= sub_wire7(7); + sub_wire2(10, 8) <= sub_wire7(8); + sub_wire2(10, 9) <= sub_wire7(9); + sub_wire2(10, 10) <= sub_wire7(10); + sub_wire2(10, 11) <= sub_wire7(11); + sub_wire2(10, 12) <= sub_wire7(12); + sub_wire2(10, 13) <= sub_wire7(13); + sub_wire2(10, 14) <= sub_wire7(14); + sub_wire2(10, 15) <= sub_wire7(15); + sub_wire2(10, 16) <= sub_wire7(16); + sub_wire2(10, 17) <= sub_wire7(17); + sub_wire2(10, 18) <= sub_wire7(18); + sub_wire2(10, 19) <= sub_wire7(19); + sub_wire2(10, 20) <= sub_wire7(20); + sub_wire2(10, 21) <= sub_wire7(21); + sub_wire2(10, 22) <= sub_wire7(22); + sub_wire2(10, 23) <= sub_wire7(23); + sub_wire2(10, 24) <= sub_wire7(24); + sub_wire2(10, 25) <= sub_wire7(25); + sub_wire2(10, 26) <= sub_wire7(26); + sub_wire2(10, 27) <= sub_wire7(27); + sub_wire2(10, 28) <= sub_wire7(28); + sub_wire2(10, 29) <= sub_wire7(29); + sub_wire2(10, 30) <= sub_wire7(30); + sub_wire2(10, 31) <= sub_wire7(31); + sub_wire2(10, 32) <= sub_wire7(32); + sub_wire2(10, 33) <= sub_wire7(33); + sub_wire2(10, 34) <= sub_wire7(34); + sub_wire2(10, 35) <= sub_wire7(35); + sub_wire2(10, 36) <= sub_wire7(36); + sub_wire2(10, 37) <= sub_wire7(37); + sub_wire2(10, 38) <= sub_wire7(38); + sub_wire2(10, 39) <= sub_wire7(39); + sub_wire2(10, 40) <= sub_wire7(40); + sub_wire2(10, 41) <= sub_wire7(41); + sub_wire2(10, 42) <= sub_wire7(42); + sub_wire2(10, 43) <= sub_wire7(43); + sub_wire2(10, 44) <= sub_wire7(44); + sub_wire2(10, 45) <= sub_wire7(45); + sub_wire2(10, 46) <= sub_wire7(46); + sub_wire2(10, 47) <= sub_wire7(47); + sub_wire2(10, 48) <= sub_wire7(48); + sub_wire2(10, 49) <= sub_wire7(49); + sub_wire2(10, 50) <= sub_wire7(50); + sub_wire2(10, 51) <= sub_wire7(51); + sub_wire2(10, 52) <= sub_wire7(52); + sub_wire2(10, 53) <= sub_wire7(53); + sub_wire2(10, 54) <= sub_wire7(54); + sub_wire2(10, 55) <= sub_wire7(55); + sub_wire2(10, 56) <= sub_wire7(56); + sub_wire2(10, 57) <= sub_wire7(57); + sub_wire2(10, 58) <= sub_wire7(58); + sub_wire2(10, 59) <= sub_wire7(59); + sub_wire2(10, 60) <= sub_wire7(60); + sub_wire2(10, 61) <= sub_wire7(61); + sub_wire2(10, 62) <= sub_wire7(62); + sub_wire2(10, 63) <= sub_wire7(63); + sub_wire2(10, 64) <= sub_wire7(64); + sub_wire2(10, 65) <= sub_wire7(65); + sub_wire2(10, 66) <= sub_wire7(66); + sub_wire2(10, 67) <= sub_wire7(67); + sub_wire2(10, 68) <= sub_wire7(68); + sub_wire2(10, 69) <= sub_wire7(69); + sub_wire2(10, 70) <= sub_wire7(70); + sub_wire2(10, 71) <= sub_wire7(71); + sub_wire2(10, 72) <= sub_wire7(72); + sub_wire2(10, 73) <= sub_wire7(73); + sub_wire2(10, 74) <= sub_wire7(74); + sub_wire2(10, 75) <= sub_wire7(75); + sub_wire2(10, 76) <= sub_wire7(76); + sub_wire2(10, 77) <= sub_wire7(77); + sub_wire2(10, 78) <= sub_wire7(78); + sub_wire2(10, 79) <= sub_wire7(79); + sub_wire2(10, 80) <= sub_wire7(80); + sub_wire2(10, 81) <= sub_wire7(81); + sub_wire2(10, 82) <= sub_wire7(82); + sub_wire2(10, 83) <= sub_wire7(83); + sub_wire2(10, 84) <= sub_wire7(84); + sub_wire2(10, 85) <= sub_wire7(85); + sub_wire2(10, 86) <= sub_wire7(86); + sub_wire2(10, 87) <= sub_wire7(87); + sub_wire2(10, 88) <= sub_wire7(88); + sub_wire2(10, 89) <= sub_wire7(89); + sub_wire2(10, 90) <= sub_wire7(90); + sub_wire2(10, 91) <= sub_wire7(91); + sub_wire2(10, 92) <= sub_wire7(92); + sub_wire2(10, 93) <= sub_wire7(93); + sub_wire2(10, 94) <= sub_wire7(94); + sub_wire2(10, 95) <= sub_wire7(95); + sub_wire2(10, 96) <= sub_wire7(96); + sub_wire2(10, 97) <= sub_wire7(97); + sub_wire2(10, 98) <= sub_wire7(98); + sub_wire2(10, 99) <= sub_wire7(99); + sub_wire2(10, 100) <= sub_wire7(100); + sub_wire2(10, 101) <= sub_wire7(101); + sub_wire2(10, 102) <= sub_wire7(102); + sub_wire2(10, 103) <= sub_wire7(103); + sub_wire2(10, 104) <= sub_wire7(104); + sub_wire2(10, 105) <= sub_wire7(105); + sub_wire2(10, 106) <= sub_wire7(106); + sub_wire2(10, 107) <= sub_wire7(107); + sub_wire2(10, 108) <= sub_wire7(108); + sub_wire2(10, 109) <= sub_wire7(109); + sub_wire2(10, 110) <= sub_wire7(110); + sub_wire2(10, 111) <= sub_wire7(111); + sub_wire2(10, 112) <= sub_wire7(112); + sub_wire2(10, 113) <= sub_wire7(113); + sub_wire2(10, 114) <= sub_wire7(114); + sub_wire2(10, 115) <= sub_wire7(115); + sub_wire2(10, 116) <= sub_wire7(116); + sub_wire2(10, 117) <= sub_wire7(117); + sub_wire2(10, 118) <= sub_wire7(118); + sub_wire2(10, 119) <= sub_wire7(119); + sub_wire2(10, 120) <= sub_wire7(120); + sub_wire2(10, 121) <= sub_wire7(121); + sub_wire2(10, 122) <= sub_wire7(122); + sub_wire2(10, 123) <= sub_wire7(123); + sub_wire2(10, 124) <= sub_wire7(124); + sub_wire2(10, 125) <= sub_wire7(125); + sub_wire2(10, 126) <= sub_wire7(126); + sub_wire2(10, 127) <= sub_wire7(127); + sub_wire2(9, 0) <= sub_wire8(0); + sub_wire2(9, 1) <= sub_wire8(1); + sub_wire2(9, 2) <= sub_wire8(2); + sub_wire2(9, 3) <= sub_wire8(3); + sub_wire2(9, 4) <= sub_wire8(4); + sub_wire2(9, 5) <= sub_wire8(5); + sub_wire2(9, 6) <= sub_wire8(6); + sub_wire2(9, 7) <= sub_wire8(7); + sub_wire2(9, 8) <= sub_wire8(8); + sub_wire2(9, 9) <= sub_wire8(9); + sub_wire2(9, 10) <= sub_wire8(10); + sub_wire2(9, 11) <= sub_wire8(11); + sub_wire2(9, 12) <= sub_wire8(12); + sub_wire2(9, 13) <= sub_wire8(13); + sub_wire2(9, 14) <= sub_wire8(14); + sub_wire2(9, 15) <= sub_wire8(15); + sub_wire2(9, 16) <= sub_wire8(16); + sub_wire2(9, 17) <= sub_wire8(17); + sub_wire2(9, 18) <= sub_wire8(18); + sub_wire2(9, 19) <= sub_wire8(19); + sub_wire2(9, 20) <= sub_wire8(20); + sub_wire2(9, 21) <= sub_wire8(21); + sub_wire2(9, 22) <= sub_wire8(22); + sub_wire2(9, 23) <= sub_wire8(23); + sub_wire2(9, 24) <= sub_wire8(24); + sub_wire2(9, 25) <= sub_wire8(25); + sub_wire2(9, 26) <= sub_wire8(26); + sub_wire2(9, 27) <= sub_wire8(27); + sub_wire2(9, 28) <= sub_wire8(28); + sub_wire2(9, 29) <= sub_wire8(29); + sub_wire2(9, 30) <= sub_wire8(30); + sub_wire2(9, 31) <= sub_wire8(31); + sub_wire2(9, 32) <= sub_wire8(32); + sub_wire2(9, 33) <= sub_wire8(33); + sub_wire2(9, 34) <= sub_wire8(34); + sub_wire2(9, 35) <= sub_wire8(35); + sub_wire2(9, 36) <= sub_wire8(36); + sub_wire2(9, 37) <= sub_wire8(37); + sub_wire2(9, 38) <= sub_wire8(38); + sub_wire2(9, 39) <= sub_wire8(39); + sub_wire2(9, 40) <= sub_wire8(40); + sub_wire2(9, 41) <= sub_wire8(41); + sub_wire2(9, 42) <= sub_wire8(42); + sub_wire2(9, 43) <= sub_wire8(43); + sub_wire2(9, 44) <= sub_wire8(44); + sub_wire2(9, 45) <= sub_wire8(45); + sub_wire2(9, 46) <= sub_wire8(46); + sub_wire2(9, 47) <= sub_wire8(47); + sub_wire2(9, 48) <= sub_wire8(48); + sub_wire2(9, 49) <= sub_wire8(49); + sub_wire2(9, 50) <= sub_wire8(50); + sub_wire2(9, 51) <= sub_wire8(51); + sub_wire2(9, 52) <= sub_wire8(52); + sub_wire2(9, 53) <= sub_wire8(53); + sub_wire2(9, 54) <= sub_wire8(54); + sub_wire2(9, 55) <= sub_wire8(55); + sub_wire2(9, 56) <= sub_wire8(56); + sub_wire2(9, 57) <= sub_wire8(57); + sub_wire2(9, 58) <= sub_wire8(58); + sub_wire2(9, 59) <= sub_wire8(59); + sub_wire2(9, 60) <= sub_wire8(60); + sub_wire2(9, 61) <= sub_wire8(61); + sub_wire2(9, 62) <= sub_wire8(62); + sub_wire2(9, 63) <= sub_wire8(63); + sub_wire2(9, 64) <= sub_wire8(64); + sub_wire2(9, 65) <= sub_wire8(65); + sub_wire2(9, 66) <= sub_wire8(66); + sub_wire2(9, 67) <= sub_wire8(67); + sub_wire2(9, 68) <= sub_wire8(68); + sub_wire2(9, 69) <= sub_wire8(69); + sub_wire2(9, 70) <= sub_wire8(70); + sub_wire2(9, 71) <= sub_wire8(71); + sub_wire2(9, 72) <= sub_wire8(72); + sub_wire2(9, 73) <= sub_wire8(73); + sub_wire2(9, 74) <= sub_wire8(74); + sub_wire2(9, 75) <= sub_wire8(75); + sub_wire2(9, 76) <= sub_wire8(76); + sub_wire2(9, 77) <= sub_wire8(77); + sub_wire2(9, 78) <= sub_wire8(78); + sub_wire2(9, 79) <= sub_wire8(79); + sub_wire2(9, 80) <= sub_wire8(80); + sub_wire2(9, 81) <= sub_wire8(81); + sub_wire2(9, 82) <= sub_wire8(82); + sub_wire2(9, 83) <= sub_wire8(83); + sub_wire2(9, 84) <= sub_wire8(84); + sub_wire2(9, 85) <= sub_wire8(85); + sub_wire2(9, 86) <= sub_wire8(86); + sub_wire2(9, 87) <= sub_wire8(87); + sub_wire2(9, 88) <= sub_wire8(88); + sub_wire2(9, 89) <= sub_wire8(89); + sub_wire2(9, 90) <= sub_wire8(90); + sub_wire2(9, 91) <= sub_wire8(91); + sub_wire2(9, 92) <= sub_wire8(92); + sub_wire2(9, 93) <= sub_wire8(93); + sub_wire2(9, 94) <= sub_wire8(94); + sub_wire2(9, 95) <= sub_wire8(95); + sub_wire2(9, 96) <= sub_wire8(96); + sub_wire2(9, 97) <= sub_wire8(97); + sub_wire2(9, 98) <= sub_wire8(98); + sub_wire2(9, 99) <= sub_wire8(99); + sub_wire2(9, 100) <= sub_wire8(100); + sub_wire2(9, 101) <= sub_wire8(101); + sub_wire2(9, 102) <= sub_wire8(102); + sub_wire2(9, 103) <= sub_wire8(103); + sub_wire2(9, 104) <= sub_wire8(104); + sub_wire2(9, 105) <= sub_wire8(105); + sub_wire2(9, 106) <= sub_wire8(106); + sub_wire2(9, 107) <= sub_wire8(107); + sub_wire2(9, 108) <= sub_wire8(108); + sub_wire2(9, 109) <= sub_wire8(109); + sub_wire2(9, 110) <= sub_wire8(110); + sub_wire2(9, 111) <= sub_wire8(111); + sub_wire2(9, 112) <= sub_wire8(112); + sub_wire2(9, 113) <= sub_wire8(113); + sub_wire2(9, 114) <= sub_wire8(114); + sub_wire2(9, 115) <= sub_wire8(115); + sub_wire2(9, 116) <= sub_wire8(116); + sub_wire2(9, 117) <= sub_wire8(117); + sub_wire2(9, 118) <= sub_wire8(118); + sub_wire2(9, 119) <= sub_wire8(119); + sub_wire2(9, 120) <= sub_wire8(120); + sub_wire2(9, 121) <= sub_wire8(121); + sub_wire2(9, 122) <= sub_wire8(122); + sub_wire2(9, 123) <= sub_wire8(123); + sub_wire2(9, 124) <= sub_wire8(124); + sub_wire2(9, 125) <= sub_wire8(125); + sub_wire2(9, 126) <= sub_wire8(126); + sub_wire2(9, 127) <= sub_wire8(127); + sub_wire2(8, 0) <= sub_wire9(0); + sub_wire2(8, 1) <= sub_wire9(1); + sub_wire2(8, 2) <= sub_wire9(2); + sub_wire2(8, 3) <= sub_wire9(3); + sub_wire2(8, 4) <= sub_wire9(4); + sub_wire2(8, 5) <= sub_wire9(5); + sub_wire2(8, 6) <= sub_wire9(6); + sub_wire2(8, 7) <= sub_wire9(7); + sub_wire2(8, 8) <= sub_wire9(8); + sub_wire2(8, 9) <= sub_wire9(9); + sub_wire2(8, 10) <= sub_wire9(10); + sub_wire2(8, 11) <= sub_wire9(11); + sub_wire2(8, 12) <= sub_wire9(12); + sub_wire2(8, 13) <= sub_wire9(13); + sub_wire2(8, 14) <= sub_wire9(14); + sub_wire2(8, 15) <= sub_wire9(15); + sub_wire2(8, 16) <= sub_wire9(16); + sub_wire2(8, 17) <= sub_wire9(17); + sub_wire2(8, 18) <= sub_wire9(18); + sub_wire2(8, 19) <= sub_wire9(19); + sub_wire2(8, 20) <= sub_wire9(20); + sub_wire2(8, 21) <= sub_wire9(21); + sub_wire2(8, 22) <= sub_wire9(22); + sub_wire2(8, 23) <= sub_wire9(23); + sub_wire2(8, 24) <= sub_wire9(24); + sub_wire2(8, 25) <= sub_wire9(25); + sub_wire2(8, 26) <= sub_wire9(26); + sub_wire2(8, 27) <= sub_wire9(27); + sub_wire2(8, 28) <= sub_wire9(28); + sub_wire2(8, 29) <= sub_wire9(29); + sub_wire2(8, 30) <= sub_wire9(30); + sub_wire2(8, 31) <= sub_wire9(31); + sub_wire2(8, 32) <= sub_wire9(32); + sub_wire2(8, 33) <= sub_wire9(33); + sub_wire2(8, 34) <= sub_wire9(34); + sub_wire2(8, 35) <= sub_wire9(35); + sub_wire2(8, 36) <= sub_wire9(36); + sub_wire2(8, 37) <= sub_wire9(37); + sub_wire2(8, 38) <= sub_wire9(38); + sub_wire2(8, 39) <= sub_wire9(39); + sub_wire2(8, 40) <= sub_wire9(40); + sub_wire2(8, 41) <= sub_wire9(41); + sub_wire2(8, 42) <= sub_wire9(42); + sub_wire2(8, 43) <= sub_wire9(43); + sub_wire2(8, 44) <= sub_wire9(44); + sub_wire2(8, 45) <= sub_wire9(45); + sub_wire2(8, 46) <= sub_wire9(46); + sub_wire2(8, 47) <= sub_wire9(47); + sub_wire2(8, 48) <= sub_wire9(48); + sub_wire2(8, 49) <= sub_wire9(49); + sub_wire2(8, 50) <= sub_wire9(50); + sub_wire2(8, 51) <= sub_wire9(51); + sub_wire2(8, 52) <= sub_wire9(52); + sub_wire2(8, 53) <= sub_wire9(53); + sub_wire2(8, 54) <= sub_wire9(54); + sub_wire2(8, 55) <= sub_wire9(55); + sub_wire2(8, 56) <= sub_wire9(56); + sub_wire2(8, 57) <= sub_wire9(57); + sub_wire2(8, 58) <= sub_wire9(58); + sub_wire2(8, 59) <= sub_wire9(59); + sub_wire2(8, 60) <= sub_wire9(60); + sub_wire2(8, 61) <= sub_wire9(61); + sub_wire2(8, 62) <= sub_wire9(62); + sub_wire2(8, 63) <= sub_wire9(63); + sub_wire2(8, 64) <= sub_wire9(64); + sub_wire2(8, 65) <= sub_wire9(65); + sub_wire2(8, 66) <= sub_wire9(66); + sub_wire2(8, 67) <= sub_wire9(67); + sub_wire2(8, 68) <= sub_wire9(68); + sub_wire2(8, 69) <= sub_wire9(69); + sub_wire2(8, 70) <= sub_wire9(70); + sub_wire2(8, 71) <= sub_wire9(71); + sub_wire2(8, 72) <= sub_wire9(72); + sub_wire2(8, 73) <= sub_wire9(73); + sub_wire2(8, 74) <= sub_wire9(74); + sub_wire2(8, 75) <= sub_wire9(75); + sub_wire2(8, 76) <= sub_wire9(76); + sub_wire2(8, 77) <= sub_wire9(77); + sub_wire2(8, 78) <= sub_wire9(78); + sub_wire2(8, 79) <= sub_wire9(79); + sub_wire2(8, 80) <= sub_wire9(80); + sub_wire2(8, 81) <= sub_wire9(81); + sub_wire2(8, 82) <= sub_wire9(82); + sub_wire2(8, 83) <= sub_wire9(83); + sub_wire2(8, 84) <= sub_wire9(84); + sub_wire2(8, 85) <= sub_wire9(85); + sub_wire2(8, 86) <= sub_wire9(86); + sub_wire2(8, 87) <= sub_wire9(87); + sub_wire2(8, 88) <= sub_wire9(88); + sub_wire2(8, 89) <= sub_wire9(89); + sub_wire2(8, 90) <= sub_wire9(90); + sub_wire2(8, 91) <= sub_wire9(91); + sub_wire2(8, 92) <= sub_wire9(92); + sub_wire2(8, 93) <= sub_wire9(93); + sub_wire2(8, 94) <= sub_wire9(94); + sub_wire2(8, 95) <= sub_wire9(95); + sub_wire2(8, 96) <= sub_wire9(96); + sub_wire2(8, 97) <= sub_wire9(97); + sub_wire2(8, 98) <= sub_wire9(98); + sub_wire2(8, 99) <= sub_wire9(99); + sub_wire2(8, 100) <= sub_wire9(100); + sub_wire2(8, 101) <= sub_wire9(101); + sub_wire2(8, 102) <= sub_wire9(102); + sub_wire2(8, 103) <= sub_wire9(103); + sub_wire2(8, 104) <= sub_wire9(104); + sub_wire2(8, 105) <= sub_wire9(105); + sub_wire2(8, 106) <= sub_wire9(106); + sub_wire2(8, 107) <= sub_wire9(107); + sub_wire2(8, 108) <= sub_wire9(108); + sub_wire2(8, 109) <= sub_wire9(109); + sub_wire2(8, 110) <= sub_wire9(110); + sub_wire2(8, 111) <= sub_wire9(111); + sub_wire2(8, 112) <= sub_wire9(112); + sub_wire2(8, 113) <= sub_wire9(113); + sub_wire2(8, 114) <= sub_wire9(114); + sub_wire2(8, 115) <= sub_wire9(115); + sub_wire2(8, 116) <= sub_wire9(116); + sub_wire2(8, 117) <= sub_wire9(117); + sub_wire2(8, 118) <= sub_wire9(118); + sub_wire2(8, 119) <= sub_wire9(119); + sub_wire2(8, 120) <= sub_wire9(120); + sub_wire2(8, 121) <= sub_wire9(121); + sub_wire2(8, 122) <= sub_wire9(122); + sub_wire2(8, 123) <= sub_wire9(123); + sub_wire2(8, 124) <= sub_wire9(124); + sub_wire2(8, 125) <= sub_wire9(125); + sub_wire2(8, 126) <= sub_wire9(126); + sub_wire2(8, 127) <= sub_wire9(127); + sub_wire2(7, 0) <= sub_wire10(0); + sub_wire2(7, 1) <= sub_wire10(1); + sub_wire2(7, 2) <= sub_wire10(2); + sub_wire2(7, 3) <= sub_wire10(3); + sub_wire2(7, 4) <= sub_wire10(4); + sub_wire2(7, 5) <= sub_wire10(5); + sub_wire2(7, 6) <= sub_wire10(6); + sub_wire2(7, 7) <= sub_wire10(7); + sub_wire2(7, 8) <= sub_wire10(8); + sub_wire2(7, 9) <= sub_wire10(9); + sub_wire2(7, 10) <= sub_wire10(10); + sub_wire2(7, 11) <= sub_wire10(11); + sub_wire2(7, 12) <= sub_wire10(12); + sub_wire2(7, 13) <= sub_wire10(13); + sub_wire2(7, 14) <= sub_wire10(14); + sub_wire2(7, 15) <= sub_wire10(15); + sub_wire2(7, 16) <= sub_wire10(16); + sub_wire2(7, 17) <= sub_wire10(17); + sub_wire2(7, 18) <= sub_wire10(18); + sub_wire2(7, 19) <= sub_wire10(19); + sub_wire2(7, 20) <= sub_wire10(20); + sub_wire2(7, 21) <= sub_wire10(21); + sub_wire2(7, 22) <= sub_wire10(22); + sub_wire2(7, 23) <= sub_wire10(23); + sub_wire2(7, 24) <= sub_wire10(24); + sub_wire2(7, 25) <= sub_wire10(25); + sub_wire2(7, 26) <= sub_wire10(26); + sub_wire2(7, 27) <= sub_wire10(27); + sub_wire2(7, 28) <= sub_wire10(28); + sub_wire2(7, 29) <= sub_wire10(29); + sub_wire2(7, 30) <= sub_wire10(30); + sub_wire2(7, 31) <= sub_wire10(31); + sub_wire2(7, 32) <= sub_wire10(32); + sub_wire2(7, 33) <= sub_wire10(33); + sub_wire2(7, 34) <= sub_wire10(34); + sub_wire2(7, 35) <= sub_wire10(35); + sub_wire2(7, 36) <= sub_wire10(36); + sub_wire2(7, 37) <= sub_wire10(37); + sub_wire2(7, 38) <= sub_wire10(38); + sub_wire2(7, 39) <= sub_wire10(39); + sub_wire2(7, 40) <= sub_wire10(40); + sub_wire2(7, 41) <= sub_wire10(41); + sub_wire2(7, 42) <= sub_wire10(42); + sub_wire2(7, 43) <= sub_wire10(43); + sub_wire2(7, 44) <= sub_wire10(44); + sub_wire2(7, 45) <= sub_wire10(45); + sub_wire2(7, 46) <= sub_wire10(46); + sub_wire2(7, 47) <= sub_wire10(47); + sub_wire2(7, 48) <= sub_wire10(48); + sub_wire2(7, 49) <= sub_wire10(49); + sub_wire2(7, 50) <= sub_wire10(50); + sub_wire2(7, 51) <= sub_wire10(51); + sub_wire2(7, 52) <= sub_wire10(52); + sub_wire2(7, 53) <= sub_wire10(53); + sub_wire2(7, 54) <= sub_wire10(54); + sub_wire2(7, 55) <= sub_wire10(55); + sub_wire2(7, 56) <= sub_wire10(56); + sub_wire2(7, 57) <= sub_wire10(57); + sub_wire2(7, 58) <= sub_wire10(58); + sub_wire2(7, 59) <= sub_wire10(59); + sub_wire2(7, 60) <= sub_wire10(60); + sub_wire2(7, 61) <= sub_wire10(61); + sub_wire2(7, 62) <= sub_wire10(62); + sub_wire2(7, 63) <= sub_wire10(63); + sub_wire2(7, 64) <= sub_wire10(64); + sub_wire2(7, 65) <= sub_wire10(65); + sub_wire2(7, 66) <= sub_wire10(66); + sub_wire2(7, 67) <= sub_wire10(67); + sub_wire2(7, 68) <= sub_wire10(68); + sub_wire2(7, 69) <= sub_wire10(69); + sub_wire2(7, 70) <= sub_wire10(70); + sub_wire2(7, 71) <= sub_wire10(71); + sub_wire2(7, 72) <= sub_wire10(72); + sub_wire2(7, 73) <= sub_wire10(73); + sub_wire2(7, 74) <= sub_wire10(74); + sub_wire2(7, 75) <= sub_wire10(75); + sub_wire2(7, 76) <= sub_wire10(76); + sub_wire2(7, 77) <= sub_wire10(77); + sub_wire2(7, 78) <= sub_wire10(78); + sub_wire2(7, 79) <= sub_wire10(79); + sub_wire2(7, 80) <= sub_wire10(80); + sub_wire2(7, 81) <= sub_wire10(81); + sub_wire2(7, 82) <= sub_wire10(82); + sub_wire2(7, 83) <= sub_wire10(83); + sub_wire2(7, 84) <= sub_wire10(84); + sub_wire2(7, 85) <= sub_wire10(85); + sub_wire2(7, 86) <= sub_wire10(86); + sub_wire2(7, 87) <= sub_wire10(87); + sub_wire2(7, 88) <= sub_wire10(88); + sub_wire2(7, 89) <= sub_wire10(89); + sub_wire2(7, 90) <= sub_wire10(90); + sub_wire2(7, 91) <= sub_wire10(91); + sub_wire2(7, 92) <= sub_wire10(92); + sub_wire2(7, 93) <= sub_wire10(93); + sub_wire2(7, 94) <= sub_wire10(94); + sub_wire2(7, 95) <= sub_wire10(95); + sub_wire2(7, 96) <= sub_wire10(96); + sub_wire2(7, 97) <= sub_wire10(97); + sub_wire2(7, 98) <= sub_wire10(98); + sub_wire2(7, 99) <= sub_wire10(99); + sub_wire2(7, 100) <= sub_wire10(100); + sub_wire2(7, 101) <= sub_wire10(101); + sub_wire2(7, 102) <= sub_wire10(102); + sub_wire2(7, 103) <= sub_wire10(103); + sub_wire2(7, 104) <= sub_wire10(104); + sub_wire2(7, 105) <= sub_wire10(105); + sub_wire2(7, 106) <= sub_wire10(106); + sub_wire2(7, 107) <= sub_wire10(107); + sub_wire2(7, 108) <= sub_wire10(108); + sub_wire2(7, 109) <= sub_wire10(109); + sub_wire2(7, 110) <= sub_wire10(110); + sub_wire2(7, 111) <= sub_wire10(111); + sub_wire2(7, 112) <= sub_wire10(112); + sub_wire2(7, 113) <= sub_wire10(113); + sub_wire2(7, 114) <= sub_wire10(114); + sub_wire2(7, 115) <= sub_wire10(115); + sub_wire2(7, 116) <= sub_wire10(116); + sub_wire2(7, 117) <= sub_wire10(117); + sub_wire2(7, 118) <= sub_wire10(118); + sub_wire2(7, 119) <= sub_wire10(119); + sub_wire2(7, 120) <= sub_wire10(120); + sub_wire2(7, 121) <= sub_wire10(121); + sub_wire2(7, 122) <= sub_wire10(122); + sub_wire2(7, 123) <= sub_wire10(123); + sub_wire2(7, 124) <= sub_wire10(124); + sub_wire2(7, 125) <= sub_wire10(125); + sub_wire2(7, 126) <= sub_wire10(126); + sub_wire2(7, 127) <= sub_wire10(127); + sub_wire2(6, 0) <= sub_wire11(0); + sub_wire2(6, 1) <= sub_wire11(1); + sub_wire2(6, 2) <= sub_wire11(2); + sub_wire2(6, 3) <= sub_wire11(3); + sub_wire2(6, 4) <= sub_wire11(4); + sub_wire2(6, 5) <= sub_wire11(5); + sub_wire2(6, 6) <= sub_wire11(6); + sub_wire2(6, 7) <= sub_wire11(7); + sub_wire2(6, 8) <= sub_wire11(8); + sub_wire2(6, 9) <= sub_wire11(9); + sub_wire2(6, 10) <= sub_wire11(10); + sub_wire2(6, 11) <= sub_wire11(11); + sub_wire2(6, 12) <= sub_wire11(12); + sub_wire2(6, 13) <= sub_wire11(13); + sub_wire2(6, 14) <= sub_wire11(14); + sub_wire2(6, 15) <= sub_wire11(15); + sub_wire2(6, 16) <= sub_wire11(16); + sub_wire2(6, 17) <= sub_wire11(17); + sub_wire2(6, 18) <= sub_wire11(18); + sub_wire2(6, 19) <= sub_wire11(19); + sub_wire2(6, 20) <= sub_wire11(20); + sub_wire2(6, 21) <= sub_wire11(21); + sub_wire2(6, 22) <= sub_wire11(22); + sub_wire2(6, 23) <= sub_wire11(23); + sub_wire2(6, 24) <= sub_wire11(24); + sub_wire2(6, 25) <= sub_wire11(25); + sub_wire2(6, 26) <= sub_wire11(26); + sub_wire2(6, 27) <= sub_wire11(27); + sub_wire2(6, 28) <= sub_wire11(28); + sub_wire2(6, 29) <= sub_wire11(29); + sub_wire2(6, 30) <= sub_wire11(30); + sub_wire2(6, 31) <= sub_wire11(31); + sub_wire2(6, 32) <= sub_wire11(32); + sub_wire2(6, 33) <= sub_wire11(33); + sub_wire2(6, 34) <= sub_wire11(34); + sub_wire2(6, 35) <= sub_wire11(35); + sub_wire2(6, 36) <= sub_wire11(36); + sub_wire2(6, 37) <= sub_wire11(37); + sub_wire2(6, 38) <= sub_wire11(38); + sub_wire2(6, 39) <= sub_wire11(39); + sub_wire2(6, 40) <= sub_wire11(40); + sub_wire2(6, 41) <= sub_wire11(41); + sub_wire2(6, 42) <= sub_wire11(42); + sub_wire2(6, 43) <= sub_wire11(43); + sub_wire2(6, 44) <= sub_wire11(44); + sub_wire2(6, 45) <= sub_wire11(45); + sub_wire2(6, 46) <= sub_wire11(46); + sub_wire2(6, 47) <= sub_wire11(47); + sub_wire2(6, 48) <= sub_wire11(48); + sub_wire2(6, 49) <= sub_wire11(49); + sub_wire2(6, 50) <= sub_wire11(50); + sub_wire2(6, 51) <= sub_wire11(51); + sub_wire2(6, 52) <= sub_wire11(52); + sub_wire2(6, 53) <= sub_wire11(53); + sub_wire2(6, 54) <= sub_wire11(54); + sub_wire2(6, 55) <= sub_wire11(55); + sub_wire2(6, 56) <= sub_wire11(56); + sub_wire2(6, 57) <= sub_wire11(57); + sub_wire2(6, 58) <= sub_wire11(58); + sub_wire2(6, 59) <= sub_wire11(59); + sub_wire2(6, 60) <= sub_wire11(60); + sub_wire2(6, 61) <= sub_wire11(61); + sub_wire2(6, 62) <= sub_wire11(62); + sub_wire2(6, 63) <= sub_wire11(63); + sub_wire2(6, 64) <= sub_wire11(64); + sub_wire2(6, 65) <= sub_wire11(65); + sub_wire2(6, 66) <= sub_wire11(66); + sub_wire2(6, 67) <= sub_wire11(67); + sub_wire2(6, 68) <= sub_wire11(68); + sub_wire2(6, 69) <= sub_wire11(69); + sub_wire2(6, 70) <= sub_wire11(70); + sub_wire2(6, 71) <= sub_wire11(71); + sub_wire2(6, 72) <= sub_wire11(72); + sub_wire2(6, 73) <= sub_wire11(73); + sub_wire2(6, 74) <= sub_wire11(74); + sub_wire2(6, 75) <= sub_wire11(75); + sub_wire2(6, 76) <= sub_wire11(76); + sub_wire2(6, 77) <= sub_wire11(77); + sub_wire2(6, 78) <= sub_wire11(78); + sub_wire2(6, 79) <= sub_wire11(79); + sub_wire2(6, 80) <= sub_wire11(80); + sub_wire2(6, 81) <= sub_wire11(81); + sub_wire2(6, 82) <= sub_wire11(82); + sub_wire2(6, 83) <= sub_wire11(83); + sub_wire2(6, 84) <= sub_wire11(84); + sub_wire2(6, 85) <= sub_wire11(85); + sub_wire2(6, 86) <= sub_wire11(86); + sub_wire2(6, 87) <= sub_wire11(87); + sub_wire2(6, 88) <= sub_wire11(88); + sub_wire2(6, 89) <= sub_wire11(89); + sub_wire2(6, 90) <= sub_wire11(90); + sub_wire2(6, 91) <= sub_wire11(91); + sub_wire2(6, 92) <= sub_wire11(92); + sub_wire2(6, 93) <= sub_wire11(93); + sub_wire2(6, 94) <= sub_wire11(94); + sub_wire2(6, 95) <= sub_wire11(95); + sub_wire2(6, 96) <= sub_wire11(96); + sub_wire2(6, 97) <= sub_wire11(97); + sub_wire2(6, 98) <= sub_wire11(98); + sub_wire2(6, 99) <= sub_wire11(99); + sub_wire2(6, 100) <= sub_wire11(100); + sub_wire2(6, 101) <= sub_wire11(101); + sub_wire2(6, 102) <= sub_wire11(102); + sub_wire2(6, 103) <= sub_wire11(103); + sub_wire2(6, 104) <= sub_wire11(104); + sub_wire2(6, 105) <= sub_wire11(105); + sub_wire2(6, 106) <= sub_wire11(106); + sub_wire2(6, 107) <= sub_wire11(107); + sub_wire2(6, 108) <= sub_wire11(108); + sub_wire2(6, 109) <= sub_wire11(109); + sub_wire2(6, 110) <= sub_wire11(110); + sub_wire2(6, 111) <= sub_wire11(111); + sub_wire2(6, 112) <= sub_wire11(112); + sub_wire2(6, 113) <= sub_wire11(113); + sub_wire2(6, 114) <= sub_wire11(114); + sub_wire2(6, 115) <= sub_wire11(115); + sub_wire2(6, 116) <= sub_wire11(116); + sub_wire2(6, 117) <= sub_wire11(117); + sub_wire2(6, 118) <= sub_wire11(118); + sub_wire2(6, 119) <= sub_wire11(119); + sub_wire2(6, 120) <= sub_wire11(120); + sub_wire2(6, 121) <= sub_wire11(121); + sub_wire2(6, 122) <= sub_wire11(122); + sub_wire2(6, 123) <= sub_wire11(123); + sub_wire2(6, 124) <= sub_wire11(124); + sub_wire2(6, 125) <= sub_wire11(125); + sub_wire2(6, 126) <= sub_wire11(126); + sub_wire2(6, 127) <= sub_wire11(127); + sub_wire2(5, 0) <= sub_wire12(0); + sub_wire2(5, 1) <= sub_wire12(1); + sub_wire2(5, 2) <= sub_wire12(2); + sub_wire2(5, 3) <= sub_wire12(3); + sub_wire2(5, 4) <= sub_wire12(4); + sub_wire2(5, 5) <= sub_wire12(5); + sub_wire2(5, 6) <= sub_wire12(6); + sub_wire2(5, 7) <= sub_wire12(7); + sub_wire2(5, 8) <= sub_wire12(8); + sub_wire2(5, 9) <= sub_wire12(9); + sub_wire2(5, 10) <= sub_wire12(10); + sub_wire2(5, 11) <= sub_wire12(11); + sub_wire2(5, 12) <= sub_wire12(12); + sub_wire2(5, 13) <= sub_wire12(13); + sub_wire2(5, 14) <= sub_wire12(14); + sub_wire2(5, 15) <= sub_wire12(15); + sub_wire2(5, 16) <= sub_wire12(16); + sub_wire2(5, 17) <= sub_wire12(17); + sub_wire2(5, 18) <= sub_wire12(18); + sub_wire2(5, 19) <= sub_wire12(19); + sub_wire2(5, 20) <= sub_wire12(20); + sub_wire2(5, 21) <= sub_wire12(21); + sub_wire2(5, 22) <= sub_wire12(22); + sub_wire2(5, 23) <= sub_wire12(23); + sub_wire2(5, 24) <= sub_wire12(24); + sub_wire2(5, 25) <= sub_wire12(25); + sub_wire2(5, 26) <= sub_wire12(26); + sub_wire2(5, 27) <= sub_wire12(27); + sub_wire2(5, 28) <= sub_wire12(28); + sub_wire2(5, 29) <= sub_wire12(29); + sub_wire2(5, 30) <= sub_wire12(30); + sub_wire2(5, 31) <= sub_wire12(31); + sub_wire2(5, 32) <= sub_wire12(32); + sub_wire2(5, 33) <= sub_wire12(33); + sub_wire2(5, 34) <= sub_wire12(34); + sub_wire2(5, 35) <= sub_wire12(35); + sub_wire2(5, 36) <= sub_wire12(36); + sub_wire2(5, 37) <= sub_wire12(37); + sub_wire2(5, 38) <= sub_wire12(38); + sub_wire2(5, 39) <= sub_wire12(39); + sub_wire2(5, 40) <= sub_wire12(40); + sub_wire2(5, 41) <= sub_wire12(41); + sub_wire2(5, 42) <= sub_wire12(42); + sub_wire2(5, 43) <= sub_wire12(43); + sub_wire2(5, 44) <= sub_wire12(44); + sub_wire2(5, 45) <= sub_wire12(45); + sub_wire2(5, 46) <= sub_wire12(46); + sub_wire2(5, 47) <= sub_wire12(47); + sub_wire2(5, 48) <= sub_wire12(48); + sub_wire2(5, 49) <= sub_wire12(49); + sub_wire2(5, 50) <= sub_wire12(50); + sub_wire2(5, 51) <= sub_wire12(51); + sub_wire2(5, 52) <= sub_wire12(52); + sub_wire2(5, 53) <= sub_wire12(53); + sub_wire2(5, 54) <= sub_wire12(54); + sub_wire2(5, 55) <= sub_wire12(55); + sub_wire2(5, 56) <= sub_wire12(56); + sub_wire2(5, 57) <= sub_wire12(57); + sub_wire2(5, 58) <= sub_wire12(58); + sub_wire2(5, 59) <= sub_wire12(59); + sub_wire2(5, 60) <= sub_wire12(60); + sub_wire2(5, 61) <= sub_wire12(61); + sub_wire2(5, 62) <= sub_wire12(62); + sub_wire2(5, 63) <= sub_wire12(63); + sub_wire2(5, 64) <= sub_wire12(64); + sub_wire2(5, 65) <= sub_wire12(65); + sub_wire2(5, 66) <= sub_wire12(66); + sub_wire2(5, 67) <= sub_wire12(67); + sub_wire2(5, 68) <= sub_wire12(68); + sub_wire2(5, 69) <= sub_wire12(69); + sub_wire2(5, 70) <= sub_wire12(70); + sub_wire2(5, 71) <= sub_wire12(71); + sub_wire2(5, 72) <= sub_wire12(72); + sub_wire2(5, 73) <= sub_wire12(73); + sub_wire2(5, 74) <= sub_wire12(74); + sub_wire2(5, 75) <= sub_wire12(75); + sub_wire2(5, 76) <= sub_wire12(76); + sub_wire2(5, 77) <= sub_wire12(77); + sub_wire2(5, 78) <= sub_wire12(78); + sub_wire2(5, 79) <= sub_wire12(79); + sub_wire2(5, 80) <= sub_wire12(80); + sub_wire2(5, 81) <= sub_wire12(81); + sub_wire2(5, 82) <= sub_wire12(82); + sub_wire2(5, 83) <= sub_wire12(83); + sub_wire2(5, 84) <= sub_wire12(84); + sub_wire2(5, 85) <= sub_wire12(85); + sub_wire2(5, 86) <= sub_wire12(86); + sub_wire2(5, 87) <= sub_wire12(87); + sub_wire2(5, 88) <= sub_wire12(88); + sub_wire2(5, 89) <= sub_wire12(89); + sub_wire2(5, 90) <= sub_wire12(90); + sub_wire2(5, 91) <= sub_wire12(91); + sub_wire2(5, 92) <= sub_wire12(92); + sub_wire2(5, 93) <= sub_wire12(93); + sub_wire2(5, 94) <= sub_wire12(94); + sub_wire2(5, 95) <= sub_wire12(95); + sub_wire2(5, 96) <= sub_wire12(96); + sub_wire2(5, 97) <= sub_wire12(97); + sub_wire2(5, 98) <= sub_wire12(98); + sub_wire2(5, 99) <= sub_wire12(99); + sub_wire2(5, 100) <= sub_wire12(100); + sub_wire2(5, 101) <= sub_wire12(101); + sub_wire2(5, 102) <= sub_wire12(102); + sub_wire2(5, 103) <= sub_wire12(103); + sub_wire2(5, 104) <= sub_wire12(104); + sub_wire2(5, 105) <= sub_wire12(105); + sub_wire2(5, 106) <= sub_wire12(106); + sub_wire2(5, 107) <= sub_wire12(107); + sub_wire2(5, 108) <= sub_wire12(108); + sub_wire2(5, 109) <= sub_wire12(109); + sub_wire2(5, 110) <= sub_wire12(110); + sub_wire2(5, 111) <= sub_wire12(111); + sub_wire2(5, 112) <= sub_wire12(112); + sub_wire2(5, 113) <= sub_wire12(113); + sub_wire2(5, 114) <= sub_wire12(114); + sub_wire2(5, 115) <= sub_wire12(115); + sub_wire2(5, 116) <= sub_wire12(116); + sub_wire2(5, 117) <= sub_wire12(117); + sub_wire2(5, 118) <= sub_wire12(118); + sub_wire2(5, 119) <= sub_wire12(119); + sub_wire2(5, 120) <= sub_wire12(120); + sub_wire2(5, 121) <= sub_wire12(121); + sub_wire2(5, 122) <= sub_wire12(122); + sub_wire2(5, 123) <= sub_wire12(123); + sub_wire2(5, 124) <= sub_wire12(124); + sub_wire2(5, 125) <= sub_wire12(125); + sub_wire2(5, 126) <= sub_wire12(126); + sub_wire2(5, 127) <= sub_wire12(127); + sub_wire2(4, 0) <= sub_wire13(0); + sub_wire2(4, 1) <= sub_wire13(1); + sub_wire2(4, 2) <= sub_wire13(2); + sub_wire2(4, 3) <= sub_wire13(3); + sub_wire2(4, 4) <= sub_wire13(4); + sub_wire2(4, 5) <= sub_wire13(5); + sub_wire2(4, 6) <= sub_wire13(6); + sub_wire2(4, 7) <= sub_wire13(7); + sub_wire2(4, 8) <= sub_wire13(8); + sub_wire2(4, 9) <= sub_wire13(9); + sub_wire2(4, 10) <= sub_wire13(10); + sub_wire2(4, 11) <= sub_wire13(11); + sub_wire2(4, 12) <= sub_wire13(12); + sub_wire2(4, 13) <= sub_wire13(13); + sub_wire2(4, 14) <= sub_wire13(14); + sub_wire2(4, 15) <= sub_wire13(15); + sub_wire2(4, 16) <= sub_wire13(16); + sub_wire2(4, 17) <= sub_wire13(17); + sub_wire2(4, 18) <= sub_wire13(18); + sub_wire2(4, 19) <= sub_wire13(19); + sub_wire2(4, 20) <= sub_wire13(20); + sub_wire2(4, 21) <= sub_wire13(21); + sub_wire2(4, 22) <= sub_wire13(22); + sub_wire2(4, 23) <= sub_wire13(23); + sub_wire2(4, 24) <= sub_wire13(24); + sub_wire2(4, 25) <= sub_wire13(25); + sub_wire2(4, 26) <= sub_wire13(26); + sub_wire2(4, 27) <= sub_wire13(27); + sub_wire2(4, 28) <= sub_wire13(28); + sub_wire2(4, 29) <= sub_wire13(29); + sub_wire2(4, 30) <= sub_wire13(30); + sub_wire2(4, 31) <= sub_wire13(31); + sub_wire2(4, 32) <= sub_wire13(32); + sub_wire2(4, 33) <= sub_wire13(33); + sub_wire2(4, 34) <= sub_wire13(34); + sub_wire2(4, 35) <= sub_wire13(35); + sub_wire2(4, 36) <= sub_wire13(36); + sub_wire2(4, 37) <= sub_wire13(37); + sub_wire2(4, 38) <= sub_wire13(38); + sub_wire2(4, 39) <= sub_wire13(39); + sub_wire2(4, 40) <= sub_wire13(40); + sub_wire2(4, 41) <= sub_wire13(41); + sub_wire2(4, 42) <= sub_wire13(42); + sub_wire2(4, 43) <= sub_wire13(43); + sub_wire2(4, 44) <= sub_wire13(44); + sub_wire2(4, 45) <= sub_wire13(45); + sub_wire2(4, 46) <= sub_wire13(46); + sub_wire2(4, 47) <= sub_wire13(47); + sub_wire2(4, 48) <= sub_wire13(48); + sub_wire2(4, 49) <= sub_wire13(49); + sub_wire2(4, 50) <= sub_wire13(50); + sub_wire2(4, 51) <= sub_wire13(51); + sub_wire2(4, 52) <= sub_wire13(52); + sub_wire2(4, 53) <= sub_wire13(53); + sub_wire2(4, 54) <= sub_wire13(54); + sub_wire2(4, 55) <= sub_wire13(55); + sub_wire2(4, 56) <= sub_wire13(56); + sub_wire2(4, 57) <= sub_wire13(57); + sub_wire2(4, 58) <= sub_wire13(58); + sub_wire2(4, 59) <= sub_wire13(59); + sub_wire2(4, 60) <= sub_wire13(60); + sub_wire2(4, 61) <= sub_wire13(61); + sub_wire2(4, 62) <= sub_wire13(62); + sub_wire2(4, 63) <= sub_wire13(63); + sub_wire2(4, 64) <= sub_wire13(64); + sub_wire2(4, 65) <= sub_wire13(65); + sub_wire2(4, 66) <= sub_wire13(66); + sub_wire2(4, 67) <= sub_wire13(67); + sub_wire2(4, 68) <= sub_wire13(68); + sub_wire2(4, 69) <= sub_wire13(69); + sub_wire2(4, 70) <= sub_wire13(70); + sub_wire2(4, 71) <= sub_wire13(71); + sub_wire2(4, 72) <= sub_wire13(72); + sub_wire2(4, 73) <= sub_wire13(73); + sub_wire2(4, 74) <= sub_wire13(74); + sub_wire2(4, 75) <= sub_wire13(75); + sub_wire2(4, 76) <= sub_wire13(76); + sub_wire2(4, 77) <= sub_wire13(77); + sub_wire2(4, 78) <= sub_wire13(78); + sub_wire2(4, 79) <= sub_wire13(79); + sub_wire2(4, 80) <= sub_wire13(80); + sub_wire2(4, 81) <= sub_wire13(81); + sub_wire2(4, 82) <= sub_wire13(82); + sub_wire2(4, 83) <= sub_wire13(83); + sub_wire2(4, 84) <= sub_wire13(84); + sub_wire2(4, 85) <= sub_wire13(85); + sub_wire2(4, 86) <= sub_wire13(86); + sub_wire2(4, 87) <= sub_wire13(87); + sub_wire2(4, 88) <= sub_wire13(88); + sub_wire2(4, 89) <= sub_wire13(89); + sub_wire2(4, 90) <= sub_wire13(90); + sub_wire2(4, 91) <= sub_wire13(91); + sub_wire2(4, 92) <= sub_wire13(92); + sub_wire2(4, 93) <= sub_wire13(93); + sub_wire2(4, 94) <= sub_wire13(94); + sub_wire2(4, 95) <= sub_wire13(95); + sub_wire2(4, 96) <= sub_wire13(96); + sub_wire2(4, 97) <= sub_wire13(97); + sub_wire2(4, 98) <= sub_wire13(98); + sub_wire2(4, 99) <= sub_wire13(99); + sub_wire2(4, 100) <= sub_wire13(100); + sub_wire2(4, 101) <= sub_wire13(101); + sub_wire2(4, 102) <= sub_wire13(102); + sub_wire2(4, 103) <= sub_wire13(103); + sub_wire2(4, 104) <= sub_wire13(104); + sub_wire2(4, 105) <= sub_wire13(105); + sub_wire2(4, 106) <= sub_wire13(106); + sub_wire2(4, 107) <= sub_wire13(107); + sub_wire2(4, 108) <= sub_wire13(108); + sub_wire2(4, 109) <= sub_wire13(109); + sub_wire2(4, 110) <= sub_wire13(110); + sub_wire2(4, 111) <= sub_wire13(111); + sub_wire2(4, 112) <= sub_wire13(112); + sub_wire2(4, 113) <= sub_wire13(113); + sub_wire2(4, 114) <= sub_wire13(114); + sub_wire2(4, 115) <= sub_wire13(115); + sub_wire2(4, 116) <= sub_wire13(116); + sub_wire2(4, 117) <= sub_wire13(117); + sub_wire2(4, 118) <= sub_wire13(118); + sub_wire2(4, 119) <= sub_wire13(119); + sub_wire2(4, 120) <= sub_wire13(120); + sub_wire2(4, 121) <= sub_wire13(121); + sub_wire2(4, 122) <= sub_wire13(122); + sub_wire2(4, 123) <= sub_wire13(123); + sub_wire2(4, 124) <= sub_wire13(124); + sub_wire2(4, 125) <= sub_wire13(125); + sub_wire2(4, 126) <= sub_wire13(126); + sub_wire2(4, 127) <= sub_wire13(127); + sub_wire2(3, 0) <= sub_wire14(0); + sub_wire2(3, 1) <= sub_wire14(1); + sub_wire2(3, 2) <= sub_wire14(2); + sub_wire2(3, 3) <= sub_wire14(3); + sub_wire2(3, 4) <= sub_wire14(4); + sub_wire2(3, 5) <= sub_wire14(5); + sub_wire2(3, 6) <= sub_wire14(6); + sub_wire2(3, 7) <= sub_wire14(7); + sub_wire2(3, 8) <= sub_wire14(8); + sub_wire2(3, 9) <= sub_wire14(9); + sub_wire2(3, 10) <= sub_wire14(10); + sub_wire2(3, 11) <= sub_wire14(11); + sub_wire2(3, 12) <= sub_wire14(12); + sub_wire2(3, 13) <= sub_wire14(13); + sub_wire2(3, 14) <= sub_wire14(14); + sub_wire2(3, 15) <= sub_wire14(15); + sub_wire2(3, 16) <= sub_wire14(16); + sub_wire2(3, 17) <= sub_wire14(17); + sub_wire2(3, 18) <= sub_wire14(18); + sub_wire2(3, 19) <= sub_wire14(19); + sub_wire2(3, 20) <= sub_wire14(20); + sub_wire2(3, 21) <= sub_wire14(21); + sub_wire2(3, 22) <= sub_wire14(22); + sub_wire2(3, 23) <= sub_wire14(23); + sub_wire2(3, 24) <= sub_wire14(24); + sub_wire2(3, 25) <= sub_wire14(25); + sub_wire2(3, 26) <= sub_wire14(26); + sub_wire2(3, 27) <= sub_wire14(27); + sub_wire2(3, 28) <= sub_wire14(28); + sub_wire2(3, 29) <= sub_wire14(29); + sub_wire2(3, 30) <= sub_wire14(30); + sub_wire2(3, 31) <= sub_wire14(31); + sub_wire2(3, 32) <= sub_wire14(32); + sub_wire2(3, 33) <= sub_wire14(33); + sub_wire2(3, 34) <= sub_wire14(34); + sub_wire2(3, 35) <= sub_wire14(35); + sub_wire2(3, 36) <= sub_wire14(36); + sub_wire2(3, 37) <= sub_wire14(37); + sub_wire2(3, 38) <= sub_wire14(38); + sub_wire2(3, 39) <= sub_wire14(39); + sub_wire2(3, 40) <= sub_wire14(40); + sub_wire2(3, 41) <= sub_wire14(41); + sub_wire2(3, 42) <= sub_wire14(42); + sub_wire2(3, 43) <= sub_wire14(43); + sub_wire2(3, 44) <= sub_wire14(44); + sub_wire2(3, 45) <= sub_wire14(45); + sub_wire2(3, 46) <= sub_wire14(46); + sub_wire2(3, 47) <= sub_wire14(47); + sub_wire2(3, 48) <= sub_wire14(48); + sub_wire2(3, 49) <= sub_wire14(49); + sub_wire2(3, 50) <= sub_wire14(50); + sub_wire2(3, 51) <= sub_wire14(51); + sub_wire2(3, 52) <= sub_wire14(52); + sub_wire2(3, 53) <= sub_wire14(53); + sub_wire2(3, 54) <= sub_wire14(54); + sub_wire2(3, 55) <= sub_wire14(55); + sub_wire2(3, 56) <= sub_wire14(56); + sub_wire2(3, 57) <= sub_wire14(57); + sub_wire2(3, 58) <= sub_wire14(58); + sub_wire2(3, 59) <= sub_wire14(59); + sub_wire2(3, 60) <= sub_wire14(60); + sub_wire2(3, 61) <= sub_wire14(61); + sub_wire2(3, 62) <= sub_wire14(62); + sub_wire2(3, 63) <= sub_wire14(63); + sub_wire2(3, 64) <= sub_wire14(64); + sub_wire2(3, 65) <= sub_wire14(65); + sub_wire2(3, 66) <= sub_wire14(66); + sub_wire2(3, 67) <= sub_wire14(67); + sub_wire2(3, 68) <= sub_wire14(68); + sub_wire2(3, 69) <= sub_wire14(69); + sub_wire2(3, 70) <= sub_wire14(70); + sub_wire2(3, 71) <= sub_wire14(71); + sub_wire2(3, 72) <= sub_wire14(72); + sub_wire2(3, 73) <= sub_wire14(73); + sub_wire2(3, 74) <= sub_wire14(74); + sub_wire2(3, 75) <= sub_wire14(75); + sub_wire2(3, 76) <= sub_wire14(76); + sub_wire2(3, 77) <= sub_wire14(77); + sub_wire2(3, 78) <= sub_wire14(78); + sub_wire2(3, 79) <= sub_wire14(79); + sub_wire2(3, 80) <= sub_wire14(80); + sub_wire2(3, 81) <= sub_wire14(81); + sub_wire2(3, 82) <= sub_wire14(82); + sub_wire2(3, 83) <= sub_wire14(83); + sub_wire2(3, 84) <= sub_wire14(84); + sub_wire2(3, 85) <= sub_wire14(85); + sub_wire2(3, 86) <= sub_wire14(86); + sub_wire2(3, 87) <= sub_wire14(87); + sub_wire2(3, 88) <= sub_wire14(88); + sub_wire2(3, 89) <= sub_wire14(89); + sub_wire2(3, 90) <= sub_wire14(90); + sub_wire2(3, 91) <= sub_wire14(91); + sub_wire2(3, 92) <= sub_wire14(92); + sub_wire2(3, 93) <= sub_wire14(93); + sub_wire2(3, 94) <= sub_wire14(94); + sub_wire2(3, 95) <= sub_wire14(95); + sub_wire2(3, 96) <= sub_wire14(96); + sub_wire2(3, 97) <= sub_wire14(97); + sub_wire2(3, 98) <= sub_wire14(98); + sub_wire2(3, 99) <= sub_wire14(99); + sub_wire2(3, 100) <= sub_wire14(100); + sub_wire2(3, 101) <= sub_wire14(101); + sub_wire2(3, 102) <= sub_wire14(102); + sub_wire2(3, 103) <= sub_wire14(103); + sub_wire2(3, 104) <= sub_wire14(104); + sub_wire2(3, 105) <= sub_wire14(105); + sub_wire2(3, 106) <= sub_wire14(106); + sub_wire2(3, 107) <= sub_wire14(107); + sub_wire2(3, 108) <= sub_wire14(108); + sub_wire2(3, 109) <= sub_wire14(109); + sub_wire2(3, 110) <= sub_wire14(110); + sub_wire2(3, 111) <= sub_wire14(111); + sub_wire2(3, 112) <= sub_wire14(112); + sub_wire2(3, 113) <= sub_wire14(113); + sub_wire2(3, 114) <= sub_wire14(114); + sub_wire2(3, 115) <= sub_wire14(115); + sub_wire2(3, 116) <= sub_wire14(116); + sub_wire2(3, 117) <= sub_wire14(117); + sub_wire2(3, 118) <= sub_wire14(118); + sub_wire2(3, 119) <= sub_wire14(119); + sub_wire2(3, 120) <= sub_wire14(120); + sub_wire2(3, 121) <= sub_wire14(121); + sub_wire2(3, 122) <= sub_wire14(122); + sub_wire2(3, 123) <= sub_wire14(123); + sub_wire2(3, 124) <= sub_wire14(124); + sub_wire2(3, 125) <= sub_wire14(125); + sub_wire2(3, 126) <= sub_wire14(126); + sub_wire2(3, 127) <= sub_wire14(127); + sub_wire2(2, 0) <= sub_wire15(0); + sub_wire2(2, 1) <= sub_wire15(1); + sub_wire2(2, 2) <= sub_wire15(2); + sub_wire2(2, 3) <= sub_wire15(3); + sub_wire2(2, 4) <= sub_wire15(4); + sub_wire2(2, 5) <= sub_wire15(5); + sub_wire2(2, 6) <= sub_wire15(6); + sub_wire2(2, 7) <= sub_wire15(7); + sub_wire2(2, 8) <= sub_wire15(8); + sub_wire2(2, 9) <= sub_wire15(9); + sub_wire2(2, 10) <= sub_wire15(10); + sub_wire2(2, 11) <= sub_wire15(11); + sub_wire2(2, 12) <= sub_wire15(12); + sub_wire2(2, 13) <= sub_wire15(13); + sub_wire2(2, 14) <= sub_wire15(14); + sub_wire2(2, 15) <= sub_wire15(15); + sub_wire2(2, 16) <= sub_wire15(16); + sub_wire2(2, 17) <= sub_wire15(17); + sub_wire2(2, 18) <= sub_wire15(18); + sub_wire2(2, 19) <= sub_wire15(19); + sub_wire2(2, 20) <= sub_wire15(20); + sub_wire2(2, 21) <= sub_wire15(21); + sub_wire2(2, 22) <= sub_wire15(22); + sub_wire2(2, 23) <= sub_wire15(23); + sub_wire2(2, 24) <= sub_wire15(24); + sub_wire2(2, 25) <= sub_wire15(25); + sub_wire2(2, 26) <= sub_wire15(26); + sub_wire2(2, 27) <= sub_wire15(27); + sub_wire2(2, 28) <= sub_wire15(28); + sub_wire2(2, 29) <= sub_wire15(29); + sub_wire2(2, 30) <= sub_wire15(30); + sub_wire2(2, 31) <= sub_wire15(31); + sub_wire2(2, 32) <= sub_wire15(32); + sub_wire2(2, 33) <= sub_wire15(33); + sub_wire2(2, 34) <= sub_wire15(34); + sub_wire2(2, 35) <= sub_wire15(35); + sub_wire2(2, 36) <= sub_wire15(36); + sub_wire2(2, 37) <= sub_wire15(37); + sub_wire2(2, 38) <= sub_wire15(38); + sub_wire2(2, 39) <= sub_wire15(39); + sub_wire2(2, 40) <= sub_wire15(40); + sub_wire2(2, 41) <= sub_wire15(41); + sub_wire2(2, 42) <= sub_wire15(42); + sub_wire2(2, 43) <= sub_wire15(43); + sub_wire2(2, 44) <= sub_wire15(44); + sub_wire2(2, 45) <= sub_wire15(45); + sub_wire2(2, 46) <= sub_wire15(46); + sub_wire2(2, 47) <= sub_wire15(47); + sub_wire2(2, 48) <= sub_wire15(48); + sub_wire2(2, 49) <= sub_wire15(49); + sub_wire2(2, 50) <= sub_wire15(50); + sub_wire2(2, 51) <= sub_wire15(51); + sub_wire2(2, 52) <= sub_wire15(52); + sub_wire2(2, 53) <= sub_wire15(53); + sub_wire2(2, 54) <= sub_wire15(54); + sub_wire2(2, 55) <= sub_wire15(55); + sub_wire2(2, 56) <= sub_wire15(56); + sub_wire2(2, 57) <= sub_wire15(57); + sub_wire2(2, 58) <= sub_wire15(58); + sub_wire2(2, 59) <= sub_wire15(59); + sub_wire2(2, 60) <= sub_wire15(60); + sub_wire2(2, 61) <= sub_wire15(61); + sub_wire2(2, 62) <= sub_wire15(62); + sub_wire2(2, 63) <= sub_wire15(63); + sub_wire2(2, 64) <= sub_wire15(64); + sub_wire2(2, 65) <= sub_wire15(65); + sub_wire2(2, 66) <= sub_wire15(66); + sub_wire2(2, 67) <= sub_wire15(67); + sub_wire2(2, 68) <= sub_wire15(68); + sub_wire2(2, 69) <= sub_wire15(69); + sub_wire2(2, 70) <= sub_wire15(70); + sub_wire2(2, 71) <= sub_wire15(71); + sub_wire2(2, 72) <= sub_wire15(72); + sub_wire2(2, 73) <= sub_wire15(73); + sub_wire2(2, 74) <= sub_wire15(74); + sub_wire2(2, 75) <= sub_wire15(75); + sub_wire2(2, 76) <= sub_wire15(76); + sub_wire2(2, 77) <= sub_wire15(77); + sub_wire2(2, 78) <= sub_wire15(78); + sub_wire2(2, 79) <= sub_wire15(79); + sub_wire2(2, 80) <= sub_wire15(80); + sub_wire2(2, 81) <= sub_wire15(81); + sub_wire2(2, 82) <= sub_wire15(82); + sub_wire2(2, 83) <= sub_wire15(83); + sub_wire2(2, 84) <= sub_wire15(84); + sub_wire2(2, 85) <= sub_wire15(85); + sub_wire2(2, 86) <= sub_wire15(86); + sub_wire2(2, 87) <= sub_wire15(87); + sub_wire2(2, 88) <= sub_wire15(88); + sub_wire2(2, 89) <= sub_wire15(89); + sub_wire2(2, 90) <= sub_wire15(90); + sub_wire2(2, 91) <= sub_wire15(91); + sub_wire2(2, 92) <= sub_wire15(92); + sub_wire2(2, 93) <= sub_wire15(93); + sub_wire2(2, 94) <= sub_wire15(94); + sub_wire2(2, 95) <= sub_wire15(95); + sub_wire2(2, 96) <= sub_wire15(96); + sub_wire2(2, 97) <= sub_wire15(97); + sub_wire2(2, 98) <= sub_wire15(98); + sub_wire2(2, 99) <= sub_wire15(99); + sub_wire2(2, 100) <= sub_wire15(100); + sub_wire2(2, 101) <= sub_wire15(101); + sub_wire2(2, 102) <= sub_wire15(102); + sub_wire2(2, 103) <= sub_wire15(103); + sub_wire2(2, 104) <= sub_wire15(104); + sub_wire2(2, 105) <= sub_wire15(105); + sub_wire2(2, 106) <= sub_wire15(106); + sub_wire2(2, 107) <= sub_wire15(107); + sub_wire2(2, 108) <= sub_wire15(108); + sub_wire2(2, 109) <= sub_wire15(109); + sub_wire2(2, 110) <= sub_wire15(110); + sub_wire2(2, 111) <= sub_wire15(111); + sub_wire2(2, 112) <= sub_wire15(112); + sub_wire2(2, 113) <= sub_wire15(113); + sub_wire2(2, 114) <= sub_wire15(114); + sub_wire2(2, 115) <= sub_wire15(115); + sub_wire2(2, 116) <= sub_wire15(116); + sub_wire2(2, 117) <= sub_wire15(117); + sub_wire2(2, 118) <= sub_wire15(118); + sub_wire2(2, 119) <= sub_wire15(119); + sub_wire2(2, 120) <= sub_wire15(120); + sub_wire2(2, 121) <= sub_wire15(121); + sub_wire2(2, 122) <= sub_wire15(122); + sub_wire2(2, 123) <= sub_wire15(123); + sub_wire2(2, 124) <= sub_wire15(124); + sub_wire2(2, 125) <= sub_wire15(125); + sub_wire2(2, 126) <= sub_wire15(126); + sub_wire2(2, 127) <= sub_wire15(127); + sub_wire2(1, 0) <= sub_wire16(0); + sub_wire2(1, 1) <= sub_wire16(1); + sub_wire2(1, 2) <= sub_wire16(2); + sub_wire2(1, 3) <= sub_wire16(3); + sub_wire2(1, 4) <= sub_wire16(4); + sub_wire2(1, 5) <= sub_wire16(5); + sub_wire2(1, 6) <= sub_wire16(6); + sub_wire2(1, 7) <= sub_wire16(7); + sub_wire2(1, 8) <= sub_wire16(8); + sub_wire2(1, 9) <= sub_wire16(9); + sub_wire2(1, 10) <= sub_wire16(10); + sub_wire2(1, 11) <= sub_wire16(11); + sub_wire2(1, 12) <= sub_wire16(12); + sub_wire2(1, 13) <= sub_wire16(13); + sub_wire2(1, 14) <= sub_wire16(14); + sub_wire2(1, 15) <= sub_wire16(15); + sub_wire2(1, 16) <= sub_wire16(16); + sub_wire2(1, 17) <= sub_wire16(17); + sub_wire2(1, 18) <= sub_wire16(18); + sub_wire2(1, 19) <= sub_wire16(19); + sub_wire2(1, 20) <= sub_wire16(20); + sub_wire2(1, 21) <= sub_wire16(21); + sub_wire2(1, 22) <= sub_wire16(22); + sub_wire2(1, 23) <= sub_wire16(23); + sub_wire2(1, 24) <= sub_wire16(24); + sub_wire2(1, 25) <= sub_wire16(25); + sub_wire2(1, 26) <= sub_wire16(26); + sub_wire2(1, 27) <= sub_wire16(27); + sub_wire2(1, 28) <= sub_wire16(28); + sub_wire2(1, 29) <= sub_wire16(29); + sub_wire2(1, 30) <= sub_wire16(30); + sub_wire2(1, 31) <= sub_wire16(31); + sub_wire2(1, 32) <= sub_wire16(32); + sub_wire2(1, 33) <= sub_wire16(33); + sub_wire2(1, 34) <= sub_wire16(34); + sub_wire2(1, 35) <= sub_wire16(35); + sub_wire2(1, 36) <= sub_wire16(36); + sub_wire2(1, 37) <= sub_wire16(37); + sub_wire2(1, 38) <= sub_wire16(38); + sub_wire2(1, 39) <= sub_wire16(39); + sub_wire2(1, 40) <= sub_wire16(40); + sub_wire2(1, 41) <= sub_wire16(41); + sub_wire2(1, 42) <= sub_wire16(42); + sub_wire2(1, 43) <= sub_wire16(43); + sub_wire2(1, 44) <= sub_wire16(44); + sub_wire2(1, 45) <= sub_wire16(45); + sub_wire2(1, 46) <= sub_wire16(46); + sub_wire2(1, 47) <= sub_wire16(47); + sub_wire2(1, 48) <= sub_wire16(48); + sub_wire2(1, 49) <= sub_wire16(49); + sub_wire2(1, 50) <= sub_wire16(50); + sub_wire2(1, 51) <= sub_wire16(51); + sub_wire2(1, 52) <= sub_wire16(52); + sub_wire2(1, 53) <= sub_wire16(53); + sub_wire2(1, 54) <= sub_wire16(54); + sub_wire2(1, 55) <= sub_wire16(55); + sub_wire2(1, 56) <= sub_wire16(56); + sub_wire2(1, 57) <= sub_wire16(57); + sub_wire2(1, 58) <= sub_wire16(58); + sub_wire2(1, 59) <= sub_wire16(59); + sub_wire2(1, 60) <= sub_wire16(60); + sub_wire2(1, 61) <= sub_wire16(61); + sub_wire2(1, 62) <= sub_wire16(62); + sub_wire2(1, 63) <= sub_wire16(63); + sub_wire2(1, 64) <= sub_wire16(64); + sub_wire2(1, 65) <= sub_wire16(65); + sub_wire2(1, 66) <= sub_wire16(66); + sub_wire2(1, 67) <= sub_wire16(67); + sub_wire2(1, 68) <= sub_wire16(68); + sub_wire2(1, 69) <= sub_wire16(69); + sub_wire2(1, 70) <= sub_wire16(70); + sub_wire2(1, 71) <= sub_wire16(71); + sub_wire2(1, 72) <= sub_wire16(72); + sub_wire2(1, 73) <= sub_wire16(73); + sub_wire2(1, 74) <= sub_wire16(74); + sub_wire2(1, 75) <= sub_wire16(75); + sub_wire2(1, 76) <= sub_wire16(76); + sub_wire2(1, 77) <= sub_wire16(77); + sub_wire2(1, 78) <= sub_wire16(78); + sub_wire2(1, 79) <= sub_wire16(79); + sub_wire2(1, 80) <= sub_wire16(80); + sub_wire2(1, 81) <= sub_wire16(81); + sub_wire2(1, 82) <= sub_wire16(82); + sub_wire2(1, 83) <= sub_wire16(83); + sub_wire2(1, 84) <= sub_wire16(84); + sub_wire2(1, 85) <= sub_wire16(85); + sub_wire2(1, 86) <= sub_wire16(86); + sub_wire2(1, 87) <= sub_wire16(87); + sub_wire2(1, 88) <= sub_wire16(88); + sub_wire2(1, 89) <= sub_wire16(89); + sub_wire2(1, 90) <= sub_wire16(90); + sub_wire2(1, 91) <= sub_wire16(91); + sub_wire2(1, 92) <= sub_wire16(92); + sub_wire2(1, 93) <= sub_wire16(93); + sub_wire2(1, 94) <= sub_wire16(94); + sub_wire2(1, 95) <= sub_wire16(95); + sub_wire2(1, 96) <= sub_wire16(96); + sub_wire2(1, 97) <= sub_wire16(97); + sub_wire2(1, 98) <= sub_wire16(98); + sub_wire2(1, 99) <= sub_wire16(99); + sub_wire2(1, 100) <= sub_wire16(100); + sub_wire2(1, 101) <= sub_wire16(101); + sub_wire2(1, 102) <= sub_wire16(102); + sub_wire2(1, 103) <= sub_wire16(103); + sub_wire2(1, 104) <= sub_wire16(104); + sub_wire2(1, 105) <= sub_wire16(105); + sub_wire2(1, 106) <= sub_wire16(106); + sub_wire2(1, 107) <= sub_wire16(107); + sub_wire2(1, 108) <= sub_wire16(108); + sub_wire2(1, 109) <= sub_wire16(109); + sub_wire2(1, 110) <= sub_wire16(110); + sub_wire2(1, 111) <= sub_wire16(111); + sub_wire2(1, 112) <= sub_wire16(112); + sub_wire2(1, 113) <= sub_wire16(113); + sub_wire2(1, 114) <= sub_wire16(114); + sub_wire2(1, 115) <= sub_wire16(115); + sub_wire2(1, 116) <= sub_wire16(116); + sub_wire2(1, 117) <= sub_wire16(117); + sub_wire2(1, 118) <= sub_wire16(118); + sub_wire2(1, 119) <= sub_wire16(119); + sub_wire2(1, 120) <= sub_wire16(120); + sub_wire2(1, 121) <= sub_wire16(121); + sub_wire2(1, 122) <= sub_wire16(122); + sub_wire2(1, 123) <= sub_wire16(123); + sub_wire2(1, 124) <= sub_wire16(124); + sub_wire2(1, 125) <= sub_wire16(125); + sub_wire2(1, 126) <= sub_wire16(126); + sub_wire2(1, 127) <= sub_wire16(127); + sub_wire2(0, 0) <= sub_wire17(0); + sub_wire2(0, 1) <= sub_wire17(1); + sub_wire2(0, 2) <= sub_wire17(2); + sub_wire2(0, 3) <= sub_wire17(3); + sub_wire2(0, 4) <= sub_wire17(4); + sub_wire2(0, 5) <= sub_wire17(5); + sub_wire2(0, 6) <= sub_wire17(6); + sub_wire2(0, 7) <= sub_wire17(7); + sub_wire2(0, 8) <= sub_wire17(8); + sub_wire2(0, 9) <= sub_wire17(9); + sub_wire2(0, 10) <= sub_wire17(10); + sub_wire2(0, 11) <= sub_wire17(11); + sub_wire2(0, 12) <= sub_wire17(12); + sub_wire2(0, 13) <= sub_wire17(13); + sub_wire2(0, 14) <= sub_wire17(14); + sub_wire2(0, 15) <= sub_wire17(15); + sub_wire2(0, 16) <= sub_wire17(16); + sub_wire2(0, 17) <= sub_wire17(17); + sub_wire2(0, 18) <= sub_wire17(18); + sub_wire2(0, 19) <= sub_wire17(19); + sub_wire2(0, 20) <= sub_wire17(20); + sub_wire2(0, 21) <= sub_wire17(21); + sub_wire2(0, 22) <= sub_wire17(22); + sub_wire2(0, 23) <= sub_wire17(23); + sub_wire2(0, 24) <= sub_wire17(24); + sub_wire2(0, 25) <= sub_wire17(25); + sub_wire2(0, 26) <= sub_wire17(26); + sub_wire2(0, 27) <= sub_wire17(27); + sub_wire2(0, 28) <= sub_wire17(28); + sub_wire2(0, 29) <= sub_wire17(29); + sub_wire2(0, 30) <= sub_wire17(30); + sub_wire2(0, 31) <= sub_wire17(31); + sub_wire2(0, 32) <= sub_wire17(32); + sub_wire2(0, 33) <= sub_wire17(33); + sub_wire2(0, 34) <= sub_wire17(34); + sub_wire2(0, 35) <= sub_wire17(35); + sub_wire2(0, 36) <= sub_wire17(36); + sub_wire2(0, 37) <= sub_wire17(37); + sub_wire2(0, 38) <= sub_wire17(38); + sub_wire2(0, 39) <= sub_wire17(39); + sub_wire2(0, 40) <= sub_wire17(40); + sub_wire2(0, 41) <= sub_wire17(41); + sub_wire2(0, 42) <= sub_wire17(42); + sub_wire2(0, 43) <= sub_wire17(43); + sub_wire2(0, 44) <= sub_wire17(44); + sub_wire2(0, 45) <= sub_wire17(45); + sub_wire2(0, 46) <= sub_wire17(46); + sub_wire2(0, 47) <= sub_wire17(47); + sub_wire2(0, 48) <= sub_wire17(48); + sub_wire2(0, 49) <= sub_wire17(49); + sub_wire2(0, 50) <= sub_wire17(50); + sub_wire2(0, 51) <= sub_wire17(51); + sub_wire2(0, 52) <= sub_wire17(52); + sub_wire2(0, 53) <= sub_wire17(53); + sub_wire2(0, 54) <= sub_wire17(54); + sub_wire2(0, 55) <= sub_wire17(55); + sub_wire2(0, 56) <= sub_wire17(56); + sub_wire2(0, 57) <= sub_wire17(57); + sub_wire2(0, 58) <= sub_wire17(58); + sub_wire2(0, 59) <= sub_wire17(59); + sub_wire2(0, 60) <= sub_wire17(60); + sub_wire2(0, 61) <= sub_wire17(61); + sub_wire2(0, 62) <= sub_wire17(62); + sub_wire2(0, 63) <= sub_wire17(63); + sub_wire2(0, 64) <= sub_wire17(64); + sub_wire2(0, 65) <= sub_wire17(65); + sub_wire2(0, 66) <= sub_wire17(66); + sub_wire2(0, 67) <= sub_wire17(67); + sub_wire2(0, 68) <= sub_wire17(68); + sub_wire2(0, 69) <= sub_wire17(69); + sub_wire2(0, 70) <= sub_wire17(70); + sub_wire2(0, 71) <= sub_wire17(71); + sub_wire2(0, 72) <= sub_wire17(72); + sub_wire2(0, 73) <= sub_wire17(73); + sub_wire2(0, 74) <= sub_wire17(74); + sub_wire2(0, 75) <= sub_wire17(75); + sub_wire2(0, 76) <= sub_wire17(76); + sub_wire2(0, 77) <= sub_wire17(77); + sub_wire2(0, 78) <= sub_wire17(78); + sub_wire2(0, 79) <= sub_wire17(79); + sub_wire2(0, 80) <= sub_wire17(80); + sub_wire2(0, 81) <= sub_wire17(81); + sub_wire2(0, 82) <= sub_wire17(82); + sub_wire2(0, 83) <= sub_wire17(83); + sub_wire2(0, 84) <= sub_wire17(84); + sub_wire2(0, 85) <= sub_wire17(85); + sub_wire2(0, 86) <= sub_wire17(86); + sub_wire2(0, 87) <= sub_wire17(87); + sub_wire2(0, 88) <= sub_wire17(88); + sub_wire2(0, 89) <= sub_wire17(89); + sub_wire2(0, 90) <= sub_wire17(90); + sub_wire2(0, 91) <= sub_wire17(91); + sub_wire2(0, 92) <= sub_wire17(92); + sub_wire2(0, 93) <= sub_wire17(93); + sub_wire2(0, 94) <= sub_wire17(94); + sub_wire2(0, 95) <= sub_wire17(95); + sub_wire2(0, 96) <= sub_wire17(96); + sub_wire2(0, 97) <= sub_wire17(97); + sub_wire2(0, 98) <= sub_wire17(98); + sub_wire2(0, 99) <= sub_wire17(99); + sub_wire2(0, 100) <= sub_wire17(100); + sub_wire2(0, 101) <= sub_wire17(101); + sub_wire2(0, 102) <= sub_wire17(102); + sub_wire2(0, 103) <= sub_wire17(103); + sub_wire2(0, 104) <= sub_wire17(104); + sub_wire2(0, 105) <= sub_wire17(105); + sub_wire2(0, 106) <= sub_wire17(106); + sub_wire2(0, 107) <= sub_wire17(107); + sub_wire2(0, 108) <= sub_wire17(108); + sub_wire2(0, 109) <= sub_wire17(109); + sub_wire2(0, 110) <= sub_wire17(110); + sub_wire2(0, 111) <= sub_wire17(111); + sub_wire2(0, 112) <= sub_wire17(112); + sub_wire2(0, 113) <= sub_wire17(113); + sub_wire2(0, 114) <= sub_wire17(114); + sub_wire2(0, 115) <= sub_wire17(115); + sub_wire2(0, 116) <= sub_wire17(116); + sub_wire2(0, 117) <= sub_wire17(117); + sub_wire2(0, 118) <= sub_wire17(118); + sub_wire2(0, 119) <= sub_wire17(119); + sub_wire2(0, 120) <= sub_wire17(120); + sub_wire2(0, 121) <= sub_wire17(121); + sub_wire2(0, 122) <= sub_wire17(122); + sub_wire2(0, 123) <= sub_wire17(123); + sub_wire2(0, 124) <= sub_wire17(124); + sub_wire2(0, 125) <= sub_wire17(125); + sub_wire2(0, 126) <= sub_wire17(126); + sub_wire2(0, 127) <= sub_wire17(127); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 16, + lpm_type => "LPM_MUX", + lpm_width => 128, + lpm_widths => 4 + ) + PORT MAP ( + sel => sel, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" +-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0] +-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0] +-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0] +-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0] +-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0] +-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0] +-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0] +-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0] +-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0] +-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0] +-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0] +-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0] +-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0] +-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0] +-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0] +-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0] +-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0] +-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0] +-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 +-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_shiftreg0.bsf b/Video/lpm_shiftreg0.bsf index 44c4c53..fb70a4b 100644 --- a/Video/lpm_shiftreg0.bsf +++ b/Video/lpm_shiftreg0.bsf @@ -1,78 +1,70 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 128) - (text "lpm_shiftreg0" (rect 33 0 128 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 113 26 124)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "load" (rect 0 0 25 13)(font "Arial" (font_size 8))) - (text "load" (rect 20 26 41 38)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)) - ) - (port - (pt 0 48) - (input) - (text "data[15..0]" (rect 0 0 61 13)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 42 72 54)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 3)) - ) - (port - (pt 0 80) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 26 74 51 86)(font "Arial" (font_size 8))) - (line (pt 0 80)(pt 16 80)) - ) - (port - (pt 0 96) - (input) - (text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 90 48 102)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)) - ) - (port - (pt 144 64) - (output) - (text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8))) - (text "shiftout" (rect 91 58 126 70)(font "Arial" (font_size 8))) - (line (pt 144 64)(pt 128 64)) - ) - (drawing - (text "left shift" (rect 96 18 227 46)(font "Arial" )) - (line (pt 16 16)(pt 16 112)) - (line (pt 16 16)(pt 128 16)) - (line (pt 16 112)(pt 128 112)) - (line (pt 128 16)(pt 128 112)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 130)) - (line (pt 0 130)(pt 146 130)) - (line (pt 0 0)(pt 0 130)) - (line (pt 16 74)(pt 22 80)) - (line (pt 22 80)(pt 16 86)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 128) + (text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "load" (rect 0 0 23 14)(font "Arial" (font_size 8))) + (text "load" (rect 20 26 41 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 144 72) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8))) + (line (pt 144 72)(pt 128 72)(line_width 1)) + ) + (drawing + (text "left shift" (rect 92 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 112)(line_width 1)) + (line (pt 128 112)(pt 16 112)(line_width 1)) + (line (pt 16 112)(pt 16 16)(line_width 1)) + (line (pt 16 74)(pt 22 80)(line_width 1)) + (line (pt 22 80)(pt 16 86)(line_width 1)) + ) +) diff --git a/Video/lpm_shiftreg0.cmp b/Video/lpm_shiftreg0.cmp index 90bc948..c0613d5 100644 --- a/Video/lpm_shiftreg0.cmp +++ b/Video/lpm_shiftreg0.cmp @@ -1,25 +1,25 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_shiftreg0 - PORT - ( - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - load : IN STD_LOGIC ; - shiftin : IN STD_LOGIC ; - shiftout : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg0 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + load : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/Video/lpm_shiftreg0.inc b/Video/lpm_shiftreg0.inc index 51be562..1c0c4a2 100644 --- a/Video/lpm_shiftreg0.inc +++ b/Video/lpm_shiftreg0.inc @@ -1,26 +1,26 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_shiftreg0 -( - clock, - data[15..0], - load, - shiftin -) - -RETURNS ( - shiftout -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg0 +( + clock, + data[15..0], + load, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/Video/lpm_shiftreg0.qip b/Video/lpm_shiftreg0.qip index 4720c56..a233319 100644 --- a/Video/lpm_shiftreg0.qip +++ b/Video/lpm_shiftreg0.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"] diff --git a/Video/lpm_shiftreg0.vhd b/Video/lpm_shiftreg0.vhd index f849c43..6e5d954 100644 --- a/Video/lpm_shiftreg0.vhd +++ b/Video/lpm_shiftreg0.vhd @@ -1,136 +1,135 @@ --- megafunction wizard: %LPM_SHIFTREG% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_SHIFTREG - --- ============================================================ --- File Name: lpm_shiftreg0.vhd --- Megafunction Name(s): --- LPM_SHIFTREG --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_shiftreg0 IS - PORT - ( - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - load : IN STD_LOGIC ; - shiftin : IN STD_LOGIC ; - shiftout : OUT STD_LOGIC - ); -END lpm_shiftreg0; - - -ARCHITECTURE SYN OF lpm_shiftreg0 IS - - SIGNAL sub_wire0 : STD_LOGIC ; - - - - COMPONENT lpm_shiftreg - GENERIC ( - lpm_direction : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - load : IN STD_LOGIC ; - shiftout : OUT STD_LOGIC ; - shiftin : IN STD_LOGIC - ); - END COMPONENT; - -BEGIN - shiftout <= sub_wire0; - - LPM_SHIFTREG_component : LPM_SHIFTREG - GENERIC MAP ( - lpm_direction => "LEFT", - lpm_type => "LPM_SHIFTREG", - lpm_width => 16 - ) - PORT MAP ( - clock => clock, - data => data, - load => load, - shiftin => shiftin, - shiftout => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACLR NUMERIC "0" --- Retrieval info: PRIVATE: ALOAD NUMERIC "0" --- Retrieval info: PRIVATE: ASET NUMERIC "0" --- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: LeftShift NUMERIC "1" --- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1" --- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" --- Retrieval info: PRIVATE: SCLR NUMERIC "0" --- Retrieval info: PRIVATE: SLOAD NUMERIC "1" --- Retrieval info: PRIVATE: SSET NUMERIC "0" --- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" --- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" --- Retrieval info: PRIVATE: nBit NUMERIC "16" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" --- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL "load" --- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin" --- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 --- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0 --- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 --- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg0.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg0 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + load : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg0; + + +ARCHITECTURE SYN OF lpm_shiftreg0 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + load : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "LEFT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 16 + ) + PORT MAP ( + load => load, + clock => clock, + data => data, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "1" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "1" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_shiftreg4.bsf b/Video/lpm_shiftreg4.bsf index 8f17ef6..658958d 100644 --- a/Video/lpm_shiftreg4.bsf +++ b/Video/lpm_shiftreg4.bsf @@ -1,64 +1,56 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg4" (rect 33 0 129 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 65 26 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)) - ) - (port - (pt 144 48) - (output) - (text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8))) - (text "shiftout" (rect 91 42 126 54)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)) - ) - (drawing - (text "right shift" (rect 90 18 220 46)(font "Arial" )) - (line (pt 16 16)(pt 16 64)) - (line (pt 16 16)(pt 128 16)) - (line (pt 16 64)(pt 128 64)) - (line (pt 128 16)(pt 128 64)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 82)) - (line (pt 0 82)(pt 146 82)) - (line (pt 0 0)(pt 0 82)) - (line (pt 16 26)(pt 22 32)) - (line (pt 22 32)(pt 16 38)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/Video/lpm_shiftreg4.cmp b/Video/lpm_shiftreg4.cmp index a5ffe97..83fb9e5 100644 --- a/Video/lpm_shiftreg4.cmp +++ b/Video/lpm_shiftreg4.cmp @@ -1,23 +1,23 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_shiftreg4 - PORT - ( - clock : IN STD_LOGIC ; - shiftin : IN STD_LOGIC ; - shiftout : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg4 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/Video/lpm_shiftreg4.inc b/Video/lpm_shiftreg4.inc index 366cf1e..322863a 100644 --- a/Video/lpm_shiftreg4.inc +++ b/Video/lpm_shiftreg4.inc @@ -1,24 +1,24 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_shiftreg4 -( - clock, - shiftin -) - -RETURNS ( - shiftout -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg4 +( + clock, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/Video/lpm_shiftreg4.qip b/Video/lpm_shiftreg4.qip index 9b08d8c..363cd59 100644 --- a/Video/lpm_shiftreg4.qip +++ b/Video/lpm_shiftreg4.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"] diff --git a/Video/lpm_shiftreg4.vhd b/Video/lpm_shiftreg4.vhd index 0fec137..3d8f5d1 100644 --- a/Video/lpm_shiftreg4.vhd +++ b/Video/lpm_shiftreg4.vhd @@ -1,126 +1,125 @@ --- megafunction wizard: %LPM_SHIFTREG% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_SHIFTREG - --- ============================================================ --- File Name: lpm_shiftreg4.vhd --- Megafunction Name(s): --- LPM_SHIFTREG --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_shiftreg4 IS - PORT - ( - clock : IN STD_LOGIC ; - shiftin : IN STD_LOGIC ; - shiftout : OUT STD_LOGIC - ); -END lpm_shiftreg4; - - -ARCHITECTURE SYN OF lpm_shiftreg4 IS - - SIGNAL sub_wire0 : STD_LOGIC ; - - - - COMPONENT lpm_shiftreg - GENERIC ( - lpm_direction : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - clock : IN STD_LOGIC ; - shiftin : IN STD_LOGIC ; - shiftout : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - shiftout <= sub_wire0; - - LPM_SHIFTREG_component : LPM_SHIFTREG - GENERIC MAP ( - lpm_direction => "RIGHT", - lpm_type => "LPM_SHIFTREG", - lpm_width => 5 - ) - PORT MAP ( - clock => clock, - shiftin => shiftin, - shiftout => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACLR NUMERIC "0" --- Retrieval info: PRIVATE: ALOAD NUMERIC "0" --- Retrieval info: PRIVATE: ASET NUMERIC "0" --- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: LeftShift NUMERIC "0" --- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" --- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" --- Retrieval info: PRIVATE: SCLR NUMERIC "0" --- Retrieval info: PRIVATE: SLOAD NUMERIC "0" --- Retrieval info: PRIVATE: SSET NUMERIC "0" --- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" --- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" --- Retrieval info: PRIVATE: nBit NUMERIC "5" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin" --- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 --- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg4.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg4 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg4; + + +ARCHITECTURE SYN OF lpm_shiftreg4 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/Video/lpm_shiftreg6.bsf b/Video/lpm_shiftreg6.bsf index add57d8..aa0296b 100644 --- a/Video/lpm_shiftreg6.bsf +++ b/Video/lpm_shiftreg6.bsf @@ -1,64 +1,56 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg6" (rect 33 0 128 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 65 26 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)) - ) - (port - (pt 144 48) - (output) - (text "q[4..0]" (rect 0 0 36 13)(font "Arial" (font_size 8))) - (text "q[4..0]" (rect 95 42 126 54)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "right shift" (rect 90 18 220 46)(font "Arial" )) - (line (pt 16 16)(pt 16 64)) - (line (pt 16 16)(pt 128 16)) - (line (pt 16 64)(pt 128 64)) - (line (pt 128 16)(pt 128 64)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 82)) - (line (pt 0 82)(pt 146 82)) - (line (pt 0 0)(pt 0 82)) - (line (pt 16 26)(pt 22 32)) - (line (pt 22 32)(pt 16 38)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/Video/lpm_shiftreg6.cmp b/Video/lpm_shiftreg6.cmp index 00da69b..c9f7a9b 100644 --- a/Video/lpm_shiftreg6.cmp +++ b/Video/lpm_shiftreg6.cmp @@ -1,23 +1,23 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_shiftreg6 - PORT - ( - clock : IN STD_LOGIC ; - shiftin : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg6 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/Video/lpm_shiftreg6.inc b/Video/lpm_shiftreg6.inc index 5c8f30a..7767c57 100644 --- a/Video/lpm_shiftreg6.inc +++ b/Video/lpm_shiftreg6.inc @@ -1,24 +1,24 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION lpm_shiftreg6 -( - clock, - shiftin -) - -RETURNS ( - q[4..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg6 +( + clock, + shiftin +) + +RETURNS ( + q[4..0] +); diff --git a/Video/lpm_shiftreg6.qip b/Video/lpm_shiftreg6.qip index 80d8e7a..adb4909 100644 --- a/Video/lpm_shiftreg6.qip +++ b/Video/lpm_shiftreg6.qip @@ -1,6 +1,6 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"] diff --git a/Video/lpm_shiftreg6.vhd b/Video/lpm_shiftreg6.vhd index 4524f59..773243e 100644 --- a/Video/lpm_shiftreg6.vhd +++ b/Video/lpm_shiftreg6.vhd @@ -1,126 +1,125 @@ --- megafunction wizard: %LPM_SHIFTREG% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_SHIFTREG - --- ============================================================ --- File Name: lpm_shiftreg6.vhd --- Megafunction Name(s): --- LPM_SHIFTREG --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_shiftreg6 IS - PORT - ( - clock : IN STD_LOGIC ; - shiftin : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); -END lpm_shiftreg6; - - -ARCHITECTURE SYN OF lpm_shiftreg6 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - - - - COMPONENT lpm_shiftreg - GENERIC ( - lpm_direction : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - shiftin : IN STD_LOGIC - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(4 DOWNTO 0); - - LPM_SHIFTREG_component : LPM_SHIFTREG - GENERIC MAP ( - lpm_direction => "RIGHT", - lpm_type => "LPM_SHIFTREG", - lpm_width => 5 - ) - PORT MAP ( - clock => clock, - shiftin => shiftin, - q => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACLR NUMERIC "0" --- Retrieval info: PRIVATE: ALOAD NUMERIC "0" --- Retrieval info: PRIVATE: ASET NUMERIC "0" --- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: LeftShift NUMERIC "0" --- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" --- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" --- Retrieval info: PRIVATE: SCLR NUMERIC "0" --- Retrieval info: PRIVATE: SLOAD NUMERIC "0" --- Retrieval info: PRIVATE: SSET NUMERIC "0" --- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" --- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" --- Retrieval info: PRIVATE: nBit NUMERIC "5" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]" --- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg6.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg6 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_shiftreg6; + + +ARCHITECTURE SYN OF lpm_shiftreg6 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(4 DOWNTO 0); + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0] +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/altddio_out3.bsf b/altddio_out3.bsf index f419e88..ba8c153 100644 --- a/altddio_out3.bsf +++ b/altddio_out3.bsf @@ -1,64 +1,64 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 192 112) - (text "altddio_out3" (rect 57 0 156 17)(font "Dialog" (font_size 10))) - (text "inst" (rect 8 97 26 108)(font "Arial" )) - (port - (pt 0 48) - (input) - (text "datain_h[0]" (rect 0 0 73 13)(font "Dialog" (font_size 8))) - (text "datain_h[0]" (rect 4 35 67 47)(font "Dialog" (font_size 8))) - (line (pt 0 48)(pt 64 48)(line_width 3)) - ) - (port - (pt 0 64) - (input) - (text "datain_l[0]" (rect 0 0 69 13)(font "Dialog" (font_size 8))) - (text "datain_l[0]" (rect 4 51 63 63)(font "Dialog" (font_size 8))) - (line (pt 0 64)(pt 64 64)(line_width 3)) - ) - (port - (pt 0 80) - (input) - (text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8))) - (text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8))) - (line (pt 0 80)(pt 64 80)) - ) - (port - (pt 192 48) - (output) - (text "dataout[0]" (rect 0 0 68 13)(font "Dialog" (font_size 8))) - (text "dataout[0]" (rect 131 35 190 47)(font "Dialog" (font_size 8))) - (line (pt 192 48)(pt 128 48)(line_width 3)) - ) - (drawing - (line (pt 64 32)(pt 128 32)) - (line (pt 128 32)(pt 128 96)) - (line (pt 64 96)(pt 128 96)) - (line (pt 64 32)(pt 64 96)) - (line (pt 0 0)(pt 192 0)) - (line (pt 192 0)(pt 192 112)) - (line (pt 0 112)(pt 192 112)) - (line (pt 0 0)(pt 0 112)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 1)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 1)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/altddio_out3.cmp b/altddio_out3.cmp index 00beaf6..ce5862c 100644 --- a/altddio_out3.cmp +++ b/altddio_out3.cmp @@ -1,24 +1,24 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altddio_out3 - PORT - ( - datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0); - outclock : IN STD_LOGIC ; - dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out3 + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +end component; diff --git a/altddio_out3.inc b/altddio_out3.inc index 064cbc2..f6b4097 100644 --- a/altddio_out3.inc +++ b/altddio_out3.inc @@ -1,25 +1,25 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altddio_out3 -( - datain_h[0..0], - datain_l[0..0], - outclock -) - -RETURNS ( - dataout[0..0] -); +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out3 +( + datain_h, + datain_l, + outclock +) + +RETURNS ( + dataout +); diff --git a/altddio_out3.ppf b/altddio_out3.ppf index d74ad90..e914df8 100644 --- a/altddio_out3.ppf +++ b/altddio_out3.ppf @@ -1,11 +1,11 @@ - - - - - - - - - - - + + + + + + + + + + + diff --git a/altddio_out3.qip b/altddio_out3.qip index 6c6b8d6..8f94ee3 100644 --- a/altddio_out3.qip +++ b/altddio_out3.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"] diff --git a/altddio_out3.vhd b/altddio_out3.vhd index 60e7263..e55160f 100644 --- a/altddio_out3.vhd +++ b/altddio_out3.vhd @@ -1,110 +1,146 @@ --- megafunction wizard: %ALTDDIO_OUT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: ALTDDIO_OUT - --- ============================================================ --- File Name: altddio_out3.vhd --- Megafunction Name(s): --- ALTDDIO_OUT --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY altddio_out3 IS - PORT - ( - datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0); - outclock : IN STD_LOGIC ; - dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) - ); -END altddio_out3; - - -ARCHITECTURE SYN OF altddio_out3 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); - -BEGIN - dataout <= sub_wire0(0 DOWNTO 0); - - ALTDDIO_OUT_component : ALTDDIO_OUT - GENERIC MAP ( - extend_oe_disable => "OFF", - intended_device_family => "Cyclone III", - invert_output => "OFF", - lpm_hint => "UNUSED", - lpm_type => "altddio_out", - oe_reg => "UNREGISTERED", - power_up_high => "OFF", - width => 1 - ) - PORT MAP ( - datain_h => datain_h, - datain_l => datain_l, - outclock => outclock, - dataout => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" --- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" --- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" --- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" --- Retrieval info: CONSTANT: WIDTH NUMERIC "1" --- Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]" --- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0 --- Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]" --- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0 --- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" --- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 --- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" --- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.qip TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out3.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out3 IS + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +END altddio_out3; + + +ARCHITECTURE SYN OF altddio_out3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire1 <= sub_wire0(0); + dataout <= sub_wire1; + sub_wire2 <= datain_h; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= datain_l; + sub_wire5(0) <= sub_wire4; + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + outclock => outclock, + datain_h => sub_wire3, + datain_l => sub_wire5, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "1" +-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h +-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l +-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0 +-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0 +-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/altpll1.bsf b/altpll1.bsf index 42fb92b..c19a3a7 100644 --- a/altpll1.bsf +++ b/altpll1.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2013 Altera Corporation +Copyright (C) 1991-2014 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -21,7 +21,7 @@ applicable agreement for further details. (header "symbol" (version "1.2")) (symbol (rect 0 0 272 176) - (text "altpll1" (rect 119 0 161 16)(font "Arial" (font_size 10))) + (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10))) (text "inst" (rect 8 161 26 172)(font "Arial" )) (port (pt 0 64) @@ -39,8 +39,8 @@ applicable agreement for further details. (port (pt 272 80) (output) - (text "c1" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c1" (rect 257 67 269 79)(font "Arial" (font_size 8))) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8))) ) (port (pt 272 96) @@ -59,35 +59,35 @@ applicable agreement for further details. (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) (text "Clk " (rect 51 91 117 192)(font "Arial" )) - (text "Ratio" (rect 74 91 171 192)(font "Arial" )) - (text "Ph (dg)" (rect 104 91 239 192)(font "Arial" )) - (text "DC (%)" (rect 139 91 310 192)(font "Arial" )) + (text "Ratio" (rect 82 91 187 192)(font "Arial" )) + (text "Ph (dg)" (rect 119 91 269 192)(font "Arial" )) + (text "DC (%)" (rect 154 91 340 192)(font "Arial" )) (text "c0" (rect 54 104 119 218)(font "Arial" )) - (text "1/66" (rect 76 104 171 218)(font "Arial" )) - (text "0.00" (rect 110 104 239 218)(font "Arial" )) - (text "50.00" (rect 143 104 310 218)(font "Arial" )) - (text "c1" (rect 54 117 119 244)(font "Arial" )) - (text "67/900" (rect 71 117 171 244)(font "Arial" )) - (text "0.00" (rect 110 117 239 244)(font "Arial" )) - (text "50.00" (rect 143 117 310 244)(font "Arial" )) + (text "1/66" (rect 84 104 186 218)(font "Arial" )) + (text "0.00" (rect 125 104 269 218)(font "Arial" )) + (text "50.00" (rect 158 104 340 218)(font "Arial" )) + (text "c1" (rect 54 117 118 244)(font "Arial" )) + (text "512/6875" (rect 74 117 187 244)(font "Arial" )) + (text "0.00" (rect 125 117 269 244)(font "Arial" )) + (text "50.00" (rect 158 117 340 244)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" )) - (text "67/90" (rect 74 130 172 270)(font "Arial" )) - (text "0.00" (rect 110 130 239 270)(font "Arial" )) - (text "50.00" (rect 143 130 310 270)(font "Arial" )) + (text "1024/1375" (rect 71 130 185 270)(font "Arial" )) + (text "0.00" (rect 125 130 269 270)(font "Arial" )) + (text "50.00" (rect 158 130 340 270)(font "Arial" )) (line (pt 0 0)(pt 273 0)) (line (pt 273 0)(pt 273 177)) (line (pt 0 177)(pt 273 177)) (line (pt 0 0)(pt 0 177)) - (line (pt 48 89)(pt 171 89)) - (line (pt 48 101)(pt 171 101)) - (line (pt 48 114)(pt 171 114)) - (line (pt 48 127)(pt 171 127)) - (line (pt 48 140)(pt 171 140)) + (line (pt 48 89)(pt 186 89)) + (line (pt 48 101)(pt 186 101)) + (line (pt 48 114)(pt 186 114)) + (line (pt 48 127)(pt 186 127)) + (line (pt 48 140)(pt 186 140)) (line (pt 48 89)(pt 48 140)) (line (pt 68 89)(pt 68 140)(line_width 3)) - (line (pt 101 89)(pt 101 140)(line_width 3)) - (line (pt 136 89)(pt 136 140)(line_width 3)) - (line (pt 170 89)(pt 170 140)) + (line (pt 116 89)(pt 116 140)(line_width 3)) + (line (pt 151 89)(pt 151 140)(line_width 3)) + (line (pt 185 89)(pt 185 140)) (line (pt 40 48)(pt 223 48)) (line (pt 223 48)(pt 223 159)) (line (pt 40 159)(pt 223 159)) diff --git a/altpll1.cmp b/altpll1.cmp index 1e96bfe..75df12e 100644 --- a/altpll1.cmp +++ b/altpll1.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2013 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/altpll1.inc b/altpll1.inc index dde00bd..aafe483 100644 --- a/altpll1.inc +++ b/altpll1.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2013 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/altpll1.vhd b/altpll1.vhd index 36411b0..967a797 100644 --- a/altpll1.vhd +++ b/altpll1.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2013 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -157,13 +157,13 @@ BEGIN clk0_duty_cycle => 50, clk0_multiply_by => 1, clk0_phase_shift => "0", - clk1_divide_by => 900, + clk1_divide_by => 6875, clk1_duty_cycle => 50, - clk1_multiply_by => 67, + clk1_multiply_by => 512, clk1_phase_shift => "0", - clk2_divide_by => 90, + clk2_divide_by => 1375, clk2_duty_cycle => 50, - clk2_multiply_by => 67, + clk2_multiply_by => 1024, clk2_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 30303, @@ -251,8 +251,8 @@ END SYN; -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -287,8 +287,8 @@ END SYN; -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" @@ -342,13 +342,13 @@ END SYN; -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" diff --git a/altpll2.bsf b/altpll2.bsf index 79679d7..4bad59d 100644 --- a/altpll2.bsf +++ b/altpll2.bsf @@ -1,117 +1,117 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 304 248) - (text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 229 31 244)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 304 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) - (line (pt 304 72)(pt 272 72)(line_width 1)) - ) - (port - (pt 304 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) - (line (pt 304 96)(pt 272 96)(line_width 1)) - ) - (port - (pt 304 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) - (line (pt 304 120)(pt 272 120)(line_width 1)) - ) - (port - (pt 304 144) - (output) - (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) - (line (pt 304 144)(pt 272 144)(line_width 1)) - ) - (port - (pt 304 168) - (output) - (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8))) - (line (pt 304 168)(pt 272 168)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 229 230 277 244)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) - (text "Clk " (rect 59 111 76 125)(font "Arial" )) - (text "Ratio" (rect 85 111 109 125)(font "Arial" )) - (text "Ph (dg)" (rect 119 111 154 125)(font "Arial" )) - (text "DC (%)" (rect 164 111 199 125)(font "Arial" )) - (text "c0" (rect 63 129 75 143)(font "Arial" )) - (text "4/1" (rect 91 129 106 143)(font "Arial" )) - (text "240.00" (rect 120 129 153 143)(font "Arial" )) - (text "50.00" (rect 169 129 196 143)(font "Arial" )) - (text "c1" (rect 63 147 75 161)(font "Arial" )) - (text "4/1" (rect 91 147 106 161)(font "Arial" )) - (text "0.00" (rect 127 147 148 161)(font "Arial" )) - (text "50.00" (rect 169 147 196 161)(font "Arial" )) - (text "c2" (rect 63 165 75 179)(font "Arial" )) - (text "4/1" (rect 91 165 106 179)(font "Arial" )) - (text "180.00" (rect 120 165 153 179)(font "Arial" )) - (text "50.00" (rect 169 165 196 179)(font "Arial" )) - (text "c3" (rect 63 183 75 197)(font "Arial" )) - (text "4/1" (rect 91 183 106 197)(font "Arial" )) - (text "105.00" (rect 120 183 153 197)(font "Arial" )) - (text "50.00" (rect 169 183 196 197)(font "Arial" )) - (text "c4" (rect 63 201 75 215)(font "Arial" )) - (text "2/1" (rect 91 201 106 215)(font "Arial" )) - (text "270.00" (rect 120 201 153 215)(font "Arial" )) - (text "50.00" (rect 169 201 196 215)(font "Arial" )) - (line (pt 0 0)(pt 305 0)(line_width 1)) - (line (pt 305 0)(pt 305 249)(line_width 1)) - (line (pt 0 249)(pt 305 249)(line_width 1)) - (line (pt 0 0)(pt 0 249)(line_width 1)) - (line (pt 56 108)(pt 206 108)(line_width 1)) - (line (pt 56 125)(pt 206 125)(line_width 1)) - (line (pt 56 143)(pt 206 143)(line_width 1)) - (line (pt 56 161)(pt 206 161)(line_width 1)) - (line (pt 56 179)(pt 206 179)(line_width 1)) - (line (pt 56 197)(pt 206 197)(line_width 1)) - (line (pt 56 215)(pt 206 215)(line_width 1)) - (line (pt 56 108)(pt 56 215)(line_width 1)) - (line (pt 82 108)(pt 82 215)(line_width 3)) - (line (pt 116 108)(pt 116 215)(line_width 3)) - (line (pt 161 108)(pt 161 215)(line_width 3)) - (line (pt 205 108)(pt 205 215)(line_width 1)) - (line (pt 48 56)(pt 272 56)(line_width 1)) - (line (pt 272 56)(pt 272 232)(line_width 1)) - (line (pt 48 232)(pt 272 232)(line_width 1)) - (line (pt 48 56)(pt 48 232)(line_width 1)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2014 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 256 200) + (text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 185 26 196)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) + ) + (port + (pt 256 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) + ) + (port + (pt 256 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8))) + ) + (port + (pt 256 96) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8))) + ) + (port + (pt 256 112) + (output) + (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8))) + ) + (port + (pt 256 128) + (output) + (text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone III" (rect 198 186 442 382)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) + (text "Clk " (rect 51 91 117 192)(font "Arial" )) + (text "Ratio" (rect 71 91 165 192)(font "Arial" )) + (text "Ph (dg)" (rect 97 91 225 192)(font "Arial" )) + (text "DC (%)" (rect 132 91 296 192)(font "Arial" )) + (text "c0" (rect 54 104 119 218)(font "Arial" )) + (text "4/1" (rect 76 104 165 218)(font "Arial" )) + (text "240.00" (rect 98 104 225 218)(font "Arial" )) + (text "50.00" (rect 136 104 296 218)(font "Arial" )) + (text "c1" (rect 54 117 118 244)(font "Arial" )) + (text "4/1" (rect 76 117 165 244)(font "Arial" )) + (text "0.00" (rect 103 117 225 244)(font "Arial" )) + (text "50.00" (rect 136 117 296 244)(font "Arial" )) + (text "c2" (rect 54 130 119 270)(font "Arial" )) + (text "4/1" (rect 76 130 165 270)(font "Arial" )) + (text "180.00" (rect 98 130 224 270)(font "Arial" )) + (text "50.00" (rect 136 130 296 270)(font "Arial" )) + (text "c3" (rect 54 143 119 296)(font "Arial" )) + (text "4/1" (rect 76 143 165 296)(font "Arial" )) + (text "105.00" (rect 98 143 224 296)(font "Arial" )) + (text "50.00" (rect 136 143 296 296)(font "Arial" )) + (text "c4" (rect 54 156 119 322)(font "Arial" )) + (text "2/1" (rect 76 156 165 322)(font "Arial" )) + (text "270.00" (rect 98 156 225 322)(font "Arial" )) + (text "50.00" (rect 136 156 296 322)(font "Arial" )) + (line (pt 0 0)(pt 257 0)) + (line (pt 257 0)(pt 257 201)) + (line (pt 0 201)(pt 257 201)) + (line (pt 0 0)(pt 0 201)) + (line (pt 48 89)(pt 164 89)) + (line (pt 48 101)(pt 164 101)) + (line (pt 48 114)(pt 164 114)) + (line (pt 48 127)(pt 164 127)) + (line (pt 48 140)(pt 164 140)) + (line (pt 48 153)(pt 164 153)) + (line (pt 48 166)(pt 164 166)) + (line (pt 48 89)(pt 48 166)) + (line (pt 68 89)(pt 68 166)(line_width 3)) + (line (pt 94 89)(pt 94 166)(line_width 3)) + (line (pt 129 89)(pt 129 166)(line_width 3)) + (line (pt 163 89)(pt 163 166)) + (line (pt 40 48)(pt 223 48)) + (line (pt 223 48)(pt 223 183)) + (line (pt 40 183)(pt 223 183)) + (line (pt 40 48)(pt 40 183)) + (line (pt 255 64)(pt 223 64)) + (line (pt 255 80)(pt 223 80)) + (line (pt 255 96)(pt 223 96)) + (line (pt 255 112)(pt 223 112)) + (line (pt 255 128)(pt 223 128)) + ) +) diff --git a/altpll2.cmp b/altpll2.cmp index c6fe758..2a70d95 100644 --- a/altpll2.cmp +++ b/altpll2.cmp @@ -1,26 +1,26 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altpll2 - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; - c4 : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll2 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +end component; diff --git a/altpll2.inc b/altpll2.inc index e75913b..db081f6 100644 --- a/altpll2.inc +++ b/altpll2.inc @@ -1,27 +1,27 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altpll2 -( - inclk0 -) - -RETURNS ( - c0, - c1, - c2, - c3, - c4 -); +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll2 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3, + c4 +); diff --git a/altpll2.ppf b/altpll2.ppf index b1c71cc..0e421c1 100644 --- a/altpll2.ppf +++ b/altpll2.ppf @@ -1,13 +1,13 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + diff --git a/altpll2.qip b/altpll2.qip index 74cc641..294e5db 100644 --- a/altpll2.qip +++ b/altpll2.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "9.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] diff --git a/altpll2.vhd b/altpll2.vhd index 2c55f08..c79f465 100644 --- a/altpll2.vhd +++ b/altpll2.vhd @@ -1,477 +1,477 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: altpll2.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY altpll2 IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; - c4 : OUT STD_LOGIC - ); -END altpll2; - - -ARCHITECTURE SYN OF altpll2 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - clk4_divide_by : NATURAL; - clk4_duty_cycle : NATURAL; - clk4_multiply_by : NATURAL; - clk4_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire8_bv(0 DOWNTO 0) <= "0"; - sub_wire8 <= To_stdlogicvector(sub_wire8_bv); - sub_wire5 <= sub_wire0(4); - sub_wire4 <= sub_wire0(3); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - c2 <= sub_wire3; - c3 <= sub_wire4; - c4 <= sub_wire5; - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 1, - clk0_duty_cycle => 50, - clk0_multiply_by => 4, - clk0_phase_shift => "5051", - clk1_divide_by => 1, - clk1_duty_cycle => 50, - clk1_multiply_by => 4, - clk1_phase_shift => "0", - clk2_divide_by => 1, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "3788", - clk3_divide_by => 1, - clk3_duty_cycle => 50, - clk3_multiply_by => 4, - clk3_phase_shift => "2210", - clk4_divide_by => 1, - clk4_duty_cycle => 50, - clk4_multiply_by => 2, - clk4_phase_shift => "11364", - compensate_clock => "CLK0", - inclk0_input_frequency => 30303, - intended_device_family => "Cyclone III", - lpm_type => "altpll", - operation_mode => "SOURCE_SYNCHRONOUS", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_USED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire7, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000" --- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLK4 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210" --- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll2.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll2 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +END altpll2; + + +ARCHITECTURE SYN OF altpll2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + clk4_divide_by : NATURAL; + clk4_duty_cycle : NATURAL; + clk4_multiply_by : NATURAL; + clk4_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(4); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + c4 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "5051", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 1, + clk2_duty_cycle => 50, + clk2_multiply_by => 4, + clk2_phase_shift => "3788", + clk3_divide_by => 1, + clk3_duty_cycle => 50, + clk3_multiply_by => 4, + clk3_phase_shift => "2210", + clk4_divide_by => 1, + clk4_duty_cycle => 50, + clk4_multiply_by => 2, + clk4_phase_shift => "11364", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_USED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire7, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK4 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210" +-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/altpll3.bsf b/altpll3.bsf index c72a7d5..98eb9cf 100644 --- a/altpll3.bsf +++ b/altpll3.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2013 Altera Corporation +Copyright (C) 1991-2014 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -39,8 +39,8 @@ applicable agreement for further details. (port (pt 256 80) (output) - (text "c1" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c1" (rect 241 67 253 79)(font "Arial" (font_size 8))) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8))) ) (port (pt 256 96) @@ -59,40 +59,40 @@ applicable agreement for further details. (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) (text "Clk " (rect 51 91 117 192)(font "Arial" )) - (text "Ratio" (rect 71 91 165 192)(font "Arial" )) - (text "Ph (dg)" (rect 98 91 227 192)(font "Arial" )) - (text "DC (%)" (rect 133 91 298 192)(font "Arial" )) + (text "Ratio" (rect 77 91 177 192)(font "Arial" )) + (text "Ph (dg)" (rect 109 91 249 192)(font "Arial" )) + (text "DC (%)" (rect 144 91 320 192)(font "Arial" )) (text "c0" (rect 54 104 119 218)(font "Arial" )) - (text "2/33" (rect 73 104 165 218)(font "Arial" )) - (text "0.00" (rect 104 104 227 218)(font "Arial" )) - (text "50.00" (rect 137 104 298 218)(font "Arial" )) - (text "c1" (rect 54 117 119 244)(font "Arial" )) - (text "16/33" (rect 71 117 166 244)(font "Arial" )) - (text "0.00" (rect 104 117 227 244)(font "Arial" )) - (text "50.00" (rect 137 117 298 244)(font "Arial" )) + (text "2/33" (rect 79 104 177 218)(font "Arial" )) + (text "0.00" (rect 115 104 249 218)(font "Arial" )) + (text "50.00" (rect 148 104 320 218)(font "Arial" )) + (text "c1" (rect 54 117 118 244)(font "Arial" )) + (text "16/33" (rect 77 117 177 244)(font "Arial" )) + (text "0.00" (rect 115 117 249 244)(font "Arial" )) + (text "50.00" (rect 148 117 320 244)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" )) - (text "25/33" (rect 71 130 166 270)(font "Arial" )) - (text "0.00" (rect 104 130 227 270)(font "Arial" )) - (text "50.00" (rect 137 130 298 270)(font "Arial" )) + (text "227/300" (rect 71 130 176 270)(font "Arial" )) + (text "0.00" (rect 115 130 249 270)(font "Arial" )) + (text "50.00" (rect 148 130 320 270)(font "Arial" )) (text "c3" (rect 54 143 119 296)(font "Arial" )) - (text "16/11" (rect 71 143 166 296)(font "Arial" )) - (text "0.00" (rect 104 143 227 296)(font "Arial" )) - (text "50.00" (rect 137 143 298 296)(font "Arial" )) + (text "227/156" (rect 71 143 176 296)(font "Arial" )) + (text "0.00" (rect 115 143 249 296)(font "Arial" )) + (text "50.00" (rect 148 143 320 296)(font "Arial" )) (line (pt 0 0)(pt 257 0)) (line (pt 257 0)(pt 257 185)) (line (pt 0 185)(pt 257 185)) (line (pt 0 0)(pt 0 185)) - (line (pt 48 89)(pt 165 89)) - (line (pt 48 101)(pt 165 101)) - (line (pt 48 114)(pt 165 114)) - (line (pt 48 127)(pt 165 127)) - (line (pt 48 140)(pt 165 140)) - (line (pt 48 153)(pt 165 153)) + (line (pt 48 89)(pt 176 89)) + (line (pt 48 101)(pt 176 101)) + (line (pt 48 114)(pt 176 114)) + (line (pt 48 127)(pt 176 127)) + (line (pt 48 140)(pt 176 140)) + (line (pt 48 153)(pt 176 153)) (line (pt 48 89)(pt 48 153)) (line (pt 68 89)(pt 68 153)(line_width 3)) - (line (pt 95 89)(pt 95 153)(line_width 3)) - (line (pt 130 89)(pt 130 153)(line_width 3)) - (line (pt 164 89)(pt 164 153)) + (line (pt 106 89)(pt 106 153)(line_width 3)) + (line (pt 141 89)(pt 141 153)(line_width 3)) + (line (pt 175 89)(pt 175 153)) (line (pt 40 48)(pt 223 48)) (line (pt 223 48)(pt 223 167)) (line (pt 40 167)(pt 223 167)) diff --git a/altpll3.cmp b/altpll3.cmp index 279494c..233616a 100644 --- a/altpll3.cmp +++ b/altpll3.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2013 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/altpll3.inc b/altpll3.inc index 7d8f108..66f8ef8 100644 --- a/altpll3.inc +++ b/altpll3.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2013 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/altpll3.vhd b/altpll3.vhd index 382fd66..be0649b 100644 --- a/altpll3.vhd +++ b/altpll3.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2013 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -164,13 +164,13 @@ BEGIN clk1_duty_cycle => 50, clk1_multiply_by => 16, clk1_phase_shift => "0", - clk2_divide_by => 33, + clk2_divide_by => 300, clk2_duty_cycle => 50, - clk2_multiply_by => 25, + clk2_multiply_by => 227, clk2_phase_shift => "0", - clk3_divide_by => 11, + clk3_divide_by => 156, clk3_duty_cycle => 50, - clk3_multiply_by => 16, + clk3_multiply_by => 227, clk3_phase_shift => "0", compensate_clock => "CLK1", inclk0_input_frequency => 30303, @@ -249,18 +249,18 @@ END SYN; -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -289,16 +289,16 @@ END SYN; -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" @@ -365,13 +365,13 @@ END SYN; -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156" -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227" -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" @@ -440,6 +440,6 @@ END SYN; -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/altpll4.bsf b/altpll4.bsf index e071d43..f74527e 100644 --- a/altpll4.bsf +++ b/altpll4.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2010 Altera Corporation +Copyright (C) 1991-2014 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.1")) +(header "symbol" (version "1.2")) (symbol - (rect 0 0 376 232) - (text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 213 31 228)(font "Arial" )) + (rect 0 0 312 184) + (text "altpll4" (rect 139 0 179 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 25 180)(font "Arial" )) (port - (pt 0 72) + (pt 0 64) (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 88 72)(line_width 1)) + (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 72 64)) + ) + (port + (pt 0 80) + (input) + (text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 72 80)) ) (port (pt 0 96) (input) - (text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) - (text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 88 96)(line_width 1)) + (text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 82 39 95)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 72 96)) ) (port - (pt 0 120) + (pt 0 112) (input) - (text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 88 120)(line_width 1)) + (text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 98 47 111)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 72 112)) + ) + (port + (pt 0 128) + (input) + (text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 114 57 127)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 72 128)) ) (port (pt 0 144) (input) - (text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) - (text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 88 144)(line_width 1)) + (text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 130 65 143)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 72 144)) ) (port - (pt 0 168) - (input) - (text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8))) - (text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 88 168)(line_width 1)) - ) - (port - (pt 0 192) - (input) - (text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8))) - (text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8))) - (line (pt 0 192)(pt 88 192)(line_width 1)) - ) - (port - (pt 376 72) + (pt 312 64) (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) - (line (pt 376 72)(pt 288 72)(line_width 1)) + (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c0" (rect 296 50 306 63)(font "Arial" (font_size 8))) ) (port - (pt 376 96) + (pt 312 80) (output) - (text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) - (text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) - (line (pt 376 96)(pt 288 96)(line_width 1)) + (text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "scandataout" (rect 248 66 306 79)(font "Arial" (font_size 8))) ) (port - (pt 376 120) + (pt 312 96) (output) - (text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) - (text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) - (line (pt 376 120)(pt 288 120)(line_width 1)) + (text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8))) + (text "scandone" (rect 260 82 306 95)(font "Arial" (font_size 8))) ) (port - (pt 376 144) + (pt 312 112) (output) - (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) - (text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) - (line (pt 376 144)(pt 288 144)(line_width 1)) + (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "locked" (rect 277 98 306 111)(font "Arial" (font_size 8))) ) (drawing - (text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) - (text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) - (text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) - (text "Clk " (rect 99 167 116 181)(font "Arial" )) - (text "Ratio" (rect 125 167 149 181)(font "Arial" )) - (text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) - (text "DC (%)" (rect 204 167 239 181)(font "Arial" )) - (text "c0" (rect 103 185 115 199)(font "Arial" )) - (text "2/1" (rect 131 185 146 199)(font "Arial" )) - (text "0.00" (rect 167 185 188 199)(font "Arial" )) - (text "50.00" (rect 209 185 236 199)(font "Arial" )) - (line (pt 0 0)(pt 377 0)(line_width 1)) - (line (pt 377 0)(pt 377 233)(line_width 1)) - (line (pt 0 233)(pt 377 233)(line_width 1)) - (line (pt 0 0)(pt 0 233)(line_width 1)) - (line (pt 96 164)(pt 246 164)(line_width 1)) - (line (pt 96 181)(pt 246 181)(line_width 1)) - (line (pt 96 199)(pt 246 199)(line_width 1)) - (line (pt 96 164)(pt 96 199)(line_width 1)) - (line (pt 122 164)(pt 122 199)(line_width 3)) - (line (pt 156 164)(pt 156 199)(line_width 3)) - (line (pt 201 164)(pt 201 199)(line_width 3)) - (line (pt 245 164)(pt 245 199)(line_width 1)) - (line (pt 88 56)(pt 288 56)(line_width 1)) - (line (pt 288 56)(pt 288 216)(line_width 1)) - (line (pt 88 216)(pt 288 216)(line_width 1)) - (line (pt 88 56)(pt 88 216)(line_width 1)) + (text "Cyclone III" (rect 250 169 545 349)(font "Arial" )) + (text "inclk0 frequency: 48.019 MHz" (rect 82 92 287 195)(font "Arial" )) + (text "Operation Mode: Normal" (rect 82 105 263 221)(font "Arial" )) + (text "Clk " (rect 83 126 180 263)(font "Arial" )) + (text "Ratio" (rect 104 126 228 263)(font "Arial" )) + (text "Ph (dg)" (rect 130 126 289 263)(font "Arial" )) + (text "DC (%)" (rect 164 126 358 263)(font "Arial" )) + (text "c0" (rect 86 140 180 291)(font "Arial" )) + (text "2/1" (rect 109 140 228 291)(font "Arial" )) + (text "0.00" (rect 136 140 288 291)(font "Arial" )) + (text "50.00" (rect 168 140 357 291)(font "Arial" )) + (line (pt 0 0)(pt 313 0)) + (line (pt 313 0)(pt 313 186)) + (line (pt 0 186)(pt 313 186)) + (line (pt 0 0)(pt 0 186)) + (line (pt 80 124)(pt 196 124)) + (line (pt 80 137)(pt 196 137)) + (line (pt 80 151)(pt 196 151)) + (line (pt 80 124)(pt 80 151)) + (line (pt 101 124)(pt 101 151)(line_width 3)) + (line (pt 127 124)(pt 127 151)(line_width 3)) + (line (pt 161 124)(pt 161 151)(line_width 3)) + (line (pt 195 124)(pt 195 151)) + (line (pt 72 48)(pt 239 48)) + (line (pt 239 48)(pt 239 168)) + (line (pt 72 168)(pt 239 168)) + (line (pt 72 48)(pt 72 168)) + (line (pt 311 64)(pt 239 64)) + (line (pt 311 80)(pt 239 80)) + (line (pt 311 96)(pt 239 96)) + (line (pt 311 112)(pt 239 112)) ) ) diff --git a/altpll4.cmp b/altpll4.cmp index 83b3c1e..ac5def2 100644 --- a/altpll4.cmp +++ b/altpll4.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/altpll4.inc b/altpll4.inc index 39f54c9..c622d5e 100644 --- a/altpll4.inc +++ b/altpll4.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/altpll4.mif b/altpll4.mif index e50eda2..b526227 100644 --- a/altpll4.mif +++ b/altpll4.mif @@ -1,4 +1,4 @@ --- Copyright (C) 1991-2010 Altera Corporation +-- Copyright (C) 1991-2014 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing @@ -17,8 +17,8 @@ -- Device Part: - -- Device Speed Grade: 8 -- PLL Scan Chain: Fast PLL (144 bits) --- File Name: C:\FireBee\FPGA\altpll4.mif --- Generated: Mon Dec 06 01:47:24 2010 +-- File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif +-- Generated: Mon Sep 21 17:50:54 2015 WIDTH=1; DEPTH=144; diff --git a/altpll4.qip b/altpll4.qip index f44acdc..ded02bb 100644 --- a/altpll4.qip +++ b/altpll4.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name IP_TOOL_VERSION "13.1" set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] diff --git a/altpll4.tdf b/altpll4.tdf index 3ec77d4..8e72bcc 100644 --- a/altpll4.tdf +++ b/altpll4.tdf @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -59,7 +59,7 @@ VARIABLE CLK0_MULTIPLY_BY = 2, CLK0_PHASE_SHIFT = "0", COMPENSATE_CLOCK = "CLK0", - INCLK0_INPUT_FREQUENCY = 20833, + INCLK0_INPUT_FREQUENCY = 20824, INTENDED_DEVICE_FAMILY = "Cyclone III", LPM_TYPE = "altpll", OPERATION_MODE = "NORMAL", @@ -113,16 +113,16 @@ VARIABLE BEGIN c0 = altpll_component.clk[0..0]; - scandone = altpll_component.scandone; scandataout = altpll_component.scandataout; + scandone = altpll_component.scandone; locked = altpll_component.locked; - altpll_component.scanclkena = scanclkena; + altpll_component.areset = areset; + altpll_component.configupdate = configupdate; altpll_component.inclk[0..0] = inclk0; altpll_component.inclk[1..1] = GND; - altpll_component.scandata = scandata; - altpll_component.areset = areset; altpll_component.scanclk = scanclk; - altpll_component.configupdate = configupdate; + altpll_component.scanclkena = scanclkena; + altpll_component.scandata = scandata; END; @@ -148,7 +148,7 @@ END; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -156,7 +156,7 @@ END; -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" @@ -166,7 +166,7 @@ END; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" @@ -217,7 +217,7 @@ END; -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" @@ -277,22 +277,22 @@ END; -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 --- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 --- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 --- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 +-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 +-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE -- Retrieval info: LIB_FILE: altera_mf diff --git a/firebee1.bdf b/firebee1.bdf index 46507a2..abc22f8 100644 --- a/firebee1.bdf +++ b/firebee1.bdf @@ -1,5837 +1,6196 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -//#pragma file_not_in_maxplusii_format -(header "graphic" (version "1.3")) -(properties - (page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n1\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n") -) -(pin - (input) - (rect 208 1392 376 1408) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "FB_ALE" (rect 9 0 60 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 136 1408 192 1424)) -) -(pin - (input) - (rect 992 936 1160 952) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nFB_WR" (rect 9 0 66 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 944 952 1000 968)) -) -(pin - (input) - (rect 168 296 336 312) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "CLK33M" (rect 9 0 64 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 104 312 176 328)) -) -(pin - (input) - (rect 992 960 1160 976) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nFB_CS1" (rect 5 0 67 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 944 976 1000 992)) -) -(pin - (input) - (rect 992 984 1160 1000) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nFB_CS2" (rect 5 0 67 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 944 1000 1000 1016)) -) -(pin - (input) - (rect 1008 360 1176 376) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nFB_CS3" (rect 5 0 67 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 952 376 1008 392)) -) -(pin - (input) - (rect 992 1008 1160 1024) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "FB_SIZE0" (rect 5 0 69 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 944 1024 1000 1040)) -) -(pin - (input) - (rect 992 1032 1160 1048) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "FB_SIZE1" (rect 5 0 69 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 944 1048 1000 1064)) -) -(pin - (input) - (rect 992 1056 1160 1072) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nFB_BURST" (rect 5 0 87 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 944 1072 1000 1088)) -) -(pin - (input) - (rect 936 1168 1104 1184) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "LP_BUSY" (rect 5 0 68 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 888 1184 952 1200)) -) -(pin - (input) - (rect 856 1200 1024 1216) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nACSI_DRQ" (rect 5 0 85 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1216 864 1232)) -) -(pin - (input) - (rect 856 1224 1024 1240) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nACSI_INT" (rect 5 0 75 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1240 864 1256)) -) -(pin - (input) - (rect 936 1392 1104 1408) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "RxD" (rect 5 0 32 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1408 944 1424)) -) -(pin - (input) - (rect 936 1416 1104 1432) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "CTS" (rect 5 0 33 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1432 944 1448)) -) -(pin - (input) - (rect 936 1440 1104 1456) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "RI" (rect 5 0 19 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1456 944 1472)) -) -(pin - (input) - (rect 936 1464 1104 1480) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "DCD" (rect 5 0 36 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1480 944 1496)) -) -(pin - (input) - (rect 608 1488 776 1504) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "AMKB_RX" (rect 5 0 69 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 560 1504 616 1520)) -) -(pin - (input) - (rect 608 1512 776 1528) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "PIC_AMKB_RX" (rect 5 0 101 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 560 1528 616 1544)) -) -(pin - (input) - (rect 936 1544 1104 1560) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "IDE_RDY" (rect 5 0 66 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 888 1560 944 1576)) -) -(pin - (input) - (rect 936 1568 1104 1584) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "IDE_INT" (rect 5 0 59 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1584 944 1600)) -) -(pin - (input) - (rect 936 1592 1104 1608) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "WP_CF_CARD" (rect 5 0 102 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 888 1608 944 1624)) -) -(pin - (input) - (rect 872 1672 1040 1688) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "TRACK00" (rect 5 0 68 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 816 1688 880 1704)) -) -(pin - (input) - (rect 872 1696 1040 1712) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nWP" (rect 5 0 35 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 816 1712 880 1728)) -) -(pin - (input) - (rect 872 1744 1040 1760) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nDCHG" (rect 5 0 55 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 816 1760 880 1776)) -) -(pin - (input) - (rect 936 1776 1104 1792) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "SD_DATA0" (rect 5 0 76 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1792 944 1808)) -) -(pin - (input) - (rect 936 1800 1104 1816) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "SD_DATA1" (rect 5 0 76 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1816 944 1832)) -) -(pin - (input) - (rect 936 1824 1104 1840) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "SD_DATA2" (rect 5 0 76 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1840 944 1856)) -) -(pin - (input) - (rect 936 1848 1128 1864) - (text "INPUT" (rect 157 0 193 13)(font "Arial" (font_size 6))) - (text "SD_CARD_DEDECT" (rect 5 0 140 15)(font "Arial" )) - (pt 192 8) - (drawing - (line (pt 116 12)(pt 141 12)(line_width 1)) - (line (pt 116 4)(pt 141 4)(line_width 1)) - (line (pt 145 8)(pt 192 8)(line_width 1)) - (line (pt 116 12)(pt 116 4)(line_width 1)) - (line (pt 141 4)(pt 145 8)(line_width 1)) - (line (pt 141 12)(pt 145 8)(line_width 1)) - ) - (text "VCC" (rect 160 7 184 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1864 952 1880)) -) -(pin - (input) - (rect 872 1360 1040 1376) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "MIDI_IN" (rect 5 0 55 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 816 1376 880 1392)) -) -(pin - (input) - (rect 936 1256 1104 1272) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nSCSI_DRQ" (rect 5 0 86 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 888 1272 944 1288)) -) -(pin - (input) - (rect 936 1872 1104 1888) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "SD_WP" (rect 5 0 55 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1888 952 1904)) -) -(pin - (input) - (rect 872 1720 1040 1736) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nRD_DATA" (rect 5 0 78 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 816 1736 880 1752)) -) -(pin - (input) - (rect 936 1280 1104 1296) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nSCSI_C_D" (rect 5 0 84 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 888 1296 944 1312)) -) -(pin - (input) - (rect 936 1304 1104 1320) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nSCSI_I_O" (rect 5 0 76 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 888 1320 944 1336)) -) -(pin - (input) - (rect 936 1328 1104 1344) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nSCSI_MSG" (rect 5 0 85 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 888 1344 944 1360)) -) -(pin - (input) - (rect 992 1104 1160 1120) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nDACK0" (rect 5 0 60 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 1120 1000 1136)) -) -(pin - (input) - (rect 984 2592 1152 2608) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "PIC_INT" (rect 5 0 59 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 2608 1000 2624)) -) -(pin - (input) - (rect 992 912 1160 928) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nFB_OE" (rect 5 0 59 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 944 928 1000 944)) -) -(pin - (input) - (rect 360 2616 528 2632) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "TOUT0" (rect 5 0 51 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 304 2632 368 2648)) -) -(pin - (input) - (rect 360 2504 528 2520) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nMASTER" (rect 5 0 69 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 304 2520 368 2536)) -) -(pin - (input) - (rect 984 2640 1152 2656) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "DVI_INT" (rect 5 0 58 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 2656 992 2672)) -) -(pin - (input) - (rect 360 2408 528 2424) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nDACK1" (rect 5 0 60 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 304 2424 368 2440)) -) -(pin - (input) - (rect 984 2664 1152 2680) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nPCI_INTD" (rect 5 0 78 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 2680 992 2696)) -) -(pin - (input) - (rect 984 2688 1152 2704) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nPCI_INTC" (rect 5 0 78 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 2704 992 2720)) -) -(pin - (input) - (rect 984 2712 1152 2728) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nPCI_INTB" (rect 5 0 76 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 2728 992 2744)) -) -(pin - (input) - (rect 984 2736 1152 2752) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nPCI_INTA" (rect 5 0 75 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 2752 1000 2768)) -) -(pin - (input) - (rect 984 2616 1152 2632) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "E0_INT" (rect 5 0 53 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 2632 992 2648)) -) -(pin - (input) - (rect 872 1648 1040 1664) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "nINDEX" (rect 5 0 55 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 816 1664 880 1680)) -) -(pin - (input) - (rect 872 1624 1040 1640) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "HD_DD" (rect 5 0 55 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1632 872 1648)) -) -(pin - (input) - (rect 96 -288 264 -272) - (text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6))) - (text "MAIN_CLK" (rect 9 0 78 15)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)(line_width 1)) - (line (pt 92 4)(pt 117 4)(line_width 1)) - (line (pt 121 8)(pt 168 8)(line_width 1)) - (line (pt 92 12)(pt 92 4)(line_width 1)) - (line (pt 117 4)(pt 121 8)(line_width 1)) - (line (pt 117 12)(pt 121 8)(line_width 1)) - ) - (text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 56 -304 120 -288)) -) -(pin - (input) - (rect 664 440 840 456) - (text "INPUT" (rect 141 0 177 13)(font "Arial" (font_size 6))) - (text "nRSTO_MCF" (rect 5 0 89 15)(font "Arial" )) - (pt 176 8) - (drawing - (line (pt 100 12)(pt 125 12)(line_width 1)) - (line (pt 100 4)(pt 125 4)(line_width 1)) - (line (pt 129 8)(pt 176 8)(line_width 1)) - (line (pt 100 12)(pt 100 4)(line_width 1)) - (line (pt 125 4)(pt 129 8)(line_width 1)) - (line (pt 125 12)(pt 129 8)(line_width 1)) - ) - (text "VCC" (rect 144 7 168 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 600 448 664 464)) -) -(pin - (output) - (rect 864 288 1040 304) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "CLK24M576" (rect 90 0 170 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 1040 304 1112 320)) -) -(pin - (output) - (rect 1832 832 2008 848) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "LP_STR" (rect 90 0 144 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 840 2064 856)) -) -(pin - (output) - (rect 1832 936 2008 952) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nACSI_ACK" (rect 90 0 166 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 952 2072 968)) -) -(pin - (output) - (rect 1832 960 2008 976) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nACSI_RESET" (rect 90 0 185 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 976 2072 992)) -) -(pin - (output) - (rect 1832 984 2008 1000) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nACSI_CS" (rect 90 0 158 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 1000 2072 1016)) -) -(pin - (output) - (rect 1832 1008 2008 1024) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "ACSI_DIR" (rect 90 0 154 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 1024 2064 1040)) -) -(pin - (output) - (rect 1832 1032 2008 1048) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "ACSI_A1" (rect 90 0 146 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 1048 2072 1064)) -) -(pin - (output) - (rect 1840 1112 2016 1128) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSCSI_ACK" (rect 90 0 167 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2016 1128 2072 1144)) -) -(pin - (output) - (rect 1840 1136 2016 1152) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSCSI_ATN" (rect 90 0 166 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2016 1152 2080 1168)) -) -(pin - (output) - (rect 1840 1160 2016 1176) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "SCSI_DIR" (rect 90 0 156 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2016 1176 2072 1192)) -) -(pin - (output) - (rect 1920 1264 2096 1280) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "MIDI_OLR" (rect 90 0 156 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2096 1280 2152 1296)) -) -(pin - (output) - (rect 1920 1288 2096 1304) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "MIDI_TLR" (rect 90 0 153 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2096 1304 2152 1320)) -) -(pin - (output) - (rect 1840 1320 2016 1336) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "TxD" (rect 90 0 114 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2016 1336 2080 1352)) -) -(pin - (output) - (rect 1840 1344 2016 1360) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "RTS" (rect 90 0 118 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2016 1360 2080 1376)) -) -(pin - (output) - (rect 1848 1368 2024 1384) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "DTR" (rect 90 0 119 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2024 1384 2088 1400)) -) -(pin - (output) - (rect 2112 1400 2288 1416) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "AMKB_TX" (rect 90 0 152 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2288 1416 2392 1448)) -) -(pin - (output) - (rect 1848 1432 2024 1448) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "IDE_RES" (rect 90 0 151 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2024 1448 2088 1464)) -) -(pin - (output) - (rect 1848 1456 2024 1472) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nIDE_CS0" (rect 90 0 158 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2024 1472 2080 1488)) -) -(pin - (output) - (rect 1856 1480 2032 1496) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nIDE_CS1" (rect 90 0 158 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2032 1496 2088 1512)) -) -(pin - (output) - (rect 1848 1504 2024 1520) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nIDE_WR" (rect 90 0 153 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2024 1520 2080 1536)) -) -(pin - (output) - (rect 1848 1528 2024 1544) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nIDE_RD" (rect 90 0 151 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2024 1544 2080 1560)) -) -(pin - (output) - (rect 1848 1552 2024 1568) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nCF_CS0" (rect 90 0 153 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2024 1568 2088 1584)) -) -(pin - (output) - (rect 1848 1576 2024 1592) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nCF_CS1" (rect 90 0 153 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2024 1592 2088 1608)) -) -(pin - (output) - (rect 1920 1608 2096 1624) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nROM3" (rect 90 0 138 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2096 1624 2152 1640)) -) -(pin - (output) - (rect 1920 1632 2096 1648) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nROM4" (rect 90 0 138 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2096 1648 2152 1664)) -) -(pin - (output) - (rect 1920 1656 2096 1672) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nRP_UDS" (rect 90 0 157 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2096 1672 2152 1688)) -) -(pin - (output) - (rect 1920 1680 2096 1696) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nRP_LDS" (rect 90 0 154 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2096 1696 2152 1712)) -) -(pin - (output) - (rect 1856 1856 2032 1872) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSDSEL" (rect 90 0 145 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2032 1872 2096 1888)) -) -(pin - (output) - (rect 2136 1832 2312 1848) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nWR_GATE" (rect 90 0 166 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2312 1848 2376 1864)) -) -(pin - (output) - (rect 2136 1808 2312 1824) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nWR" (rect 90 0 121 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2312 1824 2376 1840)) -) -(pin - (output) - (rect 1928 1912 2104 1928) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "YM_QA" (rect 90 0 136 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2104 1928 2168 1944)) -) -(pin - (output) - (rect 1928 1936 2104 1952) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "YM_QB" (rect 90 0 137 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2104 1952 2168 1968)) -) -(pin - (output) - (rect 1928 1960 2104 1976) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "YM_QC" (rect 90 0 138 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2104 1976 2168 1992)) -) -(pin - (output) - (rect 1856 2040 2032 2056) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "SD_CLK" (rect 90 0 146 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2032 2056 2096 2072)) -) -(pin - (output) - (rect 1856 1712 2032 1728) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "DSA_D" (rect 90 0 137 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2032 1728 2096 1744)) -) -(pin - (output) - (rect 2080 72 2256 88) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "VR[7..0]" (rect 90 0 139 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2256 88 2344 232)) -) -(pin - (output) - (rect 2000 96 2176 112) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "VG[7..0]" (rect 90 0 139 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2176 112 2264 256)) -) -(pin - (output) - (rect 1912 120 2088 136) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "VB[7..0]" (rect 90 0 138 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2088 136 2176 280)) -) -(pin - (output) - (rect 2528 320 2704 336) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "VA[12..0]" (rect 90 0 145 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2704 336 2776 560)) -) -(pin - (output) - (rect 2400 344 2576 360) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nVWE" (rect 90 0 128 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2576 360 2640 392)) -) -(pin - (output) - (rect 2304 368 2480 384) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nVCAS" (rect 90 0 134 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2480 384 2552 416)) -) -(pin - (output) - (rect 2208 392 2384 408) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nVRAS" (rect 90 0 134 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2384 408 2456 440)) -) -(pin - (output) - (rect 2040 416 2216 432) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nVCS" (rect 90 0 126 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2216 432 2280 464)) -) -(pin - (output) - (rect 1944 560 2120 576) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "VDM[3..0]" (rect 90 0 150 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2120 576 2192 656)) -) -(pin - (output) - (rect 1832 264 2008 280) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nPD_VGA" (rect 90 0 153 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 280 2064 296)) -) -(pin - (output) - (rect 1832 2416 2008 2432) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nIRQ[7..2]" (rect 90 0 153 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 2432 2112 2576)) -) -(pin - (output) - (rect 864 24 1040 40) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "CLK25M" (rect 90 0 145 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 1040 40 1096 56)) -) -(pin - (output) - (rect 1832 2632 2008 2648) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "TIN0" (rect 90 0 120 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 2648 2064 2664)) -) -(pin - (output) - (rect 1824 3280 2000 3296) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSRCS" (rect 90 0 138 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2000 3296 2056 3312)) -) -(pin - (output) - (rect 1824 3304 2000 3320) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSRBLE" (rect 90 0 145 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2000 3320 2056 3336)) -) -(pin - (output) - (rect 1824 3328 2000 3344) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSRBHE" (rect 90 0 147 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2000 3344 2056 3360)) -) -(pin - (output) - (rect 1824 3352 2000 3368) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSRWE" (rect 90 0 140 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2000 3368 2056 3384)) -) -(pin - (output) - (rect 616 2408 792 2424) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nDREQ1" (rect 90 0 147 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 792 2424 856 2440)) -) -(pin - (output) - (rect 608 2128 784 2144) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "LED_FPGA_OK" (rect 90 0 191 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 784 2144 848 2176)) -) -(pin - (output) - (rect 1824 3376 2000 3392) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSROE" (rect 90 0 138 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2000 3392 2064 3408)) -) -(pin - (output) - (rect 1944 440 2120 456) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "VCKE" (rect 90 0 127 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2120 456 2184 488)) -) -(pin - (output) - (rect 2056 728 2232 744) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nFB_TA" (rect 90 0 140 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2232 744 2288 760)) -) -(pin - (output) - (rect 2712 880 2888 896) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nDDR_CLK" (rect 90 0 166 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2888 896 2960 928)) -) -(pin - (output) - (rect 2536 752 2712 768) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "DDR_CLK" (rect 90 0 158 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2712 768 2784 800)) -) -(pin - (output) - (rect 1832 464 2008 480) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "BA[1..0]" (rect 90 0 138 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 480 2080 528)) -) -(pin - (output) - (rect 2136 -72 2312 -56) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "VSYNC_PAD" (rect 90 0 173 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2312 -56 2400 -24)) -) -(pin - (output) - (rect 2712 -88 2888 -72) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "HSYNC_PAD" (rect 90 0 176 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2888 -72 2976 -40)) -) -(pin - (output) - (rect 2712 32 2888 48) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nBLANK_PAD" (rect 90 0 180 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2888 48 2976 80)) -) -(pin - (output) - (rect 2712 160 2891 176) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "PIXEL_CLK_PAD" (rect 90 0 202 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2888 176 2976 208)) -) -(pin - (output) - (rect 1832 216 2008 232) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSYNC" (rect 90 0 137 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 232 2112 264)) -) -(pin - (output) - (rect 2136 1736 2312 1752) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nMOT_ON" (rect 90 0 157 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2312 1752 2376 1768)) -) -(pin - (output) - (rect 2136 1760 2312 1776) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSTEP_DIR" (rect 90 0 167 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2312 1776 2376 1792)) -) -(pin - (output) - (rect 2136 1784 2312 1800) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "nSTEP" (rect 90 0 134 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2312 1800 2376 1816)) -) -(pin - (output) - (rect 840 48 1016 64) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "CLKUSB" (rect 90 0 147 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 1000 64 1056 80)) -) -(pin - (output) - (rect 1832 856 2008 872) - (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) - (text "LPDIR" (rect 90 0 132 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 52 4)(pt 78 4)(line_width 1)) - (line (pt 52 12)(pt 78 12)(line_width 1)) - (line (pt 52 12)(pt 52 4)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 82 8)(pt 78 12)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - ) - (annotation_block (location)(rect 2008 864 2064 880)) -) -(pin - (bidir) - (rect 1840 1088 2016 1104) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "SCSI_PAR" (rect 90 0 159 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1104 2080 1120)) -) -(pin - (bidir) - (rect 1840 1184 2016 1200) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "nSCSI_RST" (rect 90 0 167 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1200 2072 1216)) -) -(pin - (bidir) - (rect 1840 1208 2016 1224) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "nSCSI_SEL" (rect 90 0 166 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1224 2080 1240)) -) -(pin - (bidir) - (rect 1840 1232 2016 1248) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "nSCSI_BUSY" (rect 90 0 177 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1248 2072 1264)) -) -(pin - (bidir) - (rect 1856 1992 2032 2008) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "SD_CD_DATA3" (rect 90 0 191 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2032 2008 2096 2024)) -) -(pin - (bidir) - (rect 1856 2016 2032 2032) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "SD_CMD_D1" (rect 90 0 177 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2032 2032 2096 2048)) -) -(pin - (bidir) - (rect 1936 1064 2112 1080) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "SCSI_D[7..0]" (rect 90 0 172 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2112 1080 2176 1208)) -) -(pin - (bidir) - (rect 1904 888 2080 904) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "ACSI_D[7..0]" (rect 90 0 171 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2080 904 2144 1032)) -) -(pin - (bidir) - (rect 1960 808 2136 824) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "LP_D[7..0]" (rect 90 0 157 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2136 824 2200 952)) -) -(pin - (bidir) - (rect 176 1360 352 1376) - (text "BIDIR" (rect 151 0 182 13)(font "Arial" (font_size 6))) - (text "FB_AD[31..0]" (rect 5 0 88 15)(font "Arial" )) - (pt 176 8) - (drawing - (line (pt 120 4)(pt 98 4)(line_width 1)) - (line (pt 176 8)(pt 124 8)(line_width 1)) - (line (pt 120 12)(pt 98 12)(line_width 1)) - (line (pt 98 4)(pt 94 8)(line_width 1)) - (line (pt 98 12)(pt 94 8)(line_width 1)) - (line (pt 120 4)(pt 124 8)(line_width 1)) - (line (pt 124 8)(pt 120 12)(line_width 1)) - ) - (flipy) - (text "VCC" (rect 152 7 176 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 96 840 168 1352)) -) -(pin - (bidir) - (rect 2104 3232 2280 3248) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "IO[17..0]" (rect 90 0 143 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2280 3248 2344 3536)) -) -(pin - (bidir) - (rect 1944 3256 2120 3272) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "SRD[15..0]" (rect 90 0 159 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2120 3272 2184 3528)) -) -(pin - (bidir) - (rect 2040 536 2216 552) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "VDQS[3..0]" (rect 90 0 159 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2216 552 2288 632)) -) -(pin - (bidir) - (rect 2648 296 2824 312) - (text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "VD[31..0]" (rect 90 0 147 15)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 56 4)(pt 78 4)(line_width 1)) - (line (pt 0 8)(pt 52 8)(line_width 1)) - (line (pt 56 12)(pt 78 12)(line_width 1)) - (line (pt 78 4)(pt 82 8)(line_width 1)) - (line (pt 78 12)(pt 82 8)(line_width 1)) - (line (pt 56 4)(pt 52 8)(line_width 1)) - (line (pt 52 8)(pt 56 12)(line_width 1)) - ) - (text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2824 312 2896 840)) -) -(symbol - (rect 544 2024 688 2088) - (text "lpm_counter0" (rect 33 1 148 20)(font "Arial" (font_size 10))) - (text "inst18" (rect 8 48 48 63)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 62 42)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 144 40) - (output) - (text "q[17..0]" (rect 0 0 51 16)(font "Arial" (font_size 8))) - (text "q[17..0]" (rect 89 34 140 50)(font "Arial" (font_size 8))) - (line (pt 144 40)(pt 128 40)(line_width 3)) - ) - (drawing - (text "up counter" (rect 84 17 152 32)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 48)(line_width 1)) - (line (pt 128 48)(pt 16 48)(line_width 1)) - (line (pt 16 48)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) -(symbol - (rect 440 2120 488 2152) - (text "WIRE" (rect 1 0 31 13)(font "Arial" (font_size 6))) - (text "inst3" (rect 3 21 34 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 14 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 32 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 14 7)(pt 32 16)(line_width 1)) - (line (pt 14 25)(pt 14 7)(line_width 1)) - (line (pt 14 25)(pt 32 16)(line_width 1)) - ) -) -(symbol - (rect 464 1336 608 1432) - (text "lpm_ff0" (rect 52 1 114 20)(font "Arial" (font_size 10))) - (text "inst1" (rect 8 80 39 95)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 0 64) - (input) - (text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8))) - (text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 16 64)(line_width 1)) - ) - (port - (pt 144 56) - (output) - (text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8))) - (text "q[31..0]" (rect 89 50 140 66)(font "Arial" (font_size 8))) - (line (pt 144 56)(pt 128 56)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 136 32)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 80)(line_width 1)) - (line (pt 128 80)(pt 16 80)(line_width 1)) - (line (pt 16 80)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) -(symbol - (rect 1880 696 1944 776) - (text "NOR4" (rect 1 0 34 13)(font "Arial" (font_size 6))) - (text "inst2" (rect 3 69 34 84)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible)) - (text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 14 16)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "IN3" (rect 2 39 26 55)(font "Courier New" (bold))(invisible)) - (text "IN3" (rect 2 39 26 55)(font "Courier New" (bold))(invisible)) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 0 32) - (input) - (text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible)) - (text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible)) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 64) - (input) - (text "IN4" (rect 2 55 26 71)(font "Courier New" (bold))(invisible)) - (text "IN4" (rect 2 55 26 71)(font "Courier New" (bold))(invisible)) - (line (pt 0 64)(pt 14 64)(line_width 1)) - ) - (port - (pt 64 40) - (output) - (text "OUT" (rect 48 31 72 47)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 48 31 72 47)(font "Courier New" (bold))(invisible)) - (line (pt 56 40)(pt 64 40)(line_width 1)) - ) - (drawing - (line (pt 14 29)(pt 25 29)(line_width 1)) - (line (pt 14 52)(pt 25 52)(line_width 1)) - (line (pt 14 29)(pt 14 13)(line_width 1)) - (line (pt 14 67)(pt 14 51)(line_width 1)) - (arc (pt 25 51)(pt 48 40)(rect -4 -7 55 52)(line_width 1)) - (arc (pt 48 40)(pt 25 29)(rect -4 29 55 88)(line_width 1)) - (arc (pt 8 45)(pt 8 35)(rect -13 24 20 57)(line_width 1)) - (circle (rect 48 36 56 44)(line_width 1)) - ) -) -(symbol - (rect 2632 872 2680 904) - (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) - (text "inst4" (rect 3 21 34 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 13 25)(pt 13 7)(line_width 1)) - (line (pt 13 7)(pt 31 16)(line_width 1)) - (line (pt 13 25)(pt 31 16)(line_width 1)) - (circle (rect 31 12 39 20)(line_width 1)) - ) -) -(symbol - (rect 1896 -88 2128 32) - (text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10))) - (text "inst5" (rect 8 104 39 119)(font "Arial" )) - (port - (pt 0 24) - (input) - (text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8))) - (line (pt 0 24)(pt 88 24)(line_width 1)) - ) - (port - (pt 0 40) - (input) - (text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 88 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 88 56)(line_width 1)) - ) - (port - (pt 232 24) - (output) - (text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8))) - (line (pt 232 24)(pt 152 24)(line_width 1)) - ) - (drawing - (text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8))) - (text "output" (rect 105 42 147 58)(font "Arial" (font_size 8))) - (text "power up" (rect 92 74 152 89)(font "Arial" )) - (text "low" (rect 92 84 114 99)(font "Arial" )) - (line (pt 88 16)(pt 152 16)(line_width 1)) - (line (pt 152 16)(pt 152 96)(line_width 1)) - (line (pt 152 96)(pt 88 96)(line_width 1)) - (line (pt 88 96)(pt 88 16)(line_width 1)) - ) -) -(symbol - (rect 2464 -104 2696 16) - (text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10))) - (text "inst6" (rect 8 104 39 119)(font "Arial" )) - (port - (pt 0 24) - (input) - (text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8))) - (line (pt 0 24)(pt 88 24)(line_width 1)) - ) - (port - (pt 0 40) - (input) - (text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 88 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 88 56)(line_width 1)) - ) - (port - (pt 232 24) - (output) - (text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8))) - (line (pt 232 24)(pt 152 24)(line_width 1)) - ) - (drawing - (text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8))) - (text "output" (rect 105 42 147 58)(font "Arial" (font_size 8))) - (text "power up" (rect 92 74 152 89)(font "Arial" )) - (text "low" (rect 92 84 114 99)(font "Arial" )) - (line (pt 88 16)(pt 152 16)(line_width 1)) - (line (pt 152 16)(pt 152 96)(line_width 1)) - (line (pt 152 96)(pt 88 96)(line_width 1)) - (line (pt 88 96)(pt 88 16)(line_width 1)) - ) -) -(symbol - (rect 2464 16 2696 136) - (text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10))) - (text "inst8" (rect 8 104 39 119)(font "Arial" )) - (port - (pt 0 24) - (input) - (text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8))) - (line (pt 0 24)(pt 88 24)(line_width 1)) - ) - (port - (pt 0 40) - (input) - (text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 88 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 88 56)(line_width 1)) - ) - (port - (pt 232 24) - (output) - (text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8))) - (line (pt 232 24)(pt 152 24)(line_width 1)) - ) - (drawing - (text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8))) - (text "output" (rect 105 42 147 58)(font "Arial" (font_size 8))) - (text "power up" (rect 92 74 152 89)(font "Arial" )) - (text "low" (rect 92 84 114 99)(font "Arial" )) - (line (pt 88 16)(pt 152 16)(line_width 1)) - (line (pt 152 16)(pt 152 96)(line_width 1)) - (line (pt 152 96)(pt 88 96)(line_width 1)) - (line (pt 88 96)(pt 88 16)(line_width 1)) - ) -) -(symbol - (rect 2464 144 2696 264) - (text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10))) - (text "inst9" (rect 8 104 39 119)(font "Arial" )) - (port - (pt 0 24) - (input) - (text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8))) - (line (pt 0 24)(pt 88 24)(line_width 1)) - ) - (port - (pt 0 40) - (input) - (text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 88 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8))) - (text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 88 56)(line_width 1)) - ) - (port - (pt 232 24) - (output) - (text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8))) - (line (pt 232 24)(pt 152 24)(line_width 1)) - ) - (drawing - (text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8))) - (text "output" (rect 105 42 147 58)(font "Arial" (font_size 8))) - (text "power up" (rect 92 74 152 89)(font "Arial" )) - (text "low" (rect 92 84 114 99)(font "Arial" )) - (line (pt 88 16)(pt 152 16)(line_width 1)) - (line (pt 152 16)(pt 152 96)(line_width 1)) - (line (pt 152 96)(pt 88 96)(line_width 1)) - (line (pt 88 96)(pt 88 16)(line_width 1)) - ) -) -(symbol - (rect 2368 120 2400 152) - (text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical)) - (text "inst10" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible)) - (port - (pt 32 16) - (output) - (text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible)) - (text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible)) - (line (pt 24 16)(pt 32 16)(line_width 1)) - ) - (drawing - (line (pt 24 8)(pt 16 16)(line_width 1)) - (line (pt 16 16)(pt 24 24)(line_width 1)) - (line (pt 24 8)(pt 24 24)(line_width 1)) - ) - (rotate270) -) -(symbol - (rect 2408 144 2424 176) - (text "VCC" (rect 0 7 13 31)(font "Arial" (font_size 6))(vertical)) - (text "inst11" (rect 5 3 20 43)(font "Arial" )(vertical)(invisible)) - (port - (pt 16 16) - (output) - (text "1" (rect 19 7 27 23)(font "Courier New" (bold))(invisible)) - (text "1" (rect 7 19 23 27)(font "Courier New" (bold))(vertical)(invisible)) - (line (pt 16 16)(pt 8 16)(line_width 1)) - ) - (drawing - (line (pt 8 8)(pt 8 24)(line_width 1)) - ) - (flipy_rotate90) -) -(symbol - (rect 1800 1728 1848 1760) - (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) - (text "inst14" (rect 3 21 43 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 13 25)(pt 13 7)(line_width 1)) - (line (pt 13 7)(pt 31 16)(line_width 1)) - (line (pt 13 25)(pt 31 16)(line_width 1)) - (circle (rect 31 12 39 20)(line_width 1)) - ) -) -(symbol - (rect 1856 1752 1904 1784) - (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) - (text "inst15" (rect 3 21 43 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 13 25)(pt 13 7)(line_width 1)) - (line (pt 13 7)(pt 31 16)(line_width 1)) - (line (pt 13 25)(pt 31 16)(line_width 1)) - (circle (rect 31 12 39 20)(line_width 1)) - ) -) -(symbol - (rect 1800 1776 1848 1808) - (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) - (text "inst16" (rect 3 21 43 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 13 25)(pt 13 7)(line_width 1)) - (line (pt 13 7)(pt 31 16)(line_width 1)) - (line (pt 13 25)(pt 31 16)(line_width 1)) - (circle (rect 31 12 39 20)(line_width 1)) - ) -) -(symbol - (rect 1856 1800 1904 1832) - (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) - (text "inst17" (rect 3 21 43 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 13 25)(pt 13 7)(line_width 1)) - (line (pt 13 7)(pt 31 16)(line_width 1)) - (line (pt 13 25)(pt 31 16)(line_width 1)) - (circle (rect 31 12 39 20)(line_width 1)) - ) -) -(symbol - (rect 1800 1824 1848 1856) - (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) - (text "inst19" (rect 3 21 43 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 13 25)(pt 13 7)(line_width 1)) - (line (pt 13 7)(pt 31 16)(line_width 1)) - (line (pt 13 25)(pt 31 16)(line_width 1)) - (circle (rect 31 12 39 20)(line_width 1)) - ) -) -(symbol - (rect 448 -352 752 -104) - (text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10))) - (text "inst12" (rect 8 229 48 244)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 44 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 304 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 287 56 303 72)(font "Arial" (font_size 8))) - (line (pt 304 72)(pt 272 72)(line_width 1)) - ) - (port - (pt 304 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 287 80 303 96)(font "Arial" (font_size 8))) - (line (pt 304 96)(pt 272 96)(line_width 1)) - ) - (port - (pt 304 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 287 104 303 120)(font "Arial" (font_size 8))) - (line (pt 304 120)(pt 272 120)(line_width 1)) - ) - (port - (pt 304 144) - (output) - (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c3" (rect 287 128 303 144)(font "Arial" (font_size 8))) - (line (pt 304 144)(pt 272 144)(line_width 1)) - ) - (port - (pt 304 168) - (output) - (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c4" (rect 287 152 303 168)(font "Arial" (font_size 8))) - (line (pt 304 168)(pt 272 168)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 229 230 295 245)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 244 82)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 266 99)(font "Arial" )) - (text "Clk " (rect 59 111 83 126)(font "Arial" )) - (text "Ratio" (rect 85 111 119 126)(font "Arial" )) - (text "Ph (dg)" (rect 119 111 166 126)(font "Arial" )) - (text "DC (%)" (rect 164 111 211 126)(font "Arial" )) - (text "c0" (rect 63 129 78 144)(font "Arial" )) - (text "4/1" (rect 91 129 111 144)(font "Arial" )) - (text "240.00" (rect 120 129 164 144)(font "Arial" )) - (text "50.00" (rect 169 129 205 144)(font "Arial" )) - (text "c1" (rect 63 147 78 162)(font "Arial" )) - (text "4/1" (rect 91 147 111 162)(font "Arial" )) - (text "0.00" (rect 127 147 155 162)(font "Arial" )) - (text "50.00" (rect 169 147 205 162)(font "Arial" )) - (text "c2" (rect 63 165 78 180)(font "Arial" )) - (text "4/1" (rect 91 165 111 180)(font "Arial" )) - (text "180.00" (rect 120 165 164 180)(font "Arial" )) - (text "50.00" (rect 169 165 205 180)(font "Arial" )) - (text "c3" (rect 63 183 78 198)(font "Arial" )) - (text "4/1" (rect 91 183 111 198)(font "Arial" )) - (text "105.00" (rect 120 183 164 198)(font "Arial" )) - (text "50.00" (rect 169 183 205 198)(font "Arial" )) - (text "c4" (rect 63 201 78 216)(font "Arial" )) - (text "2/1" (rect 91 201 111 216)(font "Arial" )) - (text "270.00" (rect 120 201 164 216)(font "Arial" )) - (text "50.00" (rect 169 201 205 216)(font "Arial" )) - (line (pt 0 0)(pt 305 0)(line_width 1)) - (line (pt 305 0)(pt 305 249)(line_width 1)) - (line (pt 0 249)(pt 305 249)(line_width 1)) - (line (pt 0 0)(pt 0 249)(line_width 1)) - (line (pt 56 108)(pt 206 108)(line_width 1)) - (line (pt 56 125)(pt 206 125)(line_width 1)) - (line (pt 56 143)(pt 206 143)(line_width 1)) - (line (pt 56 161)(pt 206 161)(line_width 1)) - (line (pt 56 179)(pt 206 179)(line_width 1)) - (line (pt 56 197)(pt 206 197)(line_width 1)) - (line (pt 56 215)(pt 206 215)(line_width 1)) - (line (pt 56 108)(pt 56 215)(line_width 1)) - (line (pt 82 108)(pt 82 215)(line_width 3)) - (line (pt 116 108)(pt 116 215)(line_width 3)) - (line (pt 161 108)(pt 161 215)(line_width 3)) - (line (pt 205 108)(pt 205 215)(line_width 1)) - (line (pt 48 56)(pt 272 56)(line_width 1)) - (line (pt 272 56)(pt 272 232)(line_width 1)) - (line (pt 48 232)(pt 272 232)(line_width 1)) - (line (pt 48 56)(pt 48 232)(line_width 1)) - ) -) -(symbol - (rect -16 680 32 712) - (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) - (text "inst23" (rect 3 21 43 36)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)(line_width 1)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)(line_width 1)) - ) - (drawing - (line (pt 13 25)(pt 13 7)(line_width 1)) - (line (pt 13 7)(pt 31 16)(line_width 1)) - (line (pt 13 25)(pt 31 16)(line_width 1)) - (circle (rect 31 12 39 20)(line_width 1)) - ) -) -(symbol - (rect 192 472 408 768) - (text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10))) - (text "inst7" (rect 8 277 39 292)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "reconfig" (rect 20 32 73 48)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 16 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8))) - (text "read_param" (rect 20 48 100 64)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8))) - (text "write_param" (rect 20 64 102 80)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8))) - (text "data_in[8..0]" (rect 20 88 104 104)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 3)) - ) - (port - (pt 0 112) - (input) - (text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8))) - (text "counter_type[3..0]" (rect 20 104 143 120)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 16 112)(line_width 3)) - ) - (port - (pt 0 128) - (input) - (text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8))) - (text "counter_param[2..0]" (rect 20 120 156 136)(font "Arial" (font_size 8))) - (line (pt 0 128)(pt 16 128)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8))) - (text "pll_scandataout" (rect 20 160 127 176)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 16 168)(line_width 1)) - ) - (port - (pt 0 184) - (input) - (text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8))) - (text "pll_scandone" (rect 20 176 109 192)(font "Arial" (font_size 8))) - (line (pt 0 184)(pt 16 184)(line_width 1)) - ) - (port - (pt 0 208) - (input) - (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clock" (rect 20 200 56 216)(font "Arial" (font_size 8))) - (line (pt 0 208)(pt 16 208)(line_width 1)) - ) - (port - (pt 0 224) - (input) - (text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8))) - (text "reset" (rect 20 216 54 232)(font "Arial" (font_size 8))) - (line (pt 0 224)(pt 16 224)(line_width 1)) - ) - (port - (pt 0 248) - (input) - (text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8))) - (text "pll_areset_in" (rect 20 240 106 256)(font "Arial" (font_size 8))) - (line (pt 0 248)(pt 16 248)(line_width 1)) - ) - (port - (pt 216 40) - (output) - (text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8))) - (text "busy" (rect 169 32 202 48)(font "Arial" (font_size 8))) - (line (pt 216 40)(pt 200 40)(line_width 1)) - ) - (port - (pt 216 96) - (output) - (text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8))) - (text "data_out[8..0]" (rect 117 88 211 104)(font "Arial" (font_size 8))) - (line (pt 216 96)(pt 200 96)(line_width 3)) - ) - (port - (pt 216 152) - (output) - (text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8))) - (text "pll_scandata" (rect 124 144 210 160)(font "Arial" (font_size 8))) - (line (pt 216 152)(pt 200 152)(line_width 1)) - ) - (port - (pt 216 168) - (output) - (text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8))) - (text "pll_scanclk" (rect 132 160 208 176)(font "Arial" (font_size 8))) - (line (pt 216 168)(pt 200 168)(line_width 1)) - ) - (port - (pt 216 200) - (output) - (text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8))) - (text "pll_scanclkena" (rect 111 192 212 208)(font "Arial" (font_size 8))) - (line (pt 216 200)(pt 200 200)(line_width 1)) - ) - (port - (pt 216 216) - (output) - (text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8))) - (text "pll_configupdate" (rect 104 208 213 224)(font "Arial" (font_size 8))) - (line (pt 216 216)(pt 200 216)(line_width 1)) - ) - (port - (pt 216 248) - (output) - (text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8))) - (text "pll_areset" (rect 141 240 207 256)(font "Arial" (font_size 8))) - (line (pt 216 248)(pt 200 248)(line_width 1)) - ) - (drawing - (line (pt 0 0)(pt 217 0)(line_width 1)) - (line (pt 217 0)(pt 217 297)(line_width 1)) - (line (pt 0 297)(pt 217 297)(line_width 1)) - (line (pt 0 0)(pt 0 297)(line_width 1)) - (line (pt 16 24)(pt 201 24)(line_width 1)) - (line (pt 201 24)(pt 201 273)(line_width 1)) - (line (pt 16 273)(pt 201 273)(line_width 1)) - (line (pt 16 24)(pt 16 273)(line_width 1)) - ) -) -(symbol - (rect 608 496 984 728) - (text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) - (text "inst22" (rect 8 213 48 228)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 44 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 88 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) - (text "areset" (rect 4 80 46 96)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 88 96)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "scanclk" (rect 4 104 57 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 88 120)(line_width 1)) - ) - (port - (pt 0 144) - (input) - (text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) - (text "scandata" (rect 4 128 66 144)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 88 144)(line_width 1)) - ) - (port - (pt 0 168) - (input) - (text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8))) - (text "scanclkena" (rect 4 152 81 168)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 88 168)(line_width 1)) - ) - (port - (pt 0 192) - (input) - (text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8))) - (text "configupdate" (rect 4 176 90 192)(font "Arial" (font_size 8))) - (line (pt 0 192)(pt 88 192)(line_width 1)) - ) - (port - (pt 376 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 359 56 375 72)(font "Arial" (font_size 8))) - (line (pt 376 72)(pt 288 72)(line_width 1)) - ) - (port - (pt 376 96) - (output) - (text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) - (text "scandataout" (rect 302 80 385 96)(font "Arial" (font_size 8))) - (line (pt 376 96)(pt 288 96)(line_width 1)) - ) - (port - (pt 376 120) - (output) - (text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) - (text "scandone" (rect 317 104 383 120)(font "Arial" (font_size 8))) - (line (pt 376 120)(pt 288 120)(line_width 1)) - ) - (port - (pt 376 144) - (output) - (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) - (text "locked" (rect 335 128 379 144)(font "Arial" (font_size 8))) - (line (pt 376 144)(pt 288 144)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 301 214 367 229)(font "Arial" )) - (text "inclk0 frequency: 48.000 MHz" (rect 98 123 284 138)(font "Arial" )) - (text "Operation Mode: Normal" (rect 98 140 256 155)(font "Arial" )) - (text "Clk " (rect 99 167 123 182)(font "Arial" )) - (text "Ratio" (rect 125 167 159 182)(font "Arial" )) - (text "Ph (dg)" (rect 159 167 206 182)(font "Arial" )) - (text "DC (%)" (rect 204 167 251 182)(font "Arial" )) - (text "c0" (rect 103 185 118 200)(font "Arial" )) - (text "2/1" (rect 131 185 151 200)(font "Arial" )) - (text "0.00" (rect 167 185 195 200)(font "Arial" )) - (text "50.00" (rect 209 185 245 200)(font "Arial" )) - (line (pt 0 0)(pt 377 0)(line_width 1)) - (line (pt 377 0)(pt 377 233)(line_width 1)) - (line (pt 0 233)(pt 377 233)(line_width 1)) - (line (pt 0 0)(pt 0 233)(line_width 1)) - (line (pt 96 164)(pt 246 164)(line_width 1)) - (line (pt 96 181)(pt 246 181)(line_width 1)) - (line (pt 96 199)(pt 246 199)(line_width 1)) - (line (pt 96 164)(pt 96 199)(line_width 1)) - (line (pt 122 164)(pt 122 199)(line_width 3)) - (line (pt 156 164)(pt 156 199)(line_width 3)) - (line (pt 201 164)(pt 201 199)(line_width 3)) - (line (pt 245 164)(pt 245 199)(line_width 1)) - (line (pt 88 56)(pt 288 56)(line_width 1)) - (line (pt 288 56)(pt 288 216)(line_width 1)) - (line (pt 88 216)(pt 288 216)(line_width 1)) - (line (pt 88 56)(pt 88 216)(line_width 1)) - ) -) -(symbol - (rect 440 -88 744 144) - (text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10))) - (text "inst13" (rect 8 213 48 228)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 44 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 304 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 287 56 303 72)(font "Arial" (font_size 8))) - (line (pt 304 72)(pt 272 72)(line_width 1)) - ) - (port - (pt 304 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 287 80 303 96)(font "Arial" (font_size 8))) - (line (pt 304 96)(pt 272 96)(line_width 1)) - ) - (port - (pt 304 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 287 104 303 120)(font "Arial" (font_size 8))) - (line (pt 304 120)(pt 272 120)(line_width 1)) - ) - (port - (pt 304 144) - (output) - (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c3" (rect 287 128 303 144)(font "Arial" (font_size 8))) - (line (pt 304 144)(pt 272 144)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 229 214 295 229)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 244 82)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 266 99)(font "Arial" )) - (text "Clk " (rect 59 111 83 126)(font "Arial" )) - (text "Ratio" (rect 86 111 120 126)(font "Arial" )) - (text "Ph (dg)" (rect 121 111 168 126)(font "Arial" )) - (text "DC (%)" (rect 166 111 213 126)(font "Arial" )) - (text "c0" (rect 63 129 78 144)(font "Arial" )) - (text "2/33" (rect 88 129 116 144)(font "Arial" )) - (text "0.00" (rect 129 129 157 144)(font "Arial" )) - (text "50.00" (rect 171 129 207 144)(font "Arial" )) - (text "c1" (rect 63 147 78 162)(font "Arial" )) - (text "16/33" (rect 85 147 121 162)(font "Arial" )) - (text "0.00" (rect 129 147 157 162)(font "Arial" )) - (text "50.00" (rect 171 147 207 162)(font "Arial" )) - (text "c2" (rect 63 165 78 180)(font "Arial" )) - (text "25/33" (rect 85 165 121 180)(font "Arial" )) - (text "0.00" (rect 129 165 157 180)(font "Arial" )) - (text "50.00" (rect 171 165 207 180)(font "Arial" )) - (text "c3" (rect 63 183 78 198)(font "Arial" )) - (text "16/11" (rect 85 183 121 198)(font "Arial" )) - (text "0.00" (rect 129 183 157 198)(font "Arial" )) - (text "50.00" (rect 171 183 207 198)(font "Arial" )) - (line (pt 0 0)(pt 305 0)(line_width 1)) - (line (pt 305 0)(pt 305 233)(line_width 1)) - (line (pt 0 233)(pt 305 233)(line_width 1)) - (line (pt 0 0)(pt 0 233)(line_width 1)) - (line (pt 56 108)(pt 208 108)(line_width 1)) - (line (pt 56 125)(pt 208 125)(line_width 1)) - (line (pt 56 143)(pt 208 143)(line_width 1)) - (line (pt 56 161)(pt 208 161)(line_width 1)) - (line (pt 56 179)(pt 208 179)(line_width 1)) - (line (pt 56 197)(pt 208 197)(line_width 1)) - (line (pt 56 108)(pt 56 197)(line_width 1)) - (line (pt 82 108)(pt 82 197)(line_width 3)) - (line (pt 118 108)(pt 118 197)(line_width 3)) - (line (pt 163 108)(pt 163 197)(line_width 3)) - (line (pt 207 108)(pt 207 197)(line_width 1)) - (line (pt 48 56)(pt 272 56)(line_width 1)) - (line (pt 272 56)(pt 272 216)(line_width 1)) - (line (pt 48 216)(pt 272 216)(line_width 1)) - (line (pt 48 56)(pt 48 216)(line_width 1)) - ) -) -(symbol - (rect 440 176 768 392) - (text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 197 31 212)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 44 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 328 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 311 56 327 72)(font "Arial" (font_size 8))) - (line (pt 328 72)(pt 272 72)(line_width 1)) - ) - (port - (pt 328 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 311 80 327 96)(font "Arial" (font_size 8))) - (line (pt 328 96)(pt 272 96)(line_width 1)) - ) - (port - (pt 328 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 311 104 327 120)(font "Arial" (font_size 8))) - (line (pt 328 120)(pt 272 120)(line_width 1)) - ) - (port - (pt 328 144) - (output) - (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) - (text "locked" (rect 287 128 331 144)(font "Arial" (font_size 8))) - (line (pt 328 144)(pt 272 144)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 253 198 319 213)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 244 82)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 266 99)(font "Arial" )) - (text "Clk " (rect 59 111 83 126)(font "Arial" )) - (text "Ratio" (rect 90 111 124 126)(font "Arial" )) - (text "Ph (dg)" (rect 128 111 175 126)(font "Arial" )) - (text "DC (%)" (rect 173 111 220 126)(font "Arial" )) - (text "c0" (rect 63 129 78 144)(font "Arial" )) - (text "1/66" (rect 92 129 120 144)(font "Arial" )) - (text "0.00" (rect 136 129 164 144)(font "Arial" )) - (text "50.00" (rect 178 129 214 144)(font "Arial" )) - (text "c1" (rect 63 147 78 162)(font "Arial" )) - (text "67/900" (rect 85 147 129 162)(font "Arial" )) - (text "0.00" (rect 136 147 164 162)(font "Arial" )) - (text "50.00" (rect 178 147 214 162)(font "Arial" )) - (text "c2" (rect 63 165 78 180)(font "Arial" )) - (text "67/90" (rect 89 165 125 180)(font "Arial" )) - (text "0.00" (rect 136 165 164 180)(font "Arial" )) - (text "50.00" (rect 178 165 214 180)(font "Arial" )) - (line (pt 0 0)(pt 329 0)(line_width 1)) - (line (pt 329 0)(pt 329 217)(line_width 1)) - (line (pt 0 217)(pt 329 217)(line_width 1)) - (line (pt 0 0)(pt 0 217)(line_width 1)) - (line (pt 56 108)(pt 215 108)(line_width 1)) - (line (pt 56 125)(pt 215 125)(line_width 1)) - (line (pt 56 143)(pt 215 143)(line_width 1)) - (line (pt 56 161)(pt 215 161)(line_width 1)) - (line (pt 56 179)(pt 215 179)(line_width 1)) - (line (pt 56 108)(pt 56 179)(line_width 1)) - (line (pt 82 108)(pt 82 179)(line_width 3)) - (line (pt 125 108)(pt 125 179)(line_width 3)) - (line (pt 170 108)(pt 170 179)(line_width 3)) - (line (pt 214 108)(pt 214 179)(line_width 1)) - (line (pt 48 56)(pt 272 56)(line_width 1)) - (line (pt 272 56)(pt 272 200)(line_width 1)) - (line (pt 48 200)(pt 272 200)(line_width 1)) - (line (pt 48 56)(pt 48 200)(line_width 1)) - ) -) -(symbol - (rect 944 416 1008 464) - (text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6))) - (text "inst25" (rect 3 37 43 52)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible)) - (text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 14 16)(line_width 1)) - ) - (port - (pt 0 32) - (input) - (text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible)) - (text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible)) - (line (pt 0 32)(pt 14 32)(line_width 1)) - ) - (port - (pt 64 24) - (output) - (text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible)) - (line (pt 42 24)(pt 64 24)(line_width 1)) - ) - (drawing - (line (pt 14 12)(pt 30 12)(line_width 1)) - (line (pt 14 37)(pt 31 37)(line_width 1)) - (line (pt 14 12)(pt 14 37)(line_width 1)) - (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1)) - ) -) -(block - (rect 1264 2944 1672 3560) - (text "DSP" (rect 5 5 36 21)(font "Arial" (font_size 8))) (text "Mathias_Alles" (rect 5 602 95 617)(font "Arial" )) (block_io "CLK33M" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "nFB_OE" (input)) - (block_io "nFB_WR" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "nRSTO" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nSRCS" (output)) - (block_io "nSRBLE" (output)) - (block_io "nSRBHE" (output)) - (block_io "nSRWE" (output)) - (block_io "nSROE" (output)) - (block_io "DSP_INT" (output)) - (block_io "DSP_TA" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "IO[17..0]" (bidir)) - (block_io "SRD[15..0]" (bidir)) - (mapper - (pt 408 416) - (bidir) - ) - (mapper - (pt 408 392) - (bidir) - ) - (mapper - (pt 408 368) - (bidir) - ) - (mapper - (pt 408 320) - (bidir) - ) - (mapper - (pt 408 440) - (bidir) - ) - (mapper - (pt 408 344) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 408 40) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 408 576) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) -) -(block - (rect 1264 2344 1672 2904) - (text "interrupt_handler" (rect 5 5 118 21)(font "Arial" (font_size 8))) (text "nobody" (rect 5 546 52 561)(font "Arial" )) (block_io "MAIN_CLK" (input)) - (block_io "nFB_WR" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "PIC_INT" (input)) - (block_io "E0_INT" (input)) - (block_io "DVI_INT" (input)) - (block_io "nPCI_INTA" (input)) - (block_io "nPCI_INTB" (input)) - (block_io "nPCI_INTC" (input)) - (block_io "nPCI_INTD" (input)) - (block_io "nMFP_INT" (input)) - (block_io "nFB_OE" (input)) - (block_io "DSP_INT" (input)) - (block_io "VSYNC" (input)) - (block_io "HSYNC" (input)) - (block_io "DMA_DRQ" (input)) - (block_io "nIRQ[7..2]" (output)) - (block_io "INT_HANDLER_TA" (output)) - (block_io "ACP_CONF[31..0]" (output)) - (block_io "TIN0" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (mapper - (pt 0 136) - (bidir) - ) - (mapper - (pt 0 160) - (bidir) - ) - (mapper - (pt 0 184) - (bidir) - ) - (mapper - (pt 0 88) - (bidir) - ) - (mapper - (pt 0 112) - (bidir) - ) - (mapper - (pt 0 40) - (bidir) - ) - (mapper - (pt 408 56) - (bidir) - ) - (mapper - (pt 408 80) - (bidir) - ) - (mapper - (pt 0 256) - (bidir) - ) - (mapper - (pt 0 280) - (bidir) - ) - (mapper - (pt 0 304) - (bidir) - ) - (mapper - (pt 0 208) - (bidir) - ) - (mapper - (pt 0 64) - (bidir) - ) - (mapper - (pt 0 376) - (bidir) - ) - (mapper - (pt 0 400) - (bidir) - ) - (mapper - (pt 0 328) - (bidir) - ) - (mapper - (pt 0 352) - (bidir) - ) - (mapper - (pt 0 432) - (bidir) - ) - (mapper - (pt 0 456) - (bidir) - ) - (mapper - (pt 0 480) - (bidir) - ) - (mapper - (pt 0 504) - (bidir) - ) - (mapper - (pt 408 504) - (bidir) - ) - (mapper - (pt 0 528) - (bidir) - ) - (mapper - (pt 408 240) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) -) -(block - (rect 1264 744 1672 2264) - (text "FalconIO_SDCard_IDE_CF" (rect 5 5 189 21)(font "Arial" (font_size 8))) (text "Wolfgang_Foerster_and_Fredi_Aschwanden" (rect 5 1506 295 1521)(font "Arial" )) (block_io "CLK33M" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "CLK2M" (input)) - (block_io "CLK500k" (input)) - (block_io "nFB_CS1" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "LP_BUSY" (input)) - (block_io "nACSI_DRQ" (input)) - (block_io "nACSI_INT" (input)) - (block_io "nSCSI_DRQ" (input)) - (block_io "nSCSI_MSG" (input)) - (block_io "MIDI_IN" (input)) - (block_io "RxD" (input)) - (block_io "CTS" (input)) - (block_io "RI" (input)) - (block_io "DCD" (input)) - (block_io "AMKB_RX" (input)) - (block_io "PIC_AMKB_RX" (input)) - (block_io "IDE_RDY" (input)) - (block_io "IDE_INT" (input)) - (block_io "WP_CS_CARD" (input)) - (block_io "nINDEX" (input)) - (block_io "TRACK00" (input)) - (block_io "nRD_DATA" (input)) - (block_io "nDCHG" (input)) - (block_io "SD_DATA0" (input)) - (block_io "SD_DATA1" (input)) - (block_io "SD_DATA2" (input)) - (block_io "SD_CARD_DEDECT" (input)) - (block_io "SD_WP" (input)) - (block_io "nDACK0" (input)) - (block_io "nFB_WR" (input)) - (block_io "WP_CF_CARD" (input)) - (block_io "nWP" (input)) - (block_io "nFB_CS2" (input)) - (block_io "nRSTO" (input)) - (block_io "nSCSI_C_D" (input)) - (block_io "nSCSI_I_O" (input)) - (block_io "CLK2M4576" (input)) - (block_io "nFB_OE" (input)) - (block_io "VSYNC" (input)) - (block_io "HSYNC" (input)) - (block_io "DSP_INT" (input)) - (block_io "nBLANK" (input)) - (block_io "FDC_CLK" (input)) - (block_io "FB_ALE" (input)) - (block_io "ACP_CONF[31..24]" (input)) - (block_io "HD_DD" (input)) - (block_io "nIDE_CS1" (output)) - (block_io "nIDE_CS0" (output)) - (block_io "LP_STR" (output)) - (block_io "LP_DIR" (output)) - (block_io "nACSI_ACK" (output)) - (block_io "nACSI_RESET" (output)) - (block_io "nACSI_CS" (output)) - (block_io "ACSI_DIR" (output)) - (block_io "ACSI_A1" (output)) - (block_io "nSCSI_ACK" (output)) - (block_io "nSCSI_ATN" (output)) - (block_io "SCSI_DIR" (output)) - (block_io "SD_CLK" (output)) - (block_io "YM_QA" (output)) - (block_io "YM_QC" (output)) - (block_io "YM_QB" (output)) - (block_io "nSDSEL" (output)) - (block_io "STEP" (output)) - (block_io "MOT_ON" (output)) - (block_io "nRP_LDS" (output)) - (block_io "nRP_UDS" (output)) - (block_io "nROM4" (output)) - (block_io "nROM3" (output)) - (block_io "nCF_CS1" (output)) - (block_io "nCF_CS0" (output)) - (block_io "nIDE_RD" (output)) - (block_io "nIDE_WR" (output)) - (block_io "AMKB_TX" (output)) - (block_io "IDE_RES" (output)) - (block_io "DTR" (output)) - (block_io "RTS" (output)) - (block_io "TxD" (output)) - (block_io "MIDI_OLR" (output)) - (block_io "MIDI_TLR" (output)) - (block_io "nDREQ0" (output)) - (block_io "DSA_D" (output)) - (block_io "nMFP_INT" (output)) - (block_io "FALCON_IO_TA" (output)) - (block_io "STEP_DIR" (output)) - (block_io "WR_DATA" (output)) - (block_io "WR_GATE" (output)) - (block_io "DMA_DRQ" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "LP_D[7..0]" (bidir)) - (block_io "ACSI_D[7..0]" (bidir)) - (block_io "SCSI_D[7..0]" (bidir)) - (block_io "SCSI_PAR" (bidir)) - (block_io "nSCSI_SEL" (bidir)) - (block_io "nSCSI_BUSY" (bidir)) - (block_io "nSCSI_RST" (bidir)) - (block_io "SD_CD_DATA3" (bidir)) - (block_io "SD_CDM_D1" (bidir)) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 408 96) - (bidir) - ) - (mapper - (pt 408 120) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 408 152) - (bidir) - ) - (mapper - (pt 408 200) - (bidir) - ) - (mapper - (pt 408 224) - (bidir) - ) - (mapper - (pt 408 248) - (bidir) - ) - (mapper - (pt 408 272) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 408 424) - (bidir) - ) - (mapper - (pt 408 352) - (bidir) - ) - (mapper - (pt 408 328) - (bidir) - ) - (mapper - (pt 408 448) - (bidir) - ) - (mapper - (pt 408 400) - (bidir) - ) - (mapper - (pt 408 376) - (bidir) - ) - (mapper - (pt 408 472) - (bidir) - ) - (mapper - (pt 408 496) - (bidir) - ) - (mapper - (pt 408 608) - (bidir) - ) - (mapper - (pt 408 632) - (bidir) - ) - (mapper - (pt 408 528) - (bidir) - ) - (mapper - (pt 408 552) - (bidir) - ) - (mapper - (pt 408 584) - (bidir) - ) - (mapper - (pt 0 624) - (bidir) - ) - (mapper - (pt 0 656) - (bidir) - ) - (mapper - (pt 0 680) - (bidir) - ) - (mapper - (pt 0 704) - (bidir) - ) - (mapper - (pt 0 728) - (bidir) - ) - (mapper - (pt 0 752) - (bidir) - ) - (mapper - (pt 0 776) - (bidir) - ) - (mapper - (pt 408 664) - (bidir) - ) - (mapper - (pt 0 808) - (bidir) - ) - (mapper - (pt 0 832) - (bidir) - ) - (mapper - (pt 408 696) - (bidir) - ) - (mapper - (pt 408 720) - (bidir) - ) - (mapper - (pt 408 744) - (bidir) - ) - (mapper - (pt 408 768) - (bidir) - ) - (mapper - (pt 408 792) - (bidir) - ) - (mapper - (pt 408 816) - (bidir) - ) - (mapper - (pt 408 840) - (bidir) - ) - (mapper - (pt 0 856) - (bidir) - ) - (mapper - (pt 408 872) - (bidir) - ) - (mapper - (pt 408 896) - (bidir) - ) - (mapper - (pt 408 920) - (bidir) - ) - (mapper - (pt 408 944) - (bidir) - ) - (mapper - (pt 0 912) - (bidir) - ) - (mapper - (pt 0 936) - (bidir) - ) - (mapper - (pt 0 960) - (bidir) - ) - (mapper - (pt 0 984) - (bidir) - ) - (mapper - (pt 0 1008) - (bidir) - ) - (mapper - (pt 408 976) - (bidir) - ) - (mapper - (pt 408 1000) - (bidir) - ) - (mapper - (pt 408 1072) - (bidir) - ) - (mapper - (pt 408 1096) - (bidir) - ) - (mapper - (pt 408 1176) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 1256) - (bidir) - ) - (mapper - (pt 0 1040) - (bidir) - ) - (mapper - (pt 0 1064) - (bidir) - ) - (mapper - (pt 0 1088) - (bidir) - ) - (mapper - (pt 0 1112) - (bidir) - ) - (mapper - (pt 0 1136) - (bidir) - ) - (mapper - (pt 0 432) - (bidir) - ) - (mapper - (pt 0 464) - (bidir) - ) - (mapper - (pt 0 488) - (bidir) - ) - (mapper - (pt 0 520) - (bidir) - ) - (mapper - (pt 0 544) - (bidir) - ) - (mapper - (pt 0 568) - (bidir) - ) - (mapper - (pt 0 592) - (bidir) - ) - (mapper - (pt 408 1424) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) - (mapper - (pt 0 344) - (bidir) - ) - (mapper - (pt 0 1168) - (bidir) - ) - (mapper - (pt 0 1192) - (bidir) - ) - (mapper - (pt 0 368) - (bidir) - ) - (mapper - (pt 0 392) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 1216) - (bidir) - ) - (mapper - (pt 408 48) - (bidir) - ) - (mapper - (pt 408 16) - (bidir) - ) - (mapper - (pt 0 1240) - (bidir) - ) - (mapper - (pt 408 1304) - (bidir) - ) - (mapper - (pt 408 1200) - (bidir) - ) - (mapper - (pt 408 1344) - (bidir) - ) - (mapper - (pt 408 1280) - (bidir) - ) - (mapper - (pt 408 1224) - (bidir) - ) - (mapper - (pt 408 1120) - (bidir) - ) - (mapper - (pt 408 1048) - (bidir) - ) - (mapper - (pt 408 1024) - (bidir) - ) - (mapper - (pt 0 32) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 408 1368) - (bidir) - ) - (mapper - (pt 0 1264) - (bidir) - ) - (mapper - (pt 0 1336) - (bidir) - ) - (mapper - (pt 0 888) - (bidir) - ) -) -(block - (rect 1264 -48 1672 728) - (text "Video" (rect 5 5 43 21)(font "Arial" (font_size 8))) (text "Fredi_Aschwanden" (rect 5 762 130 777)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nFB_WR" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nRSTO" (input)) - (block_io "nFB_OE" (input)) - (block_io "FB_ALE" (input)) - (block_io "DDRCLK[3..0]" (input)) - (block_io "DDR_SYNC_66M" (input)) - (block_io "CLK33M" (input)) - (block_io "CLK25M" (input)) - (block_io "CLK_VIDEO" (input)) - (block_io "VR_D[8..0]" (input)) - (block_io "VR_BUSY" (input)) - (block_io "VR_RD" (output)) - (block_io "VG[7..0]" (output)) - (block_io "VB[7..0]" (output)) - (block_io "VR[7..0]" (output)) - (block_io "nBLANK" (output)) - (block_io "VA[12..0]" (output)) - (block_io "nVWE" (output)) - (block_io "nVCAS" (output)) - (block_io "nVRAS" (output)) - (block_io "nVCS" (output)) - (block_io "VDM[3..0]" (output)) - (block_io "nPD_VGA" (output)) - (block_io "VCKE" (output)) - (block_io "VSYNC" (output)) - (block_io "HSYNC" (output)) - (block_io "nSYNC" (output)) - (block_io "VIDEO_TA" (output)) - (block_io "PIXEL_CLK" (output)) - (block_io "BA[1..0]" (output)) - (block_io "VIDEO_RECONFIG" (output)) - (block_io "VR_WR" (output)) - (block_io "VDQS[3..0]" (bidir)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "VD[31..0]" (bidir)) - (mapper - (pt 408 448) - (bidir) - ) - (mapper - (pt 408 496) - (bidir) - ) - (mapper - (pt 408 592) - (bidir) - ) - (mapper - (pt 408 352) - (bidir) - ) - (mapper - (pt 408 760) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 0 392) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 344) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 128) - (bidir) - ) - (mapper - (pt 408 152) - (bidir) - ) - (mapper - (pt 408 176) - (bidir) - ) - (mapper - (pt 408 200) - (bidir) - ) - (mapper - (pt 408 224) - (bidir) - ) - (mapper - (pt 408 248) - (bidir) - ) - (mapper - (pt 408 272) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 0 416) - (bidir) - ) - (mapper - (pt 408 320) - (bidir) - ) - (mapper - (pt 408 472) - (bidir) - ) - (mapper - (pt 408 424) - (bidir) - ) - (mapper - (pt 408 400) - (bidir) - ) - (mapper - (pt 408 376) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 368) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 408 568) - (bidir) - ) - (mapper - (pt 408 520) - (bidir) - ) - (mapper - (pt 0 648) - (bidir) - ) - (mapper - (pt 0 672) - (bidir) - ) - (mapper - (pt 0 616) - (bidir) - ) - (mapper - (pt 0 528) - (bidir) - ) - (mapper - (pt 408 656) - (bidir) - ) - (mapper - (pt 408 640) - (bidir) - ) - (mapper - (pt 408 624) - (bidir) - ) - (mapper - (pt 0 512) - (bidir) - ) -) -(connector - (text "FB_AD[31..0]" (rect 1682 776 1765 791)(font "Arial" )) - (pt 1832 792) - (pt 1672 792) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 1072 1240 1087)(font "Arial" )) - (pt 1112 1088) - (pt 1264 1088) - (bus) -) -(connector - (text "MAIN_CLK" (rect 1162 784 1231 799)(font "Arial" )) - (pt 1152 800) - (pt 1264 800) -) -(connector - (text "CLK33M" (rect 1210 760 1265 775)(font "Arial" )) - (pt 1200 776) - (pt 1264 776) -) -(connector - (text "CLK2M" (rect 1202 808 1249 823)(font "Arial" )) - (pt 1192 824) - (pt 1264 824) -) -(connector - (text "CLK500k" (rect 1202 832 1262 847)(font "Arial" )) - (pt 1192 848) - (pt 1264 848) -) -(connector - (text "LP_DIR" (rect 1682 848 1732 863)(font "Arial" )) - (pt 1672 864) - (pt 1832 864) -) -(connector - (text "LP_STR" (rect 1682 824 1736 839)(font "Arial" )) - (pt 1672 840) - (pt 1832 840) -) -(connector - (text "nACSI_ACK" (rect 1682 928 1758 943)(font "Arial" )) - (pt 1672 944) - (pt 1832 944) -) -(connector - (text "nACSI_RESET" (rect 1682 952 1777 967)(font "Arial" )) - (pt 1672 968) - (pt 1832 968) -) -(connector - (text "nACSI_CS" (rect 1682 976 1750 991)(font "Arial" )) - (pt 1672 992) - (pt 1832 992) -) -(connector - (text "ACSI_DIR" (rect 1682 1000 1746 1015)(font "Arial" )) - (pt 1672 1016) - (pt 1832 1016) -) -(connector - (text "ACSI_A1" (rect 1682 1024 1738 1039)(font "Arial" )) - (pt 1672 1040) - (pt 1832 1040) -) -(connector - (text "nSCSI_ATN" (rect 1682 1128 1758 1143)(font "Arial" )) - (pt 1672 1144) - (pt 1840 1144) -) -(connector - (text "SCSI_DIR" (rect 1682 1152 1748 1167)(font "Arial" )) - (pt 1672 1168) - (pt 1840 1168) -) -(connector - (text "nSCSI_DRQ" (rect 1114 1248 1195 1263)(font "Arial" )) - (pt 1264 1264) - (pt 1104 1264) -) -(connector - (text "nSCSI_MSG" (rect 1114 1320 1194 1335)(font "Arial" )) - (pt 1104 1336) - (pt 1264 1336) -) -(connector - (text "nSCSI_RST" (rect 1682 1176 1759 1191)(font "Arial" )) - (pt 1672 1192) - (pt 1840 1192) -) -(connector - (text "nSCSI_SEL" (rect 1680 1200 1756 1215)(font "Arial" )) - (pt 1672 1216) - (pt 1840 1216) -) -(connector - (text "nSCSI_BUSY" (rect 1682 1224 1769 1239)(font "Arial" )) - (pt 1672 1240) - (pt 1840 1240) -) -(connector - (text "TxD" (rect 1682 1312 1706 1327)(font "Arial" )) - (pt 1672 1328) - (pt 1840 1328) -) -(connector - (text "RTS" (rect 1682 1336 1710 1351)(font "Arial" )) - (pt 1672 1352) - (pt 1840 1352) -) -(connector - (text "DTR" (rect 1680 1360 1709 1375)(font "Arial" )) - (pt 1672 1376) - (pt 1848 1376) -) -(connector - (text "CTS" (rect 1114 1408 1142 1423)(font "Arial" )) - (pt 1104 1424) - (pt 1264 1424) -) -(connector - (text "RI" (rect 1114 1432 1128 1447)(font "Arial" )) - (pt 1104 1448) - (pt 1264 1448) -) -(connector - (text "DCD" (rect 1114 1456 1145 1471)(font "Arial" )) - (pt 1104 1472) - (pt 1264 1472) -) -(connector - (text "IDE_RDY" (rect 1114 1536 1175 1551)(font "Arial" )) - (pt 1264 1552) - (pt 1104 1552) -) -(connector - (text "IDE_INT" (rect 1114 1560 1168 1575)(font "Arial" )) - (pt 1104 1576) - (pt 1264 1576) -) -(connector - (text "IDE_RES" (rect 1682 1424 1743 1439)(font "Arial" )) - (pt 1672 1440) - (pt 1848 1440) -) -(connector - (text "nIDE_CS0" (rect 1682 1448 1750 1463)(font "Arial" )) - (pt 1672 1464) - (pt 1848 1464) -) -(connector - (text "nIDE_CS1" (rect 1682 1472 1750 1487)(font "Arial" )) - (pt 1672 1488) - (pt 1856 1488) -) -(connector - (text "nIDE_WR" (rect 1682 1496 1745 1511)(font "Arial" )) - (pt 1672 1512) - (pt 1848 1512) -) -(connector - (text "nIDE_RD" (rect 1682 1520 1743 1535)(font "Arial" )) - (pt 1672 1536) - (pt 1848 1536) -) -(connector - (text "nCF_CS0" (rect 1682 1544 1745 1559)(font "Arial" )) - (pt 1672 1560) - (pt 1848 1560) -) -(connector - (text "nCF_CS1" (rect 1682 1568 1745 1583)(font "Arial" )) - (pt 1672 1584) - (pt 1848 1584) -) -(connector - (text "WP_CF_CARD" (rect 1112 1584 1209 1599)(font "Arial" )) - (pt 1104 1600) - (pt 1264 1600) -) -(connector - (text "nSDSEL" (rect 1682 1848 1737 1863)(font "Arial" )) - (pt 1672 1864) - (pt 1856 1864) -) -(connector - (text "nDREQ0" (rect 1682 2152 1739 2167)(font "Arial" )) - (pt 1672 2168) - (pt 1856 2168) -) -(connector - (text "SD_CLK" (rect 1682 2032 1738 2047)(font "Arial" )) - (pt 1856 2048) - (pt 1672 2048) -) -(connector - (text "SD_DATA0" (rect 1114 1768 1185 1783)(font "Arial" )) - (pt 1104 1784) - (pt 1264 1784) -) -(connector - (text "SD_DATA1" (rect 1114 1792 1185 1807)(font "Arial" )) - (pt 1104 1808) - (pt 1264 1808) -) -(connector - (text "SD_DATA2" (rect 1114 1816 1185 1831)(font "Arial" )) - (pt 1104 1832) - (pt 1264 1832) -) -(connector - (text "SD_WP" (rect 1114 1864 1164 1879)(font "Arial" )) - (pt 1104 1880) - (pt 1264 1880) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 2536 1240 2551)(font "Arial" )) - (pt 1112 2552) - (pt 1264 2552) - (bus) -) -(connector - (text "nFB_WR" (rect 1162 2416 1219 2431)(font "Arial" )) - (pt 1152 2432) - (pt 1264 2432) -) -(connector - (text "nFB_CS1" (rect 1154 2440 1216 2455)(font "Arial" )) - (pt 1152 2456) - (pt 1264 2456) -) -(connector - (text "FB_SIZE0" (rect 1154 2488 1218 2503)(font "Arial" )) - (pt 1152 2504) - (pt 1264 2504) -) -(connector - (text "FB_SIZE1" (rect 1154 2512 1218 2527)(font "Arial" )) - (pt 1152 2528) - (pt 1264 2528) -) -(connector - (text "MAIN_CLK" (rect 1162 2368 1231 2383)(font "Arial" )) - (pt 1152 2384) - (pt 1264 2384) -) -(connector - (text "nFB_CS2" (rect 1162 2464 1224 2479)(font "Arial" )) - (pt 1152 2480) - (pt 1264 2480) -) -(connector - (text "FB_AD[31..0]" (rect 1682 2384 1765 2399)(font "Arial" )) - (pt 1832 2400) - (pt 1672 2400) - (bus) -) -(connector - (text "nSCSI_ACK" (rect 1682 1104 1759 1119)(font "Arial" )) - (pt 1672 1120) - (pt 1840 1120) -) -(connector - (text "SCSI_PAR" (rect 1682 1080 1751 1095)(font "Arial" )) - (pt 1672 1096) - (pt 1840 1096) -) -(connector - (text "MIDI_OLR" (rect 1762 1256 1828 1271)(font "Arial" )) - (pt 1672 1272) - (pt 1920 1272) -) -(connector - (text "MIDI_TLR" (rect 1770 1280 1833 1295)(font "Arial" )) - (pt 1672 1296) - (pt 1920 1296) -) -(connector - (text "nROM3" (rect 1754 1600 1802 1615)(font "Arial" )) - (pt 1672 1616) - (pt 1920 1616) -) -(connector - (text "nROM4" (rect 1754 1624 1802 1639)(font "Arial" )) - (pt 1672 1640) - (pt 1920 1640) -) -(connector - (text "nRP_UDS" (rect 1744 1648 1811 1663)(font "Arial" )) - (pt 1672 1664) - (pt 1920 1664) -) -(connector - (text "nRP_LDS" (rect 1746 1672 1810 1687)(font "Arial" )) - (pt 1672 1688) - (pt 1920 1688) -) -(connector - (text "YM_QA" (rect 1762 1904 1808 1919)(font "Arial" )) - (pt 1672 1920) - (pt 1928 1920) -) -(connector - (text "YM_QB" (rect 1762 1928 1809 1943)(font "Arial" )) - (pt 1672 1944) - (pt 1928 1944) -) -(connector - (text "YM_QC" (rect 1762 1952 1810 1967)(font "Arial" )) - (pt 1672 1968) - (pt 1928 1968) -) -(connector - (text "LP_BUSY" (rect 1114 1160 1177 1175)(font "Arial" )) - (pt 1264 1176) - (pt 1104 1176) -) -(connector - (text "nACSI_DRQ" (rect 1034 1192 1114 1207)(font "Arial" )) - (pt 1024 1208) - (pt 1264 1208) -) -(connector - (text "nACSI_INT" (rect 1034 1216 1104 1231)(font "Arial" )) - (pt 1024 1232) - (pt 1264 1232) -) -(connector - (text "MIDI_IN" (rect 1050 1352 1100 1367)(font "Arial" )) - (pt 1040 1368) - (pt 1264 1368) -) -(connector - (text "RxD" (rect 1114 1384 1141 1399)(font "Arial" )) - (pt 1264 1400) - (pt 1104 1400) -) -(connector - (text "nINDEX" (rect 1050 1640 1100 1655)(font "Arial" )) - (pt 1040 1656) - (pt 1264 1656) -) -(connector - (text "TRACK00" (rect 1050 1664 1113 1679)(font "Arial" )) - (pt 1040 1680) - (pt 1264 1680) -) -(connector - (text "nWP" (rect 1050 1688 1080 1703)(font "Arial" )) - (pt 1040 1704) - (pt 1264 1704) -) -(connector - (text "nRD_DATA" (rect 1050 1712 1123 1727)(font "Arial" )) - (pt 1040 1728) - (pt 1264 1728) -) -(connector - (text "nDCHG" (rect 1050 1736 1100 1751)(font "Arial" )) - (pt 1040 1752) - (pt 1264 1752) -) -(connector - (text "SD_CARD_DEDECT" (rect 1138 1840 1273 1855)(font "Arial" )) - (pt 1264 1856) - (pt 1128 1856) -) -(connector - (text "SD_CD_DATA3" (rect 1682 1984 1783 1999)(font "Arial" )) - (pt 1672 2000) - (pt 1856 2000) -) -(connector - (text "SD_CDM_D1" (rect 1682 2008 1769 2023)(font "Arial" )) - (pt 1672 2024) - (pt 1856 2024) -) -(connector - (text "nSCSI_C_D" (rect 1114 1272 1193 1287)(font "Arial" )) - (pt 1104 1288) - (pt 1264 1288) -) -(connector - (text "nSCSI_I_O" (rect 1114 1296 1185 1311)(font "Arial" )) - (pt 1104 1312) - (pt 1264 1312) -) -(connector - (text "DSA_D" (rect 1682 1704 1729 1719)(font "Arial" )) - (pt 1672 1720) - (pt 1856 1720) -) -(connector - (text "FB_AD[31..0]" (rect 1682 8 1765 23)(font "Arial" )) - (pt 1832 24) - (pt 1672 24) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 328 1240 343)(font "Arial" )) - (pt 1112 344) - (pt 1264 344) - (bus) -) -(connector - (text "nFB_WR" (rect 1162 184 1219 199)(font "Arial" )) - (pt 1152 200) - (pt 1264 200) -) -(connector - (text "nFB_CS1" (rect 1154 208 1216 223)(font "Arial" )) - (pt 1152 224) - (pt 1264 224) -) -(connector - (text "FB_SIZE0" (rect 1154 256 1218 271)(font "Arial" )) - (pt 1152 272) - (pt 1264 272) -) -(connector - (text "FB_SIZE1" (rect 1154 280 1218 295)(font "Arial" )) - (pt 1152 296) - (pt 1264 296) -) -(connector - (text "nFB_CS2" (rect 1162 232 1224 247)(font "Arial" )) - (pt 1152 248) - (pt 1264 248) -) -(connector - (text "nBLANK" (rect 1682 184 1736 199)(font "Arial" )) - (pt 1672 200) - (pt 1832 200) -) -(connector - (text "nSYNC" (rect 1682 208 1729 223)(font "Arial" )) - (pt 1672 224) - (pt 1832 224) -) -(connector - (text "nFB_CS3" (rect 1186 352 1248 367)(font "Arial" )) - (pt 1264 368) - (pt 1176 368) -) -(connector - (text "nFB_WR" (rect 1170 928 1227 943)(font "Arial" )) - (pt 1264 944) - (pt 1160 944) -) -(connector - (text "nFB_CS1" (rect 1162 952 1224 967)(font "Arial" )) - (pt 1264 968) - (pt 1160 968) -) -(connector - (text "nFB_CS2" (rect 1170 976 1232 991)(font "Arial" )) - (pt 1264 992) - (pt 1160 992) -) -(connector - (text "FB_SIZE0" (rect 1162 1000 1226 1015)(font "Arial" )) - (pt 1264 1016) - (pt 1160 1016) -) -(connector - (text "FB_SIZE1" (rect 1162 1024 1226 1039)(font "Arial" )) - (pt 1264 1040) - (pt 1160 1040) -) -(connector - (text "nFB_BURST" (rect 1162 1048 1244 1063)(font "Arial" )) - (pt 1264 1064) - (pt 1160 1064) -) -(connector - (text "nDACK0" (rect 1250 1096 1305 1111)(font "Arial" )) - (pt 1264 1112) - (pt 1160 1112) -) -(connector - (text "nRSTO" (rect 1170 1120 1217 1135)(font "Arial" )) - (pt 1264 1136) - (pt 1160 1136) -) -(connector - (text "nPD_VGA" (rect 1682 256 1745 271)(font "Arial" )) - (pt 1672 272) - (pt 1832 272) -) -(connector - (text "PIC_INT" (rect 1162 2584 1216 2599)(font "Arial" )) - (pt 1152 2600) - (pt 1264 2600) -) -(connector - (text "nIRQ[7..2]" (rect 1682 2408 1745 2423)(font "Arial" )) - (pt 1672 2424) - (pt 1832 2424) - (bus) -) -(connector - (text "CLK2M4576" (rect 1202 856 1282 871)(font "Arial" )) - (pt 1192 872) - (pt 1264 872) -) -(connector - (text "nFB_OE" (rect 1170 904 1224 919)(font "Arial" )) - (pt 1264 920) - (pt 1160 920) -) -(connector - (text "nFB_OE" (rect 1170 160 1224 175)(font "Arial" )) - (pt 1264 176) - (pt 1160 176) -) -(connector - (text "nFB_OE" (rect 1170 2392 1224 2407)(font "Arial" )) - (pt 1264 2408) - (pt 1160 2408) -) -(connector - (text "DVI_INT" (rect 1162 2632 1215 2647)(font "Arial" )) - (pt 1152 2648) - (pt 1264 2648) -) -(connector - (text "nPCI_INTA" (rect 1162 2728 1232 2743)(font "Arial" )) - (pt 1152 2744) - (pt 1264 2744) -) -(connector - (text "nPCI_INTB" (rect 1162 2704 1233 2719)(font "Arial" )) - (pt 1152 2720) - (pt 1264 2720) -) -(connector - (text "nPCI_INTC" (rect 1162 2680 1235 2695)(font "Arial" )) - (pt 1152 2696) - (pt 1264 2696) -) -(connector - (text "nPCI_INTD" (rect 1162 2656 1235 2671)(font "Arial" )) - (pt 1152 2672) - (pt 1264 2672) -) -(connector - (text "nMFP_INT" (rect 1162 2760 1229 2775)(font "Arial" )) - (pt 1152 2776) - (pt 1264 2776) -) -(connector - (text "nMFP_INT" (rect 1682 2072 1749 2087)(font "Arial" )) - (pt 1672 2088) - (pt 1784 2088) -) -(connector - (text "E0_INT" (rect 1162 2608 1210 2623)(font "Arial" )) - (pt 1152 2624) - (pt 1264 2624) -) -(connector - (text "FB_AD[31..0]" (rect 1682 2968 1765 2983)(font "Arial" )) - (pt 1832 2984) - (pt 1672 2984) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 3224 1240 3239)(font "Arial" )) - (pt 1112 3240) - (pt 1264 3240) - (bus) -) -(connector - (text "MAIN_CLK" (rect 1162 3008 1231 3023)(font "Arial" )) - (pt 1152 3024) - (pt 1264 3024) -) -(connector - (text "CLK33M" (rect 1210 2984 1265 2999)(font "Arial" )) - (pt 1200 3000) - (pt 1264 3000) -) -(connector - (text "nFB_WR" (rect 1170 3056 1227 3071)(font "Arial" )) - (pt 1264 3072) - (pt 1160 3072) -) -(connector - (text "nFB_CS1" (rect 1162 3080 1224 3095)(font "Arial" )) - (pt 1264 3096) - (pt 1160 3096) -) -(connector - (text "nFB_CS2" (rect 1170 3104 1232 3119)(font "Arial" )) - (pt 1264 3120) - (pt 1160 3120) -) -(connector - (text "FB_SIZE0" (rect 1162 3152 1226 3167)(font "Arial" )) - (pt 1264 3168) - (pt 1160 3168) -) -(connector - (text "FB_SIZE1" (rect 1162 3176 1226 3191)(font "Arial" )) - (pt 1264 3192) - (pt 1160 3192) -) -(connector - (text "nFB_BURST" (rect 1162 3200 1244 3215)(font "Arial" )) - (pt 1264 3216) - (pt 1160 3216) -) -(connector - (text "nRSTO" (rect 1170 3248 1217 3263)(font "Arial" )) - (pt 1264 3264) - (pt 1160 3264) -) -(connector - (text "nFB_OE" (rect 1170 3032 1224 3047)(font "Arial" )) - (pt 1264 3048) - (pt 1160 3048) -) -(connector - (text "nSRCS" (rect 1682 3272 1730 3287)(font "Arial" )) - (pt 1824 3288) - (pt 1672 3288) -) -(connector - (text "nSRBLE" (rect 1682 3296 1737 3311)(font "Arial" )) - (pt 1824 3312) - (pt 1672 3312) -) -(connector - (text "nSRBHE" (rect 1682 3320 1739 3335)(font "Arial" )) - (pt 1824 3336) - (pt 1672 3336) -) -(connector - (text "nSRWE" (rect 1682 3344 1732 3359)(font "Arial" )) - (pt 1824 3360) - (pt 1672 3360) -) -(connector - (text "nSROE" (rect 1682 3368 1730 3383)(font "Arial" )) - (pt 1824 3384) - (pt 1672 3384) -) -(connector - (text "DSP_INT" (rect 1130 2832 1190 2847)(font "Arial" )) - (pt 1264 2848) - (pt 1120 2848) -) -(connector - (text "DSP_INT" (rect 1682 3000 1742 3015)(font "Arial" )) - (pt 1816 3016) - (pt 1672 3016) -) -(connector - (text "CLK500k" (rect 482 2040 542 2055)(font "Arial" )) - (pt 472 2056) - (pt 544 2056) -) -(connector - (pt 528 2416) - (pt 616 2416) -) -(connector - (text "FB_ALE" (rect 1194 304 1245 319)(font "Arial" )) - (pt 1264 320) - (pt 1184 320) -) -(connector - (text "DDRCLK[3..0]" (rect 1162 136 1252 151)(font "Arial" )) - (pt 1152 152) - (pt 1264 152) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 1178 112 1292 127)(font "Arial" )) - (pt 1168 128) - (pt 1264 128) -) -(connector - (text "VD[31..0]" (rect 1682 288 1739 303)(font "Arial" )) - (pt 1672 304) - (pt 2648 304) - (bus) -) -(connector - (text "VA[12..0]" (rect 1682 312 1737 327)(font "Arial" )) - (pt 1672 328) - (pt 2528 328) - (bus) -) -(connector - (text "nVWE" (rect 1682 336 1720 351)(font "Arial" )) - (pt 1672 352) - (pt 2400 352) -) -(connector - (text "nVCAS" (rect 1690 360 1734 375)(font "Arial" )) - (pt 1672 376) - (pt 2304 376) -) -(connector - (text "nVRAS" (rect 1690 384 1734 399)(font "Arial" )) - (pt 1672 400) - (pt 2208 400) -) -(connector - (text "nVCS" (rect 1690 408 1726 423)(font "Arial" )) - (pt 1672 424) - (pt 2040 424) -) -(connector - (text "VCKE" (rect 1690 432 1727 447)(font "Arial" )) - (pt 1672 448) - (pt 1944 448) -) -(connector - (text "VSYNC" (rect 1682 136 1729 151)(font "Arial" )) - (pt 1672 152) - (pt 1832 152) -) -(connector - (text "HSYNC" (rect 1682 160 1731 175)(font "Arial" )) - (pt 1672 176) - (pt 1832 176) -) -(connector - (text "VB[7..0]" (rect 1754 112 1802 127)(font "Arial" )) - (pt 1672 128) - (pt 1912 128) - (bus) -) -(connector - (text "VG[7..0]" (rect 1842 88 1891 103)(font "Arial" )) - (pt 1672 104) - (pt 2000 104) - (bus) -) -(connector - (text "VR[7..0]" (rect 1922 64 1971 79)(font "Arial" )) - (pt 1672 80) - (pt 2080 80) - (bus) -) -(connector - (text "IO[17..0]" (rect 1962 3224 2015 3239)(font "Arial" )) - (pt 1672 3240) - (pt 2104 3240) - (bus) -) -(connector - (text "SRD[15..0]" (rect 1802 3248 1871 3263)(font "Arial" )) - (pt 1672 3264) - (pt 1944 3264) - (bus) -) -(connector - (text "SCSI_D[7..0]" (rect 1786 1056 1868 1071)(font "Arial" )) - (pt 1672 1072) - (pt 1936 1072) - (bus) -) -(connector - (text "ACSI_D[7..0]" (rect 1754 880 1835 895)(font "Arial" )) - (pt 1672 896) - (pt 1904 896) - (bus) -) -(connector - (text "LP_D[7..0]" (rect 1810 800 1877 815)(font "Arial" )) - (pt 1672 816) - (pt 1960 816) - (bus) -) -(connector - (text "AMKB_RX" (rect 786 1480 850 1495)(font "Arial" )) - (pt 776 1496) - (pt 1264 1496) -) -(connector - (text "CLK33M" (rect 346 288 401 303)(font "Arial" )) - (pt 336 304) - (pt 400 304) -) -(connector - (text "CLK25M" (rect 1202 608 1257 623)(font "Arial" )) - (pt 1192 624) - (pt 1264 624) -) -(connector - (text "TIMEBASE[17]" (rect 354 2120 446 2135)(font "Arial" )) - (pt 440 2136) - (pt 344 2136) -) -(connector - (text "TIMEBASE[17..0]" (rect 706 2048 813 2063)(font "Arial" )) - (pt 688 2064) - (pt 808 2064) - (bus) -) -(connector - (text "HSYNC" (rect 1130 2784 1179 2799)(font "Arial" )) - (pt 1264 2800) - (pt 1120 2800) -) -(connector - (text "VSYNC" (rect 1130 2808 1177 2823)(font "Arial" )) - (pt 1264 2824) - (pt 1120 2824) -) -(connector - (text "VSYNC" (rect 1130 1920 1177 1935)(font "Arial" )) - (pt 1264 1936) - (pt 1120 1936) -) -(connector - (text "HSYNC" (rect 1130 1896 1179 1911)(font "Arial" )) - (pt 1264 1912) - (pt 1120 1912) -) -(connector - (pt 488 2136) - (pt 608 2136) -) -(connector - (text "nFB_TA" (rect 1946 720 1996 735)(font "Arial" )) - (pt 1944 736) - (pt 2056 736) -) -(connector - (text "INT_HANDLER_TA" (rect 1682 2832 1805 2847)(font "Arial" )) - (pt 1672 2848) - (pt 1808 2848) -) -(connector - (text "DSP_TA" (rect 1682 3504 1736 3519)(font "Arial" )) - (pt 1672 3520) - (pt 1792 3520) -) -(connector - (text "Video_TA" (rect 1682 696 1743 711)(font "Arial" )) - (pt 1672 712) - (pt 1880 712) -) -(connector - (text "FALCON_IO_TA" (rect 1682 744 1785 759)(font "Arial" )) - (pt 1672 760) - (pt 1880 760) -) -(connector - (text "INT_HANDLER_TA" (rect 1810 728 1933 743)(font "Arial" )) - (pt 1880 744) - (pt 1800 744) -) -(connector - (text "DSP_TA" (rect 1810 712 1864 727)(font "Arial" )) - (pt 1880 728) - (pt 1800 728) -) -(connector - (pt 2680 888) - (pt 2712 888) -) -(connector - (pt 2632 888) - (pt 2504 888) -) -(connector - (pt 2504 888) - (pt 2504 760) -) -(connector - (text "DDRCLK[0]" (rect 2450 744 2525 759)(font "Arial" )) - (pt 2440 760) - (pt 2504 760) -) -(connector - (pt 2504 760) - (pt 2536 760) -) -(connector - (text "MAIN_CLK" (rect 1186 88 1255 103)(font "Arial" )) - (pt 1184 104) - (pt 1264 104) -) -(connector - (text "nRSTO" (rect 1194 40 1241 55)(font "Arial" )) - (pt 1184 56) - (pt 1264 56) -) -(connector - (text "BA[1..0]" (rect 1682 456 1730 471)(font "Arial" )) - (pt 1672 472) - (pt 1832 472) - (bus) -) -(connector - (text "PIXEL_CLK" (rect 2394 -64 2469 -49)(font "Arial" )) - (pt 2384 -48) - (pt 2464 -48) -) -(connector - (text "PIXEL_CLK" (rect 2394 56 2469 71)(font "Arial" )) - (pt 2384 72) - (pt 2464 72) -) -(connector - (text "nBLANK" (rect 2394 24 2448 39)(font "Arial" )) - (pt 2464 40) - (pt 2384 40) -) -(connector - (text "nBLANK" (rect 2394 40 2448 55)(font "Arial" )) - (pt 2464 56) - (pt 2384 56) -) -(connector - (pt 2696 -80) - (pt 2712 -80) -) -(connector - (pt 2696 40) - (pt 2712 40) -) -(connector - (text "PIXEL_CLK" (rect 1826 -48 1901 -33)(font "Arial" )) - (pt 1816 -32) - (pt 1896 -32) -) -(connector - (pt 2128 -64) - (pt 2136 -64) -) -(connector - (text "PIXEL_CLK" (rect 1682 232 1757 247)(font "Arial" )) - (pt 1744 248) - (pt 1672 248) -) -(connector - (text "PIXEL_CLK" (rect 2394 184 2469 199)(font "Arial" )) - (pt 2384 200) - (pt 2464 200) -) -(connector - (pt 2456 168) - (pt 2456 136) -) -(connector - (pt 2464 168) - (pt 2456 168) -) -(connector - (pt 2456 136) - (pt 2400 136) -) -(connector - (pt 2464 184) - (pt 2440 184) -) -(connector - (pt 2712 168) - (pt 2696 168) -) -(connector - (pt 2440 160) - (pt 2424 160) -) -(connector - (pt 2440 184) - (pt 2440 160) -) -(connector - (text "nFB_CS3" (rect 1170 3128 1232 3143)(font "Arial" )) - (pt 1264 3144) - (pt 1160 3144) -) -(connector - (text "nBLANK" (rect 1154 1968 1208 1983)(font "Arial" )) - (pt 1264 1984) - (pt 1144 1984) -) -(connector - (text "DSP_INT" (rect 1154 1944 1214 1959)(font "Arial" )) - (pt 1264 1960) - (pt 1144 1960) -) -(connector - (text "STEP_DIR" (rect 1682 1752 1751 1767)(font "Arial" )) - (pt 1672 1768) - (pt 1856 1768) -) -(connector - (pt 1904 1768) - (pt 2136 1768) -) -(connector - (pt 1904 1816) - (pt 2136 1816) -) -(connector - (text "WR_DATA" (rect 1682 1800 1749 1815)(font "Arial" )) - (pt 1672 1816) - (pt 1856 1816) -) -(connector - (text "DMA_DRQ" (rect 1130 2856 1199 2871)(font "Arial" )) - (pt 1264 2872) - (pt 1120 2872) -) -(connector - (text "DMA_DRQ" (rect 1682 2096 1751 2111)(font "Arial" )) - (pt 1784 2112) - (pt 1672 2112) -) -(connector - (text "FDC_CLK" (rect 1202 880 1268 895)(font "Arial" )) - (pt 1192 896) - (pt 1264 896) -) -(connector - (text "MOT_ON" (rect 1626 1728 1685 1743)(font "Arial" )) - (pt 1672 1744) - (pt 1800 1744) -) -(connector - (pt 1848 1744) - (pt 2136 1744) -) -(connector - (text "STEP" (rect 1626 1776 1662 1791)(font "Arial" )) - (pt 1672 1792) - (pt 1800 1792) -) -(connector - (pt 1848 1792) - (pt 2136 1792) -) -(connector - (text "WR_GATE" (rect 1690 1824 1758 1839)(font "Arial" )) - (pt 1672 1840) - (pt 1800 1840) -) -(connector - (pt 1848 1840) - (pt 2136 1840) -) -(connector - (text "FB_ALE" (rect 1186 1992 1237 2007)(font "Arial" )) - (pt 1144 2008) - (pt 1264 2008) -) -(connector - (text "AMKB_TX" (rect 1946 1392 2008 1407)(font "Arial" )) - (pt 1672 1408) - (pt 2112 1408) -) -(connector - (text "PIC_AMKB_RX" (rect 786 1504 882 1519)(font "Arial" )) - (pt 776 1520) - (pt 1264 1520) -) -(connector - (pt 400 -16) - (pt 440 -16) -) -(connector - (pt 440 248) - (pt 400 248) -) -(connector - (pt 400 -16) - (pt 400 248) -) -(connector - (pt 400 248) - (pt 400 304) -) -(connector - (text "CLK2M" (rect 754 -32 801 -17)(font "Arial" )) - (pt 744 -16) - (pt 816 -16) -) -(connector - (text "FDC_CLK" (rect 754 -8 820 7)(font "Arial" )) - (pt 744 8) - (pt 816 8) -) -(connector - (text "FB_AD[31..0]" (rect 370 1352 453 1367)(font "Arial" )) - (pt 352 1368) - (pt 464 1368) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 642 1376 736 1391)(font "Arial" )) - (pt 608 1392) - (pt 760 1392) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 378 1368 492 1383)(font "Arial" )) - (pt 368 1384) - (pt 464 1384) -) -(connector - (text "FB_ALE" (rect 386 1384 437 1399)(font "Arial" )) - (pt 376 1400) - (pt 464 1400) -) -(connector - (text "ACP_CONF[31..0]" (rect 1682 2568 1797 2583)(font "Arial" )) - (pt 1672 2584) - (pt 1832 2584) - (bus) -) -(connector - (text "ACP_CONF[31..24]" (rect 1146 2064 1269 2079)(font "Arial" )) - (pt 1136 2080) - (pt 1264 2080) - (bus) -) -(connector - (text "TIN0" (rect 1682 2624 1712 2639)(font "Arial" )) - (pt 1832 2640) - (pt 1672 2640) -) -(connector - (pt 1896 -48) - (pt 1856 -48) -) -(connector - (pt 1856 -48) - (pt 1856 -64) -) -(connector - (pt 1856 -64) - (pt 1896 -64) -) -(connector - (pt 2464 -64) - (pt 2424 -64) -) -(connector - (pt 2424 -80) - (pt 2424 -64) -) -(connector - (text "HD_DD" (rect 1050 1616 1100 1631)(font "Arial" )) - (pt 1040 1632) - (pt 1264 1632) -) -(connector - (text "CLK48M" (rect 754 40 809 55)(font "Arial" )) - (pt 744 56) - (pt 840 56) -) -(connector - (text "CLK25M" (rect 754 16 809 31)(font "Arial" )) - (pt 744 32) - (pt 864 32) -) -(connector - (text "DDRCLK[0]" (rect 762 -296 837 -281)(font "Arial" )) - (pt 752 -280) - (pt 848 -280) -) -(connector - (text "DDRCLK[1]" (rect 762 -272 837 -257)(font "Arial" )) - (pt 752 -256) - (pt 848 -256) -) -(connector - (text "DDRCLK[2]" (rect 762 -248 837 -233)(font "Arial" )) - (pt 752 -232) - (pt 848 -232) -) -(connector - (text "DDRCLK[3]" (rect 762 -224 837 -209)(font "Arial" )) - (pt 752 -208) - (pt 848 -208) -) -(connector - (text "DDR_SYNC_66M" (rect 762 -200 876 -185)(font "Arial" )) - (pt 752 -184) - (pt 848 -184) -) -(connector - (pt 408 672) - (pt 472 672) -) -(connector - (text "VIDEO_RECONFIG" (rect 74 496 199 511)(font "Arial" )) - (pt 192 512) - (pt 64 512) -) -(connector - (text "MAIN_CLK" (rect 330 -296 399 -281)(font "Arial" )) - (pt 264 -280) - (pt 448 -280) -) -(connector - (pt 408 640) - (pt 472 640) -) -(connector - (pt 408 624) - (pt 512 624) -) -(connector - (text "VR_D[8..0]" (rect 418 552 486 567)(font "Arial" )) - (pt 496 568) - (pt 408 568) - (bus) -) -(connector - (text "MAIN_CLK" (rect 122 664 191 679)(font "Arial" )) - (pt 112 680) - (pt 192 680) -) -(connector - (pt 536 720) - (pt 408 720) -) -(connector - (pt 1064 808) - (pt 1064 616) -) -(connector - (pt 1072 816) - (pt 1072 592) -) -(connector - (pt 472 672) - (pt 472 664) -) -(connector - (pt 472 640) - (pt 472 616) -) -(connector - (pt 512 624) - (pt 512 640) -) -(connector - (pt 536 720) - (pt 536 592) -) -(connector - (pt 536 592) - (pt 608 592) -) -(connector - (pt 472 616) - (pt 608 616) -) -(connector - (pt 512 640) - (pt 608 640) -) -(connector - (pt 472 664) - (pt 608 664) -) -(connector - (pt 408 688) - (pt 608 688) -) -(connector - (pt 984 592) - (pt 1072 592) -) -(connector - (pt 984 616) - (pt 1064 616) -) -(connector - (text "FB_ADR[5..2]" (rect 82 568 168 583)(font "Arial" )) - (pt 192 584) - (pt 72 584) - (bus) -) -(connector - (pt 1064 808) - (pt 80 808) -) -(connector - (pt 192 656) - (pt 80 656) -) -(connector - (pt 80 656) - (pt 80 808) -) -(connector - (pt 1072 816) - (pt 72 816) -) -(connector - (pt 192 640) - (pt 72 640) -) -(connector - (pt 72 640) - (pt 72 816) -) -(connector - (text "FB_ADR[8..6]" (rect 82 584 168 599)(font "Arial" )) - (pt 192 600) - (pt 72 600) - (bus) -) -(connector - (text "VR_RD" (rect 98 512 146 527)(font "Arial" )) - (pt 64 528) - (pt 192 528) -) -(connector - (text "VR_WR" (rect 98 528 148 543)(font "Arial" )) - (pt 64 544) - (pt 192 544) -) -(connector - (text "VR_D[8..0]" (rect 1170 464 1238 479)(font "Arial" )) - (pt 1144 480) - (pt 1264 480) - (bus) -) -(connector - (text "VDQS[3..0]" (rect 1674 504 1743 519)(font "Arial" )) - (pt 2040 544) - (pt 1960 544) - (bus) -) -(connector - (pt 1672 544) - (pt 1888 544) - (bus) -) -(connector - (pt 1888 544) - (pt 1888 568) - (bus) -) -(connector - (text "VDM[3..0]" (rect 1682 528 1742 543)(font "Arial" )) - (pt 1944 568) - (pt 1888 568) - (bus) -) -(connector - (pt 1672 520) - (pt 1960 520) - (bus) -) -(connector - (pt 1960 544) - (pt 1960 520) - (bus) -) -(connector - (text "VIDEO_RECONFIG" (rect 1674 560 1799 575)(font "Arial" )) - (pt 1672 576) - (pt 1792 576) -) -(connector - (text "VR_WR" (rect 1698 592 1748 607)(font "Arial" )) - (pt 1672 608) - (pt 1792 608) -) -(connector - (text "VR_BUSY" (rect 418 496 482 511)(font "Arial" )) - (pt 408 512) - (pt 480 512) -) -(connector - (text "VR_BUSY" (rect 1170 448 1234 463)(font "Arial" )) - (pt 1144 464) - (pt 1264 464) -) -(connector - (text "VR_RD" (rect 1698 576 1746 591)(font "Arial" )) - (pt 1792 592) - (pt 1672 592) -) -(connector - (text "nRSTO" (rect -86 680 -39 695)(font "Arial" )) - (pt -96 696) - (pt -16 696) -) -(connector - (pt 32 696) - (pt 192 696) -) -(connector - (text "FB_AD[24..16]" (rect 82 552 174 567)(font "Arial" )) - (pt 72 568) - (pt 192 568) - (bus) -) -(connector - (text "CLK48M" (rect 538 552 593 567)(font "Arial" )) - (pt 528 568) - (pt 608 568) -) -(connector - (text "CLK_VIDEO" (rect 1162 552 1241 567)(font "Arial" )) - (pt 984 568) - (pt 1264 568) -) -(connector - (text "CLK33M" (rect 1202 584 1257 599)(font "Arial" )) - (pt 1264 600) - (pt 1192 600) -) -(connector - (text "CLK500k" (rect 802 232 862 247)(font "Arial" )) - (pt 768 248) - (pt 864 248) -) -(connector - (text "CLK2M4576" (rect 802 256 882 271)(font "Arial" )) - (pt 768 272) - (pt 864 272) -) -(connector - (text "CLK24M576" (rect 802 280 882 295)(font "Arial" )) - (pt 768 296) - (pt 864 296) -) -(connector - (text "nRSTO" (rect 1018 424 1065 439)(font "Arial" )) - (pt 1008 440) - (pt 1096 440) -) -(connector - (pt 768 320) - (pt 872 320) -) -(connector - (pt 872 432) - (pt 944 432) -) -(connector - (pt 840 448) - (pt 944 448) -) -(connector - (pt 872 320) - (pt 872 432) -) -(connector - (text "HSYNC" (rect 2314 -96 2363 -81)(font "Arial" )) - (pt 2304 -80) - (pt 2424 -80) -) -(connector - (pt 2424 -80) - (pt 2464 -80) -) -(connector - (text "VSYNC" (rect 1746 -80 1793 -65)(font "Arial" )) - (pt 1736 -64) - (pt 1856 -64) -) -(junction (pt 2504 760)) -(junction (pt 400 248)) -(junction (pt 1856 -64)) -(junction (pt 2424 -80)) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2014 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +//#pragma file_not_in_maxplusii_format +(header "graphic" (version "1.4")) +(properties + (page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n1\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n") +) +(pin + (input) + (rect 208 1392 384 1408) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "FB_ALE" (rect 9 0 51 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 152 1408 208 1424)) +) +(pin + (input) + (rect 992 936 1168 952) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nFB_WR" (rect 9 0 55 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 936 952 992 968)) +) +(pin + (input) + (rect 992 960 1168 976) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nFB_CS1" (rect 9 0 57 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 936 976 992 992)) +) +(pin + (input) + (rect 992 984 1168 1000) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nFB_CS2" (rect 9 0 58 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 936 1000 992 1016)) +) +(pin + (input) + (rect 1008 360 1184 376) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nFB_CS3" (rect 9 0 58 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 952 376 1008 392)) +) +(pin + (input) + (rect 992 1008 1168 1024) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "FB_SIZE0" (rect 9 0 60 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 936 1024 992 1040)) +) +(pin + (input) + (rect 992 1032 1168 1048) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "FB_SIZE1" (rect 9 0 59 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 936 1048 992 1064)) +) +(pin + (input) + (rect 992 1056 1168 1072) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nFB_BURST" (rect 9 0 73 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 936 1072 992 1088)) +) +(pin + (input) + (rect 936 1168 1112 1184) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "LP_BUSY" (rect 9 0 60 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 880 1184 936 1200)) +) +(pin + (input) + (rect 856 1200 1032 1216) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nACSI_DRQ" (rect 9 0 72 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 800 1216 856 1232)) +) +(pin + (input) + (rect 856 1224 1032 1240) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nACSI_INT" (rect 9 0 66 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 800 1240 856 1256)) +) +(pin + (input) + (rect 936 1392 1112 1408) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "RxD" (rect 9 0 32 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1408 936 1424)) +) +(pin + (input) + (rect 936 1416 1112 1432) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "CTS" (rect 9 0 32 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1432 936 1448)) +) +(pin + (input) + (rect 936 1440 1112 1456) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "RI" (rect 9 0 20 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1456 936 1472)) +) +(pin + (input) + (rect 936 1464 1112 1480) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "DCD" (rect 9 0 34 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1480 936 1496)) +) +(pin + (input) + (rect 608 1488 784 1504) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "AMKB_RX" (rect 9 0 64 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 552 1504 608 1520)) +) +(pin + (input) + (rect 608 1512 784 1528) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "PIC_AMKB_RX" (rect 9 0 89 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 552 1528 608 1544)) +) +(pin + (input) + (rect 936 1544 1112 1560) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "IDE_RDY" (rect 9 0 59 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 880 1560 936 1576)) +) +(pin + (input) + (rect 936 1568 1112 1584) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "IDE_INT" (rect 9 0 52 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1584 936 1600)) +) +(pin + (input) + (rect 936 1592 1112 1608) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "WP_CF_CARD" (rect 9 0 86 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 880 1608 936 1624)) +) +(pin + (input) + (rect 872 1672 1048 1688) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "TRACK00" (rect 9 0 59 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 808 1688 872 1704)) +) +(pin + (input) + (rect 872 1696 1048 1712) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nWP" (rect 9 0 34 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 808 1712 872 1728)) +) +(pin + (input) + (rect 872 1744 1048 1760) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nDCHG" (rect 9 0 49 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 808 1760 872 1776)) +) +(pin + (input) + (rect 936 1776 1112 1792) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "SD_DATA0" (rect 9 0 68 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1792 936 1808)) +) +(pin + (input) + (rect 936 1800 1112 1816) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "SD_DATA1" (rect 9 0 66 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1816 936 1832)) +) +(pin + (input) + (rect 936 1824 1112 1840) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "SD_DATA2" (rect 9 0 68 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1840 936 1856)) +) +(pin + (input) + (rect 936 1848 1112 1864) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "SD_CARD_DEDECT" (rect 9 0 115 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1864 936 1880)) +) +(pin + (input) + (rect 872 1360 1048 1376) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "MIDI_IN" (rect 9 0 50 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 808 1376 872 1392)) +) +(pin + (input) + (rect 936 1256 1112 1272) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nSCSI_DRQ" (rect 9 0 72 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 880 1272 936 1288)) +) +(pin + (input) + (rect 936 1872 1112 1888) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "SD_WP" (rect 9 0 50 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 872 1888 936 1904)) +) +(pin + (input) + (rect 872 1720 1048 1736) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nRD_DATA" (rect 9 0 69 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 808 1736 872 1752)) +) +(pin + (input) + (rect 936 1280 1112 1296) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nSCSI_C_D" (rect 9 0 70 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 880 1296 936 1312)) +) +(pin + (input) + (rect 936 1304 1112 1320) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nSCSI_I_O" (rect 9 0 66 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 880 1320 936 1336)) +) +(pin + (input) + (rect 936 1328 1112 1344) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nSCSI_MSG" (rect 9 0 73 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 880 1344 936 1360)) +) +(pin + (input) + (rect 992 1104 1168 1120) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nDACK0" (rect 9 0 53 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 928 1120 992 1136)) +) +(pin + (input) + (rect 984 2592 1160 2608) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "PIC_INT" (rect 9 0 52 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 920 2608 984 2624)) +) +(pin + (input) + (rect 992 912 1168 928) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nFB_OE" (rect 9 0 52 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 936 928 992 944)) +) +(pin + (input) + (rect 360 2616 536 2632) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "TOUT0" (rect 9 0 46 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 296 2632 360 2648)) +) +(pin + (input) + (rect 360 2504 536 2520) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nMASTER" (rect 9 0 63 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 304 2520 360 2536)) +) +(pin + (input) + (rect 984 2640 1160 2656) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "DVI_INT" (rect 9 0 52 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 920 2656 984 2672)) +) +(pin + (input) + (rect 360 2408 536 2424) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nDACK1" (rect 9 0 52 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 296 2424 360 2440)) +) +(pin + (input) + (rect 984 2664 1160 2680) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nPCI_INTD" (rect 9 0 66 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 928 2680 984 2696)) +) +(pin + (input) + (rect 984 2688 1160 2704) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nPCI_INTC" (rect 9 0 66 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 928 2704 984 2720)) +) +(pin + (input) + (rect 984 2712 1160 2728) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nPCI_INTB" (rect 9 0 66 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 928 2728 984 2744)) +) +(pin + (input) + (rect 984 2736 1160 2752) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nPCI_INTA" (rect 9 0 68 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 920 2752 984 2768)) +) +(pin + (input) + (rect 984 2616 1160 2632) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "E0_INT" (rect 9 0 47 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 920 2632 984 2648)) +) +(pin + (input) + (rect 872 1648 1048 1664) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nINDEX" (rect 9 0 51 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 808 1664 872 1680)) +) +(pin + (input) + (rect 872 1624 1048 1640) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "HD_DD" (rect 9 0 49 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 808 1640 872 1656)) +) +(pin + (input) + (rect 664 440 840 456) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nRSTO_MCF" (rect 9 0 77 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 600 456 664 472)) +) +(pin + (input) + (rect 168 296 344 312) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "MAIN_CLK" (rect 9 0 66 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 112 312 168 328)) +) +(pin + (output) + (rect 864 288 1040 304) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "CLK24M576" (rect 90 0 152 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1040 304 1112 320)) +) +(pin + (output) + (rect 1832 832 2008 848) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LP_STR" (rect 90 0 133 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 848 2064 864)) +) +(pin + (output) + (rect 1832 936 2008 952) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nACSI_ACK" (rect 90 0 153 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 952 2064 968)) +) +(pin + (output) + (rect 1832 960 2008 976) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nACSI_RESET" (rect 90 0 166 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 976 2064 992)) +) +(pin + (output) + (rect 1832 984 2008 1000) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nACSI_CS" (rect 90 0 145 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 1000 2064 1016)) +) +(pin + (output) + (rect 1832 1008 2008 1024) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "ACSI_DIR" (rect 90 0 141 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 1024 2064 1040)) +) +(pin + (output) + (rect 1832 1032 2008 1048) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "ACSI_A1" (rect 90 0 136 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 1048 2064 1064)) +) +(pin + (output) + (rect 1840 1112 2016 1128) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSCSI_ACK" (rect 90 0 153 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2016 1128 2072 1144)) +) +(pin + (output) + (rect 1840 1136 2016 1152) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSCSI_ATN" (rect 90 0 150 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2016 1152 2072 1168)) +) +(pin + (output) + (rect 1840 1160 2016 1176) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "SCSI_DIR" (rect 90 0 141 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2016 1176 2072 1192)) +) +(pin + (output) + (rect 1920 1264 2096 1280) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "MIDI_OLR" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2096 1280 2152 1296)) +) +(pin + (output) + (rect 1920 1288 2096 1304) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "MIDI_TLR" (rect 90 0 141 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2096 1304 2152 1320)) +) +(pin + (output) + (rect 1840 1320 2016 1336) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "TxD" (rect 90 0 112 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2016 1336 2080 1352)) +) +(pin + (output) + (rect 1840 1344 2016 1360) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "RTS" (rect 90 0 113 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2016 1360 2080 1376)) +) +(pin + (output) + (rect 1848 1368 2024 1384) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "DTR" (rect 90 0 114 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2024 1384 2088 1400)) +) +(pin + (output) + (rect 2112 1400 2288 1416) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "AMKB_TX" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2288 1416 2344 1432)) +) +(pin + (output) + (rect 1848 1432 2024 1448) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "IDE_RES" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2024 1448 2080 1464)) +) +(pin + (output) + (rect 1848 1456 2024 1472) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nIDE_CS0" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2024 1472 2080 1488)) +) +(pin + (output) + (rect 1856 1480 2032 1496) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nIDE_CS1" (rect 90 0 143 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2032 1496 2088 1512)) +) +(pin + (output) + (rect 1848 1504 2024 1520) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nIDE_WR" (rect 90 0 140 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2024 1520 2080 1536)) +) +(pin + (output) + (rect 1848 1528 2024 1544) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nIDE_RD" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2024 1544 2080 1560)) +) +(pin + (output) + (rect 1848 1552 2024 1568) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nCF_CS0" (rect 90 0 139 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2024 1568 2080 1584)) +) +(pin + (output) + (rect 1848 1576 2024 1592) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nCF_CS1" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2024 1592 2080 1608)) +) +(pin + (output) + (rect 1920 1608 2096 1624) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nROM3" (rect 90 0 130 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2096 1624 2152 1640)) +) +(pin + (output) + (rect 1920 1632 2096 1648) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nROM4" (rect 90 0 130 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2096 1648 2152 1664)) +) +(pin + (output) + (rect 1920 1656 2096 1672) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nRP_UDS" (rect 90 0 143 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2096 1672 2152 1688)) +) +(pin + (output) + (rect 1920 1680 2096 1696) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nRP_LDS" (rect 90 0 140 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2096 1696 2152 1712)) +) +(pin + (output) + (rect 1856 1856 2032 1872) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSDSEL" (rect 90 0 133 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2032 1872 2096 1888)) +) +(pin + (output) + (rect 2136 1832 2312 1848) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nWR_GATE" (rect 90 0 152 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2312 1848 2376 1864)) +) +(pin + (output) + (rect 2136 1808 2312 1824) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nWR" (rect 90 0 115 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2312 1824 2376 1840)) +) +(pin + (output) + (rect 1928 1912 2104 1928) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "YM_QA" (rect 90 0 131 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2104 1928 2168 1944)) +) +(pin + (output) + (rect 1928 1936 2104 1952) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "YM_QB" (rect 90 0 130 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2104 1952 2168 1968)) +) +(pin + (output) + (rect 1928 1960 2104 1976) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "YM_QC" (rect 90 0 131 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2104 1976 2168 1992)) +) +(pin + (output) + (rect 1856 2040 2032 2056) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "SD_CLK" (rect 90 0 136 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2032 2056 2096 2072)) +) +(pin + (output) + (rect 1856 1712 2032 1728) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "DSA_D" (rect 90 0 128 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2032 1728 2096 1744)) +) +(pin + (output) + (rect 2080 72 2256 88) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "VR[7..0]" (rect 90 0 130 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2256 88 2312 104)) +) +(pin + (output) + (rect 2000 96 2176 112) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "VG[7..0]" (rect 90 0 131 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2176 112 2240 128)) +) +(pin + (output) + (rect 1912 120 2088 136) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "VB[7..0]" (rect 90 0 130 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2088 136 2152 152)) +) +(pin + (output) + (rect 2528 320 2704 336) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "VA[12..0]" (rect 90 0 136 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2704 336 2768 352)) +) +(pin + (output) + (rect 2400 344 2576 360) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nVWE" (rect 90 0 123 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2576 360 2640 376)) +) +(pin + (output) + (rect 2304 368 2480 384) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nVCAS" (rect 90 0 127 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2480 384 2552 400)) +) +(pin + (output) + (rect 2208 392 2384 408) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nVRAS" (rect 90 0 127 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2384 408 2448 424)) +) +(pin + (output) + (rect 2040 416 2216 432) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nVCS" (rect 90 0 120 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2216 432 2280 448)) +) +(pin + (output) + (rect 1944 560 2120 576) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "VDM[3..0]" (rect 90 0 139 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2120 576 2192 592)) +) +(pin + (output) + (rect 1832 264 2008 280) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nPD_VGA" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 280 2064 296)) +) +(pin + (output) + (rect 1832 2416 2008 2432) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nIRQ[7..2]" (rect 90 0 140 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 2432 2064 2448)) +) +(pin + (output) + (rect 776 0 952 16) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "CLK25M" (rect 90 0 134 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 952 16 1008 32)) +) +(pin + (output) + (rect 1832 2632 2008 2648) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "TIN0" (rect 90 0 115 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 2648 2064 2664)) +) +(pin + (output) + (rect 1824 3280 2000 3296) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSRCS" (rect 90 0 128 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2000 3296 2056 3312)) +) +(pin + (output) + (rect 1824 3304 2000 3320) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSRBLE" (rect 90 0 133 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2000 3320 2056 3336)) +) +(pin + (output) + (rect 1824 3328 2000 3344) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSRBHE" (rect 90 0 136 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2000 3344 2056 3360)) +) +(pin + (output) + (rect 1824 3352 2000 3368) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSRWE" (rect 90 0 131 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2000 3368 2056 3384)) +) +(pin + (output) + (rect 616 2408 792 2424) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nDREQ1" (rect 90 0 134 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 792 2424 848 2440)) +) +(pin + (output) + (rect 608 2128 784 2144) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LED_FPGA_OK" (rect 90 0 172 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 784 2144 848 2160)) +) +(pin + (output) + (rect 1824 3376 2000 3392) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSROE" (rect 90 0 128 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2000 3392 2056 3408)) +) +(pin + (output) + (rect 1944 440 2120 456) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "VCKE" (rect 90 0 121 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2120 456 2184 472)) +) +(pin + (output) + (rect 2056 728 2232 744) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nFB_TA" (rect 90 0 133 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2232 744 2288 760)) +) +(pin + (output) + (rect 2712 880 2888 896) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nDDR_CLK" (rect 90 0 150 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2888 896 2960 912)) +) +(pin + (output) + (rect 2536 752 2712 768) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "DDR_CLK" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2712 768 2784 784)) +) +(pin + (output) + (rect 1832 464 2008 480) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "BA[1..0]" (rect 90 0 130 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 480 2072 496)) +) +(pin + (output) + (rect 2136 -72 2312 -56) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "VSYNC_PAD" (rect 90 0 158 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2312 -56 2376 -40)) +) +(pin + (output) + (rect 2712 -88 2888 -72) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HSYNC_PAD" (rect 90 0 158 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2888 -72 2952 -56)) +) +(pin + (output) + (rect 2712 32 2888 48) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nBLANK_PAD" (rect 90 0 163 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2888 48 2952 64)) +) +(pin + (output) + (rect 2712 160 2888 176) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "PIXEL_CLK_PAD" (rect 90 0 179 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2888 176 2952 192)) +) +(pin + (output) + (rect 1832 216 2008 232) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSYNC" (rect 90 0 128 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 232 2072 248)) +) +(pin + (output) + (rect 2136 1736 2312 1752) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nMOT_ON" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2312 1752 2376 1768)) +) +(pin + (output) + (rect 2136 1760 2312 1776) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSTEP_DIR" (rect 90 0 151 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2312 1776 2376 1792)) +) +(pin + (output) + (rect 2136 1784 2312 1800) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "nSTEP" (rect 90 0 126 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2312 1800 2376 1816)) +) +(pin + (output) + (rect 840 48 1016 64) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "CLKUSB" (rect 90 0 136 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1016 64 1072 80)) +) +(pin + (output) + (rect 1832 856 2008 872) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LPDIR" (rect 90 0 124 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2008 872 2064 888)) +) +(pin + (bidir) + (rect 1840 1088 2016 1104) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "SCSI_PAR" (rect 90 0 146 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2016 1104 2072 1120)) +) +(pin + (bidir) + (rect 1840 1184 2016 1200) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "nSCSI_RST" (rect 90 0 151 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2016 1200 2072 1216)) +) +(pin + (bidir) + (rect 1840 1208 2016 1224) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "nSCSI_SEL" (rect 90 0 150 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2016 1224 2072 1240)) +) +(pin + (bidir) + (rect 1840 1232 2016 1248) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "nSCSI_BUSY" (rect 90 0 160 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2016 1248 2072 1264)) +) +(pin + (bidir) + (rect 1856 1992 2032 2008) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "SD_CD_DATA3" (rect 90 0 170 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2032 2008 2096 2024)) +) +(pin + (bidir) + (rect 1856 2016 2032 2032) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "SD_CMD_D1" (rect 90 0 157 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2032 2032 2096 2048)) +) +(pin + (bidir) + (rect 1936 1064 2112 1080) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "SCSI_D[7..0]" (rect 90 0 154 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2112 1080 2168 1096)) +) +(pin + (bidir) + (rect 1904 888 2080 904) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "ACSI_D[7..0]" (rect 90 0 154 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2080 904 2136 920)) +) +(pin + (bidir) + (rect 1960 808 2136 824) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "LP_D[7..0]" (rect 90 0 143 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2136 824 2192 840)) +) +(pin + (bidir) + (rect 176 1360 352 1376) + (text "BIDIR" (rect 148 0 175 10)(font "Arial" (font_size 6))) + (text "FB_AD[31..0]" (rect 20 0 86 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 120 4)(pt 98 4)) + (line (pt 176 8)(pt 124 8)) + (line (pt 120 12)(pt 98 12)) + (line (pt 98 4)(pt 94 8)) + (line (pt 98 12)(pt 94 8)) + (line (pt 120 4)(pt 124 8)) + (line (pt 124 8)(pt 120 12)) + ) + (flipy) + (text "VCC" (rect 151 7 172 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 352 1376 408 1392)) +) +(pin + (bidir) + (rect 2104 3232 2280 3248) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "IO[17..0]" (rect 90 0 132 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2280 3248 2336 3264)) +) +(pin + (bidir) + (rect 1944 3256 2120 3272) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "SRD[15..0]" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2120 3272 2176 3288)) +) +(pin + (bidir) + (rect 2040 536 2216 552) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "VDQS[3..0]" (rect 90 0 146 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2216 552 2288 568)) +) +(pin + (bidir) + (rect 2648 296 2824 312) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "VD[31..0]" (rect 90 0 136 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2824 312 2888 328)) +) +(symbol + (rect 464 1336 608 1432) + (text "lpm_ff0" (rect 52 1 105 17)(font "Arial" (font_size 10))) + (text "inst1" (rect 8 80 31 91)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 61 13)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 81 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 57 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "enable" (rect 0 0 38 13)(font "Arial" (font_size 8))) + (text "enable" (rect 20 58 58 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 144 56) + (output) + (text "q[31..0]" (rect 0 0 43 13)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 89 50 132 63)(font "Arial" (font_size 8))) + (line (pt 144 56)(pt 128 56)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 132 28)(font "Arial" )) + (line (pt 16 16)(pt 128 16)) + (line (pt 128 16)(pt 128 80)) + (line (pt 128 80)(pt 16 80)) + (line (pt 16 80)(pt 16 16)) + (line (pt 16 42)(pt 22 48)) + (line (pt 22 48)(pt 16 54)) + ) +) +(symbol + (rect 544 2024 688 2088) + (text "lpm_counter0" (rect 33 1 129 17)(font "Arial" (font_size 10))) + (text "inst18" (rect 8 48 38 59)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 57 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 144 40) + (output) + (text "q[17..0]" (rect 0 0 43 13)(font "Arial" (font_size 8))) + (text "q[17..0]" (rect 87 34 130 47)(font "Arial" (font_size 8))) + (line (pt 144 40)(pt 128 40)(line_width 3)) + ) + (drawing + (text "up counter" (rect 84 17 139 28)(font "Arial" )) + (line (pt 16 16)(pt 128 16)) + (line (pt 128 16)(pt 128 48)) + (line (pt 128 48)(pt 16 48)) + (line (pt 16 48)(pt 16 16)) + (line (pt 16 26)(pt 22 32)) + (line (pt 22 32)(pt 16 38)) + ) +) +(symbol + (rect 440 2120 488 2152) + (text "WIRE" (rect 1 0 26 10)(font "Arial" (font_size 6))) + (text "inst3" (rect 3 21 27 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 32 16)(pt 48 16)) + ) + (drawing + (line (pt 14 7)(pt 32 16)) + (line (pt 14 25)(pt 14 7)) + (line (pt 14 25)(pt 32 16)) + ) +) +(symbol + (rect 1880 696 1944 776) + (text "NOR4" (rect 1 0 30 10)(font "Arial" (font_size 6))) + (text "inst2" (rect 3 69 27 80)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 48) + (input) + (text "IN3" (rect 2 39 22 50)(font "Courier New" (bold))(invisible)) + (text "IN3" (rect 2 39 22 50)(font "Courier New" (bold))(invisible)) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 64) + (input) + (text "IN4" (rect 2 55 22 66)(font "Courier New" (bold))(invisible)) + (text "IN4" (rect 2 55 22 66)(font "Courier New" (bold))(invisible)) + (line (pt 0 64)(pt 14 64)) + ) + (port + (pt 64 40) + (output) + (text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible)) + (line (pt 56 40)(pt 64 40)) + ) + (drawing + (line (pt 14 29)(pt 25 29)) + (line (pt 14 52)(pt 25 52)) + (line (pt 14 29)(pt 14 13)) + (line (pt 14 67)(pt 14 51)) + (arc (pt 25 51)(pt 48 40)(rect -4 -7 55 52)) + (arc (pt 48 40)(pt 25 29)(rect -4 29 55 88)) + (arc (pt 8 45)(pt 8 35)(rect -13 24 20 57)) + (circle (rect 48 36 56 44)) + ) +) +(symbol + (rect 2632 872 2680 904) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst4" (rect 3 21 27 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect 1896 -88 2128 32) + (text "altddio_out3" (rect 81 1 168 17)(font "Arial" (font_size 10))) + (text "inst5" (rect 8 104 32 115)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 53 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 46 13)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 50 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 53 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)) + ) + (drawing + (text "ddio" (rect 110 27 135 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 141 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 139 85)(font "Arial" )) + (text "low" (rect 92 84 109 95)(font "Arial" )) + (line (pt 88 16)(pt 152 16)) + (line (pt 152 16)(pt 152 96)) + (line (pt 152 96)(pt 88 96)) + (line (pt 88 96)(pt 88 16)) + ) +) +(symbol + (rect 2464 -104 2696 16) + (text "altddio_out3" (rect 81 1 168 17)(font "Arial" (font_size 10))) + (text "inst6" (rect 8 104 32 115)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 53 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 46 13)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 50 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 53 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)) + ) + (drawing + (text "ddio" (rect 110 27 135 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 141 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 139 85)(font "Arial" )) + (text "low" (rect 92 84 109 95)(font "Arial" )) + (line (pt 88 16)(pt 152 16)) + (line (pt 152 16)(pt 152 96)) + (line (pt 152 96)(pt 88 96)) + (line (pt 88 96)(pt 88 16)) + ) +) +(symbol + (rect 2464 16 2696 136) + (text "altddio_out3" (rect 81 1 168 17)(font "Arial" (font_size 10))) + (text "inst8" (rect 8 104 32 115)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 53 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 46 13)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 50 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 53 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)) + ) + (drawing + (text "ddio" (rect 110 27 135 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 141 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 139 85)(font "Arial" )) + (text "low" (rect 92 84 109 95)(font "Arial" )) + (line (pt 88 16)(pt 152 16)) + (line (pt 152 16)(pt 152 96)) + (line (pt 152 96)(pt 88 96)) + (line (pt 88 96)(pt 88 16)) + ) +) +(symbol + (rect 2464 144 2696 264) + (text "altddio_out3" (rect 81 1 168 17)(font "Arial" (font_size 10))) + (text "inst9" (rect 8 104 32 115)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 53 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 46 13)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 50 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 53 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)) + ) + (drawing + (text "ddio" (rect 110 27 135 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 141 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 139 85)(font "Arial" )) + (text "low" (rect 92 84 109 95)(font "Arial" )) + (line (pt 88 16)(pt 152 16)) + (line (pt 152 16)(pt 152 96)) + (line (pt 152 96)(pt 88 96)) + (line (pt 88 96)(pt 88 16)) + ) +) +(symbol + (rect 2368 120 2400 152) + (text "GND" (rect 6 8 16 30)(font "Arial" (font_size 6))(vertical)) + (text "inst10" (rect 0 3 11 33)(font "Arial" )(vertical)(invisible)) + (port + (pt 32 16) + (output) + (text "1" (rect 18 0 25 11)(font "Courier New" (bold))(invisible)) + (text "1" (rect 21 18 32 25)(font "Courier New" (bold))(vertical)(invisible)) + (line (pt 24 16)(pt 32 16)) + ) + (drawing + (line (pt 24 8)(pt 16 16)) + (line (pt 16 16)(pt 24 24)) + (line (pt 24 8)(pt 24 24)) + ) + (rotate270) +) +(symbol + (rect 2408 144 2424 176) + (text "VCC" (rect 0 7 10 28)(font "Arial" (font_size 6))(vertical)) + (text "inst11" (rect 5 3 16 32)(font "Arial" )(vertical)(invisible)) + (port + (pt 16 16) + (output) + (text "1" (rect 19 7 26 18)(font "Courier New" (bold))(invisible)) + (text "1" (rect 7 19 18 26)(font "Courier New" (bold))(vertical)(invisible)) + (line (pt 16 16)(pt 8 16)) + ) + (drawing + (line (pt 8 8)(pt 8 24)) + ) + (flipy_rotate90) +) +(symbol + (rect 1800 1728 1848 1760) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst14" (rect 3 21 33 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect 1856 1752 1904 1784) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst15" (rect 3 21 33 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect 1800 1776 1848 1808) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst16" (rect 3 21 33 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect 1856 1800 1904 1832) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst17" (rect 3 21 33 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect 1800 1824 1848 1856) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst19" (rect 3 21 33 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect -16 680 32 712) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst23" (rect 3 21 33 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(symbol + (rect 944 416 1008 464) + (text "AND2" (rect 1 0 29 10)(font "Arial" (font_size 6))) + (text "inst25" (rect 3 37 33 48)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) +(symbol + (rect 456 -352 760 -104) + (text "altpll2" (rect 132 1 174 17)(font "Arial" (font_size 10))) + (text "i_ddr_clk_pll" (rect 8 229 70 240)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)) + ) + (port + (pt 304 72) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 302 69)(font "Arial" (font_size 8))) + (line (pt 304 72)(pt 272 72)) + ) + (port + (pt 304 96) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 287 80 301 93)(font "Arial" (font_size 8))) + (line (pt 304 96)(pt 272 96)) + ) + (port + (pt 304 120) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 287 104 302 117)(font "Arial" (font_size 8))) + (line (pt 304 120)(pt 272 120)) + ) + (port + (pt 304 144) + (output) + (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c3" (rect 287 128 302 141)(font "Arial" (font_size 8))) + (line (pt 304 144)(pt 272 144)) + ) + (port + (pt 304 168) + (output) + (text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c4" (rect 287 152 302 165)(font "Arial" (font_size 8))) + (line (pt 304 168)(pt 272 168)) + ) + (drawing + (text "Cyclone III" (rect 229 230 280 241)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 204 78)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 220 95)(font "Arial" )) + (text "Clk " (rect 59 111 79 122)(font "Arial" )) + (text "Ratio" (rect 85 111 112 122)(font "Arial" )) + (text "Ph (dg)" (rect 119 111 156 122)(font "Arial" )) + (text "DC (%)" (rect 164 111 201 122)(font "Arial" )) + (text "c0" (rect 63 129 75 140)(font "Arial" )) + (text "4/1" (rect 91 129 106 140)(font "Arial" )) + (text "240.00" (rect 120 129 155 140)(font "Arial" )) + (text "50.00" (rect 169 129 198 140)(font "Arial" )) + (text "c1" (rect 63 147 74 158)(font "Arial" )) + (text "4/1" (rect 91 147 106 158)(font "Arial" )) + (text "0.00" (rect 127 147 150 158)(font "Arial" )) + (text "50.00" (rect 169 147 198 158)(font "Arial" )) + (text "c2" (rect 63 165 75 176)(font "Arial" )) + (text "4/1" (rect 91 165 106 176)(font "Arial" )) + (text "180.00" (rect 120 165 155 176)(font "Arial" )) + (text "50.00" (rect 169 165 198 176)(font "Arial" )) + (text "c3" (rect 63 183 75 194)(font "Arial" )) + (text "4/1" (rect 91 183 106 194)(font "Arial" )) + (text "105.00" (rect 120 183 155 194)(font "Arial" )) + (text "50.00" (rect 169 183 198 194)(font "Arial" )) + (text "c4" (rect 63 201 75 212)(font "Arial" )) + (text "2/1" (rect 91 201 106 212)(font "Arial" )) + (text "270.00" (rect 120 201 155 212)(font "Arial" )) + (text "50.00" (rect 169 201 198 212)(font "Arial" )) + (line (pt 0 0)(pt 305 0)) + (line (pt 305 0)(pt 305 249)) + (line (pt 0 249)(pt 305 249)) + (line (pt 0 0)(pt 0 249)) + (line (pt 56 108)(pt 206 108)) + (line (pt 56 125)(pt 206 125)) + (line (pt 56 143)(pt 206 143)) + (line (pt 56 161)(pt 206 161)) + (line (pt 56 179)(pt 206 179)) + (line (pt 56 197)(pt 206 197)) + (line (pt 56 215)(pt 206 215)) + (line (pt 56 108)(pt 56 215)) + (line (pt 82 108)(pt 82 215)(line_width 3)) + (line (pt 116 108)(pt 116 215)(line_width 3)) + (line (pt 161 108)(pt 161 215)(line_width 3)) + (line (pt 205 108)(pt 205 215)) + (line (pt 48 56)(pt 272 56)) + (line (pt 272 56)(pt 272 232)) + (line (pt 48 232)(pt 272 232)) + (line (pt 48 56)(pt 48 232)) + ) +) +(symbol + (rect 448 -88 704 96) + (text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10))) + (text "i_atari_clk_pll" (rect 8 169 76 180)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) + ) + (port + (pt 256 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 241 51 256 64)(font "Arial" (font_size 8))) + ) + (port + (pt 256 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 241 67 255 80)(font "Arial" (font_size 8))) + ) + (port + (pt 256 96) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 241 83 256 96)(font "Arial" (font_size 8))) + ) + (port + (pt 256 112) + (output) + (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c3" (rect 241 99 256 112)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone III" (rect 198 170 249 181)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 60 196 71)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 72 212 83)(font "Arial" )) + (text "Clk " (rect 51 91 71 102)(font "Arial" )) + (text "Ratio" (rect 77 91 104 102)(font "Arial" )) + (text "Ph (dg)" (rect 109 91 146 102)(font "Arial" )) + (text "DC (%)" (rect 144 91 181 102)(font "Arial" )) + (text "c0" (rect 54 104 66 115)(font "Arial" )) + (text "2/33" (rect 79 104 102 115)(font "Arial" )) + (text "0.00" (rect 115 104 138 115)(font "Arial" )) + (text "50.00" (rect 148 104 177 115)(font "Arial" )) + (text "c1" (rect 54 117 65 128)(font "Arial" )) + (text "16/33" (rect 77 117 106 128)(font "Arial" )) + (text "0.00" (rect 115 117 138 128)(font "Arial" )) + (text "50.00" (rect 148 117 177 128)(font "Arial" )) + (text "c2" (rect 54 130 66 141)(font "Arial" )) + (text "109/144" (rect 71 130 112 141)(font "Arial" )) + (text "0.00" (rect 115 130 138 141)(font "Arial" )) + (text "50.00" (rect 148 130 177 141)(font "Arial" )) + (text "c3" (rect 54 143 66 154)(font "Arial" )) + (text "16/11" (rect 77 143 105 154)(font "Arial" )) + (text "0.00" (rect 115 143 138 154)(font "Arial" )) + (text "50.00" (rect 148 143 177 154)(font "Arial" )) + (line (pt 0 0)(pt 257 0)) + (line (pt 257 0)(pt 257 185)) + (line (pt 0 185)(pt 257 185)) + (line (pt 0 0)(pt 0 185)) + (line (pt 48 89)(pt 176 89)) + (line (pt 48 101)(pt 176 101)) + (line (pt 48 114)(pt 176 114)) + (line (pt 48 127)(pt 176 127)) + (line (pt 48 140)(pt 176 140)) + (line (pt 48 153)(pt 176 153)) + (line (pt 48 89)(pt 48 153)) + (line (pt 68 89)(pt 68 153)(line_width 3)) + (line (pt 106 89)(pt 106 153)(line_width 3)) + (line (pt 141 89)(pt 141 153)(line_width 3)) + (line (pt 175 89)(pt 175 153)) + (line (pt 40 48)(pt 223 48)) + (line (pt 223 48)(pt 223 167)) + (line (pt 40 167)(pt 223 167)) + (line (pt 40 48)(pt 40 167)) + (line (pt 255 64)(pt 223 64)) + (line (pt 255 80)(pt 223 80)) + (line (pt 255 96)(pt 223 96)) + (line (pt 255 112)(pt 223 112)) + ) +) +(symbol + (rect 440 176 768 392) + (text "altpll1" (rect 144 1 185 17)(font "Arial" (font_size 10))) + (text "i_mfp_acia_clk_pll" (rect 8 197 100 208)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)) + ) + (port + (pt 328 72) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 311 56 326 69)(font "Arial" (font_size 8))) + (line (pt 328 72)(pt 272 72)) + ) + (port + (pt 328 96) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 311 80 325 93)(font "Arial" (font_size 8))) + (line (pt 328 96)(pt 272 96)) + ) + (port + (pt 328 120) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 311 104 326 117)(font "Arial" (font_size 8))) + (line (pt 328 120)(pt 272 120)) + ) + (port + (pt 328 144) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 287 128 324 141)(font "Arial" (font_size 8))) + (line (pt 328 144)(pt 272 144)) + ) + (drawing + (text "Cyclone III" (rect 253 198 304 209)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 204 78)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 220 95)(font "Arial" )) + (text "Clk " (rect 59 111 79 122)(font "Arial" )) + (text "Ratio" (rect 90 111 117 122)(font "Arial" )) + (text "Ph (dg)" (rect 128 111 165 122)(font "Arial" )) + (text "DC (%)" (rect 173 111 210 122)(font "Arial" )) + (text "c0" (rect 63 129 75 140)(font "Arial" )) + (text "1/66" (rect 92 129 115 140)(font "Arial" )) + (text "0.00" (rect 136 129 159 140)(font "Arial" )) + (text "50.00" (rect 178 129 207 140)(font "Arial" )) + (text "c1" (rect 63 147 74 158)(font "Arial" )) + (text "67/900" (rect 85 147 120 158)(font "Arial" )) + (text "0.00" (rect 136 147 159 158)(font "Arial" )) + (text "50.00" (rect 178 147 207 158)(font "Arial" )) + (text "c2" (rect 63 165 75 176)(font "Arial" )) + (text "67/90" (rect 89 165 118 176)(font "Arial" )) + (text "0.00" (rect 136 165 159 176)(font "Arial" )) + (text "50.00" (rect 178 165 207 176)(font "Arial" )) + (line (pt 0 0)(pt 329 0)) + (line (pt 329 0)(pt 329 217)) + (line (pt 0 217)(pt 329 217)) + (line (pt 0 0)(pt 0 217)) + (line (pt 56 108)(pt 215 108)) + (line (pt 56 125)(pt 215 125)) + (line (pt 56 143)(pt 215 143)) + (line (pt 56 161)(pt 215 161)) + (line (pt 56 179)(pt 215 179)) + (line (pt 56 108)(pt 56 179)) + (line (pt 82 108)(pt 82 179)(line_width 3)) + (line (pt 125 108)(pt 125 179)(line_width 3)) + (line (pt 170 108)(pt 170 179)(line_width 3)) + (line (pt 214 108)(pt 214 179)) + (line (pt 48 56)(pt 272 56)) + (line (pt 272 56)(pt 272 200)) + (line (pt 48 200)(pt 272 200)) + (line (pt 48 56)(pt 48 200)) + ) +) +(symbol + (rect 192 472 408 768) + (text "altpll_reconfig1" (rect 54 1 160 17)(font "Arial" (font_size 10))) + (text "i_programmable_clk" (rect 8 277 108 288)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "reconfig" (rect 0 0 46 13)(font "Arial" (font_size 8))) + (text "reconfig" (rect 20 32 66 45)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)) + ) + (port + (pt 0 56) + (input) + (text "read_param" (rect 0 0 69 13)(font "Arial" (font_size 8))) + (text "read_param" (rect 20 48 89 61)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)) + ) + (port + (pt 0 72) + (input) + (text "write_param" (rect 0 0 70 13)(font "Arial" (font_size 8))) + (text "write_param" (rect 20 64 90 77)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)) + ) + (port + (pt 0 96) + (input) + (text "data_in[8..0]" (rect 0 0 70 13)(font "Arial" (font_size 8))) + (text "data_in[8..0]" (rect 20 88 90 101)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "counter_type[3..0]" (rect 0 0 102 13)(font "Arial" (font_size 8))) + (text "counter_type[3..0]" (rect 20 104 122 117)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "counter_param[2..0]" (rect 0 0 114 13)(font "Arial" (font_size 8))) + (text "counter_param[2..0]" (rect 20 120 134 133)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "pll_scandataout" (rect 0 0 89 13)(font "Arial" (font_size 8))) + (text "pll_scandataout" (rect 20 160 109 173)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 16 168)) + ) + (port + (pt 0 184) + (input) + (text "pll_scandone" (rect 0 0 75 13)(font "Arial" (font_size 8))) + (text "pll_scandone" (rect 20 176 95 189)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 16 184)) + ) + (port + (pt 0 208) + (input) + (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) + (text "clock" (rect 20 200 51 213)(font "Arial" (font_size 8))) + (line (pt 0 208)(pt 16 208)) + ) + (port + (pt 0 224) + (input) + (text "reset" (rect 0 0 29 13)(font "Arial" (font_size 8))) + (text "reset" (rect 20 216 49 229)(font "Arial" (font_size 8))) + (line (pt 0 224)(pt 16 224)) + ) + (port + (pt 0 248) + (input) + (text "pll_areset_in" (rect 0 0 73 13)(font "Arial" (font_size 8))) + (text "pll_areset_in" (rect 20 240 93 253)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 16 248)) + ) + (port + (pt 216 40) + (output) + (text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8))) + (text "busy" (rect 171 32 200 45)(font "Arial" (font_size 8))) + (line (pt 216 40)(pt 200 40)) + ) + (port + (pt 216 96) + (output) + (text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 129 88 208 101)(font "Arial" (font_size 8))) + (line (pt 216 96)(pt 200 96)(line_width 3)) + ) + (port + (pt 216 152) + (output) + (text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 135 144 206 157)(font "Arial" (font_size 8))) + (line (pt 216 152)(pt 200 152)) + ) + (port + (pt 216 168) + (output) + (text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 141 160 205 173)(font "Arial" (font_size 8))) + (line (pt 216 168)(pt 200 168)) + ) + (port + (pt 216 200) + (output) + (text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 125 192 208 205)(font "Arial" (font_size 8))) + (line (pt 216 200)(pt 200 200)) + ) + (port + (pt 216 216) + (output) + (text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 117 208 210 221)(font "Arial" (font_size 8))) + (line (pt 216 216)(pt 200 216)) + ) + (port + (pt 216 248) + (output) + (text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 148 240 204 253)(font "Arial" (font_size 8))) + (line (pt 216 248)(pt 200 248)) + ) + (drawing + (line (pt 0 0)(pt 217 0)) + (line (pt 217 0)(pt 217 297)) + (line (pt 0 297)(pt 217 297)) + (line (pt 0 0)(pt 0 297)) + (line (pt 16 24)(pt 201 24)) + (line (pt 201 24)(pt 201 273)) + (line (pt 16 273)(pt 201 273)) + (line (pt 16 24)(pt 16 273)) + ) +) +(symbol + (rect 608 496 984 728) + (text "altpll4" (rect 168 1 210 17)(font "Arial" (font_size 10))) + (text "i_video_clk_pll" (rect 8 213 81 224)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 88 72)) + ) + (port + (pt 0 96) + (input) + (text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "areset" (rect 4 80 40 93)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 88 96)) + ) + (port + (pt 0 120) + (input) + (text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 104 48 117)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 88 120)) + ) + (port + (pt 0 144) + (input) + (text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 128 57 141)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 88 144)) + ) + (port + (pt 0 168) + (input) + (text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 152 68 165)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 88 168)) + ) + (port + (pt 0 192) + (input) + (text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 176 77 189)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 88 192)) + ) + (port + (pt 376 72) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 359 56 374 69)(font "Arial" (font_size 8))) + (line (pt 376 72)(pt 288 72)) + ) + (port + (pt 376 96) + (output) + (text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8))) + (text "scandataout" (rect 302 80 372 93)(font "Arial" (font_size 8))) + (line (pt 376 96)(pt 288 96)) + ) + (port + (pt 376 120) + (output) + (text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8))) + (text "scandone" (rect 317 104 373 117)(font "Arial" (font_size 8))) + (line (pt 376 120)(pt 288 120)) + ) + (port + (pt 376 144) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 335 128 372 141)(font "Arial" (font_size 8))) + (line (pt 376 144)(pt 288 144)) + ) + (drawing + (text "Cyclone III" (rect 301 214 352 225)(font "Arial" )) + (text "inclk0 frequency: 48.000 MHz" (rect 98 123 244 134)(font "Arial" )) + (text "Operation Mode: Normal" (rect 98 140 220 151)(font "Arial" )) + (text "Clk " (rect 99 167 119 178)(font "Arial" )) + (text "Ratio" (rect 125 167 152 178)(font "Arial" )) + (text "Ph (dg)" (rect 159 167 196 178)(font "Arial" )) + (text "DC (%)" (rect 204 167 241 178)(font "Arial" )) + (text "c0" (rect 103 185 115 196)(font "Arial" )) + (text "2/1" (rect 131 185 146 196)(font "Arial" )) + (text "0.00" (rect 167 185 190 196)(font "Arial" )) + (text "50.00" (rect 209 185 238 196)(font "Arial" )) + (line (pt 0 0)(pt 377 0)) + (line (pt 377 0)(pt 377 233)) + (line (pt 0 233)(pt 377 233)) + (line (pt 0 0)(pt 0 233)) + (line (pt 96 164)(pt 246 164)) + (line (pt 96 181)(pt 246 181)) + (line (pt 96 199)(pt 246 199)) + (line (pt 96 164)(pt 96 199)) + (line (pt 122 164)(pt 122 199)(line_width 3)) + (line (pt 156 164)(pt 156 199)(line_width 3)) + (line (pt 201 164)(pt 201 199)(line_width 3)) + (line (pt 245 164)(pt 245 199)) + (line (pt 88 56)(pt 288 56)) + (line (pt 288 56)(pt 288 216)) + (line (pt 88 216)(pt 288 216)) + (line (pt 88 56)(pt 88 216)) + ) +) +(block + (rect 1264 2344 1672 2904) + (text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input)) + (block_io "nFB_WR" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "FB_ADR[31..0]" (input)) + (block_io "PIC_INT" (input)) + (block_io "E0_INT" (input)) + (block_io "DVI_INT" (input)) + (block_io "nPCI_INTA" (input)) + (block_io "nPCI_INTB" (input)) + (block_io "nPCI_INTC" (input)) + (block_io "nPCI_INTD" (input)) + (block_io "nMFP_INT" (input)) + (block_io "nFB_OE" (input)) + (block_io "DSP_INT" (input)) + (block_io "VSYNC" (input)) + (block_io "HSYNC" (input)) + (block_io "DMA_DRQ" (input)) + (block_io "nIRQ[7..2]" (output)) + (block_io "INT_HANDLER_TA" (output)) + (block_io "ACP_CONF[31..0]" (output)) + (block_io "TIN0" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (mapper + (pt 0 136) + (bidir) + ) + (mapper + (pt 0 160) + (bidir) + ) + (mapper + (pt 0 184) + (bidir) + ) + (mapper + (pt 0 88) + (bidir) + ) + (mapper + (pt 0 112) + (bidir) + ) + (mapper + (pt 0 40) + (bidir) + ) + (mapper + (pt 408 56) + (bidir) + ) + (mapper + (pt 408 80) + (bidir) + ) + (mapper + (pt 0 256) + (bidir) + ) + (mapper + (pt 0 280) + (bidir) + ) + (mapper + (pt 0 304) + (bidir) + ) + (mapper + (pt 0 208) + (bidir) + ) + (mapper + (pt 0 64) + (bidir) + ) + (mapper + (pt 0 376) + (bidir) + ) + (mapper + (pt 0 400) + (bidir) + ) + (mapper + (pt 0 328) + (bidir) + ) + (mapper + (pt 0 352) + (bidir) + ) + (mapper + (pt 0 432) + (bidir) + ) + (mapper + (pt 0 456) + (bidir) + ) + (mapper + (pt 0 480) + (bidir) + ) + (mapper + (pt 0 504) + (bidir) + ) + (mapper + (pt 408 504) + (bidir) + ) + (mapper + (pt 0 528) + (bidir) + ) + (mapper + (pt 408 240) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) +) +(block + (rect 1264 -40 1672 736) + (text "video" (rect 5 5 36 18)(font "Arial" (font_size 8))) (text "i_video" (rect 5 762 41 773)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "nFB_CS3" (input)) + (block_io "nFB_WR" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nRSTO" (input)) + (block_io "nFB_OE" (input)) + (block_io "FB_ALE" (input)) + (block_io "DDRCLK[3..0]" (input)) + (block_io "DDR_SYNC_66M" (input)) + (block_io "CLK33M" (input)) + (block_io "CLK25M" (input)) + (block_io "CLK_VIDEO" (input)) + (block_io "VR_D[8..0]" (input)) + (block_io "VR_BUSY" (input)) + (block_io "VR_RD" (output)) + (block_io "VG[7..0]" (output)) + (block_io "VB[7..0]" (output)) + (block_io "VR[7..0]" (output)) + (block_io "nBLANK" (output)) + (block_io "VA[12..0]" (output)) + (block_io "nVWE" (output)) + (block_io "nVCAS" (output)) + (block_io "nVRAS" (output)) + (block_io "nVCS" (output)) + (block_io "VDM[3..0]" (output)) + (block_io "nPD_VGA" (output)) + (block_io "VCKE" (output)) + (block_io "VSYNC" (output)) + (block_io "HSYNC" (output)) + (block_io "nSYNC" (output)) + (block_io "VIDEO_TA" (output)) + (block_io "PIXEL_CLK" (output)) + (block_io "BA[1..0]" (output)) + (block_io "VIDEO_RECONFIG" (output)) + (block_io "VR_WR" (output)) + (block_io "VDQS[3..0]" (bidir)) + (block_io "FB_AD[31..0]" (bidir)) + (block_io "VD[31..0]" (bidir)) + (mapper + (pt 408 448) + (bidir) + ) + (mapper + (pt 408 496) + (bidir) + ) + (mapper + (pt 408 592) + (bidir) + ) + (mapper + (pt 408 352) + (bidir) + ) + (mapper + (pt 408 760) + (bidir) + ) + (mapper + (pt 408 72) + (bidir) + ) + (mapper + (pt 0 392) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 0 320) + (bidir) + ) + (mapper + (pt 0 344) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 408 128) + (bidir) + ) + (mapper + (pt 408 152) + (bidir) + ) + (mapper + (pt 408 176) + (bidir) + ) + (mapper + (pt 408 200) + (bidir) + ) + (mapper + (pt 408 224) + (bidir) + ) + (mapper + (pt 408 248) + (bidir) + ) + (mapper + (pt 408 272) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) + (mapper + (pt 0 416) + (bidir) + ) + (mapper + (pt 408 320) + (bidir) + ) + (mapper + (pt 408 472) + (bidir) + ) + (mapper + (pt 408 424) + (bidir) + ) + (mapper + (pt 408 400) + (bidir) + ) + (mapper + (pt 408 376) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 368) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 408 568) + (bidir) + ) + (mapper + (pt 408 520) + (bidir) + ) + (mapper + (pt 0 648) + (bidir) + ) + (mapper + (pt 0 672) + (bidir) + ) + (mapper + (pt 0 616) + (bidir) + ) + (mapper + (pt 0 528) + (bidir) + ) + (mapper + (pt 408 656) + (bidir) + ) + (mapper + (pt 408 640) + (bidir) + ) + (mapper + (pt 408 624) + (bidir) + ) + (mapper + (pt 0 512) + (bidir) + ) +) +(block + (rect 1264 744 1672 2264) + (text "falconio_sdcard_ide_cf" (rect 5 5 135 18)(font "Arial" (font_size 8))) (text "i_falcon_io_sdcard_ide_cf" (rect 5 1506 133 1517)(font "Arial" )) (block_io "CLK33M" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "CLK2M" (input)) + (block_io "CLK500k" (input)) + (block_io "nFB_CS1" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nFB_BURST" (input)) + (block_io "FB_ADR[31..0]" (input)) + (block_io "LP_BUSY" (input)) + (block_io "nACSI_DRQ" (input)) + (block_io "nACSI_INT" (input)) + (block_io "nSCSI_DRQ" (input)) + (block_io "nSCSI_MSG" (input)) + (block_io "MIDI_IN" (input)) + (block_io "RxD" (input)) + (block_io "CTS" (input)) + (block_io "RI" (input)) + (block_io "DCD" (input)) + (block_io "AMKB_RX" (input)) + (block_io "PIC_AMKB_RX" (input)) + (block_io "IDE_RDY" (input)) + (block_io "IDE_INT" (input)) + (block_io "WP_CS_CARD" (input)) + (block_io "nINDEX" (input)) + (block_io "TRACK00" (input)) + (block_io "nRD_DATA" (input)) + (block_io "nDCHG" (input)) + (block_io "SD_DATA0" (input)) + (block_io "SD_DATA1" (input)) + (block_io "SD_DATA2" (input)) + (block_io "SD_CARD_DEDECT" (input)) + (block_io "SD_WP" (input)) + (block_io "nDACK0" (input)) + (block_io "nFB_WR" (input)) + (block_io "WP_CF_CARD" (input)) + (block_io "nWP" (input)) + (block_io "nFB_CS2" (input)) + (block_io "nRSTO" (input)) + (block_io "nSCSI_C_D" (input)) + (block_io "nSCSI_I_O" (input)) + (block_io "CLK2M4576" (input)) + (block_io "nFB_OE" (input)) + (block_io "VSYNC" (input)) + (block_io "HSYNC" (input)) + (block_io "DSP_INT" (input)) + (block_io "nBLANK" (input)) + (block_io "FDC_CLK" (input)) + (block_io "FB_ALE" (input)) + (block_io "ACP_CONF[31..24]" (input)) + (block_io "HD_DD" (input)) + (block_io "nIDE_CS1" (output)) + (block_io "nIDE_CS0" (output)) + (block_io "LP_STR" (output)) + (block_io "LP_DIR" (output)) + (block_io "nACSI_ACK" (output)) + (block_io "nACSI_RESET" (output)) + (block_io "nACSI_CS" (output)) + (block_io "ACSI_DIR" (output)) + (block_io "ACSI_A1" (output)) + (block_io "nSCSI_ACK" (output)) + (block_io "nSCSI_ATN" (output)) + (block_io "SCSI_DIR" (output)) + (block_io "SD_CLK" (output)) + (block_io "YM_QA" (output)) + (block_io "YM_QC" (output)) + (block_io "YM_QB" (output)) + (block_io "nSDSEL" (output)) + (block_io "STEP" (output)) + (block_io "MOT_ON" (output)) + (block_io "nRP_LDS" (output)) + (block_io "nRP_UDS" (output)) + (block_io "nROM4" (output)) + (block_io "nROM3" (output)) + (block_io "nCF_CS1" (output)) + (block_io "nCF_CS0" (output)) + (block_io "nIDE_RD" (output)) + (block_io "nIDE_WR" (output)) + (block_io "AMKB_TX" (output)) + (block_io "IDE_RES" (output)) + (block_io "DTR" (output)) + (block_io "RTS" (output)) + (block_io "TxD" (output)) + (block_io "MIDI_OLR" (output)) + (block_io "MIDI_TLR" (output)) + (block_io "nDREQ0" (output)) + (block_io "DSA_D" (output)) + (block_io "nMFP_INT" (output)) + (block_io "FALCON_IO_TA" (output)) + (block_io "STEP_DIR" (output)) + (block_io "WR_DATA" (output)) + (block_io "WR_GATE" (output)) + (block_io "DMA_DRQ" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (block_io "LP_D[7..0]" (bidir)) + (block_io "ACSI_D[7..0]" (bidir)) + (block_io "SCSI_D[7..0]" (bidir)) + (block_io "SCSI_PAR" (bidir)) + (block_io "nSCSI_SEL" (bidir)) + (block_io "nSCSI_BUSY" (bidir)) + (block_io "nSCSI_RST" (bidir)) + (block_io "SD_CD_DATA3" (bidir)) + (block_io "SD_CDM_D1" (bidir)) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 408 96) + (bidir) + ) + (mapper + (pt 408 120) + (bidir) + ) + (mapper + (pt 408 72) + (bidir) + ) + (mapper + (pt 408 152) + (bidir) + ) + (mapper + (pt 408 200) + (bidir) + ) + (mapper + (pt 408 224) + (bidir) + ) + (mapper + (pt 408 248) + (bidir) + ) + (mapper + (pt 408 272) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) + (mapper + (pt 408 424) + (bidir) + ) + (mapper + (pt 408 352) + (bidir) + ) + (mapper + (pt 408 328) + (bidir) + ) + (mapper + (pt 408 448) + (bidir) + ) + (mapper + (pt 408 400) + (bidir) + ) + (mapper + (pt 408 376) + (bidir) + ) + (mapper + (pt 408 472) + (bidir) + ) + (mapper + (pt 408 496) + (bidir) + ) + (mapper + (pt 408 608) + (bidir) + ) + (mapper + (pt 408 632) + (bidir) + ) + (mapper + (pt 408 528) + (bidir) + ) + (mapper + (pt 408 552) + (bidir) + ) + (mapper + (pt 408 584) + (bidir) + ) + (mapper + (pt 0 624) + (bidir) + ) + (mapper + (pt 0 656) + (bidir) + ) + (mapper + (pt 0 680) + (bidir) + ) + (mapper + (pt 0 704) + (bidir) + ) + (mapper + (pt 0 728) + (bidir) + ) + (mapper + (pt 0 752) + (bidir) + ) + (mapper + (pt 0 776) + (bidir) + ) + (mapper + (pt 408 664) + (bidir) + ) + (mapper + (pt 0 808) + (bidir) + ) + (mapper + (pt 0 832) + (bidir) + ) + (mapper + (pt 408 696) + (bidir) + ) + (mapper + (pt 408 720) + (bidir) + ) + (mapper + (pt 408 744) + (bidir) + ) + (mapper + (pt 408 768) + (bidir) + ) + (mapper + (pt 408 792) + (bidir) + ) + (mapper + (pt 408 816) + (bidir) + ) + (mapper + (pt 408 840) + (bidir) + ) + (mapper + (pt 0 856) + (bidir) + ) + (mapper + (pt 408 872) + (bidir) + ) + (mapper + (pt 408 896) + (bidir) + ) + (mapper + (pt 408 920) + (bidir) + ) + (mapper + (pt 408 944) + (bidir) + ) + (mapper + (pt 0 912) + (bidir) + ) + (mapper + (pt 0 936) + (bidir) + ) + (mapper + (pt 0 960) + (bidir) + ) + (mapper + (pt 0 984) + (bidir) + ) + (mapper + (pt 0 1008) + (bidir) + ) + (mapper + (pt 408 976) + (bidir) + ) + (mapper + (pt 408 1000) + (bidir) + ) + (mapper + (pt 408 1072) + (bidir) + ) + (mapper + (pt 408 1096) + (bidir) + ) + (mapper + (pt 408 1176) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 408 1256) + (bidir) + ) + (mapper + (pt 0 1040) + (bidir) + ) + (mapper + (pt 0 1064) + (bidir) + ) + (mapper + (pt 0 1088) + (bidir) + ) + (mapper + (pt 0 1112) + (bidir) + ) + (mapper + (pt 0 1136) + (bidir) + ) + (mapper + (pt 0 432) + (bidir) + ) + (mapper + (pt 0 464) + (bidir) + ) + (mapper + (pt 0 488) + (bidir) + ) + (mapper + (pt 0 520) + (bidir) + ) + (mapper + (pt 0 544) + (bidir) + ) + (mapper + (pt 0 568) + (bidir) + ) + (mapper + (pt 0 592) + (bidir) + ) + (mapper + (pt 408 1424) + (bidir) + ) + (mapper + (pt 0 320) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 344) + (bidir) + ) + (mapper + (pt 0 1168) + (bidir) + ) + (mapper + (pt 0 1192) + (bidir) + ) + (mapper + (pt 0 368) + (bidir) + ) + (mapper + (pt 0 392) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 1216) + (bidir) + ) + (mapper + (pt 408 48) + (bidir) + ) + (mapper + (pt 408 16) + (bidir) + ) + (mapper + (pt 0 1240) + (bidir) + ) + (mapper + (pt 408 1304) + (bidir) + ) + (mapper + (pt 408 1200) + (bidir) + ) + (mapper + (pt 408 1344) + (bidir) + ) + (mapper + (pt 408 1280) + (bidir) + ) + (mapper + (pt 408 1224) + (bidir) + ) + (mapper + (pt 408 1120) + (bidir) + ) + (mapper + (pt 408 1048) + (bidir) + ) + (mapper + (pt 408 1024) + (bidir) + ) + (mapper + (pt 0 32) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 408 1368) + (bidir) + ) + (mapper + (pt 0 1264) + (bidir) + ) + (mapper + (pt 0 1336) + (bidir) + ) + (mapper + (pt 0 888) + (bidir) + ) +) +(block + (rect 1264 2944 1672 3560) + (text "dsp" (rect 5 5 27 18)(font "Arial" (font_size 8))) (text "i_dsp" (rect 5 602 33 613)(font "Arial" )) (block_io "CLK33M" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "nFB_OE" (input)) + (block_io "nFB_WR" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nFB_BURST" (input)) + (block_io "FB_ADR[31..0]" (input)) + (block_io "nRSTO" (input)) + (block_io "nFB_CS3" (input)) + (block_io "nSRCS" (output)) + (block_io "nSRBLE" (output)) + (block_io "nSRBHE" (output)) + (block_io "nSRWE" (output)) + (block_io "nSROE" (output)) + (block_io "DSP_INT" (output)) + (block_io "DSP_TA" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (block_io "IO[17..0]" (bidir)) + (block_io "SRD[15..0]" (bidir)) + (mapper + (pt 408 416) + (bidir) + ) + (mapper + (pt 408 392) + (bidir) + ) + (mapper + (pt 408 368) + (bidir) + ) + (mapper + (pt 408 320) + (bidir) + ) + (mapper + (pt 408 440) + (bidir) + ) + (mapper + (pt 408 344) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) + (mapper + (pt 408 40) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 408 72) + (bidir) + ) + (mapper + (pt 408 576) + (bidir) + ) + (mapper + (pt 0 320) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) +) +(connector + (text "FB_AD[31..0]" (rect 1682 776 1748 787)(font "Arial" )) + (pt 1832 792) + (pt 1672 792) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 1072 1220 1083)(font "Arial" )) + (pt 1112 1088) + (pt 1264 1088) + (bus) +) +(connector + (text "MAIN_CLK" (rect 1162 784 1219 795)(font "Arial" )) + (pt 1152 800) + (pt 1264 800) +) +(connector + (text "CLK2M" (rect 1202 808 1240 819)(font "Arial" )) + (pt 1192 824) + (pt 1264 824) +) +(connector + (text "CLK500k" (rect 1202 832 1249 843)(font "Arial" )) + (pt 1192 848) + (pt 1264 848) +) +(connector + (text "LP_DIR" (rect 1682 848 1722 859)(font "Arial" )) + (pt 1672 864) + (pt 1832 864) +) +(connector + (text "LP_STR" (rect 1682 824 1725 835)(font "Arial" )) + (pt 1672 840) + (pt 1832 840) +) +(connector + (text "nACSI_ACK" (rect 1682 928 1745 939)(font "Arial" )) + (pt 1672 944) + (pt 1832 944) +) +(connector + (text "nACSI_RESET" (rect 1682 952 1758 963)(font "Arial" )) + (pt 1672 968) + (pt 1832 968) +) +(connector + (text "nACSI_CS" (rect 1682 976 1737 987)(font "Arial" )) + (pt 1672 992) + (pt 1832 992) +) +(connector + (text "ACSI_DIR" (rect 1682 1000 1733 1011)(font "Arial" )) + (pt 1672 1016) + (pt 1832 1016) +) +(connector + (text "ACSI_A1" (rect 1682 1024 1728 1035)(font "Arial" )) + (pt 1672 1040) + (pt 1832 1040) +) +(connector + (text "nSCSI_ATN" (rect 1682 1128 1742 1139)(font "Arial" )) + (pt 1672 1144) + (pt 1840 1144) +) +(connector + (text "SCSI_DIR" (rect 1682 1152 1733 1163)(font "Arial" )) + (pt 1672 1168) + (pt 1840 1168) +) +(connector + (text "nSCSI_RST" (rect 1682 1176 1743 1187)(font "Arial" )) + (pt 1672 1192) + (pt 1840 1192) +) +(connector + (text "nSCSI_SEL" (rect 1680 1200 1740 1211)(font "Arial" )) + (pt 1672 1216) + (pt 1840 1216) +) +(connector + (text "nSCSI_BUSY" (rect 1682 1224 1752 1235)(font "Arial" )) + (pt 1672 1240) + (pt 1840 1240) +) +(connector + (text "TxD" (rect 1682 1312 1704 1323)(font "Arial" )) + (pt 1672 1328) + (pt 1840 1328) +) +(connector + (text "RTS" (rect 1682 1336 1705 1347)(font "Arial" )) + (pt 1672 1352) + (pt 1840 1352) +) +(connector + (text "DTR" (rect 1680 1360 1704 1371)(font "Arial" )) + (pt 1672 1376) + (pt 1848 1376) +) +(connector + (text "IDE_RES" (rect 1682 1424 1730 1435)(font "Arial" )) + (pt 1672 1440) + (pt 1848 1440) +) +(connector + (text "nIDE_CS0" (rect 1682 1448 1736 1459)(font "Arial" )) + (pt 1672 1464) + (pt 1848 1464) +) +(connector + (text "nIDE_CS1" (rect 1682 1472 1735 1483)(font "Arial" )) + (pt 1672 1488) + (pt 1856 1488) +) +(connector + (text "nIDE_WR" (rect 1682 1496 1732 1507)(font "Arial" )) + (pt 1672 1512) + (pt 1848 1512) +) +(connector + (text "nIDE_RD" (rect 1682 1520 1730 1531)(font "Arial" )) + (pt 1672 1536) + (pt 1848 1536) +) +(connector + (text "nCF_CS0" (rect 1682 1544 1731 1555)(font "Arial" )) + (pt 1672 1560) + (pt 1848 1560) +) +(connector + (text "nCF_CS1" (rect 1682 1568 1730 1579)(font "Arial" )) + (pt 1672 1584) + (pt 1848 1584) +) +(connector + (text "nSDSEL" (rect 1682 1848 1725 1859)(font "Arial" )) + (pt 1672 1864) + (pt 1856 1864) +) +(connector + (text "nDREQ0" (rect 1682 2152 1728 2163)(font "Arial" )) + (pt 1672 2168) + (pt 1856 2168) +) +(connector + (text "SD_CLK" (rect 1682 2032 1728 2043)(font "Arial" )) + (pt 1856 2048) + (pt 1672 2048) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 2536 1220 2547)(font "Arial" )) + (pt 1112 2552) + (pt 1264 2552) + (bus) +) +(connector + (text "nFB_WR" (rect 1162 2416 1208 2427)(font "Arial" )) + (pt 1152 2432) + (pt 1264 2432) +) +(connector + (text "nFB_CS1" (rect 1154 2440 1202 2451)(font "Arial" )) + (pt 1152 2456) + (pt 1264 2456) +) +(connector + (text "FB_SIZE0" (rect 1154 2488 1205 2499)(font "Arial" )) + (pt 1152 2504) + (pt 1264 2504) +) +(connector + (text "FB_SIZE1" (rect 1154 2512 1204 2523)(font "Arial" )) + (pt 1152 2528) + (pt 1264 2528) +) +(connector + (text "MAIN_CLK" (rect 1162 2368 1219 2379)(font "Arial" )) + (pt 1152 2384) + (pt 1264 2384) +) +(connector + (text "nFB_CS2" (rect 1162 2464 1211 2475)(font "Arial" )) + (pt 1152 2480) + (pt 1264 2480) +) +(connector + (text "FB_AD[31..0]" (rect 1682 2384 1748 2395)(font "Arial" )) + (pt 1832 2400) + (pt 1672 2400) + (bus) +) +(connector + (text "nSCSI_ACK" (rect 1682 1104 1745 1115)(font "Arial" )) + (pt 1672 1120) + (pt 1840 1120) +) +(connector + (text "SCSI_PAR" (rect 1682 1080 1738 1091)(font "Arial" )) + (pt 1672 1096) + (pt 1840 1096) +) +(connector + (text "MIDI_OLR" (rect 1762 1256 1816 1267)(font "Arial" )) + (pt 1672 1272) + (pt 1920 1272) +) +(connector + (text "MIDI_TLR" (rect 1770 1280 1821 1291)(font "Arial" )) + (pt 1672 1296) + (pt 1920 1296) +) +(connector + (text "nROM3" (rect 1754 1600 1794 1611)(font "Arial" )) + (pt 1672 1616) + (pt 1920 1616) +) +(connector + (text "nROM4" (rect 1754 1624 1794 1635)(font "Arial" )) + (pt 1672 1640) + (pt 1920 1640) +) +(connector + (text "nRP_UDS" (rect 1744 1648 1797 1659)(font "Arial" )) + (pt 1672 1664) + (pt 1920 1664) +) +(connector + (text "nRP_LDS" (rect 1746 1672 1796 1683)(font "Arial" )) + (pt 1672 1688) + (pt 1920 1688) +) +(connector + (text "YM_QA" (rect 1762 1904 1803 1915)(font "Arial" )) + (pt 1672 1920) + (pt 1928 1920) +) +(connector + (text "YM_QB" (rect 1762 1928 1802 1939)(font "Arial" )) + (pt 1672 1944) + (pt 1928 1944) +) +(connector + (text "YM_QC" (rect 1762 1952 1803 1963)(font "Arial" )) + (pt 1672 1968) + (pt 1928 1968) +) +(connector + (text "SD_CARD_DEDECT" (rect 1138 1840 1244 1851)(font "Arial" )) + (pt 1264 1856) + (pt 1128 1856) +) +(connector + (text "SD_CD_DATA3" (rect 1682 1984 1762 1995)(font "Arial" )) + (pt 1672 2000) + (pt 1856 2000) +) +(connector + (text "SD_CDM_D1" (rect 1682 2008 1749 2019)(font "Arial" )) + (pt 1672 2024) + (pt 1856 2024) +) +(connector + (text "DSA_D" (rect 1682 1704 1720 1715)(font "Arial" )) + (pt 1672 1720) + (pt 1856 1720) +) +(connector + (text "nRSTO" (rect 1170 1120 1208 1131)(font "Arial" )) + (pt 1264 1136) + (pt 1160 1136) +) +(connector + (text "nIRQ[7..2]" (rect 1682 2408 1732 2419)(font "Arial" )) + (pt 1672 2424) + (pt 1832 2424) + (bus) +) +(connector + (text "CLK2M4576" (rect 1202 856 1264 867)(font "Arial" )) + (pt 1192 872) + (pt 1264 872) +) +(connector + (text "nFB_OE" (rect 1170 2392 1213 2403)(font "Arial" )) + (pt 1264 2408) + (pt 1160 2408) +) +(connector + (text "nMFP_INT" (rect 1162 2760 1217 2771)(font "Arial" )) + (pt 1152 2776) + (pt 1264 2776) +) +(connector + (text "nMFP_INT" (rect 1682 2072 1737 2083)(font "Arial" )) + (pt 1672 2088) + (pt 1784 2088) +) +(connector + (text "DSP_INT" (rect 1130 2832 1178 2843)(font "Arial" )) + (pt 1264 2848) + (pt 1120 2848) +) +(connector + (text "CLK500k" (rect 482 2040 529 2051)(font "Arial" )) + (pt 472 2056) + (pt 544 2056) +) +(connector + (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) + (pt 1672 1072) + (pt 1936 1072) + (bus) +) +(connector + (text "ACSI_D[7..0]" (rect 1754 880 1818 891)(font "Arial" )) + (pt 1672 896) + (pt 1904 896) + (bus) +) +(connector + (text "LP_D[7..0]" (rect 1810 800 1863 811)(font "Arial" )) + (pt 1672 816) + (pt 1960 816) + (bus) +) +(connector + (text "TIMEBASE[17]" (rect 354 2120 428 2131)(font "Arial" )) + (pt 440 2136) + (pt 344 2136) +) +(connector + (text "TIMEBASE[17..0]" (rect 706 2048 792 2059)(font "Arial" )) + (pt 688 2064) + (pt 808 2064) + (bus) +) +(connector + (text "HSYNC" (rect 1130 2784 1170 2795)(font "Arial" )) + (pt 1264 2800) + (pt 1120 2800) +) +(connector + (text "VSYNC" (rect 1130 2808 1170 2819)(font "Arial" )) + (pt 1264 2824) + (pt 1120 2824) +) +(connector + (text "VSYNC" (rect 1130 1920 1170 1931)(font "Arial" )) + (pt 1264 1936) + (pt 1120 1936) +) +(connector + (text "HSYNC" (rect 1130 1896 1170 1907)(font "Arial" )) + (pt 1264 1912) + (pt 1120 1912) +) +(connector + (pt 488 2136) + (pt 608 2136) +) +(connector + (text "nFB_TA" (rect 1946 720 1989 731)(font "Arial" )) + (pt 1944 736) + (pt 2056 736) +) +(connector + (text "INT_HANDLER_TA" (rect 1682 2832 1781 2843)(font "Arial" )) + (pt 1672 2848) + (pt 1808 2848) +) +(connector + (text "FALCON_IO_TA" (rect 1682 744 1766 755)(font "Arial" )) + (pt 1672 760) + (pt 1880 760) +) +(connector + (text "INT_HANDLER_TA" (rect 1810 728 1909 739)(font "Arial" )) + (pt 1880 744) + (pt 1800 744) +) +(connector + (text "DSP_TA" (rect 1810 712 1856 723)(font "Arial" )) + (pt 1880 728) + (pt 1800 728) +) +(connector + (pt 2680 888) + (pt 2712 888) +) +(connector + (pt 2632 888) + (pt 2504 888) +) +(connector + (pt 2504 888) + (pt 2504 760) +) +(connector + (text "DDRCLK[0]" (rect 2450 744 2507 755)(font "Arial" )) + (pt 2440 760) + (pt 2504 760) +) +(connector + (pt 2504 760) + (pt 2536 760) +) +(connector + (text "PIXEL_CLK" (rect 2394 -64 2455 -53)(font "Arial" )) + (pt 2384 -48) + (pt 2464 -48) +) +(connector + (text "PIXEL_CLK" (rect 2394 56 2455 67)(font "Arial" )) + (pt 2384 72) + (pt 2464 72) +) +(connector + (text "nBLANK" (rect 2394 24 2438 35)(font "Arial" )) + (pt 2464 40) + (pt 2384 40) +) +(connector + (text "nBLANK" (rect 2394 40 2438 51)(font "Arial" )) + (pt 2464 56) + (pt 2384 56) +) +(connector + (pt 2696 -80) + (pt 2712 -80) +) +(connector + (pt 2696 40) + (pt 2712 40) +) +(connector + (text "PIXEL_CLK" (rect 1826 -48 1887 -37)(font "Arial" )) + (pt 1816 -32) + (pt 1896 -32) +) +(connector + (pt 2128 -64) + (pt 2136 -64) +) +(connector + (text "PIXEL_CLK" (rect 2394 184 2455 195)(font "Arial" )) + (pt 2384 200) + (pt 2464 200) +) +(connector + (pt 2456 168) + (pt 2456 136) +) +(connector + (pt 2464 168) + (pt 2456 168) +) +(connector + (pt 2456 136) + (pt 2400 136) +) +(connector + (pt 2464 184) + (pt 2440 184) +) +(connector + (pt 2712 168) + (pt 2696 168) +) +(connector + (pt 2440 160) + (pt 2424 160) +) +(connector + (pt 2440 184) + (pt 2440 160) +) +(connector + (text "nBLANK" (rect 1154 1968 1198 1979)(font "Arial" )) + (pt 1264 1984) + (pt 1144 1984) +) +(connector + (text "DSP_INT" (rect 1154 1944 1202 1955)(font "Arial" )) + (pt 1264 1960) + (pt 1144 1960) +) +(connector + (text "STEP_DIR" (rect 1682 1752 1737 1763)(font "Arial" )) + (pt 1672 1768) + (pt 1856 1768) +) +(connector + (pt 1904 1768) + (pt 2136 1768) +) +(connector + (pt 1904 1816) + (pt 2136 1816) +) +(connector + (text "WR_DATA" (rect 1682 1800 1738 1811)(font "Arial" )) + (pt 1672 1816) + (pt 1856 1816) +) +(connector + (text "DMA_DRQ" (rect 1130 2856 1186 2867)(font "Arial" )) + (pt 1264 2872) + (pt 1120 2872) +) +(connector + (text "DMA_DRQ" (rect 1682 2096 1738 2107)(font "Arial" )) + (pt 1784 2112) + (pt 1672 2112) +) +(connector + (text "FDC_CLK" (rect 1202 880 1255 891)(font "Arial" )) + (pt 1192 896) + (pt 1264 896) +) +(connector + (text "MOT_ON" (rect 1626 1728 1673 1739)(font "Arial" )) + (pt 1672 1744) + (pt 1800 1744) +) +(connector + (pt 1848 1744) + (pt 2136 1744) +) +(connector + (text "STEP" (rect 1626 1776 1656 1787)(font "Arial" )) + (pt 1672 1792) + (pt 1800 1792) +) +(connector + (pt 1848 1792) + (pt 2136 1792) +) +(connector + (text "WR_GATE" (rect 1690 1824 1746 1835)(font "Arial" )) + (pt 1672 1840) + (pt 1800 1840) +) +(connector + (pt 1848 1840) + (pt 2136 1840) +) +(connector + (text "FB_ALE" (rect 1186 1992 1228 2003)(font "Arial" )) + (pt 1144 2008) + (pt 1264 2008) +) +(connector + (text "AMKB_TX" (rect 1946 1392 2000 1403)(font "Arial" )) + (pt 1672 1408) + (pt 2112 1408) +) +(connector + (pt 440 248) + (pt 400 248) +) +(connector + (text "FB_AD[31..0]" (rect 370 1352 436 1363)(font "Arial" )) + (pt 352 1368) + (pt 464 1368) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 642 1376 716 1387)(font "Arial" )) + (pt 608 1392) + (pt 760 1392) + (bus) +) +(connector + (text "DDR_SYNC_66M" (rect 378 1368 467 1379)(font "Arial" )) + (pt 368 1384) + (pt 464 1384) +) +(connector + (text "ACP_CONF[31..0]" (rect 1682 2568 1772 2579)(font "Arial" )) + (pt 1672 2584) + (pt 1832 2584) + (bus) +) +(connector + (text "ACP_CONF[31..24]" (rect 1146 2064 1242 2075)(font "Arial" )) + (pt 1136 2080) + (pt 1264 2080) + (bus) +) +(connector + (text "TIN0" (rect 1682 2624 1707 2635)(font "Arial" )) + (pt 1832 2640) + (pt 1672 2640) +) +(connector + (pt 1896 -48) + (pt 1856 -48) +) +(connector + (pt 1856 -48) + (pt 1856 -64) +) +(connector + (pt 1856 -64) + (pt 1896 -64) +) +(connector + (pt 2464 -64) + (pt 2424 -64) +) +(connector + (pt 2424 -80) + (pt 2424 -64) +) +(connector + (pt 408 672) + (pt 472 672) +) +(connector + (text "VIDEO_RECONFIG" (rect 74 496 174 507)(font "Arial" )) + (pt 192 512) + (pt 64 512) +) +(connector + (pt 408 640) + (pt 472 640) +) +(connector + (pt 408 624) + (pt 512 624) +) +(connector + (text "VR_D[8..0]" (rect 418 552 472 563)(font "Arial" )) + (pt 496 568) + (pt 408 568) + (bus) +) +(connector + (text "MAIN_CLK" (rect 122 664 179 675)(font "Arial" )) + (pt 112 680) + (pt 192 680) +) +(connector + (pt 536 720) + (pt 408 720) +) +(connector + (pt 1064 808) + (pt 1064 616) +) +(connector + (pt 1072 816) + (pt 1072 592) +) +(connector + (pt 472 672) + (pt 472 664) +) +(connector + (pt 472 640) + (pt 472 616) +) +(connector + (pt 512 624) + (pt 512 640) +) +(connector + (pt 536 720) + (pt 536 592) +) +(connector + (pt 536 592) + (pt 608 592) +) +(connector + (pt 472 616) + (pt 608 616) +) +(connector + (pt 512 640) + (pt 608 640) +) +(connector + (pt 472 664) + (pt 608 664) +) +(connector + (pt 408 688) + (pt 608 688) +) +(connector + (pt 984 592) + (pt 1072 592) +) +(connector + (pt 984 616) + (pt 1064 616) +) +(connector + (text "FB_ADR[5..2]" (rect 82 568 150 579)(font "Arial" )) + (pt 192 584) + (pt 72 584) + (bus) +) +(connector + (pt 1064 808) + (pt 80 808) +) +(connector + (pt 192 656) + (pt 80 656) +) +(connector + (pt 80 656) + (pt 80 808) +) +(connector + (pt 1072 816) + (pt 72 816) +) +(connector + (pt 192 640) + (pt 72 640) +) +(connector + (pt 72 640) + (pt 72 816) +) +(connector + (text "FB_ADR[8..6]" (rect 82 584 150 595)(font "Arial" )) + (pt 192 600) + (pt 72 600) + (bus) +) +(connector + (text "VR_RD" (rect 98 512 136 523)(font "Arial" )) + (pt 64 528) + (pt 192 528) +) +(connector + (text "VR_WR" (rect 98 528 139 539)(font "Arial" )) + (pt 64 544) + (pt 192 544) +) +(connector + (text "VDQS[3..0]" (rect 1674 504 1730 515)(font "Arial" )) + (pt 2040 544) + (pt 1960 544) + (bus) +) +(connector + (text "VDM[3..0]" (rect 1682 528 1731 539)(font "Arial" )) + (pt 1944 568) + (pt 1888 568) + (bus) +) +(connector + (text "VR_BUSY" (rect 418 496 472 507)(font "Arial" )) + (pt 408 512) + (pt 480 512) +) +(connector + (text "nRSTO" (rect -86 680 -48 691)(font "Arial" )) + (pt -96 696) + (pt -16 696) +) +(connector + (pt 32 696) + (pt 192 696) +) +(connector + (text "FB_AD[24..16]" (rect 82 552 155 563)(font "Arial" )) + (pt 72 568) + (pt 192 568) + (bus) +) +(connector + (text "CLK500k" (rect 802 232 849 243)(font "Arial" )) + (pt 768 248) + (pt 864 248) +) +(connector + (text "CLK2M4576" (rect 802 256 864 267)(font "Arial" )) + (pt 768 272) + (pt 864 272) +) +(connector + (text "CLK24M576" (rect 802 280 864 291)(font "Arial" )) + (pt 768 296) + (pt 864 296) +) +(connector + (text "nRSTO" (rect 1018 424 1056 435)(font "Arial" )) + (pt 1008 440) + (pt 1096 440) +) +(connector + (pt 768 320) + (pt 872 320) +) +(connector + (pt 872 432) + (pt 944 432) +) +(connector + (pt 840 448) + (pt 944 448) +) +(connector + (pt 872 320) + (pt 872 432) +) +(connector + (text "HSYNC" (rect 2314 -96 2354 -85)(font "Arial" )) + (pt 2304 -80) + (pt 2424 -80) +) +(connector + (pt 2424 -80) + (pt 2464 -80) +) +(connector + (text "VSYNC" (rect 1746 -80 1786 -69)(font "Arial" )) + (pt 1736 -64) + (pt 1856 -64) +) +(connector + (text "FB_AD[31..0]" (rect 1682 2968 1748 2979)(font "Arial" )) + (pt 1832 2984) + (pt 1672 2984) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 3224 1220 3235)(font "Arial" )) + (pt 1112 3240) + (pt 1264 3240) + (bus) +) +(connector + (text "MAIN_CLK" (rect 1162 3008 1219 3019)(font "Arial" )) + (pt 1152 3024) + (pt 1264 3024) +) +(connector + (text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" )) + (pt 1264 3072) + (pt 1160 3072) +) +(connector + (text "nFB_CS1" (rect 1162 3080 1210 3091)(font "Arial" )) + (pt 1264 3096) + (pt 1160 3096) +) +(connector + (text "nFB_CS2" (rect 1170 3104 1219 3115)(font "Arial" )) + (pt 1264 3120) + (pt 1160 3120) +) +(connector + (text "FB_SIZE0" (rect 1162 3152 1213 3163)(font "Arial" )) + (pt 1264 3168) + (pt 1160 3168) +) +(connector + (text "FB_SIZE1" (rect 1162 3176 1212 3187)(font "Arial" )) + (pt 1264 3192) + (pt 1160 3192) +) +(connector + (text "nFB_BURST" (rect 1162 3200 1226 3211)(font "Arial" )) + (pt 1264 3216) + (pt 1160 3216) +) +(connector + (text "nRSTO" (rect 1170 3248 1208 3259)(font "Arial" )) + (pt 1264 3264) + (pt 1160 3264) +) +(connector + (text "nFB_OE" (rect 1170 3032 1213 3043)(font "Arial" )) + (pt 1264 3048) + (pt 1160 3048) +) +(connector + (text "IO[17..0]" (rect 1962 3224 2004 3235)(font "Arial" )) + (pt 2104 3240) + (pt 1672 3240) + (bus) +) +(connector + (text "SRD[15..0]" (rect 1802 3248 1856 3259)(font "Arial" )) + (pt 1944 3264) + (pt 1672 3264) + (bus) +) +(connector + (text "nSRCS" (rect 1682 3272 1720 3283)(font "Arial" )) + (pt 1824 3288) + (pt 1672 3288) +) +(connector + (text "nSRBLE" (rect 1682 3296 1725 3307)(font "Arial" )) + (pt 1824 3312) + (pt 1672 3312) +) +(connector + (text "nSRBHE" (rect 1682 3320 1728 3331)(font "Arial" )) + (pt 1824 3336) + (pt 1672 3336) +) +(connector + (text "nSRWE" (rect 1682 3344 1723 3355)(font "Arial" )) + (pt 1824 3360) + (pt 1672 3360) +) +(connector + (text "nSROE" (rect 1682 3368 1720 3379)(font "Arial" )) + (pt 1824 3384) + (pt 1672 3384) +) +(connector + (text "DSP_INT" (rect 1682 3000 1730 3011)(font "Arial" )) + (pt 1816 3016) + (pt 1672 3016) +) +(connector + (text "DSP_TA" (rect 1682 3504 1728 3515)(font "Arial" )) + (pt 1672 3520) + (pt 1792 3520) +) +(connector + (text "nFB_CS3" (rect 1170 3128 1219 3139)(font "Arial" )) + (pt 1264 3144) + (pt 1160 3144) +) +(connector + (text "MAIN_CLK" (rect 1210 760 1267 771)(font "Arial" )) + (pt 1200 776) + (pt 1264 776) +) +(connector + (text "MAIN_CLK" (rect 1210 2984 1267 2995)(font "Arial" )) + (pt 1200 3000) + (pt 1264 3000) +) +(connector + (text "DDRCLK[0]" (rect 770 -296 827 -285)(font "Arial" )) + (pt 760 -280) + (pt 856 -280) +) +(connector + (text "DDRCLK[1]" (rect 770 -272 827 -261)(font "Arial" )) + (pt 760 -256) + (pt 856 -256) +) +(connector + (text "DDRCLK[2]" (rect 770 -248 827 -237)(font "Arial" )) + (pt 760 -232) + (pt 856 -232) +) +(connector + (text "DDRCLK[3]" (rect 770 -224 827 -213)(font "Arial" )) + (pt 760 -208) + (pt 856 -208) +) +(connector + (text "DDR_SYNC_66M" (rect 770 -200 859 -189)(font "Arial" )) + (pt 760 -184) + (pt 856 -184) +) +(connector + (text "MAIN_CLK" (rect 338 -296 395 -285)(font "Arial" )) + (pt 272 -280) + (pt 456 -280) +) +(connector + (text "FB_AD[31..0]" (rect 1682 16 1748 27)(font "Arial" )) + (pt 1832 32) + (pt 1672 32) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 336 1220 347)(font "Arial" )) + (pt 1112 352) + (pt 1264 352) + (bus) +) +(connector + (text "nFB_WR" (rect 1162 192 1208 203)(font "Arial" )) + (pt 1152 208) + (pt 1264 208) +) +(connector + (text "nFB_CS1" (rect 1154 216 1202 227)(font "Arial" )) + (pt 1152 232) + (pt 1264 232) +) +(connector + (text "FB_SIZE0" (rect 1154 264 1205 275)(font "Arial" )) + (pt 1152 280) + (pt 1264 280) +) +(connector + (text "FB_SIZE1" (rect 1154 288 1204 299)(font "Arial" )) + (pt 1152 304) + (pt 1264 304) +) +(connector + (text "nFB_CS2" (rect 1162 240 1211 251)(font "Arial" )) + (pt 1152 256) + (pt 1264 256) +) +(connector + (text "nBLANK" (rect 1682 192 1726 203)(font "Arial" )) + (pt 1672 208) + (pt 1832 208) +) +(connector + (pt 1680 80) + (pt 1680 88) + (bus) +) +(connector + (pt 2080 80) + (pt 1680 80) + (bus) +) +(connector + (text "VR[7..0]" (rect 1922 72 1962 83)(font "Arial" )) + (pt 1680 88) + (pt 1672 88) + (bus) +) +(connector + (pt 1688 104) + (pt 1688 112) + (bus) +) +(connector + (pt 2000 104) + (pt 1688 104) + (bus) +) +(connector + (text "VG[7..0]" (rect 1842 96 1883 107)(font "Arial" )) + (pt 1688 112) + (pt 1672 112) + (bus) +) +(connector + (pt 1696 128) + (pt 1696 136) + (bus) +) +(connector + (pt 1912 128) + (pt 1696 128) + (bus) +) +(connector + (text "VB[7..0]" (rect 1754 120 1794 131)(font "Arial" )) + (pt 1696 136) + (pt 1672 136) + (bus) +) +(connector + (pt 1704 224) + (pt 1704 232) +) +(connector + (pt 1832 224) + (pt 1704 224) +) +(connector + (text "nSYNC" (rect 1682 216 1720 227)(font "Arial" )) + (pt 1704 232) + (pt 1672 232) +) +(connector + (pt 1712 272) + (pt 1712 280) +) +(connector + (pt 1832 272) + (pt 1712 272) +) +(connector + (text "nPD_VGA" (rect 1682 264 1736 275)(font "Arial" )) + (pt 1712 280) + (pt 1672 280) +) +(connector + (pt 1720 328) + (pt 1720 336) + (bus) +) +(connector + (pt 2528 328) + (pt 1720 328) + (bus) +) +(connector + (text "VA[12..0]" (rect 1682 320 1728 331)(font "Arial" )) + (pt 1720 336) + (pt 1672 336) + (bus) +) +(connector + (pt 1728 352) + (pt 1728 360) +) +(connector + (pt 2400 352) + (pt 1728 352) +) +(connector + (text "nVWE" (rect 1682 344 1715 355)(font "Arial" )) + (pt 1728 360) + (pt 1672 360) +) +(connector + (pt 1256 368) + (pt 1256 376) +) +(connector + (text "nFB_CS3" (rect 1186 360 1235 371)(font "Arial" )) + (pt 1256 376) + (pt 1264 376) +) +(connector + (text "nFB_OE" (rect 1170 168 1213 179)(font "Arial" )) + (pt 1264 184) + (pt 1160 184) +) +(connector + (text "FB_ALE" (rect 1194 312 1236 323)(font "Arial" )) + (pt 1264 328) + (pt 1184 328) +) +(connector + (text "DDRCLK[3..0]" (rect 1162 144 1232 155)(font "Arial" )) + (pt 1152 160) + (pt 1264 160) + (bus) +) +(connector + (text "DDR_SYNC_66M" (rect 1178 120 1267 131)(font "Arial" )) + (pt 1168 136) + (pt 1264 136) +) +(connector + (pt 1736 304) + (pt 1736 312) + (bus) +) +(connector + (pt 2648 304) + (pt 1736 304) + (bus) +) +(connector + (text "VD[31..0]" (rect 1682 296 1728 307)(font "Arial" )) + (pt 1736 312) + (pt 1672 312) + (bus) +) +(connector + (pt 1744 376) + (pt 1744 384) +) +(connector + (pt 2304 376) + (pt 1744 376) +) +(connector + (text "nVCAS" (rect 1690 368 1727 379)(font "Arial" )) + (pt 1744 384) + (pt 1672 384) +) +(connector + (pt 1752 400) + (pt 1752 408) +) +(connector + (pt 2208 400) + (pt 1752 400) +) +(connector + (text "nVRAS" (rect 1690 392 1727 403)(font "Arial" )) + (pt 1752 408) + (pt 1672 408) +) +(connector + (pt 1760 424) + (pt 1760 432) +) +(connector + (pt 2040 424) + (pt 1760 424) +) +(connector + (text "nVCS" (rect 1690 416 1720 427)(font "Arial" )) + (pt 1760 432) + (pt 1672 432) +) +(connector + (pt 1768 448) + (pt 1768 456) +) +(connector + (pt 1944 448) + (pt 1768 448) +) +(connector + (text "VCKE" (rect 1690 440 1721 451)(font "Arial" )) + (pt 1768 456) + (pt 1672 456) +) +(connector + (text "VSYNC" (rect 1682 144 1722 155)(font "Arial" )) + (pt 1672 160) + (pt 1832 160) +) +(connector + (text "HSYNC" (rect 1682 168 1722 179)(font "Arial" )) + (pt 1672 184) + (pt 1832 184) +) +(connector + (pt 1776 712) + (pt 1776 720) +) +(connector + (pt 1880 712) + (pt 1776 712) +) +(connector + (text "Video_TA" (rect 1682 704 1732 715)(font "Arial" )) + (pt 1776 720) + (pt 1672 720) +) +(connector + (text "MAIN_CLK" (rect 1186 96 1243 107)(font "Arial" )) + (pt 1184 112) + (pt 1264 112) +) +(connector + (text "nRSTO" (rect 1194 48 1232 59)(font "Arial" )) + (pt 1184 64) + (pt 1264 64) +) +(connector + (pt 1784 472) + (pt 1784 480) + (bus) +) +(connector + (pt 1832 472) + (pt 1784 472) + (bus) +) +(connector + (text "BA[1..0]" (rect 1682 464 1722 475)(font "Arial" )) + (pt 1784 480) + (pt 1672 480) + (bus) +) +(connector + (text "PIXEL_CLK" (rect 1682 240 1743 251)(font "Arial" )) + (pt 1744 256) + (pt 1672 256) +) +(connector + (text "VR_D[8..0]" (rect 1170 472 1224 483)(font "Arial" )) + (pt 1144 488) + (pt 1264 488) + (bus) +) +(connector + (pt 1888 552) + (pt 1672 552) + (bus) +) +(connector + (pt 1888 568) + (pt 1888 552) + (bus) +) +(connector + (pt 1960 528) + (pt 1672 528) + (bus) +) +(connector + (pt 1960 544) + (pt 1960 528) + (bus) +) +(connector + (text "VIDEO_RECONFIG" (rect 1674 568 1774 579)(font "Arial" )) + (pt 1672 584) + (pt 1792 584) +) +(connector + (text "VR_WR" (rect 1698 600 1739 611)(font "Arial" )) + (pt 1672 616) + (pt 1792 616) +) +(connector + (text "VR_BUSY" (rect 1170 456 1224 467)(font "Arial" )) + (pt 1144 472) + (pt 1264 472) +) +(connector + (text "VR_RD" (rect 1698 584 1736 595)(font "Arial" )) + (pt 1792 600) + (pt 1672 600) +) +(connector + (pt 1248 568) + (pt 1248 576) +) +(connector + (pt 984 568) + (pt 1248 568) +) +(connector + (text "CLK_VIDEO" (rect 1162 560 1225 571)(font "Arial" )) + (pt 1248 576) + (pt 1264 576) +) +(connector + (text "MAIN_CLK" (rect 1202 592 1259 603)(font "Arial" )) + (pt 1264 608) + (pt 1192 608) +) +(connector + (pt 1264 1264) + (pt 1112 1264) +) +(connector + (text "nSCSI_DRQ" (rect 1114 1248 1177 1259)(font "Arial" )) + (pt 1112 1264) + (pt 1104 1264) +) +(connector + (pt 1104 1336) + (pt 1112 1336) +) +(connector + (text "nSCSI_MSG" (rect 1114 1320 1178 1331)(font "Arial" )) + (pt 1112 1336) + (pt 1264 1336) +) +(connector + (pt 1104 1424) + (pt 1112 1424) +) +(connector + (text "CTS" (rect 1114 1408 1137 1419)(font "Arial" )) + (pt 1112 1424) + (pt 1264 1424) +) +(connector + (pt 1104 1448) + (pt 1112 1448) +) +(connector + (text "RI" (rect 1114 1432 1125 1443)(font "Arial" )) + (pt 1112 1448) + (pt 1264 1448) +) +(connector + (pt 1104 1472) + (pt 1112 1472) +) +(connector + (text "DCD" (rect 1114 1456 1139 1467)(font "Arial" )) + (pt 1112 1472) + (pt 1264 1472) +) +(connector + (pt 1264 1552) + (pt 1112 1552) +) +(connector + (text "IDE_RDY" (rect 1114 1536 1164 1547)(font "Arial" )) + (pt 1112 1552) + (pt 1104 1552) +) +(connector + (pt 1104 1576) + (pt 1112 1576) +) +(connector + (text "IDE_INT" (rect 1114 1560 1157 1571)(font "Arial" )) + (pt 1112 1576) + (pt 1264 1576) +) +(connector + (pt 1104 1600) + (pt 1112 1600) +) +(connector + (text "WP_CF_CARD" (rect 1112 1584 1189 1595)(font "Arial" )) + (pt 1112 1600) + (pt 1264 1600) +) +(connector + (pt 1104 1784) + (pt 1112 1784) +) +(connector + (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) + (pt 1112 1784) + (pt 1264 1784) +) +(connector + (pt 1104 1808) + (pt 1112 1808) +) +(connector + (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) + (pt 1112 1808) + (pt 1264 1808) +) +(connector + (pt 1104 1832) + (pt 1112 1832) +) +(connector + (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) + (pt 1112 1832) + (pt 1264 1832) +) +(connector + (pt 1104 1880) + (pt 1112 1880) +) +(connector + (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) + (pt 1112 1880) + (pt 1264 1880) +) +(connector + (pt 1264 1176) + (pt 1112 1176) +) +(connector + (text "LP_BUSY" (rect 1114 1160 1165 1171)(font "Arial" )) + (pt 1112 1176) + (pt 1104 1176) +) +(connector + (pt 1024 1208) + (pt 1032 1208) +) +(connector + (text "nACSI_DRQ" (rect 1034 1192 1097 1203)(font "Arial" )) + (pt 1032 1208) + (pt 1264 1208) +) +(connector + (pt 1024 1232) + (pt 1032 1232) +) +(connector + (text "nACSI_INT" (rect 1034 1216 1091 1227)(font "Arial" )) + (pt 1032 1232) + (pt 1264 1232) +) +(connector + (pt 1040 1368) + (pt 1048 1368) +) +(connector + (text "MIDI_IN" (rect 1050 1352 1091 1363)(font "Arial" )) + (pt 1048 1368) + (pt 1264 1368) +) +(connector + (pt 1264 1400) + (pt 1112 1400) +) +(connector + (text "RxD" (rect 1114 1384 1137 1395)(font "Arial" )) + (pt 1112 1400) + (pt 1104 1400) +) +(connector + (pt 1040 1656) + (pt 1048 1656) +) +(connector + (text "nINDEX" (rect 1050 1640 1092 1651)(font "Arial" )) + (pt 1048 1656) + (pt 1264 1656) +) +(connector + (pt 1040 1680) + (pt 1048 1680) +) +(connector + (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) + (pt 1048 1680) + (pt 1264 1680) +) +(connector + (pt 1040 1704) + (pt 1048 1704) +) +(connector + (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) + (pt 1048 1704) + (pt 1264 1704) +) +(connector + (pt 1040 1728) + (pt 1048 1728) +) +(connector + (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) + (pt 1048 1728) + (pt 1264 1728) +) +(connector + (pt 1040 1752) + (pt 1048 1752) +) +(connector + (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) + (pt 1048 1752) + (pt 1264 1752) +) +(connector + (pt 1104 1288) + (pt 1112 1288) +) +(connector + (text "nSCSI_C_D" (rect 1114 1272 1175 1283)(font "Arial" )) + (pt 1112 1288) + (pt 1264 1288) +) +(connector + (pt 1104 1312) + (pt 1112 1312) +) +(connector + (text "nSCSI_I_O" (rect 1114 1296 1171 1307)(font "Arial" )) + (pt 1112 1312) + (pt 1264 1312) +) +(connector + (pt 1264 944) + (pt 1168 944) +) +(connector + (text "nFB_WR" (rect 1170 928 1216 939)(font "Arial" )) + (pt 1168 944) + (pt 1160 944) +) +(connector + (pt 1264 968) + (pt 1168 968) +) +(connector + (text "nFB_CS1" (rect 1162 952 1210 963)(font "Arial" )) + (pt 1168 968) + (pt 1160 968) +) +(connector + (pt 1264 992) + (pt 1168 992) +) +(connector + (text "nFB_CS2" (rect 1170 976 1219 987)(font "Arial" )) + (pt 1168 992) + (pt 1160 992) +) +(connector + (pt 1264 1016) + (pt 1168 1016) +) +(connector + (text "FB_SIZE0" (rect 1162 1000 1213 1011)(font "Arial" )) + (pt 1168 1016) + (pt 1160 1016) +) +(connector + (pt 1264 1040) + (pt 1168 1040) +) +(connector + (text "FB_SIZE1" (rect 1162 1024 1212 1035)(font "Arial" )) + (pt 1168 1040) + (pt 1160 1040) +) +(connector + (pt 1264 1064) + (pt 1168 1064) +) +(connector + (text "nFB_BURST" (rect 1162 1048 1226 1059)(font "Arial" )) + (pt 1168 1064) + (pt 1160 1064) +) +(connector + (pt 1264 1112) + (pt 1168 1112) +) +(connector + (text "nDACK0" (rect 1250 1096 1294 1107)(font "Arial" )) + (pt 1168 1112) + (pt 1160 1112) +) +(connector + (pt 1152 2600) + (pt 1160 2600) +) +(connector + (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) + (pt 1160 2600) + (pt 1264 2600) +) +(connector + (pt 1264 920) + (pt 1168 920) +) +(connector + (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) + (pt 1168 920) + (pt 1160 920) +) +(connector + (pt 1152 2648) + (pt 1160 2648) +) +(connector + (text "DVI_INT" (rect 1162 2632 1205 2643)(font "Arial" )) + (pt 1160 2648) + (pt 1264 2648) +) +(connector + (pt 1152 2744) + (pt 1160 2744) +) +(connector + (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) + (pt 1160 2744) + (pt 1264 2744) +) +(connector + (pt 1152 2720) + (pt 1160 2720) +) +(connector + (text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" )) + (pt 1160 2720) + (pt 1264 2720) +) +(connector + (pt 1152 2696) + (pt 1160 2696) +) +(connector + (text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" )) + (pt 1160 2696) + (pt 1264 2696) +) +(connector + (pt 1152 2672) + (pt 1160 2672) +) +(connector + (text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" )) + (pt 1160 2672) + (pt 1264 2672) +) +(connector + (pt 1152 2624) + (pt 1160 2624) +) +(connector + (text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" )) + (pt 1160 2624) + (pt 1264 2624) +) +(connector + (pt 528 2416) + (pt 536 2416) +) +(connector + (pt 536 2416) + (pt 616 2416) +) +(connector + (pt 776 1496) + (pt 784 1496) +) +(connector + (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) + (pt 784 1496) + (pt 1264 1496) +) +(connector + (pt 776 1520) + (pt 784 1520) +) +(connector + (text "PIC_AMKB_RX" (rect 786 1504 866 1515)(font "Arial" )) + (pt 784 1520) + (pt 1264 1520) +) +(connector + (pt 376 1400) + (pt 384 1400) +) +(connector + (text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" )) + (pt 384 1400) + (pt 464 1400) +) +(connector + (pt 1040 1632) + (pt 1048 1632) +) +(connector + (text "HD_DD" (rect 1050 1616 1090 1627)(font "Arial" )) + (pt 1048 1632) + (pt 1264 1632) +) +(connector + (pt 336 304) + (pt 344 304) +) +(connector + (text "MAIN_CLK" (rect 346 288 403 299)(font "Arial" )) + (pt 344 304) + (pt 400 304) +) +(connector + (pt 1176 368) + (pt 1184 368) +) +(connector + (pt 1184 368) + (pt 1256 368) +) +(connector + (text "CLK2M" (rect 906 -40 944 -29)(font "Arial" )) + (pt 704 -24) + (pt 944 -24) +) +(connector + (text "FDC_CLK" (rect 954 -24 1007 -13)(font "Arial" )) + (pt 704 -8) + (pt 944 -8) +) +(connector + (pt 832 56) + (pt 832 24) +) +(connector + (pt 840 56) + (pt 832 56) +) +(connector + (pt 832 24) + (pt 704 24) +) +(connector + (pt 400 -24) + (pt 400 248) +) +(connector + (pt 400 248) + (pt 400 304) +) +(connector + (pt 448 -24) + (pt 400 -24) +) +(connector + (text "CLK25M" (rect 1210 616 1254 627)(font "Arial" )) + (pt 1264 632) + (pt 1200 632) +) +(connector + (pt 776 8) + (pt 704 8) +) +(connector + (text "CLKUSB" (rect 538 552 584 563)(font "Arial" )) + (pt 528 568) + (pt 608 568) +) +(junction (pt 2504 760)) +(junction (pt 400 248)) +(junction (pt 1856 -64)) +(junction (pt 2424 -80)) +(junction (pt 1112 1264)) +(junction (pt 1112 1336)) +(junction (pt 1112 1424)) +(junction (pt 1112 1448)) +(junction (pt 1112 1472)) +(junction (pt 1112 1552)) +(junction (pt 1112 1576)) +(junction (pt 1112 1600)) +(junction (pt 1112 1784)) +(junction (pt 1112 1808)) +(junction (pt 1112 1832)) +(junction (pt 1112 1880)) +(junction (pt 1112 1176)) +(junction (pt 1032 1208)) +(junction (pt 1032 1232)) +(junction (pt 1048 1368)) +(junction (pt 1112 1400)) +(junction (pt 1048 1656)) +(junction (pt 1048 1680)) +(junction (pt 1048 1704)) +(junction (pt 1048 1728)) +(junction (pt 1048 1752)) +(junction (pt 1112 1288)) +(junction (pt 1112 1312)) +(junction (pt 1168 944)) +(junction (pt 1168 968)) +(junction (pt 1168 992)) +(junction (pt 1168 1016)) +(junction (pt 1168 1040)) +(junction (pt 1168 1064)) +(junction (pt 1168 1112)) +(junction (pt 1160 2600)) +(junction (pt 1168 920)) +(junction (pt 1160 2648)) +(junction (pt 1160 2744)) +(junction (pt 1160 2720)) +(junction (pt 1160 2696)) +(junction (pt 1160 2672)) +(junction (pt 1160 2624)) +(junction (pt 536 2416)) +(junction (pt 784 1496)) +(junction (pt 784 1520)) +(junction (pt 384 1400)) +(junction (pt 1048 1632)) +(junction (pt 344 304)) +(junction (pt 1184 368)) diff --git a/firebee1.qsf b/firebee1.qsf index 1aaf33e..f167edb 100644 --- a/firebee1.qsf +++ b/firebee1.qsf @@ -39,394 +39,393 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_AB12 -to CLK33M -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_E12 -to MIDI_IN -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_AB12 -to CLK33M +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_E12 -to MIDI_IN +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -436,7 +435,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -446,21 +445,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -470,85 +469,85 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- # LogicLock Region Assignments # ============================ -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # end LOGICLOCK_REGION(Root Region) # --------------------------------- @@ -558,143 +557,205 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(firebee1) # -------------------- -set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name BDF_FILE firebee1.bdf -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name BDF_FILE Video/Video.bdf -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name QIP_FILE altpll_reconfig1.qip -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name ENABLE_DRC_SETTINGS ON -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk33m -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to main_clk -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -set_instance_assignment -name DQS_FREQUENCY "132 MHz" -to VDQS +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name DISABLE_OCP_HW_EVAL ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON + +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5 +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/firebee1.sdc b/firebee1.sdc index 2f6e864..5e6d787 100644 --- a/firebee1.sdc +++ b/firebee1.sdc @@ -1,30 +1,47 @@ -## Generated SDC file "ddr.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Fri Aug 22 11:04:42 2014" - -## -## DEVICE "EP3C16F484C8" -## - +#--------------------------------------------------------------# +# # +# Synopsis design constraints for the Firebee project # +# # +# This file is part of the Firebee ACP project. # +# http://www.experiment-s.de # +# # +# Description: # +# timing constraints for the Firebee VHDL config # +# # +# # +# # +# To Do: # +# - # +# # +# Author(s): # +# Markus Fröschle, mfro@mubf.de # +# # +#--------------------------------------------------------------# +# # +# Copyright (C) 2015 Markus Fröschle & the ACP project # +# # +# This source file may be used and distributed without # +# restriction provided that this copyright statement is not # +# removed from the file and that any derivative work contains # +# the original copyright notice and the associated disclaimer. # +# # +# This source file is free software; you can redistribute it # +# and/or modify it under the terms of the GNU Lesser General # +# Public License as published by the Free Software Foundation; # +# either version 2.1 of the License, or (at your option) any # +# later version. # +# # +# This source is distributed in the hope that it will be # +# useful, but WITHOUT ANY WARRANTY; without even the implied # +# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR # +# PURPOSE. See the GNU Lesser General Public License for more # +# details. # +# # +# You should have received a copy of the GNU Lesser General # +# Public License along with this source; if not, download it # +# from http://www.gnu.org/licenses/lgpl.html # +# # +################################################################ #************************************************************** # Time Information @@ -38,14 +55,48 @@ set_time_format -unit ns -decimal_places 3 # Create Clock #************************************************************** -create_clock -name {main_clk} -period 30.303 -waveform { 0.000 15.151 } [get_ports {main_clk}] -create_clock -name {clk33m} -period 30.303 -waveform {0.000 15.151} [get_ports {clk33m}] +create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}] +# Clocks used: +# MAIN_CLK 33MHz +# +# PLL1: i_mfp_acia_clk_pll +# input: MAIN_CLK +# c0: 500 kHz +# c1: 2.4576 MHz +# c2: 24.576 MHz +# +# PLL2: i_ddr_clock_pll +# input: MAIN_CLK +# c0: 132 MHz 190° +# c1: 132 MHz 0° +# c2: 132 MHz 180° +# c3: 132 MHz 105° +# c4: 66 MHz 270° +# +# PLL3: i_atari_clk_pll +# input: MAIN_CLK +# c0: 2 MHz +# c1: 16 MHz +# c2: 25 MHz +# c3: 48 MHz +# +# PLL4_ i_video_clk_pll +# input: USB_CLK (48 MHz, PLL3 c3) +# c0: 96 MHz, programmable in 1MHz steps +# #************************************************************** # Create Generated Clock #************************************************************** -derive_pll_clocks -create_base_clocks +derive_pll_clocks + +# PIXEL_CLK is either +# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO +# where CLK13M is half of CLK25M, +# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable +# clock of i_video_clk_pll +# #************************************************************** @@ -57,6 +108,9 @@ derive_pll_clocks -create_base_clocks #************************************************************** # Set Clock Uncertainty #************************************************************** + +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00 derive_clock_uncertainty @@ -64,15 +118,15 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -# constrain DDR RAM -set_input_delay -clock [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] 5ps [get_ports {VD*}] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs] + #************************************************************** # Set Output Delay #************************************************************** -# constrain DDR RAM -set_output_delay -clock [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] 5ps [get_ports {VD*}] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs] + #************************************************************** # Set Clock Groups @@ -84,61 +138,87 @@ set_output_delay -clock [get_clocks {inst12|altpll_component|auto_generated|pll1 # Set False Path #************************************************************** -set_false_path -from [get_clocks {clk33m}] -to [get_clocks {main_clk}] -set_false_path -from [get_clocks {main_clk}] -to [get_clocks {clk33m}] +# +# i_video_clk is freely programmable +# +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -# decouple video clk from all other clocks -set_false_path -from [get_clocks {*}] -to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -set_false_path -from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {*}] +# MAIN_CLK to 16 MHz clk -> false_path +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -# the same with clk25m -set_false_path -from [get_clocks {*}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {*}] +# MAIN_CLK to DDR clk and v.v. +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] + +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] + +# 2 MHz to 33 MHz +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] + +# 16 MHz to 33 MHz +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] + +# 25 MHz to 33 MHz +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] + +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] + +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] +set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] +set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] -set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {main_clk}] - -set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] -to [get_clocks {main_clk}] -set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] - -set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] - -set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] - -set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] - -set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {main_clk}] -set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] - -set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {clk33m}] -set_false_path -from [get_clocks {clk33m}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] - -set_false_path -from [get_clocks {clk33m}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] - -set_false_path -from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {main_clk}] - -set_false_path -from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {main_clk}] #************************************************************** # Set Multicycle Path #************************************************************** - - #************************************************************** # Set Maximum Delay #************************************************************** +# from here to the end of the file statements are just an experiment +#set_max_delay 25 -from [get_ports {*}] #************************************************************** # Set Minimum Delay #************************************************************** - +#set_min_delay 0.5 -from [get_ports {*}] #************************************************************** # Set Input Transition #************************************************************** +#set_input_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25 +#set_input_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5 +#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25 +#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5 +# restrict timing of video controller + +#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VA[*]}] +#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VA[*]}] + +#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {BA[*]}] +#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {BA[*]}] + +#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}] +#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}] +#set_input_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}] +#set_input_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}] diff --git a/firebeei1.qpf b/firebeei1.qpf deleted file mode 100644 index 8ab6c97..0000000 --- a/firebeei1.qpf +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (C) 1991-2008 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - - -QUARTUS_VERSION = "8.1" -DATE = "10:07:29 September 03, 2009" - - -# Revisions - -PROJECT_REVISION = "firebee1" diff --git a/lpm_counter0.bsf b/lpm_counter0.bsf index ee9919b..7fc7aaa 100644 --- a/lpm_counter0.bsf +++ b/lpm_counter0.bsf @@ -1,57 +1,49 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 64) - (text "lpm_counter0" (rect 33 0 129 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 49 26 60)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)) - ) - (port - (pt 144 40) - (output) - (text "q[17..0]" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "q[17..0]" (rect 89 34 126 46)(font "Arial" (font_size 8))) - (line (pt 144 40)(pt 128 40)(line_width 3)) - ) - (drawing - (text "up counter" (rect 84 23 213 56)(font "Arial" )) - (line (pt 16 16)(pt 16 48)) - (line (pt 16 16)(pt 128 16)) - (line (pt 16 48)(pt 128 48)) - (line (pt 128 16)(pt 128 48)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 66)) - (line (pt 0 66)(pt 146 66)) - (line (pt 0 0)(pt 0 66)) - (line (pt 16 26)(pt 22 32)) - (line (pt 22 32)(pt 16 38)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 64) + (text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 48 25 60)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 144 40) + (output) + (text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8))) + (line (pt 144 40)(pt 128 40)(line_width 3)) + ) + (drawing + (text "up counter" (rect 84 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 48)(line_width 1)) + (line (pt 128 48)(pt 16 48)(line_width 1)) + (line (pt 16 48)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/lpm_counter0.cmp b/lpm_counter0.cmp index 18e8009..ad18248 100644 --- a/lpm_counter0.cmp +++ b/lpm_counter0.cmp @@ -1,22 +1,22 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_counter0 - PORT - ( - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) - ); -end component; +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_counter0 + PORT + ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +end component; diff --git a/lpm_counter0.qip b/lpm_counter0.qip index 0062ec6..a72845b 100644 --- a/lpm_counter0.qip +++ b/lpm_counter0.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"] +set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"] diff --git a/lpm_counter0.vhd b/lpm_counter0.vhd index 3ec7e1e..9135dbc 100644 --- a/lpm_counter0.vhd +++ b/lpm_counter0.vhd @@ -1,127 +1,126 @@ --- megafunction wizard: %LPM_COUNTER% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_COUNTER - --- ============================================================ --- File Name: lpm_counter0.vhd --- Megafunction Name(s): --- LPM_COUNTER --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_counter0 IS - PORT - ( - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) - ); -END lpm_counter0; - - -ARCHITECTURE SYN OF lpm_counter0 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (17 DOWNTO 0); - - - - COMPONENT lpm_counter - GENERIC ( - lpm_direction : STRING; - lpm_port_updown : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(17 DOWNTO 0); - - LPM_COUNTER_component : LPM_COUNTER - GENERIC MAP ( - lpm_direction => "UP", - lpm_port_updown => "PORT_UNUSED", - lpm_type => "LPM_COUNTER", - lpm_width => 18 - ) - PORT MAP ( - clock => clock, - q => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACLR NUMERIC "0" --- Retrieval info: PRIVATE: ALOAD NUMERIC "0" --- Retrieval info: PRIVATE: ASET NUMERIC "0" --- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" --- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" --- Retrieval info: PRIVATE: CarryIn NUMERIC "0" --- Retrieval info: PRIVATE: CarryOut NUMERIC "0" --- Retrieval info: PRIVATE: Direction NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" --- Retrieval info: PRIVATE: ModulusValue NUMERIC "0" --- Retrieval info: PRIVATE: SCLR NUMERIC "0" --- Retrieval info: PRIVATE: SLOAD NUMERIC "0" --- Retrieval info: PRIVATE: SSET NUMERIC "0" --- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: nBit NUMERIC "18" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" --- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE --- Retrieval info: LIB_FILE: lpm +-- megafunction wizard: %LPM_COUNTER% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_counter + +-- ============================================================ +-- File Name: lpm_counter0.vhd +-- Megafunction Name(s): +-- lpm_counter +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_counter0 IS + PORT + ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +END lpm_counter0; + + +ARCHITECTURE SYN OF lpm_counter0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (17 DOWNTO 0); + + + + COMPONENT lpm_counter + GENERIC ( + lpm_direction : STRING; + lpm_port_updown : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(17 DOWNTO 0); + + lpm_counter_component : lpm_counter + GENERIC MAP ( + lpm_direction => "UP", + lpm_port_updown => "PORT_UNUSED", + lpm_type => "LPM_COUNTER", + lpm_width => 18 + ) + PORT MAP ( + clock => clock, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" +-- Retrieval info: PRIVATE: CarryIn NUMERIC "0" +-- Retrieval info: PRIVATE: CarryOut NUMERIC "0" +-- Retrieval info: PRIVATE: Direction NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" +-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "18" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" +-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: lpm