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This commit is contained in:
Markus Fröschle
2014-12-24 17:54:51 +00:00
parent 06688a9a02
commit 674406e4d3
1 changed files with 1 additions and 1 deletions
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vhdl/testbenches/ddr_ram_model.vhd
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@@ -64,7 +64,7 @@ ENTITY ddr_ram_model IS
ADDRTOP : INTEGER := 12; ADDRTOP : INTEGER := 12;
A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10 A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10
B : INTEGER := 16; -- number of bit (x16) B : INTEGER := 16; -- number of bit (x16)
NCOL : INTEGER := 10; -- top column address is CA9 (NCOL- 1) NCOL : INTEGER := 10; -- top column address is CA9 (NCOL - 1)
PAGEDEPTH : INTEGER := 1024; PAGEDEPTH : INTEGER := 1024;
NDM : INTEGER := 2; NDM : INTEGER := 2;
NDQS : INTEGER := 2 NDQS : INTEGER := 2