From 674406e4d3850460572fa37f0fe6695fb90c7be5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 24 Dec 2014 17:54:51 +0000 Subject: [PATCH] formatting --- vhdl/testbenches/ddr_ram_model.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vhdl/testbenches/ddr_ram_model.vhd b/vhdl/testbenches/ddr_ram_model.vhd index 6878079..e0f9ecc 100644 --- a/vhdl/testbenches/ddr_ram_model.vhd +++ b/vhdl/testbenches/ddr_ram_model.vhd @@ -64,7 +64,7 @@ ENTITY ddr_ram_model IS ADDRTOP : INTEGER := 12; A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10 B : INTEGER := 16; -- number of bit (x16) - NCOL : INTEGER := 10; -- top column address is CA9 (NCOL- 1) + NCOL : INTEGER := 10; -- top column address is CA9 (NCOL - 1) PAGEDEPTH : INTEGER := 1024; NDM : INTEGER := 2; NDQS : INTEGER := 2