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initialize prelaminary exception vector table

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This commit is contained in:
Markus Fröschle
2013-08-02 17:35:01 +00:00
parent a62596ac9c
commit 63d7882521
5 changed files with 30 additions and 9 deletions
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1
BaS_gcc/bas.lk.in
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@@ -103,6 +103,7 @@ SECTIONS
/* Memory mapped registers */ /* Memory mapped registers */
__MBAR = 0xFF000000; __MBAR = 0xFF000000;
//__MBAR = 0x80000000;
/* 32KB on-chip System SRAM */ /* 32KB on-chip System SRAM */
__SYS_SRAM = 0xFF010000; __SYS_SRAM = 0xFF010000;

2
BaS_gcc/flash_scripts/flash_bas.bdm
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@@ -47,6 +47,6 @@ erase 0xE0000000 0x08000
erase-wait 0xE0000000 erase-wait 0xE0000000
erase 0xE0000000 0x10000 erase 0xE0000000 0x10000
erase-wait 0xE0000000 erase-wait 0xE0000000
blank-chk 0xE0000000 0x00000 blank-chk 0xE0000000 0x10000
load -v bas.elf load -v bas.elf
wait wait

14
BaS_gcc/run_bas.bdm
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@@ -6,12 +6,12 @@ open $1
reset reset
sleep 10 sleep 10
# set VBR
write-ctrl 0x0801 0x00000000
# Turn on MBAR at 0xFF00_0000 # Turn on MBAR at 0xFF00_0000
write-ctrl 0x0C0F 0xFF000000 write-ctrl 0x0C0F 0xFF000000
# set VBR
write-ctrl 0x0801 0x00000000
# Turn on RAMBAR0 at address FF10_0000 # Turn on RAMBAR0 at address FF10_0000
write-ctrl 0x0C04 0xFF100007 write-ctrl 0x0C04 0xFF100007
@@ -54,12 +54,18 @@ write 0xFF00010C 0x46770000 4 # SDCFG2
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
sleep 100
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
sleep 100
load -v ram.elf load -v ram.elf
write-ctrl 0x80e 0x2700
write-ctrl 0x2 0xa50c8120
dump-register SR
dump-register CACR
dump-register MBAR
execute execute

11
BaS_gcc/sources/fault_vectors.c
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@@ -139,7 +139,7 @@ void fault_handler(uint32_t format_status, uint32_t pc)
xprintf("sr=%4x\r\n", sr); xprintf("sr=%4x\r\n", sr);
} }
void handler(void) void __attribute__((interrupt)) handler(void)
{ {
/* /*
* for standard routines, we'd have to save registers here. * for standard routines, we'd have to save registers here.
@@ -147,7 +147,7 @@ void handler(void)
*/ */
__asm__ __volatile__("move.l (sp),-(sp)\n\t" /* format, fault status and status register values */ __asm__ __volatile__("move.l (sp),-(sp)\n\t" /* format, fault status and status register values */
"move.l 8(sp),-(sp)\n\t" /* the program counter where the fault originated */ "move.l 8(sp),-(sp)\n\t" /* the program counter where the fault originated */
"bra _fault_handler\n\t" "bsr _fault_handler\n\t"
"halt\n\t" "halt\n\t"
: : :); : : :);
} }
@@ -156,6 +156,8 @@ void setup_vectors(void)
{ {
int i; int i;
xprintf("\r\ninstall prelaminary exception vector table:");
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
{ {
SDRAM_VECTOR_TABLE[i] = handler; SDRAM_VECTOR_TABLE[i] = handler;
@@ -165,6 +167,9 @@ void setup_vectors(void)
* make sure VBR points to our table * make sure VBR points to our table
*/ */
__asm__ __volatile__("clr.l d0\n\t" __asm__ __volatile__("clr.l d0\n\t"
"movec d0,VBR\n\t" "movec.l d0,VBR\n\t"
"nop\n\t"
"move.l d0,_rt_vbr"); "move.l d0,_rt_vbr");
xprintf("finished.\r\n");
} }

9
BaS_gcc/sources/sysinit.c
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@@ -934,6 +934,15 @@ void initialize_hardware(void) {
*/ */
xprintf(" (revision %d)\r\n",((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28)); xprintf(" (revision %d)\r\n",((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28));
/*
* install (prilaminary) exception vectors
*/
extern void setup_vectors(void);
setup_vectors();
/* make sure the handlers are called */
//* (uint32_t *) 0xC0000001 = 0x0L;
init_slt(); init_slt();
init_fbcs(); init_fbcs();
init_ddram(); init_ddram();