diff --git a/BaS_gcc/bas.lk.in b/BaS_gcc/bas.lk.in
index 7b987da..81e05a5 100644
--- a/BaS_gcc/bas.lk.in
+++ b/BaS_gcc/bas.lk.in
@@ -103,7 +103,8 @@ SECTIONS
 
 	/* Memory mapped registers */
  	__MBAR                  = 0xFF000000;
-
+	//__MBAR					  = 0x80000000;
+	
 	/* 32KB on-chip System SRAM */
  	__SYS_SRAM              = 0xFF010000;
 	__SYS_SRAM_SIZE         = 0x00008000;
diff --git a/BaS_gcc/flash_scripts/flash_bas.bdm b/BaS_gcc/flash_scripts/flash_bas.bdm
index 4d1cc31..7baad45 100755
--- a/BaS_gcc/flash_scripts/flash_bas.bdm
+++ b/BaS_gcc/flash_scripts/flash_bas.bdm
@@ -47,6 +47,6 @@ erase 0xE0000000 0x08000
 erase-wait 0xE0000000
 erase 0xE0000000 0x10000
 erase-wait 0xE0000000
-blank-chk 0xE0000000 0x00000 
+blank-chk 0xE0000000 0x10000
 load -v bas.elf
 wait
diff --git a/BaS_gcc/run_bas.bdm b/BaS_gcc/run_bas.bdm
index ff911ae..1a3e72b 100755
--- a/BaS_gcc/run_bas.bdm
+++ b/BaS_gcc/run_bas.bdm
@@ -6,12 +6,12 @@ open $1
 reset
 sleep 10
 
-# set VBR
-write-ctrl 0x0801 0x00000000
-
 # Turn on MBAR at 0xFF00_0000
 write-ctrl 0x0C0F 0xFF000000
 
+# set VBR
+write-ctrl 0x0801 0x00000000
+
 # Turn on RAMBAR0 at address FF10_0000 
 write-ctrl 0x0C04 0xFF100007
 
@@ -54,12 +54,18 @@ write 0xFF00010C 0x46770000 4	# SDCFG2
 write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
 write 0xFF000100 0x40010000 4	# SDMR (write to LEMR)
 write 0xFF000100 0x048D0000 4	# SDMR (write to LMR)
-
+sleep 100
 write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
 write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
 write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
 write 0xFF000100 0x008D0000 4	# SDMR (write to LMR)
 write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
+sleep 100
 
 load -v ram.elf
+write-ctrl 0x80e	0x2700
+write-ctrl 0x2	0xa50c8120
+dump-register SR
+dump-register CACR
+dump-register MBAR
 execute
diff --git a/BaS_gcc/sources/fault_vectors.c b/BaS_gcc/sources/fault_vectors.c
index 98f4c0c..62337ca 100644
--- a/BaS_gcc/sources/fault_vectors.c
+++ b/BaS_gcc/sources/fault_vectors.c
@@ -139,7 +139,7 @@ void fault_handler(uint32_t format_status, uint32_t pc)
 	xprintf("sr=%4x\r\n", sr);
 }
 
-void handler(void)
+void __attribute__((interrupt)) handler(void)
 {
 	/*
 	 * for standard routines, we'd have to save registers here.
@@ -147,7 +147,7 @@ void handler(void)
 	 */
 	__asm__ __volatile__("move.l	(sp),-(sp)\n\t"		/* format, fault status and status register values */
 						 "move.l	8(sp),-(sp)\n\t"	/* the program counter where the fault originated */
-						 "bra		_fault_handler\n\t"
+						 "bsr		_fault_handler\n\t"
 						 "halt\n\t"
 							: : :);
 }
@@ -156,6 +156,8 @@ void setup_vectors(void)
 {
 	int i;
 
+	xprintf("\r\ninstall prelaminary exception vector table:");
+
 	for (i = 0; i < 256; i++)
 	{
 		SDRAM_VECTOR_TABLE[i] = handler;
@@ -165,6 +167,9 @@ void setup_vectors(void)
 	 * make sure VBR points to our table
 	 */
 	__asm__ __volatile__("clr.l		d0\n\t"
-						 "movec		d0,VBR\n\t"
+						 "movec.l	d0,VBR\n\t"
+						 "nop\n\t"
 						 "move.l	d0,_rt_vbr");
+
+	xprintf("finished.\r\n");
 }
diff --git a/BaS_gcc/sources/sysinit.c b/BaS_gcc/sources/sysinit.c
index 477903d..93609bb 100644
--- a/BaS_gcc/sources/sysinit.c
+++ b/BaS_gcc/sources/sysinit.c
@@ -934,6 +934,15 @@ void initialize_hardware(void) {
 	 */
 	xprintf(" (revision %d)\r\n",((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28));
 
+	/*
+	 * install (prilaminary) exception vectors
+	 */
+	extern void setup_vectors(void);
+	setup_vectors();
+
+	/* make sure the handlers are called */
+	//* (uint32_t *) 0xC0000001 = 0x0L;
+
 	init_slt();
 	init_fbcs();
 	init_ddram();