cleaned up project - removed unused files
This commit is contained in:
Markus Fröschle
@@ -1,261 +0,0 @@
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/*
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* sd_card.c
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*
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*/
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#include <stdint.h>
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#include <MCF5475.h>
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#include <bas_printf.h>
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#include <sd_card.h>
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#include <wait.h>
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/*
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* "standard value" for DSPI module configuration register MCF_DSPC_DMCR
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*/
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const uint32_t DSPI_DMCR_CONF = MCF_DSPI_DMCR_MSTR | /* FireBee is DSPI master*/ /* 8 bit CS5 on */
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MCF_DSPI_DMCR_CSIS3 | /* CS3 inactive */
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MCF_DSPI_DMCR_CSIS2 | /* CS2 inactive */
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MCF_DSPI_DMCR_DTXF | /* disable transmit FIFO */
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MCF_DSPI_DMCR_DRXF | /* disable receive FIFO */
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MCF_DSPI_DMCR_CTXF | /* clear transmit FIFO */
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MCF_DSPI_DMCR_CRXF; /* clear receive FIFO */
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/* 0x800d3c00 */
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#ifdef _NOT_USED_ /* disabled assembler routines */
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void sd_card_idle(void)
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{
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__asm__ __volatile__ (
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".extern sd_idle\n\t"
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"bsr sd_idle\n\t"
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/* output */:
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/* input */ :
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/* clobber */: "a0","a1","a2","a3","a4","a5",
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"d0","d1","d2","d3","d4","d5","d6","d7","memory"
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);
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}
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int spi_init(void)
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{
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register int ret __asm__("d0");
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__asm__ __volatile__ (
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".extern sd_init\n\t"
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"bsr.l sd_init\n\t"
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/* output */: "=r" (ret)
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/* input */ :
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/* clobber */: "a0","a1","a2","a3","a4","a5",
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"d1","d2","d3","d4","d5","d6","d7","memory"
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);
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return ret;
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}
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#endif /* _NOT_USED_ */
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/*
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* Write data to the DSPI TX FIFO register
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* First 16 bits are the SPI command field (basically say only HOW to transfer the second
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* half), second are the data to transfer
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*/
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uint32_t sd_com(uint32_t data)
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{
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uint32_t ret;
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MCF_DSPI_DTFR = data; /* write value to TX FIFO */
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while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF)); /* wait until DSPI transfer complete */
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ret = MCF_DSPI_DRFR; /* read DSPI Rx FIFO register */
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MCF_DSPI_DSR = 0xffffffff; /* clear DSPI status register */
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return ret;
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}
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/*
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* transfer a byte to SPI. This only works if the rest of the DSPI TX FIFO has been
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* initialized previously (either by sd_com or a direct register write).
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* Returns a byte received from SPI (contents of the RX FIFO).
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*/
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inline uint8_t spi_send_byte(uint8_t byte)
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{
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* (volatile uint8_t *) (&MCF_DSPI_DTFR + 3) = byte;
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return * (volatile uint8_t *) (&MCF_DSPI_DRFR + 3);
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}
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/*
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* as above, but word sized
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*/
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inline uint16_t spi_send_word(uint16_t word)
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{
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* (volatile uint16_t *) (&MCF_DSPI_DTFR + 2) = word;
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return * (volatile uint16_t *) (&MCF_DSPI_DRFR + 2);
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}
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int spi_init(void)
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{
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uint32_t ret;
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uint8_t rb;
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int i;
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xprintf("SD-Card initialization: ");
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MCF_PAD_PAR_DSPI = 0x1fff; /* configure all DSPI GPIO pins for DSPI usage */
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MCF_PAD_PAR_TIMER = 0xff; /*
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* FIXME: really necessary or just an oversight
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* that PAD_PAR_DSPI is only 16 bit?
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*/
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MCF_DSPI_DMCR = DSPI_DMCR_CONF;
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MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) | /* transfer size = 8 bit */
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MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */
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MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */
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MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */
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MCF_DSPI_DCTAR_PBR_3CLK | /* 3 clock prescaler */
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MCF_DSPI_DCTAR_ASC(0b1001) | /* 1024 */
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MCF_DSPI_DCTAR_DT(0b1001) | /* 1024 */
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MCF_DSPI_DCTAR_BR(0b0111);
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/* 0x38558897 */
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MCF_DSPI_DSR = 0xffffffff; /* clear DSPI status register */
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wait(1000); /* wait 1ms */
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MCF_DSPI_DMCR = DSPI_DMCR_CONF | MCF_DSPI_DMCR_CSCK; /* enable continuous serial comms clock */
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/* 0xc00d3c00 */
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wait(10000);
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MCF_DSPI_DMCR = DSPI_DMCR_CONF;
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ret = sd_com(MCF_DSPI_DTFR_EOQ | MCF_DSPI_DTFR_CS5 | 0x00FF);
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for (i = 1; i < 10; i++)
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{
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rb = spi_send_byte(0xff);
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}
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MCF_DSPI_DMCR = DSPI_DMCR_CONF | MCF_DSPI_DMCR_CSIS5; /* CS5 inactive */
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/* 0x802d3c00; */
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for (i = 0; i < 2; i++)
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{
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ret = sd_com(MCF_DSPI_DTFR_EOQ | MCF_DSPI_DTFR_CS5);
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}
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MCF_DSPI_DMCR = DSPI_DMCR_CONF;
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ret = sd_com(MCF_DSPI_DTFR_EOQ | MCF_DSPI_DTFR_CS5 | 0x00FF);
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rb = spi_send_byte(0xff);
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MCF_DSPI_DMCR = DSPI_DMCR_CONF;
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wait(10000);
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sd_card_idle();
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xprintf("finished\r\n");
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return 0;
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}
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void sd_card_idle(void)
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{
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int i;
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int j;
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uint32_t ret;
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for (i = 0; i < 100; i++)
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{
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ret = spi_send_byte(0xff);
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ret = spi_send_byte(0x40);
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ret = spi_send_byte(0x00);
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ret = spi_send_byte(0x00);
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ret = spi_send_byte(0x00);
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ret = spi_send_byte(0x00);
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ret = spi_send_byte(0x95);
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for (j = 0; j < 6; j++)
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{
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ret = spi_send_byte(0xff);
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if (ret & 0x01)
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break;
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}
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if (ret & 0x01)
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break;
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}
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}
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void sd_card_read_ic(void)
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{
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uint8_t rb;
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while (/* no suitable data received */ 1)
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{
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rb = spi_send_byte(0xFF);
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rb = spi_send_byte(0x48);
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rb = spi_send_byte(0x00);
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rb = spi_send_byte(0x00);
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rb = spi_send_byte(0x01);
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rb = spi_send_byte(0xaa);
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rb = spi_send_byte(0x87);
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rb = sd_card_get_status();
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if (rb == 5)
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{
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while (rb == 5)
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{
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rb = spi_send_byte(0xff);
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rb = spi_send_byte(0x7a);
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rb = spi_send_byte(0x00);
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rb = spi_send_byte(0x00);
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rb = spi_send_byte(0x00);
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rb = spi_send_byte(0x00);
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rb = spi_send_byte(0x01);
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rb = sd_card_get_status();
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}
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}
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else if (rb == 1)
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{
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//sd_card_read_ic();
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}
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else
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{
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continue;
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}
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rb = spi_send_byte(0xff);
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/* move.b d5,d0 ? */
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}
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}
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uint8_t sd_card_get_status(void)
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{
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uint8_t ret;
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do
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{
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ret = spi_send_byte(0xFF);
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} while (ret == 0xff);
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return ret;
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}
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540
sources/sd_ide.c
540
sources/sd_ide.c
@@ -1,540 +0,0 @@
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#include "MCF5475.h"
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#include "startcf.h"
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/* imported routines */
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//extern int warten_20ms();
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//extern int warten_200us();
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//extern int warten_10us();
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/********************************************************************/
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void asm sd_test(void)
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{
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clr.w MCF_PAD_PAR_DSPI
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lea MCF_GPIO_PPDSDR_DSPI,a2 // data in
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lea MCF_GPIO_PODR_DSPI,a1 // data out
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move.b #0x00,(a1) // alle auf 0
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lea MCF_GPIO_PDDR_DSPI,a0
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move.b #0x7d,(a0) // din = input rest output
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bsr warten_20ms
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move.b #0x7f,(a1) // alle auf 1
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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bsr sd_16clk
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// sd idle
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sd_idle:
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bsr sd_16clk
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moveq #0x40,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x95,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x05,d5
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beq sd_test
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cmp.b #0x01,d5
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beq wait_of_aktiv
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cmp.b #0x04,d5
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beq sd_init_ok
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cmp.b #0x00,d5
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beq sd_init_ok
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bra sd_idle
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// acdm 41
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wait_of_aktiv:
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bsr sd_16clk
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moveq #0x77,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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bsr sd_16clk
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move.l #0xff,d6
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moveq #0x69,d4
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bsr sd_com
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and d5,d6
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moveq #00,d4
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bsr sd_com
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and d5,d6
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moveq #00,d4
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bsr sd_com
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and d5,d6
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moveq #0x02,d4
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bsr sd_com
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and d5,d6
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moveq #00,d4
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bsr sd_com
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and d5,d6
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moveq #0x01,d4
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bsr sd_com
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and d5,d6
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bsr sd_receive
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cmp.b #0x00,d5
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beq sd_init_ok
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cmp.b #0x05,d5
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beq sd_test
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bra wait_of_aktiv
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sd_init_ok:
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// blockgr<67>sse 512byt
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sd_bg:
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bsr sd_16clk
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moveq #0x50,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #02,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_bg
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// read block
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sd_rb:
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bsr sd_16clk
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moveq #0x51,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x08,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_rb
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lea 0xc00000,a4
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move.l #513,d7
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rd_rb:
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bsr sd_receive
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move.b d5,(a4)+
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subq.l #1,d7
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bne rd_rb
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// write block
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sd_wb:
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bsr sd_16clk
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moveq #0x58,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x08,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_wb
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lea 0xc00000,a4
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move.l #513,d7
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moveq.l #0x66,d4
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wr_wb:
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bsr sd_com
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// subq.l #1,d4
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moveq #0x66,d4
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subq.l #1,d7
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bne wr_wb
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bsr sd_receive
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wr_wb_el:
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moveq #0xff,d4
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bsr sd_com
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cmp.b #0xff,d5
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bne wr_wb_el
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// read block 2
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sd_rb2:
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bsr sd_16clk
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moveq #0x51,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x08,d4
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bsr sd_com
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moveq #00,d4
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bsr sd_com
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moveq #0x01,d4
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bsr sd_com
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bsr sd_receive
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cmp.b #0x00,d5
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bne sd_rb2
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lea 0xc00400,a4
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move.l #513,d7
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rd_rb2:
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bsr sd_receive
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move.b d5,(a4)+
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subq.l #1,d7
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bne rd_rb2
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nop
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nop
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rts
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sd_receive:
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moveq #0xff,d4
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bsr sd_com
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cmp.b #0xff,d5
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beq sd_receive
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||||
rts
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||||
sd_com:
|
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bclr.b #6,(a1)
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sd_comb:
|
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bsr warten_10us
|
||||
moveq #7,d2
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||||
clr.l d5
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||||
sd_com_loop:
|
||||
btst d2,d4
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||||
beq sd_com2
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||||
bset.b #0,(a1)
|
||||
bra sd_com2_1
|
||||
sd_com2:
|
||||
bclr.b #0,(a1)
|
||||
sd_com2_1:
|
||||
bsr sd_clk
|
||||
and.l #0x02,d3
|
||||
beq sd_com3
|
||||
bset.b d2,d5
|
||||
sd_com3:
|
||||
subq.l #1,d2
|
||||
bge sd_com_loop
|
||||
bsr warten_10us
|
||||
bset.b #6,(a1)
|
||||
bset.b #0,(a1)
|
||||
bsr warten_200us
|
||||
rts
|
||||
sd_clk:
|
||||
tst.b 0xfffff700
|
||||
tst.b 0xfffff700
|
||||
bset.b #2,(a1)
|
||||
tst.b 0xfffff700
|
||||
tst.b 0xfffff700
|
||||
move.b (a2),d3
|
||||
tst.b 0xfffff700
|
||||
bclr.b #2,(a1)
|
||||
rts
|
||||
|
||||
sd_15clk:
|
||||
move #15,d0
|
||||
bra sd_16clk
|
||||
sd_16clk:
|
||||
moveq #16,d0
|
||||
sd_16clk1:
|
||||
bsr sd_clk
|
||||
subq.l #1,d0
|
||||
bne sd_16clk1
|
||||
bsr warten_10us
|
||||
rts
|
||||
// warteschleife ca. 20ms
|
||||
warten_20ms:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #700000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 200us
|
||||
warten_200us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #7000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 10us
|
||||
warten_10us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #333,d6
|
||||
warten_loop:
|
||||
move.l (a0),d1
|
||||
sub.l d0,d1
|
||||
add.l d6,d1
|
||||
bpl warten_loop
|
||||
move.l (sp)+,d0
|
||||
move.l (sp)+,d1
|
||||
move.l (sp)+,d6
|
||||
move.l (sp)+,a0
|
||||
rts;
|
||||
}
|
||||
|
||||
|
||||
/**************************************************/
|
||||
void asm ide_test(void)
|
||||
{
|
||||
lea MCF_PAD_PAR_DSPI,a0
|
||||
move.w #0x1fff,(a0)
|
||||
lea MCF_DSPI_DCTAR0,a0
|
||||
move.l #0x38a644e4,(a0)
|
||||
lea MCF_DSPI_DMCR,a0
|
||||
move.l #0x802d3c00,(a0)
|
||||
clr.l MCF_DSPI_DTCR
|
||||
bsr warten_20ms
|
||||
lea MCF_DSPI_DTFR,a0
|
||||
lea MCF_DSPI_DRFR,a1
|
||||
|
||||
moveq #10,d0
|
||||
sd_reset:
|
||||
move.l #0x000100ff,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
subq.l #1,d0
|
||||
bne sd_reset
|
||||
|
||||
moveq #10,d1
|
||||
sd_loop1:
|
||||
bsr warten_20ms
|
||||
moveq #-1,d0
|
||||
// cmd 0 set to idle
|
||||
move.l #0x00200040,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200095,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
cmp.w #0x0001,d0
|
||||
beq sd_loop2
|
||||
subq.l #1,d1
|
||||
bne sd_loop1
|
||||
moveq #10,d1
|
||||
bra sd_test
|
||||
sd_loop2:
|
||||
moveq #-1,d0
|
||||
// cmd 41
|
||||
move.l #0x00200069,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200000,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
move.l #0x00200001,(a0)
|
||||
bsr warten_20ms
|
||||
and.l (a1),d0
|
||||
tst.w d0
|
||||
bne sd_loop2
|
||||
|
||||
nop
|
||||
nop
|
||||
/********************************************************************/
|
||||
#define cmd_reg (0x1d)
|
||||
#define status_reg (0x1d)
|
||||
#define seccnt (0x09)
|
||||
|
||||
ide_test:
|
||||
lea 0xfff00040,a0
|
||||
lea 0xc00000,a1
|
||||
move.b #0xec,cmd_reg(a0) //identify devcie cmd
|
||||
bsr wait_int
|
||||
bsr ds_rx
|
||||
// read sector normal
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x20,cmd_reg(a0) // read cmd
|
||||
bsr wait_int
|
||||
bsr ds_rx
|
||||
|
||||
// write testpattern sector
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x30,cmd_reg(a0) // write cmd
|
||||
bsr drq_wait
|
||||
// write pattern
|
||||
move.l #256,d0
|
||||
ide_test_loop3:
|
||||
move.w #0xa55a,(a0)
|
||||
subq.l #1,d0
|
||||
bne ide_test_loop3
|
||||
bsr wait_int
|
||||
// read testpattern sector
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x20,cmd_reg(a0) // read
|
||||
bsr wait_int
|
||||
bsr ds_rx
|
||||
// sector restauriern
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x30,cmd_reg(a0) // write
|
||||
lea -0x400(a1),a1 // vorletzer
|
||||
bsr drq_wait
|
||||
bsr ds_tx
|
||||
bsr wait_int
|
||||
// fertig und zur<75>ck
|
||||
nop
|
||||
rts
|
||||
// wait auf int
|
||||
wait_int:
|
||||
move.b 0xfffffa01,d0
|
||||
btst.b #5,d0
|
||||
bne wait_int
|
||||
move.b status_reg(a0),d0
|
||||
rts
|
||||
// wait auf drq
|
||||
drq_wait:
|
||||
move.b status_reg(a0),d0
|
||||
btst #3,d0
|
||||
beq drq_wait
|
||||
rts
|
||||
|
||||
// 1 sector lesen word
|
||||
ds_rx:
|
||||
move.l #256,d0
|
||||
ds_rx_loop:
|
||||
move.w (a0),(a1)+
|
||||
subq.l #1,d0
|
||||
bne ds_rx_loop
|
||||
rts
|
||||
// 1 sector lesen long
|
||||
ds_rxl:
|
||||
move.l #128,d0
|
||||
ds_rxl_loop:
|
||||
move.l (a0),(a1)+
|
||||
subq.l #1,d0
|
||||
bne ds_rxl_loop
|
||||
rts
|
||||
// 1 sector schreiben word
|
||||
ds_tx:
|
||||
move.l #256,d0
|
||||
ds_tx_loop:
|
||||
move.w (a1)+,(a0)
|
||||
subq.l #1,d0
|
||||
bne ds_tx_loop
|
||||
rts
|
||||
// 1 sector schreiben word
|
||||
ds_txl:
|
||||
move.l #128,d0
|
||||
ds_txl_loop:
|
||||
move.l (a1)+,(a0)
|
||||
subq.l #1,d0
|
||||
bne ds_txl_loop
|
||||
rts
|
||||
// warteschleife ca. 20ms
|
||||
warten_20ms:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #700000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 200us
|
||||
warten_200us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #7000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 10us
|
||||
warten_10us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #333,d6
|
||||
warten_loop:
|
||||
move.l (a0),d1
|
||||
sub.l d0,d1
|
||||
add.l d6,d1
|
||||
bpl warten_loop
|
||||
move.l (sp)+,d0
|
||||
move.l (sp)+,d1
|
||||
move.l (sp)+,d6
|
||||
move.l (sp)+,a0
|
||||
rts;
|
||||
}
|
||||
/********************************************************************/
|
||||
458
sources/sd_ide.s
458
sources/sd_ide.s
@@ -1,458 +0,0 @@
|
||||
|
||||
|
||||
//.include "startcf.h"
|
||||
|
||||
//.extern ___MBAR
|
||||
//#define MCF_SLT0_SCNT ___MBAR+0x908
|
||||
|
||||
//.global ide_test
|
||||
|
||||
.text
|
||||
/*
|
||||
sd_test:
|
||||
clr.w MCF_PAD_PAR_DSPI
|
||||
lea MCF_GPIO_PPDSDR_DSPI,a2 // data in
|
||||
lea MCF_GPIO_PODR_DSPI,a1 // data out
|
||||
move.b #0x00,(a1) // alle auf 0
|
||||
lea MCF_GPIO_PDDR_DSPI,a0
|
||||
move.b #0x7d,(a0) // din = input rest output
|
||||
|
||||
bsr warten_20ms
|
||||
|
||||
move.b #0x7f,(a1) // alle auf 1
|
||||
|
||||
bsr sd_16clk
|
||||
bsr sd_16clk
|
||||
bsr sd_16clk
|
||||
bsr sd_16clk
|
||||
bsr sd_16clk
|
||||
bsr sd_16clk
|
||||
bsr sd_16clk
|
||||
bsr sd_16clk
|
||||
// sd idle
|
||||
sd_idle:
|
||||
bsr sd_16clk
|
||||
moveq #0x40,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x95,d4
|
||||
bsr sd_com
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
cmp.b #0x05,d5
|
||||
beq sd_test
|
||||
cmp.b #0x01,d5
|
||||
beq wait_of_aktiv
|
||||
cmp.b #0x04,d5
|
||||
beq sd_init_ok
|
||||
cmp.b #0x00,d5
|
||||
beq sd_init_ok
|
||||
bra sd_idle
|
||||
|
||||
// acdm 41
|
||||
wait_of_aktiv:
|
||||
bsr sd_16clk
|
||||
|
||||
moveq #0x77,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x01,d4
|
||||
bsr sd_com
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
bsr sd_16clk
|
||||
|
||||
move.l #0xff,d6
|
||||
moveq #0x69,d4
|
||||
bsr sd_com
|
||||
and d5,d6
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
and d5,d6
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
and d5,d6
|
||||
moveq #0x02,d4
|
||||
bsr sd_com
|
||||
and d5,d6
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
and d5,d6
|
||||
moveq #0x01,d4
|
||||
bsr sd_com
|
||||
and d5,d6
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
cmp.b #0x00,d5
|
||||
beq sd_init_ok
|
||||
cmp.b #0x05,d5
|
||||
beq sd_test
|
||||
bra wait_of_aktiv
|
||||
|
||||
sd_init_ok:
|
||||
|
||||
// blockgr<EFBFBD>sse 512byt
|
||||
sd_bg:
|
||||
bsr sd_16clk
|
||||
moveq #0x50,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #02,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x01,d4
|
||||
bsr sd_com
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
cmp.b #0x00,d5
|
||||
bne sd_bg
|
||||
|
||||
// read block
|
||||
sd_rb:
|
||||
bsr sd_16clk
|
||||
moveq #0x51,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x08,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x01,d4
|
||||
bsr sd_com
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
cmp.b #0x00,d5
|
||||
bne sd_rb
|
||||
|
||||
lea 0xc00000,a4
|
||||
move.l #513,d7
|
||||
rd_rb:
|
||||
bsr sd_receive
|
||||
move.b d5,(a4)+
|
||||
subq.l #1,d7
|
||||
bne rd_rb
|
||||
|
||||
// write block
|
||||
sd_wb:
|
||||
bsr sd_16clk
|
||||
moveq #0x58,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x08,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x01,d4
|
||||
bsr sd_com
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
cmp.b #0x00,d5
|
||||
bne sd_wb
|
||||
|
||||
lea 0xc00000,a4
|
||||
move.l #513,d7
|
||||
moveq.l #0x66,d4
|
||||
wr_wb:
|
||||
bsr sd_com
|
||||
// subq.l #1,d4
|
||||
moveq #0x66,d4
|
||||
subq.l #1,d7
|
||||
bne wr_wb
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
wr_wb_el:
|
||||
moveq #0xff,d4
|
||||
bsr sd_com
|
||||
cmp.b #0xff,d5
|
||||
bne wr_wb_el
|
||||
|
||||
|
||||
// read block 2
|
||||
sd_rb2:
|
||||
bsr sd_16clk
|
||||
moveq #0x51,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x08,d4
|
||||
bsr sd_com
|
||||
moveq #00,d4
|
||||
bsr sd_com
|
||||
moveq #0x01,d4
|
||||
bsr sd_com
|
||||
|
||||
bsr sd_receive
|
||||
|
||||
cmp.b #0x00,d5
|
||||
bne sd_rb2
|
||||
|
||||
lea 0xc00400,a4
|
||||
move.l #513,d7
|
||||
rd_rb2:
|
||||
bsr sd_receive
|
||||
move.b d5,(a4)+
|
||||
subq.l #1,d7
|
||||
bne rd_rb2
|
||||
|
||||
|
||||
nop
|
||||
nop
|
||||
|
||||
rts
|
||||
|
||||
sd_receive:
|
||||
moveq #0xff,d4
|
||||
bsr sd_com
|
||||
cmp.b #0xff,d5
|
||||
beq sd_receive
|
||||
rts
|
||||
|
||||
sd_com:
|
||||
bclr.b #6,(a1)
|
||||
sd_comb:
|
||||
bsr warten_10us
|
||||
moveq #7,d2
|
||||
clr.l d5
|
||||
sd_com_loop:
|
||||
btst d2,d4
|
||||
beq sd_com2
|
||||
bset.b #0,(a1)
|
||||
bra sd_com2_1
|
||||
sd_com2:
|
||||
bclr.b #0,(a1)
|
||||
sd_com2_1:
|
||||
bsr sd_clk
|
||||
and.l #0x02,d3
|
||||
beq sd_com3
|
||||
bset.b d2,d5
|
||||
sd_com3:
|
||||
subq.l #1,d2
|
||||
bge sd_com_loop
|
||||
bsr warten_10us
|
||||
bset.b #6,(a1)
|
||||
bset.b #0,(a1)
|
||||
bsr warten_200us
|
||||
rts
|
||||
sd_clk:
|
||||
tst.b 0xfffff700
|
||||
tst.b 0xfffff700
|
||||
bset.b #2,(a1)
|
||||
tst.b 0xfffff700
|
||||
tst.b 0xfffff700
|
||||
move.b (a2),d3
|
||||
tst.b 0xfffff700
|
||||
bclr.b #2,(a1)
|
||||
rts
|
||||
|
||||
sd_15clk:
|
||||
move #15,d0
|
||||
bra sd_16clk
|
||||
sd_16clk:
|
||||
moveq #16,d0
|
||||
sd_16clk1:
|
||||
bsr sd_clk
|
||||
subq.l #1,d0
|
||||
bne sd_16clk1
|
||||
bsr warten_10us
|
||||
rts
|
||||
// warteschleife ca. 20ms
|
||||
warten_20ms:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #700000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 200us
|
||||
warten_200us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #7000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 10us
|
||||
warten_10us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #333,d6
|
||||
warten_loop:
|
||||
move.l (a0),d1
|
||||
sub.l d0,d1
|
||||
add.l d6,d1
|
||||
bpl warten_loop
|
||||
move.l (sp)+,d0
|
||||
move.l (sp)+,d1
|
||||
move.l (sp)+,d6
|
||||
move.l (sp)+,a0
|
||||
rts;
|
||||
/********************************************************************/
|
||||
#define cmd_reg (0x1d)
|
||||
#define status_reg (0x1d)
|
||||
#define seccnt (0x09)
|
||||
|
||||
ide_test:
|
||||
lea 0xfff00040,a0
|
||||
lea 0xc00000,a1
|
||||
move.b #0xec,cmd_reg(a0) //identify devcie cmd
|
||||
bsr wait_int
|
||||
bsr ds_rx
|
||||
// read sector normal
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x20,cmd_reg(a0) // read cmd
|
||||
bsr wait_int
|
||||
bsr ds_rx
|
||||
|
||||
// write testpattern sector
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x30,cmd_reg(a0) // write cmd
|
||||
bsr drq_wait
|
||||
// write pattern
|
||||
move.l #256,d0
|
||||
ide_test_loop3:
|
||||
move.w #0xa55a,(a0)
|
||||
subq.l #1,d0
|
||||
bne ide_test_loop3
|
||||
bsr wait_int
|
||||
// read testpattern sector
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x20,cmd_reg(a0) // read
|
||||
bsr wait_int
|
||||
bsr ds_rx
|
||||
// sector restauriern
|
||||
move.b #1,seccnt(a0) // 1 sector
|
||||
move.b #0x30,cmd_reg(a0) // write
|
||||
lea -0x400(a1),a1 // vorletzer
|
||||
bsr drq_wait
|
||||
bsr ds_tx
|
||||
bsr wait_int
|
||||
// fertig und zur<EFBFBD>ck
|
||||
nop
|
||||
rts
|
||||
// wait auf int
|
||||
wait_int:
|
||||
move.b 0xfffffa01,d0
|
||||
btst #5,d0
|
||||
bne wait_int
|
||||
move.b status_reg(a0),d0
|
||||
rts
|
||||
// wait auf drq
|
||||
drq_wait:
|
||||
move.b status_reg(a0),d0
|
||||
btst #3,d0
|
||||
beq drq_wait
|
||||
rts
|
||||
|
||||
// 1 sector lesen word
|
||||
ds_rx:
|
||||
move.l #256,d0
|
||||
ds_rx_loop:
|
||||
move.w (a0),(a1)+
|
||||
subq.l #1,d0
|
||||
bne ds_rx_loop
|
||||
rts
|
||||
// 1 sector lesen long
|
||||
ds_rxl:
|
||||
move.l #128,d0
|
||||
ds_rxl_loop:
|
||||
move.l (a0),(a1)+
|
||||
subq.l #1,d0
|
||||
bne ds_rxl_loop
|
||||
rts
|
||||
// 1 sector schreiben word
|
||||
ds_tx:
|
||||
move.l #256,d0
|
||||
ds_tx_loop:
|
||||
move.w (a1)+,(a0)
|
||||
subq.l #1,d0
|
||||
bne ds_tx_loop
|
||||
rts
|
||||
// 1 sector schreiben word
|
||||
ds_txl:
|
||||
move.l #128,d0
|
||||
ds_txl_loop:
|
||||
move.l (a1)+,(a0)
|
||||
subq.l #1,d0
|
||||
bne ds_txl_loop
|
||||
rts
|
||||
// warteschleife ca. 20ms
|
||||
warten_20ms:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #700000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 200us
|
||||
warten_200us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #7000,d6
|
||||
bra warten_loop
|
||||
// warteschleife ca. 10us
|
||||
warten_10us:
|
||||
move.l a0,-(sp)
|
||||
move.l d6,-(sp)
|
||||
move.l d1,-(sp)
|
||||
move.l d0,-(sp)
|
||||
lea MCF_SLT0_SCNT,a0
|
||||
move.l (a0),d0
|
||||
move.l #333,d6
|
||||
warten_loop:
|
||||
move.l (a0),d1
|
||||
sub.l d0,d1
|
||||
add.l d6,d1
|
||||
bpl warten_loop
|
||||
move.l (sp)+,d0
|
||||
move.l (sp)+,d1
|
||||
move.l (sp)+,d6
|
||||
move.l (sp)+,a0
|
||||
rts;
|
||||
/********************************************************************/
|
||||
Reference in New Issue
Block a user