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fix discrepancies and disable PCI interrupts (temporarily)

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seems to increase stability
This commit is contained in:
Markus Fröschle
2015-10-03 16:12:17 +00:00
parent 20339b2d60
commit 5afb746abb
3 changed files with 119 additions and 116 deletions
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4
BaS_gcc/Makefile
View File

@@ -9,7 +9,7 @@
# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint # can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
# toolchain # toolchain
COMPILE_ELF=Y COMPILE_ELF=N
ifeq (Y,$(COMPILE_ELF)) ifeq (Y,$(COMPILE_ELF))
TCPREFIX=m68k-elf- TCPREFIX=m68k-elf-
@@ -95,9 +95,11 @@ CSRCS= \
dspi.c \ dspi.c \
driver_vec.c \ driver_vec.c \
driver_mem.c \ driver_mem.c \
\
MCD_dmaApi.c \ MCD_dmaApi.c \
MCD_tasks.c \ MCD_tasks.c \
MCD_tasksInit.c \ MCD_tasksInit.c \
\
usb.c \ usb.c \
ohci-hcd.c \ ohci-hcd.c \
ehci-hcd.c \ ehci-hcd.c \

5
BaS_gcc/sys/BaS.c
View File

@@ -179,8 +179,8 @@ void nvram_init(void)
for (i = 0; i < 64; i++) for (i = 0; i < 64; i++)
{ {
uint8_t data = read_pic_byte(); uint8_t data = read_pic_byte();
*(volatile uint8_t*)0xffff8961 = i; * (volatile uint8_t*) 0xffff8961 = i;
*(volatile uint8_t*)0xffff8963 = data; * (volatile uint8_t*) 0xffff8963 = data;
} }
xprintf("finished\r\n"); xprintf("finished\r\n");
@@ -233,7 +233,6 @@ void enable_coldfire_interrupts()
MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) | MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */ MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */

226
BaS_gcc/sys/cache.c
View File

@@ -26,60 +26,61 @@
void cacr_set(uint32_t value) void cacr_set(uint32_t value)
{ {
extern uint32_t rt_cacr; extern uint32_t rt_cacr;
rt_cacr = value; rt_cacr = value;
__asm__ __volatile__("movec %0, cacr\n\t" __asm__ __volatile__(
: /* output */ " movec %0, cacr\n\t"
: "r" (rt_cacr) : /* output */
: "memory" /* clobbers */); : "r" (rt_cacr)
: "memory" /* clobbers */);
} }
uint32_t cacr_get(void) uint32_t cacr_get(void)
{ {
extern uint32_t rt_cacr; extern uint32_t rt_cacr;
return rt_cacr; return rt_cacr;
} }
void disable_data_cache(void) void disable_data_cache(void)
{ {
flush_and_invalidate_caches(); flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC); cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
} }
void disable_instruction_cache(void) void disable_instruction_cache(void)
{ {
flush_and_invalidate_caches(); flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC); cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
} }
void enable_data_cache(void) void enable_data_cache(void)
{ {
cacr_set(cacr_get() & ~CF_CACR_DCINVA); cacr_set(cacr_get() & ~CF_CACR_DCINVA);
} }
void flush_and_invalidate_caches(void) void flush_and_invalidate_caches(void)
{ {
__asm__ __volatile__( __asm__ __volatile__(
" clr.l d0 \n\t" " clr.l d0 \n\t"
" clr.l d1 \n\t" " clr.l d1 \n\t"
" move.l d0,a0 \n\t" " move.l d0,a0 \n\t"
"cfa_setloop: \n\t" "cfa_setloop: \n\t"
" cpushl bc,(a0) | flush\n\t" " cpushl bc,(a0) | flush\n\t"
" lea 0x10(a0),a0 | index+1\n\t" " lea 0x10(a0),a0 | index+1\n\t"
" addq.l #1,d1 | index+1\n\t" " addq.l #1,d1 | index+1\n\t"
" cmpi.w #512,d1 | all sets?\n\t" " cmpi.w #512,d1 | all sets?\n\t"
" bne.s cfa_setloop | no->\n\t" " bne.s cfa_setloop | no->\n\t"
" clr.l d1 \n\t" " clr.l d1 \n\t"
" addq.l #1,d0 \n\t" " addq.l #1,d0 \n\t"
" move.l d0,a0 \n\t" " move.l d0,a0 \n\t"
" cmpi.w #4,d0 | all ways?\n\t" " cmpi.w #4,d0 | all ways?\n\t"
" bne.s cfa_setloop | no->\n\t" " bne.s cfa_setloop | no->\n\t"
/* input */ : /* input */ :
/* output */ : /* output */ :
/* clobber */ : "cc", "d0", "d1", "a0" /* clobber */ : "cc", "d0", "d1", "a0"
); );
} }
/* /*
@@ -87,48 +88,48 @@ void flush_and_invalidate_caches(void)
*/ */
void flush_icache_range(void *address, size_t size) void flush_icache_range(void *address, size_t size)
{ {
uint32_t set; uint32_t set;
uint32_t start_set; uint32_t start_set;
uint32_t end_set; uint32_t end_set;
void *endaddr = address + size; void *endaddr = address + size;
start_set = (uint32_t) address & _ICACHE_SET_MASK; start_set = (uint32_t) address & _ICACHE_SET_MASK;
end_set = (uint32_t) endaddr & _ICACHE_SET_MASK; end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;
if (start_set > end_set) { if (start_set > end_set) {
/* from the begining to the lowest address */ /* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3)) for (set = 0; set <= end_set; set += (0x10 - 3))
{ {
__asm__ __volatile__( __asm__ __volatile__(
" cpushl ic,(%[set]) \n\t" " cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t" " cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t" " cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t" " cpushl ic,(%[set]) \n\t"
: /* output parameters */ : /* output parameters */
: [set] "a" (set) /* input parameters */ : [set] "a" (set) /* input parameters */
: "cc" /* clobbered registers */ : "cc" /* clobbered registers */
); );
} }
/* next loop will finish the cache ie pass the hole */ /* next loop will finish the cache ie pass the hole */
end_set = LAST_ICACHE_ADDR; end_set = LAST_ICACHE_ADDR;
} }
for (set = start_set; set <= end_set; set += (0x10 - 3)) { for (set = start_set; set <= end_set; set += (0x10 - 3)) {
__asm__ __volatile__( __asm__ __volatile__(
" cpushl ic,(%[set]) \n\t" " cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t" " cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t" " cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl ic,(%[set])" " cpushl ic,(%[set])"
: /* output parameters */ : /* output parameters */
: [set] "a" (set) : [set] "a" (set)
: "cc" : "cc"
); );
} }
} }
@@ -138,52 +139,53 @@ void flush_icache_range(void *address, size_t size)
*/ */
void flush_dcache_range(void *address, size_t size) void flush_dcache_range(void *address, size_t size)
{ {
unsigned long set; unsigned long set;
unsigned long start_set; unsigned long start_set;
unsigned long end_set; unsigned long end_set;
void *endaddr; void *endaddr;
endaddr = address + size; endaddr = address + size;
start_set = (uint32_t) address & _DCACHE_SET_MASK; start_set = (uint32_t) address & _DCACHE_SET_MASK;
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK; end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
if (start_set > end_set) { if (start_set > end_set) {
/* from the begining to the lowest address */ /* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3)) for (set = 0; set <= end_set; set += (0x10 - 3))
{ {
__asm__ __volatile__( __asm__ __volatile__(
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
: /* output parameters */ : /* output parameters */
: [set] "a" (set) : [set] "a" (set)
: "cc" /* clobbered registers */ : "cc" /* clobbered registers */
); );
} }
/* next loop will finish the cache ie pass the hole */ /* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR; end_set = LAST_DCACHE_ADDR;
} }
for (set = start_set; set <= end_set; set += (0x10 - 3)) for (set = start_set; set <= end_set; set += (0x10 - 3))
{ {
__asm__ __volatile__( __asm__ __volatile__(
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t" " addq%.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t" " addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t" " cpushl dc,(%[set]) \n\t"
: /* output parameters */ : /* output parameters */
: [set] "a" (set) : [set] "a" (set)
: "cc" /* clobbered registers */ : "cc" /* clobbered registers */
); );
} }
} }
/* /*
* flush and invalidate a specific region from the both caches. We do not know if the area is cached * flush and invalidate a specific region from the both caches. We do not know if the area is cached
* at all, we do not know in which of the four ways it is cached, but we know the index where they * at all, we do not know in which of the four ways it is cached, but we know the index where they