diff --git a/BaS_gcc/Makefile b/BaS_gcc/Makefile index c036b37..37176b9 100644 --- a/BaS_gcc/Makefile +++ b/BaS_gcc/Makefile @@ -9,7 +9,7 @@ # can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint # toolchain -COMPILE_ELF=Y +COMPILE_ELF=N ifeq (Y,$(COMPILE_ELF)) TCPREFIX=m68k-elf- @@ -95,9 +95,11 @@ CSRCS= \ dspi.c \ driver_vec.c \ driver_mem.c \ + \ MCD_dmaApi.c \ MCD_tasks.c \ MCD_tasksInit.c \ + \ usb.c \ ohci-hcd.c \ ehci-hcd.c \ diff --git a/BaS_gcc/sys/BaS.c b/BaS_gcc/sys/BaS.c index 0a81024..664cc58 100644 --- a/BaS_gcc/sys/BaS.c +++ b/BaS_gcc/sys/BaS.c @@ -179,8 +179,8 @@ void nvram_init(void) for (i = 0; i < 64; i++) { uint8_t data = read_pic_byte(); - *(volatile uint8_t*)0xffff8961 = i; - *(volatile uint8_t*)0xffff8963 = data; + * (volatile uint8_t*) 0xffff8961 = i; + * (volatile uint8_t*) 0xffff8963 = data; } xprintf("finished\r\n"); @@ -233,7 +233,6 @@ void enable_coldfire_interrupts() MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) | MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */ - MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ diff --git a/BaS_gcc/sys/cache.c b/BaS_gcc/sys/cache.c index 34edca1..0e20798 100644 --- a/BaS_gcc/sys/cache.c +++ b/BaS_gcc/sys/cache.c @@ -26,60 +26,61 @@ void cacr_set(uint32_t value) { - extern uint32_t rt_cacr; + extern uint32_t rt_cacr; - rt_cacr = value; - __asm__ __volatile__("movec %0, cacr\n\t" - : /* output */ - : "r" (rt_cacr) - : "memory" /* clobbers */); + rt_cacr = value; + __asm__ __volatile__( + " movec %0, cacr\n\t" + : /* output */ + : "r" (rt_cacr) + : "memory" /* clobbers */); } uint32_t cacr_get(void) { - extern uint32_t rt_cacr; + extern uint32_t rt_cacr; - return rt_cacr; + return rt_cacr; } void disable_data_cache(void) { - flush_and_invalidate_caches(); - cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC); + flush_and_invalidate_caches(); + cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC); } void disable_instruction_cache(void) { - flush_and_invalidate_caches(); - cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC); + flush_and_invalidate_caches(); + cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC); } void enable_data_cache(void) { - cacr_set(cacr_get() & ~CF_CACR_DCINVA); + cacr_set(cacr_get() & ~CF_CACR_DCINVA); } void flush_and_invalidate_caches(void) { - __asm__ __volatile__( - " clr.l d0 \n\t" - " clr.l d1 \n\t" - " move.l d0,a0 \n\t" - "cfa_setloop: \n\t" - " cpushl bc,(a0) | flush\n\t" - " lea 0x10(a0),a0 | index+1\n\t" - " addq.l #1,d1 | index+1\n\t" - " cmpi.w #512,d1 | all sets?\n\t" - " bne.s cfa_setloop | no->\n\t" - " clr.l d1 \n\t" - " addq.l #1,d0 \n\t" - " move.l d0,a0 \n\t" - " cmpi.w #4,d0 | all ways?\n\t" - " bne.s cfa_setloop | no->\n\t" - /* input */ : - /* output */ : - /* clobber */ : "cc", "d0", "d1", "a0" - ); + __asm__ __volatile__( + " clr.l d0 \n\t" + " clr.l d1 \n\t" + " move.l d0,a0 \n\t" + "cfa_setloop: \n\t" + " cpushl bc,(a0) | flush\n\t" + " lea 0x10(a0),a0 | index+1\n\t" + " addq.l #1,d1 | index+1\n\t" + " cmpi.w #512,d1 | all sets?\n\t" + " bne.s cfa_setloop | no->\n\t" + " clr.l d1 \n\t" + " addq.l #1,d0 \n\t" + " move.l d0,a0 \n\t" + " cmpi.w #4,d0 | all ways?\n\t" + " bne.s cfa_setloop | no->\n\t" + /* input */ : + /* output */ : + /* clobber */ : "cc", "d0", "d1", "a0" + ); } /* @@ -87,48 +88,48 @@ void flush_and_invalidate_caches(void) */ void flush_icache_range(void *address, size_t size) { - uint32_t set; - uint32_t start_set; - uint32_t end_set; - void *endaddr = address + size; + uint32_t set; + uint32_t start_set; + uint32_t end_set; + void *endaddr = address + size; - start_set = (uint32_t) address & _ICACHE_SET_MASK; - end_set = (uint32_t) endaddr & _ICACHE_SET_MASK; + start_set = (uint32_t) address & _ICACHE_SET_MASK; + end_set = (uint32_t) endaddr & _ICACHE_SET_MASK; - if (start_set > end_set) { - /* from the begining to the lowest address */ + if (start_set > end_set) { + /* from the begining to the lowest address */ for (set = 0; set <= end_set; set += (0x10 - 3)) { - __asm__ __volatile__( - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - : /* output parameters */ - : [set] "a" (set) /* input parameters */ - : "cc" /* clobbered registers */ - ); - } - /* next loop will finish the cache ie pass the hole */ - end_set = LAST_ICACHE_ADDR; - } - for (set = start_set; set <= end_set; set += (0x10 - 3)) { - __asm__ __volatile__( - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set])" - : /* output parameters */ - : [set] "a" (set) - : "cc" - ); - } + __asm__ __volatile__( + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) /* input parameters */ + : "cc" /* clobbered registers */ + ); + } + /* next loop will finish the cache ie pass the hole */ + end_set = LAST_ICACHE_ADDR; + } + for (set = start_set; set <= end_set; set += (0x10 - 3)) { + __asm__ __volatile__( + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set])" + : /* output parameters */ + : [set] "a" (set) + : "cc" + ); + } } @@ -138,52 +139,53 @@ void flush_icache_range(void *address, size_t size) */ void flush_dcache_range(void *address, size_t size) { - unsigned long set; - unsigned long start_set; - unsigned long end_set; - void *endaddr; + unsigned long set; + unsigned long start_set; + unsigned long end_set; + void *endaddr; - endaddr = address + size; - start_set = (uint32_t) address & _DCACHE_SET_MASK; - end_set = (uint32_t) endaddr & _DCACHE_SET_MASK; + endaddr = address + size; + start_set = (uint32_t) address & _DCACHE_SET_MASK; + end_set = (uint32_t) endaddr & _DCACHE_SET_MASK; - if (start_set > end_set) { - /* from the begining to the lowest address */ - for (set = 0; set <= end_set; set += (0x10 - 3)) - { - __asm__ __volatile__( - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - : /* output parameters */ - : [set] "a" (set) - : "cc" /* clobbered registers */ - ); - } - /* next loop will finish the cache ie pass the hole */ - end_set = LAST_DCACHE_ADDR; - } - for (set = start_set; set <= end_set; set += (0x10 - 3)) - { - __asm__ __volatile__( - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq%.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - : /* output parameters */ - : [set] "a" (set) - : "cc" /* clobbered registers */ - ); - } + if (start_set > end_set) { + /* from the begining to the lowest address */ + for (set = 0; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); + } + /* next loop will finish the cache ie pass the hole */ + end_set = LAST_DCACHE_ADDR; + } + for (set = start_set; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq%.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); + } } + /* * flush and invalidate a specific region from the both caches. We do not know if the area is cached * at all, we do not know in which of the four ways it is cached, but we know the index where they