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fix discrepancies and disable PCI interrupts (temporarily)

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seems to increase stability
This commit is contained in:
Markus Fröschle
2015-10-03 16:12:17 +00:00
parent 20339b2d60
commit 5afb746abb
3 changed files with 119 additions and 116 deletions
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4
BaS_gcc/Makefile
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@@ -9,7 +9,7 @@
# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint # can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
# toolchain # toolchain
COMPILE_ELF=Y COMPILE_ELF=N
ifeq (Y,$(COMPILE_ELF)) ifeq (Y,$(COMPILE_ELF))
TCPREFIX=m68k-elf- TCPREFIX=m68k-elf-
@@ -95,9 +95,11 @@ CSRCS= \
dspi.c \ dspi.c \
driver_vec.c \ driver_vec.c \
driver_mem.c \ driver_mem.c \
\
MCD_dmaApi.c \ MCD_dmaApi.c \
MCD_tasks.c \ MCD_tasks.c \
MCD_tasksInit.c \ MCD_tasksInit.c \
\
usb.c \ usb.c \
ohci-hcd.c \ ohci-hcd.c \
ehci-hcd.c \ ehci-hcd.c \

1
BaS_gcc/sys/BaS.c
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@@ -233,7 +233,6 @@ void enable_coldfire_interrupts()
MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) | MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */ MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */

4
BaS_gcc/sys/cache.c
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@@ -29,7 +29,8 @@ void cacr_set(uint32_t value)
extern uint32_t rt_cacr; extern uint32_t rt_cacr;
rt_cacr = value; rt_cacr = value;
__asm__ __volatile__("movec %0, cacr\n\t" __asm__ __volatile__(
" movec %0, cacr\n\t"
: /* output */ : /* output */
: "r" (rt_cacr) : "r" (rt_cacr)
: "memory" /* clobbers */); : "memory" /* clobbers */);
@@ -184,6 +185,7 @@ void flush_dcache_range(void *address, size_t size)
} }
} }
/* /*
* flush and invalidate a specific region from the both caches. We do not know if the area is cached * flush and invalidate a specific region from the both caches. We do not know if the area is cached
* at all, we do not know in which of the four ways it is cached, but we know the index where they * at all, we do not know in which of the four ways it is cached, but we know the index where they