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experimental branch to build BaS with a GNU toolchain.

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branched from Rev 38 of trunk
This commit is contained in:
Markus Fröschle
2012-10-11 09:50:51 +00:00
parent d5a1713089
commit 522d92cc5f
607 changed files with 187372 additions and 0 deletions
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57
BaS_GNU/BaS_codewarrior/firebeeV1/cfg/DDRAM.cfg Normal file
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; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
; $RCSfile: M5475EVB.cfg,v $
; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
ResetHalt
;Set VBR - debugger must know this in order
; to do exception capture
writecontrolreg 0x0801 0x00000000
; If MBAR changes all following writes must change
; and if a memory configuration file is used,
; the reserved areas in the register block must
; change also.
;Turn on MBAR at 0xFF00_0000
writecontrolreg 0x0C0F 0xFF000000
;Turn on RAMBAR0 at address FF10_0000
writecontrolreg 0x0C04 0xFF100035
;Turn on RAMBAR1 at address FF10_1000
writecontrolreg 0x0C05 0xFF101035
;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
writemem.l 0xFF000500 0xE0000000;
writemem.l 0xFF000508 0x00101980; 16-bit port
writemem.l 0xFF000504 0x007F0001;
;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration
writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
;writemem.l 0xFF000108 0x73611730; SDCFG1
writemem.l 0xFF000108 0x53611730; SDCFG1
;writemem.l 0xFF00010C 0x46770000; SDCFG2
writemem.l 0xFF00010C 0x24730000; SDCFG2
;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR)
;writemem.l 0xFF000100 0x048D0000; SDMR (write to LMR)
writemem.l 0xFF000100 0x04890000; SDMR (write to LMR)
;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (first refresh)
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (second refresh)
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
;writemem.l 0xFF000100 0x008D0000; SDMR (write to LMR)
writemem.l 0xFF000100 0x00890000; SDMR (write to LMR)
;writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh)
writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh)
delay 1000

47
BaS_GNU/BaS_codewarrior/firebeeV1/cfg/DDRAM.mem Normal file
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// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// LogicPD COLDARI1
//
// Reference:
// MCF5475RM.pdf
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address MBAR_BASE 0xFF000000
address MMUBAR_BASE 0xFF040000
usederivative "MCF5475"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM
reserved 0x20000000 0x5FFFFFFF
range 0x60000000 0x7FFFFFFF 4 ReadWrite
range 0x80000000 0xCFFFFFFF 4 ReadWrite
range 0xD0000000 0xFBFFFFFF 4 ReadWrite
reserved 0xFC000000 $MBAR_BASE-1
$MBAR_BASE $MBAR_BASE+0x3FFFF // Memory Mapped Registers
range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM
range $MMUBAR_BASE $MMUBAR_BASE+0xFFFF
reserved $MMUBAR_BASE+1x0000 0xFF0FFFFF // Added to fill gap in MMR
range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0)
range 0xFF101000 0xFFFFFFFF 4 ReadWrite // 4K SRAM1 (RAMBAR1)

11
BaS_GNU/BaS_codewarrior/firebeeV1/cfg/flash.cfg Normal file
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; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
; $RCSfile: M5475EVB.cfg,v $
; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes)
writemem.l 0xFF000500 0xFE000000;
writemem.l 0xFF000508 0x00101980; 16-bit port
writemem.l 0xFF000504 0x007F0001;

48
BaS_GNU/BaS_codewarrior/firebeeV1/cfg/mem.cfg Normal file
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; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
; $RCSfile: M5475EVB.cfg,v $
; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
ResetHalt
;Set VBR - debugger must know this in order
; to do exception capture
writecontrolreg 0x0801 0x00000000
; If MBAR changes all following writes must change
; and if a memory configuration file is used,
; the reserved areas in the register block must
; change also.
;Turn on MBAR at 0xFF00_0000
writecontrolreg 0x0C0F 0xFF000000
;Turn on RAMBAR0 at address FF10_0000
writecontrolreg 0x0C04 0xFF100035
;Turn on RAMBAR1 at address FF10_1000
writecontrolreg 0x0C05 0xFF101035
;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
writemem.l 0xFF000500 0xE0000000;
writemem.l 0xFF000508 0x00001180; 16-bit port
writemem.l 0xFF000504 0x007F0001;
;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration
writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
writemem.l 0xFF000108 0x53722938; SDCFG1
writemem.l 0xFF00010C 0x24330000; SDCFG2
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR)
writemem.l 0xFF000100 0x05890000; SDRM (write to LMR)
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (second refresh)
writemem.l 0xFF000100 0x01890000; SDMR (write to LMR)
writemem.l 0xFF000104 0x710F0F00; SDCR (lock SDMR and enable refresh)
delay 1000

38
BaS_GNU/BaS_codewarrior/firebeeV1/cfg/mem.mem Normal file
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// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// LogicPD COLDARI1
//
// Reference:
// MCF5475RM.pdf
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address MBAR_BASE 0xFF000000
address MMUBAR_BASE 0xFF040000
usederivative "MCF5475"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM
reserved 0x20000000 $MBAR_BASE-1
$MBAR_BASE $MBAR_BASE+0x3FFFF 4 ReadWrite // Memory Mapped Registers
range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM
reserved $MBAR_BASE+0x17FFD $MBAR_BASE+0x1FFBF
$MMUBAR_BASE $MMUBAR_BASE+0x001B
reserved $MMUBAR_BASE+0x001C 0xFF0FFFFF
range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0)
range 0xFF101000 0xFF101FFF 4 ReadWrite // 4K SRAM1 (RAMBAR1)

BIN
BaS_GNU/BaS_codewarrior/firebeeV1/firebeeV1.mcp Normal file
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47
BaS_GNU/BaS_codewarrior/firebeeV1/flash_config.xml Normal file
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<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
<fpconfig>
<targetconfwindow>
<usecustomsettings>true</usecustomsettings>
<targetprocessor>5474</targetprocessor>
<connection>PEMICRO_USB</connection>
<usetargetinit>true</usetargetinit>
<targetinitfile>C:\FireBee\codewarrior\firebeeV1\cfg\mem.cfg</targetinitfile>
<targetmembuffaddr>0x00000000</targetmembuffaddr>
<targetmembuffsize>0x00006000</targetmembuffsize>
<enablelogging>true</enablelogging>
<verifywrites>false</verifywrites>
</targetconfwindow>
<flashconfwindow>
<membaseaddr>0xE0000000</membaseaddr>
<device>M29W640DB</device>
<organization>4Mx16x1</organization>
<flashstart>0xE0000000</flashstart>
<flashend>0xE07FFFFF</flashend>
</flashconfwindow>
<programverifywindow>
<useselectedfile>true</useselectedfile>
<projbuildtargetfile>C:\FireBee\codewarrior\firebeeV1\bin\FLASH.elf.S19</projbuildtargetfile>
<fileiotype>Auto Detect</fileiotype>
<restrictaddrrange>false</restrictaddrrange>
<restrictaddrrangestart>0xFF800000</restrictaddrrangestart>
<restrictaddrrangeend>0xFFFFFFFF</restrictaddrrangeend>
<applyaddroffset>false</applyaddroffset>
<addroffset>0xC0200000</addroffset>
</programverifywindow>
<eraseblankcheckwindow>
<eraseallsectors>false</eraseallsectors>
<sector/>
<processsectorsindividually>false</processsectorsindividually>
</eraseblankcheckwindow>
<checksumwindow>
<computechecksumover>FileOnTarg</computechecksumover>
<addrstart>0xFF800000</addrstart>
<addrsize>0x007FFFFF</addrsize>
</checksumwindow>
</fpconfig>

40
BaS_GNU/BaS_codewarrior/firebeeV1/hardware_diagnostic.xml Normal file
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<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
<configsettings>
<confwindow>
<usecustomsettings>true</usecustomsettings>
<targetprocessor>5474</targetprocessor>
<connection>PEMICRO_USB</connection>
<usetargetinit>true</usetargetinit>
<targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\MCF5475.cfg</targetinitfile>
</confwindow>
<memoryreadwritewindow>
<accesstype>read</accesstype>
<accesssize>long_word</accesssize>
<targetaddress>0x60001000</targetaddress>
<valuetowrite>FFFFFFFF</valuetowrite>
</memoryreadwritewindow>
<scopelooptestwindow>
<accesstype>read</accesstype>
<accesssize>long_word</accesssize>
<targetaddress>0x00100000</targetaddress>
<valuetowrite>0x67</valuetowrite>
<speed>1000</speed>
</scopelooptestwindow>
<memorytestswindow>
<runwalking1s>true</runwalking1s>
<runbusnoise>true</runbusnoise>
<runaddress>true</runaddress>
<startaddress>0x00DE1000</startaddress>
<endaddress>0x00DE11FF</endaddress>
<accesssize>long_word</accesssize>
<passes>1</passes>
<usetargetcpu>false</usetargetcpu>
<targetscratchmemstart>0x00000100</targetscratchmemstart>
<targetscratchmemend>0x0000FFFF</targetscratchmemend>
</memorytestswindow>
</configsettings>

93
BaS_GNU/BaS_codewarrior/firebeeV1/headers/MCF5475.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_H__
#define __MCF5475_H__
/********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
#ifdef __cplusplus
extern "C" {
#endif
#pragma define_section system ".system" far_absolute RW
/***
* MCF5475 Derivative Memory map definitions from linker command files:
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
* linker symbols must be defined in the linker command file.
*/
extern __declspec(system) uint8 __MBAR[];
extern __declspec(system) uint8 __MMUBAR[];
extern __declspec(system) uint8 __RAMBAR0[];
extern __declspec(system) uint8 __RAMBAR0_SIZE[];
extern __declspec(system) uint8 __RAMBAR1[];
extern __declspec(system) uint8 __RAMBAR1_SIZE[];
#define MBAR_ADDRESS (uint32)__MBAR
#define MMUBAR_ADDRESS (uint32)__MMUBAR
#define RAMBAR0_ADDRESS (uint32)__RAMBAR0
#define RAMBAR0_SIZE (uint32)__RAMBAR0_SIZE
#define RAMBAR1_ADDRESS (uint32)__RAMBAR1
#define RAMBAR1_SIZE (uint32)__RAMBAR1_SIZE
#include "MCF5475_SIU.h"
#include "MCF5475_MMU.h"
#include "MCF5475_SDRAMC.h"
#include "MCF5475_XLB.h"
#include "MCF5475_CLOCK.h"
#include "MCF5475_FBCS.h"
#include "MCF5475_INTC.h"
#include "MCF5475_GPT.h"
#include "MCF5475_SLT.h"
#include "MCF5475_GPIO.h"
#include "MCF5475_PAD.h"
#include "MCF5475_PCI.h"
#include "MCF5475_PCIARB.h"
#include "MCF5475_EPORT.h"
#include "MCF5475_CTM.h"
#include "MCF5475_DMA.h"
#include "MCF5475_PSC.h"
#include "MCF5475_DSPI.h"
#include "MCF5475_I2C.h"
#include "MCF5475_FEC.h"
#include "MCF5475_USB.h"
#include "MCF5475_SRAM.h"
#include "MCF5475_SEC.h"
#ifdef __cplusplus
}
#endif
#endif /* __MCF5475_H__ */

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BaS_GNU/BaS_codewarrior/firebeeV1/headers/MCF5475_CLOCK.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_CLOCK_H__
#define __MCF5475_CLOCK_H__
/*********************************************************************
*
* Clock Module (CLOCK)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CLOCK_SPCR (*(vuint32*)(&__MBAR[0x300]))
/* Bit definitions and macros for MCF_CLOCK_SPCR */
#define MCF_CLOCK_SPCR_MEMEN (0x1)
#define MCF_CLOCK_SPCR_PCIEN (0x2)
#define MCF_CLOCK_SPCR_FBEN (0x4)
#define MCF_CLOCK_SPCR_CAN0EN (0x8)
#define MCF_CLOCK_SPCR_DMAEN (0x10)
#define MCF_CLOCK_SPCR_FEC0EN (0x20)
#define MCF_CLOCK_SPCR_FEC1EN (0x40)
#define MCF_CLOCK_SPCR_USBEN (0x80)
#define MCF_CLOCK_SPCR_PSCEN (0x200)
#define MCF_CLOCK_SPCR_CAN1EN (0x800)
#define MCF_CLOCK_SPCR_CRYENA (0x1000)
#define MCF_CLOCK_SPCR_CRYENB (0x2000)
#define MCF_CLOCK_SPCR_COREN (0x4000)
#define MCF_CLOCK_SPCR_PLLK (0x80000000)
#endif /* __MCF5475_CLOCK_H__ */

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BaS_GNU/BaS_codewarrior/firebeeV1/headers/MCF5475_CTM.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_CTM_H__
#define __MCF5475_CTM_H__
/*********************************************************************
*
* Comm Timer Module (CTM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CTM_CTCR0 (*(vuint32*)(&__MBAR[0x7F00]))
#define MCF_CTM_CTCR1 (*(vuint32*)(&__MBAR[0x7F04]))
#define MCF_CTM_CTCR2 (*(vuint32*)(&__MBAR[0x7F08]))
#define MCF_CTM_CTCR3 (*(vuint32*)(&__MBAR[0x7F0C]))
#define MCF_CTM_CTCR4 (*(vuint32*)(&__MBAR[0x7F10]))
#define MCF_CTM_CTCR5 (*(vuint32*)(&__MBAR[0x7F14]))
#define MCF_CTM_CTCR6 (*(vuint32*)(&__MBAR[0x7F18]))
#define MCF_CTM_CTCR7 (*(vuint32*)(&__MBAR[0x7F1C]))
#define MCF_CTM_CTCRF(x) (*(vuint32*)(&__MBAR[0x7F00 + ((x)*0x4)]))
#define MCF_CTM_CTCRV(x) (*(vuint32*)(&__MBAR[0x7F10 + ((x-4)*0x4)]))
/* Bit definitions and macros for MCF_CTM_CTCRF */
#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0)
#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10)
#define MCF_CTM_CTCRF_S_CLK_1 (0)
#define MCF_CTM_CTCRF_S_CLK_2 (0x10000)
#define MCF_CTM_CTCRF_S_CLK_4 (0x20000)
#define MCF_CTM_CTCRF_S_CLK_8 (0x30000)
#define MCF_CTM_CTCRF_S_CLK_16 (0x40000)
#define MCF_CTM_CTCRF_S_CLK_32 (0x50000)
#define MCF_CTM_CTCRF_S_CLK_64 (0x60000)
#define MCF_CTM_CTCRF_S_CLK_128 (0x70000)
#define MCF_CTM_CTCRF_S_CLK_256 (0x80000)
#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000)
#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14)
#define MCF_CTM_CTCRF_PCT_100 (0)
#define MCF_CTM_CTCRF_PCT_50 (0x100000)
#define MCF_CTM_CTCRF_PCT_25 (0x200000)
#define MCF_CTM_CTCRF_PCT_12p5 (0x300000)
#define MCF_CTM_CTCRF_PCT_6p25 (0x400000)
#define MCF_CTM_CTCRF_PCT_OFF (0x500000)
#define MCF_CTM_CTCRF_M (0x800000)
#define MCF_CTM_CTCRF_IM (0x1000000)
#define MCF_CTM_CTCRF_I (0x80000000)
/* Bit definitions and macros for MCF_CTM_CTCRV */
#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0)
#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18)
#define MCF_CTM_CTCRV_PCT_100 (0)
#define MCF_CTM_CTCRV_PCT_50 (0x1000000)
#define MCF_CTM_CTCRV_PCT_25 (0x2000000)
#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000)
#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000)
#define MCF_CTM_CTCRV_PCT_OFF (0x5000000)
#define MCF_CTM_CTCRV_M (0x8000000)
#define MCF_CTM_CTCRV_S (0x10000000)
#endif /* __MCF5475_CTM_H__ */

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BaS_GNU/BaS_codewarrior/firebeeV1/headers/MCF5475_DMA.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_DMA_H__
#define __MCF5475_DMA_H__
/*********************************************************************
*
* Multichannel DMA (DMA)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DMA_TASKBAR (*(vuint32*)(&__MBAR[0x8000]))
#define MCF_DMA_CP (*(vuint32*)(&__MBAR[0x8004]))
#define MCF_DMA_EP (*(vuint32*)(&__MBAR[0x8008]))
#define MCF_DMA_VP (*(vuint32*)(&__MBAR[0x800C]))
#define MCF_DMA_PTD (*(vuint32*)(&__MBAR[0x8010]))
#define MCF_DMA_DIPR (*(vuint32*)(&__MBAR[0x8014]))
#define MCF_DMA_DIMR (*(vuint32*)(&__MBAR[0x8018]))
#define MCF_DMA_TCR0 (*(vuint16*)(&__MBAR[0x801C]))
#define MCF_DMA_TCR1 (*(vuint16*)(&__MBAR[0x801E]))
#define MCF_DMA_TCR2 (*(vuint16*)(&__MBAR[0x8020]))
#define MCF_DMA_TCR3 (*(vuint16*)(&__MBAR[0x8022]))
#define MCF_DMA_TCR4 (*(vuint16*)(&__MBAR[0x8024]))
#define MCF_DMA_TCR5 (*(vuint16*)(&__MBAR[0x8026]))
#define MCF_DMA_TCR6 (*(vuint16*)(&__MBAR[0x8028]))
#define MCF_DMA_TCR7 (*(vuint16*)(&__MBAR[0x802A]))
#define MCF_DMA_TCR8 (*(vuint16*)(&__MBAR[0x802C]))
#define MCF_DMA_TCR9 (*(vuint16*)(&__MBAR[0x802E]))
#define MCF_DMA_TCR10 (*(vuint16*)(&__MBAR[0x8030]))
#define MCF_DMA_TCR11 (*(vuint16*)(&__MBAR[0x8032]))
#define MCF_DMA_TCR12 (*(vuint16*)(&__MBAR[0x8034]))
#define MCF_DMA_TCR13 (*(vuint16*)(&__MBAR[0x8036]))
#define MCF_DMA_TCR14 (*(vuint16*)(&__MBAR[0x8038]))
#define MCF_DMA_TCR15 (*(vuint16*)(&__MBAR[0x803A]))
#define MCF_DMA_PRIOR0 (*(vuint8 *)(&__MBAR[0x803C]))
#define MCF_DMA_PRIOR1 (*(vuint8 *)(&__MBAR[0x803D]))
#define MCF_DMA_PRIOR2 (*(vuint8 *)(&__MBAR[0x803E]))
#define MCF_DMA_PRIOR3 (*(vuint8 *)(&__MBAR[0x803F]))
#define MCF_DMA_PRIOR4 (*(vuint8 *)(&__MBAR[0x8040]))
#define MCF_DMA_PRIOR5 (*(vuint8 *)(&__MBAR[0x8041]))
#define MCF_DMA_PRIOR6 (*(vuint8 *)(&__MBAR[0x8042]))
#define MCF_DMA_PRIOR7 (*(vuint8 *)(&__MBAR[0x8043]))
#define MCF_DMA_PRIOR8 (*(vuint8 *)(&__MBAR[0x8044]))
#define MCF_DMA_PRIOR9 (*(vuint8 *)(&__MBAR[0x8045]))
#define MCF_DMA_PRIOR10 (*(vuint8 *)(&__MBAR[0x8046]))
#define MCF_DMA_PRIOR11 (*(vuint8 *)(&__MBAR[0x8047]))
#define MCF_DMA_PRIOR12 (*(vuint8 *)(&__MBAR[0x8048]))
#define MCF_DMA_PRIOR13 (*(vuint8 *)(&__MBAR[0x8049]))
#define MCF_DMA_PRIOR14 (*(vuint8 *)(&__MBAR[0x804A]))
#define MCF_DMA_PRIOR15 (*(vuint8 *)(&__MBAR[0x804B]))
#define MCF_DMA_PRIOR16 (*(vuint8 *)(&__MBAR[0x804C]))
#define MCF_DMA_PRIOR17 (*(vuint8 *)(&__MBAR[0x804D]))
#define MCF_DMA_PRIOR18 (*(vuint8 *)(&__MBAR[0x804E]))
#define MCF_DMA_PRIOR19 (*(vuint8 *)(&__MBAR[0x804F]))
#define MCF_DMA_PRIOR20 (*(vuint8 *)(&__MBAR[0x8050]))
#define MCF_DMA_PRIOR21 (*(vuint8 *)(&__MBAR[0x8051]))
#define MCF_DMA_PRIOR22 (*(vuint8 *)(&__MBAR[0x8052]))
#define MCF_DMA_PRIOR23 (*(vuint8 *)(&__MBAR[0x8053]))
#define MCF_DMA_PRIOR24 (*(vuint8 *)(&__MBAR[0x8054]))
#define MCF_DMA_PRIOR25 (*(vuint8 *)(&__MBAR[0x8055]))
#define MCF_DMA_PRIOR26 (*(vuint8 *)(&__MBAR[0x8056]))
#define MCF_DMA_PRIOR27 (*(vuint8 *)(&__MBAR[0x8057]))
#define MCF_DMA_PRIOR28 (*(vuint8 *)(&__MBAR[0x8058]))
#define MCF_DMA_PRIOR29 (*(vuint8 *)(&__MBAR[0x8059]))
#define MCF_DMA_PRIOR30 (*(vuint8 *)(&__MBAR[0x805A]))
#define MCF_DMA_PRIOR31 (*(vuint8 *)(&__MBAR[0x805B]))
#define MCF_DMA_IMCR (*(vuint32*)(&__MBAR[0x805C]))
#define MCF_DMA_TSKSZ0 (*(vuint32*)(&__MBAR[0x8060]))
#define MCF_DMA_TSKSZ1 (*(vuint32*)(&__MBAR[0x8064]))
#define MCF_DMA_DBGCOMP0 (*(vuint32*)(&__MBAR[0x8070]))
#define MCF_DMA_DBGCOMP2 (*(vuint32*)(&__MBAR[0x8074]))
#define MCF_DMA_DBGCTL (*(vuint32*)(&__MBAR[0x8078]))
#define MCF_DMA_TCR(x) (*(vuint16*)(&__MBAR[0x801C + ((x)*0x2)]))
#define MCF_DMA_PRIOR(x) (*(vuint8 *)(&__MBAR[0x803C + ((x)*0x1)]))
/* Bit definitions and macros for MCF_DMA_TASKBAR */
#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_CP */
#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_EP */
#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_VP */
#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_PTD */
#define MCF_DMA_PTD_PCTL0 (0x1)
#define MCF_DMA_PTD_PCTL1 (0x2)
#define MCF_DMA_PTD_PCTL13 (0x2000)
#define MCF_DMA_PTD_PCTL14 (0x4000)
#define MCF_DMA_PTD_PCTL15 (0x8000)
/* Bit definitions and macros for MCF_DMA_DIPR */
#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DIMR */
#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_TCR */
#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0)
#define MCF_DMA_TCR_HLDINITNUM (0x20)
#define MCF_DMA_TCR_HIPRITSKEN (0x40)
#define MCF_DMA_TCR_ASTRT (0x80)
#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8)
#define MCF_DMA_TCR_ALWINIT (0x2000)
#define MCF_DMA_TCR_V (0x4000)
#define MCF_DMA_TCR_EN (0x8000)
/* Bit definitions and macros for MCF_DMA_PRIOR */
#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0)
#define MCF_DMA_PRIOR_HLD (0x80)
/* Bit definitions and macros for MCF_DMA_IMCR */
#define MCF_DMA_IMCR_IMC0(x) (((x)&0x3)<<0)
#define MCF_DMA_IMCR_IMC1(x) (((x)&0x3)<<0x2)
#define MCF_DMA_IMCR_IMC2(x) (((x)&0x3)<<0x4)
#define MCF_DMA_IMCR_IMC3(x) (((x)&0x3)<<0x6)
#define MCF_DMA_IMCR_IMC4(x) (((x)&0x3)<<0x8)
#define MCF_DMA_IMCR_IMC5(x) (((x)&0x3)<<0xA)
#define MCF_DMA_IMCR_IMC6(x) (((x)&0x3)<<0xC)
#define MCF_DMA_IMCR_IMC7(x) (((x)&0x3)<<0xE)
#define MCF_DMA_IMCR_IMC8(x) (((x)&0x3)<<0x10)
#define MCF_DMA_IMCR_IMC9(x) (((x)&0x3)<<0x12)
#define MCF_DMA_IMCR_IMC10(x) (((x)&0x3)<<0x14)
#define MCF_DMA_IMCR_IMC11(x) (((x)&0x3)<<0x16)
#define MCF_DMA_IMCR_IMC12(x) (((x)&0x3)<<0x18)
#define MCF_DMA_IMCR_IMC13(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_IMCR_IMC14(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_IMCR_IMC15(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0)
#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2)
#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4)
#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6)
#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8)
#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA)
#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC)
#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE)
#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10)
#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12)
#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14)
#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16)
#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18)
#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0)
#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2)
#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4)
#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6)
#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8)
#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA)
#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC)
#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE)
#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10)
#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12)
#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14)
#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16)
#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18)
#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DBGCTL */
#define MCF_DMA_DBGCTL_I (0x2)
#define MCF_DMA_DBGCTL_E (0x4)
#define MCF_DMA_DBGCTL_AND_OR (0x80)
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8)
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB)
#define MCF_DMA_DBGCTL_B (0x4000)
#define MCF_DMA_DBGCTL_AA (0x8000)
#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10)
#endif /* __MCF5475_DMA_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_DSPI_H__
#define __MCF5475_DSPI_H__
/*********************************************************************
*
* DMA Serial Peripheral Interface (DSPI)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DSPI_DMCR (*(vuint32*)(&__MBAR[0x8A00]))
#define MCF_DSPI_DTCR (*(vuint32*)(&__MBAR[0x8A08]))
#define MCF_DSPI_DCTAR0 (*(vuint32*)(&__MBAR[0x8A0C]))
#define MCF_DSPI_DCTAR1 (*(vuint32*)(&__MBAR[0x8A10]))
#define MCF_DSPI_DCTAR2 (*(vuint32*)(&__MBAR[0x8A14]))
#define MCF_DSPI_DCTAR3 (*(vuint32*)(&__MBAR[0x8A18]))
#define MCF_DSPI_DCTAR4 (*(vuint32*)(&__MBAR[0x8A1C]))
#define MCF_DSPI_DCTAR5 (*(vuint32*)(&__MBAR[0x8A20]))
#define MCF_DSPI_DCTAR6 (*(vuint32*)(&__MBAR[0x8A24]))
#define MCF_DSPI_DCTAR7 (*(vuint32*)(&__MBAR[0x8A28]))
#define MCF_DSPI_DSR (*(vuint32*)(&__MBAR[0x8A2C]))
#define MCF_DSPI_DIRSR (*(vuint32*)(&__MBAR[0x8A30]))
#define MCF_DSPI_DTFR (*(vuint32*)(&__MBAR[0x8A34]))
#define MCF_DSPI_DRFR (*(vuint32*)(&__MBAR[0x8A38]))
#define MCF_DSPI_DTFDR0 (*(vuint32*)(&__MBAR[0x8A3C]))
#define MCF_DSPI_DTFDR1 (*(vuint32*)(&__MBAR[0x8A40]))
#define MCF_DSPI_DTFDR2 (*(vuint32*)(&__MBAR[0x8A44]))
#define MCF_DSPI_DTFDR3 (*(vuint32*)(&__MBAR[0x8A48]))
#define MCF_DSPI_DRFDR0 (*(vuint32*)(&__MBAR[0x8A7C]))
#define MCF_DSPI_DRFDR1 (*(vuint32*)(&__MBAR[0x8A80]))
#define MCF_DSPI_DRFDR2 (*(vuint32*)(&__MBAR[0x8A84]))
#define MCF_DSPI_DRFDR3 (*(vuint32*)(&__MBAR[0x8A88]))
#define MCF_DSPI_DCTAR(x) (*(vuint32*)(&__MBAR[0x8A0C + ((x)*0x4)]))
#define MCF_DSPI_DTFDR(x) (*(vuint32*)(&__MBAR[0x8A3C + ((x)*0x4)]))
#define MCF_DSPI_DRFDR(x) (*(vuint32*)(&__MBAR[0x8A7C + ((x)*0x4)]))
/* Bit definitions and macros for MCF_DSPI_DMCR */
#define MCF_DSPI_DMCR_HALT (0x1)
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8)
#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0)
#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100)
#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200)
#define MCF_DSPI_DMCR_CRXF (0x400)
#define MCF_DSPI_DMCR_CTXF (0x800)
#define MCF_DSPI_DMCR_DRXF (0x1000)
#define MCF_DSPI_DMCR_DTXF (0x2000)
#define MCF_DSPI_DMCR_CSIS0 (0x10000)
#define MCF_DSPI_DMCR_CSIS2 (0x40000)
#define MCF_DSPI_DMCR_CSIS3 (0x80000)
#define MCF_DSPI_DMCR_CSIS5 (0x200000)
#define MCF_DSPI_DMCR_ROOE (0x1000000)
#define MCF_DSPI_DMCR_PCSSE (0x2000000)
#define MCF_DSPI_DMCR_MTFE (0x4000000)
#define MCF_DSPI_DMCR_FRZ (0x8000000)
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C)
#define MCF_DSPI_DMCR_CSCK (0x40000000)
#define MCF_DSPI_DMCR_MSTR (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTCR */
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_DSPI_DCTAR */
#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0)
#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4)
#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8)
#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC)
#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10)
#define MCF_DSPI_DCTAR_PBR_1CLK (0)
#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000)
#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000)
#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000)
#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12)
#define MCF_DSPI_DCTAR_PDT_1CLK (0)
#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000)
#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000)
#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000)
#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14)
#define MCF_DSPI_DCTAR_PASC_1CLK (0)
#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000)
#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000)
#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000)
#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16)
#define MCF_DSPI_DCTAR_LSBFE (0x1000000)
#define MCF_DSPI_DCTAR_CPHA (0x2000000)
#define MCF_DSPI_DCTAR_CPOL (0x4000000)
#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B)
/* Bit definitions and macros for MCF_DSPI_DSR */
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0)
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4)
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8)
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC)
#define MCF_DSPI_DSR_RFDF (0x20000)
#define MCF_DSPI_DSR_RFOF (0x80000)
#define MCF_DSPI_DSR_TFFF (0x2000000)
#define MCF_DSPI_DSR_TFUF (0x8000000)
#define MCF_DSPI_DSR_EOQF (0x10000000)
#define MCF_DSPI_DSR_TXRXS (0x40000000)
#define MCF_DSPI_DSR_TCF (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DIRSR */
#define MCF_DSPI_DIRSR_RFDFS (0x10000)
#define MCF_DSPI_DIRSR_RFDFE (0x20000)
#define MCF_DSPI_DIRSR_RFOFE (0x80000)
#define MCF_DSPI_DIRSR_TFFFS (0x1000000)
#define MCF_DSPI_DIRSR_TFFFE (0x2000000)
#define MCF_DSPI_DIRSR_TFUFE (0x8000000)
#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
#define MCF_DSPI_DIRSR_TCFE (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTFR */
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0)
#define MCF_DSPI_DTFR_CS0 (0x10000)
#define MCF_DSPI_DTFR_CS2 (0x40000)
#define MCF_DSPI_DTFR_CS3 (0x80000)
#define MCF_DSPI_DTFR_CS5 (0x200000)
#define MCF_DSPI_DTFR_CTCNT (0x4000000)
#define MCF_DSPI_DTFR_EOQ (0x8000000)
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C)
#define MCF_DSPI_DTFR_CONT (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DRFR */
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DSPI_DTFDR */
#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0)
#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_DSPI_DRFDR */
#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0)
#endif /* __MCF5475_DSPI_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_EPORT_H__
#define __MCF5475_EPORT_H__
/*********************************************************************
*
* Edge Port Module (EPORT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_EPORT_EPPAR (*(vuint16*)(&__MBAR[0xF00]))
#define MCF_EPORT_EPDDR (*(vuint8 *)(&__MBAR[0xF04]))
#define MCF_EPORT_EPIER (*(vuint8 *)(&__MBAR[0xF05]))
#define MCF_EPORT_EPDR (*(vuint8 *)(&__MBAR[0xF08]))
#define MCF_EPORT_EPPDR (*(vuint8 *)(&__MBAR[0xF09]))
#define MCF_EPORT_EPFR (*(vuint8 *)(&__MBAR[0xF0C]))
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define MCF_EPORT_EPPAR_LEVEL (0)
#define MCF_EPORT_EPPAR_RISING (0x1)
#define MCF_EPORT_EPPAR_FALLING (0x2)
#define MCF_EPORT_EPPAR_BOTH (0x3)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF_EPORT_EPIER_EPIE1 (0x2)
#define MCF_EPORT_EPIER_EPIE2 (0x4)
#define MCF_EPORT_EPIER_EPIE3 (0x8)
#define MCF_EPORT_EPIER_EPIE4 (0x10)
#define MCF_EPORT_EPIER_EPIE5 (0x20)
#define MCF_EPORT_EPIER_EPIE6 (0x40)
#define MCF_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF_EPORT_EPDR_EPD1 (0x2)
#define MCF_EPORT_EPDR_EPD2 (0x4)
#define MCF_EPORT_EPDR_EPD3 (0x8)
#define MCF_EPORT_EPDR_EPD4 (0x10)
#define MCF_EPORT_EPDR_EPD5 (0x20)
#define MCF_EPORT_EPDR_EPD6 (0x40)
#define MCF_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF_EPORT_EPFR_EPF1 (0x2)
#define MCF_EPORT_EPFR_EPF2 (0x4)
#define MCF_EPORT_EPFR_EPF3 (0x8)
#define MCF_EPORT_EPFR_EPF4 (0x10)
#define MCF_EPORT_EPFR_EPF5 (0x20)
#define MCF_EPORT_EPFR_EPF6 (0x40)
#define MCF_EPORT_EPFR_EPF7 (0x80)
#endif /* __MCF5475_EPORT_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_FBCS_H__
#define __MCF5475_FBCS_H__
/*********************************************************************
*
* FlexBus Chip Select Module (FBCS)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_FBCS0_CSAR (*(vuint32*)(&__MBAR[0x500]))
#define MCF_FBCS0_CSMR (*(vuint32*)(&__MBAR[0x504]))
#define MCF_FBCS0_CSCR (*(vuint32*)(&__MBAR[0x508]))
#define MCF_FBCS1_CSAR (*(vuint32*)(&__MBAR[0x50C]))
#define MCF_FBCS1_CSMR (*(vuint32*)(&__MBAR[0x510]))
#define MCF_FBCS1_CSCR (*(vuint32*)(&__MBAR[0x514]))
#define MCF_FBCS2_CSAR (*(vuint32*)(&__MBAR[0x518]))
#define MCF_FBCS2_CSMR (*(vuint32*)(&__MBAR[0x51C]))
#define MCF_FBCS2_CSCR (*(vuint32*)(&__MBAR[0x520]))
#define MCF_FBCS3_CSAR (*(vuint32*)(&__MBAR[0x524]))
#define MCF_FBCS3_CSMR (*(vuint32*)(&__MBAR[0x528]))
#define MCF_FBCS3_CSCR (*(vuint32*)(&__MBAR[0x52C]))
#define MCF_FBCS4_CSAR (*(vuint32*)(&__MBAR[0x530]))
#define MCF_FBCS4_CSMR (*(vuint32*)(&__MBAR[0x534]))
#define MCF_FBCS4_CSCR (*(vuint32*)(&__MBAR[0x538]))
#define MCF_FBCS5_CSAR (*(vuint32*)(&__MBAR[0x53C]))
#define MCF_FBCS5_CSMR (*(vuint32*)(&__MBAR[0x540]))
#define MCF_FBCS5_CSCR (*(vuint32*)(&__MBAR[0x544]))
#define MCF_FBCS_CSAR(x) (*(vuint32*)(&__MBAR[0x500 + ((x)*0xC)]))
#define MCF_FBCS_CSMR(x) (*(vuint32*)(&__MBAR[0x504 + ((x)*0xC)]))
#define MCF_FBCS_CSCR(x) (*(vuint32*)(&__MBAR[0x508 + ((x)*0xC)]))
/* Bit definitions and macros for MCF_FBCS_CSAR */
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF_FBCS_CSMR */
#define MCF_FBCS_CSMR_V (0x1)
#define MCF_FBCS_CSMR_WP (0x100)
#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
#define MCF_FBCS_CSMR_BAM_512K (0x70000)
#define MCF_FBCS_CSMR_BAM_256K (0x30000)
#define MCF_FBCS_CSMR_BAM_128K (0x10000)
#define MCF_FBCS_CSMR_BAM_64K (0)
/* Bit definitions and macros for MCF_FBCS_CSCR */
#define MCF_FBCS_CSCR_BSTW (0x8)
#define MCF_FBCS_CSCR_BSTR (0x10)
#define MCF_FBCS_CSCR_BEM (0x20)
#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
#define MCF_FBCS_CSCR_PS_32 (0)
#define MCF_FBCS_CSCR_PS_8 (0x40)
#define MCF_FBCS_CSCR_PS_16 (0x80)
#define MCF_FBCS_CSCR_AA (0x100)
#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
#define MCF_FBCS_CSCR_SWSEN (0x800000)
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
#endif /* __MCF5475_FBCS_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_FEC_H__
#define __MCF5475_FEC_H__
/*********************************************************************
*
* Fast Ethernet Controller(FEC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_FEC0_EIR (*(vuint32*)(&__MBAR[0x9004]))
#define MCF_FEC0_EIMR (*(vuint32*)(&__MBAR[0x9008]))
#define MCF_FEC0_ECR (*(vuint32*)(&__MBAR[0x9024]))
#define MCF_FEC0_MMFR (*(vuint32*)(&__MBAR[0x9040]))
#define MCF_FEC0_MSCR (*(vuint32*)(&__MBAR[0x9044]))
#define MCF_FEC0_MIBC (*(vuint32*)(&__MBAR[0x9064]))
#define MCF_FEC0_RCR (*(vuint32*)(&__MBAR[0x9084]))
#define MCF_FEC0_RHR (*(vuint32*)(&__MBAR[0x9088]))
#define MCF_FEC0_TCR (*(vuint32*)(&__MBAR[0x90C4]))
#define MCF_FEC0_PALR (*(vuint32*)(&__MBAR[0x90E4]))
#define MCF_FEC0_PAHR (*(vuint32*)(&__MBAR[0x90E8]))
#define MCF_FEC0_OPD (*(vuint32*)(&__MBAR[0x90EC]))
#define MCF_FEC0_IAUR (*(vuint32*)(&__MBAR[0x9118]))
#define MCF_FEC0_IALR (*(vuint32*)(&__MBAR[0x911C]))
#define MCF_FEC0_GAUR (*(vuint32*)(&__MBAR[0x9120]))
#define MCF_FEC0_GALR (*(vuint32*)(&__MBAR[0x9124]))
#define MCF_FEC0_FECTFWR (*(vuint32*)(&__MBAR[0x9144]))
#define MCF_FEC0_FECRFDR (*(vuint32*)(&__MBAR[0x9184]))
#define MCF_FEC0_FECRFSR (*(vuint32*)(&__MBAR[0x9188]))
#define MCF_FEC0_FECRFCR (*(vuint32*)(&__MBAR[0x918C]))
#define MCF_FEC0_FECRLRFP (*(vuint32*)(&__MBAR[0x9190]))
#define MCF_FEC0_FECRLWFP (*(vuint32*)(&__MBAR[0x9194]))
#define MCF_FEC0_FECRFAR (*(vuint32*)(&__MBAR[0x9198]))
#define MCF_FEC0_FECRFRP (*(vuint32*)(&__MBAR[0x919C]))
#define MCF_FEC0_FECRFWP (*(vuint32*)(&__MBAR[0x91A0]))
#define MCF_FEC0_FECTFDR (*(vuint32*)(&__MBAR[0x91A4]))
#define MCF_FEC0_FECTFSR (*(vuint32*)(&__MBAR[0x91A8]))
#define MCF_FEC0_FECTFCR (*(vuint32*)(&__MBAR[0x91AC]))
#define MCF_FEC0_FECTLRFP (*(vuint32*)(&__MBAR[0x91B0]))
#define MCF_FEC0_FECTLWFP (*(vuint32*)(&__MBAR[0x91B4]))
#define MCF_FEC0_FECTFAR (*(vuint32*)(&__MBAR[0x91B8]))
#define MCF_FEC0_FECTFRP (*(vuint32*)(&__MBAR[0x91BC]))
#define MCF_FEC0_FECTFWP (*(vuint32*)(&__MBAR[0x91C0]))
#define MCF_FEC0_FECFRST (*(vuint32*)(&__MBAR[0x91C4]))
#define MCF_FEC0_FECCTCWR (*(vuint32*)(&__MBAR[0x91C8]))
#define MCF_FEC0_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9200]))
#define MCF_FEC0_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9204]))
#define MCF_FEC0_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9208]))
#define MCF_FEC0_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x920C]))
#define MCF_FEC0_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9210]))
#define MCF_FEC0_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9214]))
#define MCF_FEC0_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9218]))
#define MCF_FEC0_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x921C]))
#define MCF_FEC0_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9220]))
#define MCF_FEC0_RMON_T_COL (*(vuint32*)(&__MBAR[0x9224]))
#define MCF_FEC0_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9228]))
#define MCF_FEC0_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x922C]))
#define MCF_FEC0_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9230]))
#define MCF_FEC0_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9234]))
#define MCF_FEC0_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9238]))
#define MCF_FEC0_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x923C]))
#define MCF_FEC0_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9240]))
#define MCF_FEC0_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9244]))
#define MCF_FEC0_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9248]))
#define MCF_FEC0_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x924C]))
#define MCF_FEC0_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9250]))
#define MCF_FEC0_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9254]))
#define MCF_FEC0_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9258]))
#define MCF_FEC0_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x925C]))
#define MCF_FEC0_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9260]))
#define MCF_FEC0_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9264]))
#define MCF_FEC0_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9268]))
#define MCF_FEC0_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x926C]))
#define MCF_FEC0_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9270]))
#define MCF_FEC0_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9274]))
#define MCF_FEC0_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9280]))
#define MCF_FEC0_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9284]))
#define MCF_FEC0_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9288]))
#define MCF_FEC0_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x928C]))
#define MCF_FEC0_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9290]))
#define MCF_FEC0_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9294]))
#define MCF_FEC0_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9298]))
#define MCF_FEC0_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x929C]))
#define MCF_FEC0_RMON_R_JAB (*(vuint32*)(&__MBAR[0x92A0]))
#define MCF_FEC0_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x92A4]))
#define MCF_FEC0_RMON_R_P64 (*(vuint32*)(&__MBAR[0x92A8]))
#define MCF_FEC0_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x92AC]))
#define MCF_FEC0_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x92B0]))
#define MCF_FEC0_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x92B4]))
#define MCF_FEC0_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x92B8]))
#define MCF_FEC0_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x92BC]))
#define MCF_FEC0_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x92C0]))
#define MCF_FEC0_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x92C4]))
#define MCF_FEC0_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x92C8]))
#define MCF_FEC0_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x92CC]))
#define MCF_FEC0_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x92D0]))
#define MCF_FEC0_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x92D4]))
#define MCF_FEC0_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x92D8]))
#define MCF_FEC0_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x92DC]))
#define MCF_FEC0_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x92E0]))
#define MCF_FEC1_EIR (*(vuint32*)(&__MBAR[0x9804]))
#define MCF_FEC1_EIMR (*(vuint32*)(&__MBAR[0x9808]))
#define MCF_FEC1_ECR (*(vuint32*)(&__MBAR[0x9824]))
#define MCF_FEC1_MMFR (*(vuint32*)(&__MBAR[0x9840]))
#define MCF_FEC1_MSCR (*(vuint32*)(&__MBAR[0x9844]))
#define MCF_FEC1_MIBC (*(vuint32*)(&__MBAR[0x9864]))
#define MCF_FEC1_RCR (*(vuint32*)(&__MBAR[0x9884]))
#define MCF_FEC1_RHR (*(vuint32*)(&__MBAR[0x9888]))
#define MCF_FEC1_TCR (*(vuint32*)(&__MBAR[0x98C4]))
#define MCF_FEC1_PALR (*(vuint32*)(&__MBAR[0x98E4]))
#define MCF_FEC1_PAHR (*(vuint32*)(&__MBAR[0x98E8]))
#define MCF_FEC1_OPD (*(vuint32*)(&__MBAR[0x98EC]))
#define MCF_FEC1_IAUR (*(vuint32*)(&__MBAR[0x9918]))
#define MCF_FEC1_IALR (*(vuint32*)(&__MBAR[0x991C]))
#define MCF_FEC1_GAUR (*(vuint32*)(&__MBAR[0x9920]))
#define MCF_FEC1_GALR (*(vuint32*)(&__MBAR[0x9924]))
#define MCF_FEC1_FECTFWR (*(vuint32*)(&__MBAR[0x9944]))
#define MCF_FEC1_FECRFDR (*(vuint32*)(&__MBAR[0x9984]))
#define MCF_FEC1_FECRFSR (*(vuint32*)(&__MBAR[0x9988]))
#define MCF_FEC1_FECRFCR (*(vuint32*)(&__MBAR[0x998C]))
#define MCF_FEC1_FECRLRFP (*(vuint32*)(&__MBAR[0x9990]))
#define MCF_FEC1_FECRLWFP (*(vuint32*)(&__MBAR[0x9994]))
#define MCF_FEC1_FECRFAR (*(vuint32*)(&__MBAR[0x9998]))
#define MCF_FEC1_FECRFRP (*(vuint32*)(&__MBAR[0x999C]))
#define MCF_FEC1_FECRFWP (*(vuint32*)(&__MBAR[0x99A0]))
#define MCF_FEC1_FECTFDR (*(vuint32*)(&__MBAR[0x99A4]))
#define MCF_FEC1_FECTFSR (*(vuint32*)(&__MBAR[0x99A8]))
#define MCF_FEC1_FECTFCR (*(vuint32*)(&__MBAR[0x99AC]))
#define MCF_FEC1_FECTLRFP (*(vuint32*)(&__MBAR[0x99B0]))
#define MCF_FEC1_FECTLWFP (*(vuint32*)(&__MBAR[0x99B4]))
#define MCF_FEC1_FECTFAR (*(vuint32*)(&__MBAR[0x99B8]))
#define MCF_FEC1_FECTFRP (*(vuint32*)(&__MBAR[0x99BC]))
#define MCF_FEC1_FECTFWP (*(vuint32*)(&__MBAR[0x99C0]))
#define MCF_FEC1_FECFRST (*(vuint32*)(&__MBAR[0x99C4]))
#define MCF_FEC1_FECCTCWR (*(vuint32*)(&__MBAR[0x99C8]))
#define MCF_FEC1_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9A00]))
#define MCF_FEC1_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9A04]))
#define MCF_FEC1_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9A08]))
#define MCF_FEC1_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x9A0C]))
#define MCF_FEC1_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A10]))
#define MCF_FEC1_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A14]))
#define MCF_FEC1_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9A18]))
#define MCF_FEC1_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x9A1C]))
#define MCF_FEC1_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9A20]))
#define MCF_FEC1_RMON_T_COL (*(vuint32*)(&__MBAR[0x9A24]))
#define MCF_FEC1_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9A28]))
#define MCF_FEC1_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x9A2C]))
#define MCF_FEC1_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9A30]))
#define MCF_FEC1_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9A34]))
#define MCF_FEC1_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9A38]))
#define MCF_FEC1_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x9A3C]))
#define MCF_FEC1_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9A40]))
#define MCF_FEC1_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9A44]))
#define MCF_FEC1_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9A48]))
#define MCF_FEC1_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x9A4C]))
#define MCF_FEC1_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9A50]))
#define MCF_FEC1_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9A54]))
#define MCF_FEC1_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9A58]))
#define MCF_FEC1_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x9A5C]))
#define MCF_FEC1_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9A60]))
#define MCF_FEC1_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9A64]))
#define MCF_FEC1_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9A68]))
#define MCF_FEC1_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x9A6C]))
#define MCF_FEC1_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9A70]))
#define MCF_FEC1_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9A74]))
#define MCF_FEC1_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9A80]))
#define MCF_FEC1_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9A84]))
#define MCF_FEC1_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9A88]))
#define MCF_FEC1_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x9A8C]))
#define MCF_FEC1_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A90]))
#define MCF_FEC1_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A94]))
#define MCF_FEC1_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9A98]))
#define MCF_FEC1_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x9A9C]))
#define MCF_FEC1_RMON_R_JAB (*(vuint32*)(&__MBAR[0x9AA0]))
#define MCF_FEC1_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x9AA4]))
#define MCF_FEC1_RMON_R_P64 (*(vuint32*)(&__MBAR[0x9AA8]))
#define MCF_FEC1_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x9AAC]))
#define MCF_FEC1_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x9AB0]))
#define MCF_FEC1_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x9AB4]))
#define MCF_FEC1_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x9AB8]))
#define MCF_FEC1_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x9ABC]))
#define MCF_FEC1_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x9AC0]))
#define MCF_FEC1_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x9AC4]))
#define MCF_FEC1_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x9AC8]))
#define MCF_FEC1_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x9ACC]))
#define MCF_FEC1_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x9AD0]))
#define MCF_FEC1_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x9AD4]))
#define MCF_FEC1_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x9AD8]))
#define MCF_FEC1_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x9ADC]))
#define MCF_FEC1_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x9AE0]))
#define MCF_FEC_EIR(x) (*(vuint32*)(&__MBAR[0x9004 + ((x)*0x800)]))
#define MCF_FEC_EIMR(x) (*(vuint32*)(&__MBAR[0x9008 + ((x)*0x800)]))
#define MCF_FEC_ECR(x) (*(vuint32*)(&__MBAR[0x9024 + ((x)*0x800)]))
#define MCF_FEC_MMFR(x) (*(vuint32*)(&__MBAR[0x9040 + ((x)*0x800)]))
#define MCF_FEC_MSCR(x) (*(vuint32*)(&__MBAR[0x9044 + ((x)*0x800)]))
#define MCF_FEC_MIBC(x) (*(vuint32*)(&__MBAR[0x9064 + ((x)*0x800)]))
#define MCF_FEC_RCR(x) (*(vuint32*)(&__MBAR[0x9084 + ((x)*0x800)]))
#define MCF_FEC_RHR(x) (*(vuint32*)(&__MBAR[0x9088 + ((x)*0x800)]))
#define MCF_FEC_TCR(x) (*(vuint32*)(&__MBAR[0x90C4 + ((x)*0x800)]))
#define MCF_FEC_PALR(x) (*(vuint32*)(&__MBAR[0x90E4 + ((x)*0x800)]))
#define MCF_FEC_PAHR(x) (*(vuint32*)(&__MBAR[0x90E8 + ((x)*0x800)]))
#define MCF_FEC_OPD(x) (*(vuint32*)(&__MBAR[0x90EC + ((x)*0x800)]))
#define MCF_FEC_IAUR(x) (*(vuint32*)(&__MBAR[0x9118 + ((x)*0x800)]))
#define MCF_FEC_IALR(x) (*(vuint32*)(&__MBAR[0x911C + ((x)*0x800)]))
#define MCF_FEC_GAUR(x) (*(vuint32*)(&__MBAR[0x9120 + ((x)*0x800)]))
#define MCF_FEC_GALR(x) (*(vuint32*)(&__MBAR[0x9124 + ((x)*0x800)]))
#define MCF_FEC_FECTFWR(x) (*(vuint32*)(&__MBAR[0x9144 + ((x)*0x800)]))
#define MCF_FEC_FECRFDR(x) (*(vuint32*)(&__MBAR[0x9184 + ((x)*0x800)]))
#define MCF_FEC_FECRFSR(x) (*(vuint32*)(&__MBAR[0x9188 + ((x)*0x800)]))
#define MCF_FEC_FECRFCR(x) (*(vuint32*)(&__MBAR[0x918C + ((x)*0x800)]))
#define MCF_FEC_FECRLRFP(x) (*(vuint32*)(&__MBAR[0x9190 + ((x)*0x800)]))
#define MCF_FEC_FECRLWFP(x) (*(vuint32*)(&__MBAR[0x9194 + ((x)*0x800)]))
#define MCF_FEC_FECRFAR(x) (*(vuint32*)(&__MBAR[0x9198 + ((x)*0x800)]))
#define MCF_FEC_FECRFRP(x) (*(vuint32*)(&__MBAR[0x919C + ((x)*0x800)]))
#define MCF_FEC_FECRFWP(x) (*(vuint32*)(&__MBAR[0x91A0 + ((x)*0x800)]))
#define MCF_FEC_FECTFDR(x) (*(vuint32*)(&__MBAR[0x91A4 + ((x)*0x800)]))
#define MCF_FEC_FECTFSR(x) (*(vuint32*)(&__MBAR[0x91A8 + ((x)*0x800)]))
#define MCF_FEC_FECTFCR(x) (*(vuint32*)(&__MBAR[0x91AC + ((x)*0x800)]))
#define MCF_FEC_FECTLRFP(x) (*(vuint32*)(&__MBAR[0x91B0 + ((x)*0x800)]))
#define MCF_FEC_FECTLWFP(x) (*(vuint32*)(&__MBAR[0x91B4 + ((x)*0x800)]))
#define MCF_FEC_FECTFAR(x) (*(vuint32*)(&__MBAR[0x91B8 + ((x)*0x800)]))
#define MCF_FEC_FECTFRP(x) (*(vuint32*)(&__MBAR[0x91BC + ((x)*0x800)]))
#define MCF_FEC_FECTFWP(x) (*(vuint32*)(&__MBAR[0x91C0 + ((x)*0x800)]))
#define MCF_FEC_FECFRST(x) (*(vuint32*)(&__MBAR[0x91C4 + ((x)*0x800)]))
#define MCF_FEC_FECCTCWR(x) (*(vuint32*)(&__MBAR[0x91C8 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_DROP(x) (*(vuint32*)(&__MBAR[0x9200 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32*)(&__MBAR[0x9204 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9208 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32*)(&__MBAR[0x920C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9210 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9214 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9218 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32*)(&__MBAR[0x921C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_JAB(x) (*(vuint32*)(&__MBAR[0x9220 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_COL(x) (*(vuint32*)(&__MBAR[0x9224 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P64(x) (*(vuint32*)(&__MBAR[0x9228 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32*)(&__MBAR[0x922C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32*)(&__MBAR[0x9230 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32*)(&__MBAR[0x9234 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32*)(&__MBAR[0x9238 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x923C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x9240 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32*)(&__MBAR[0x9244 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32*)(&__MBAR[0x9248 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x924C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32*)(&__MBAR[0x9250 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32*)(&__MBAR[0x9254 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32*)(&__MBAR[0x9258 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32*)(&__MBAR[0x925C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32*)(&__MBAR[0x9260 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32*)(&__MBAR[0x9264 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32*)(&__MBAR[0x9268 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32*)(&__MBAR[0x926C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32*)(&__MBAR[0x9270 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x9274 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_DROP(x) (*(vuint32*)(&__MBAR[0x9280 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32*)(&__MBAR[0x9284 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9288 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32*)(&__MBAR[0x928C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9290 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9294 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9298 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32*)(&__MBAR[0x929C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_JAB(x) (*(vuint32*)(&__MBAR[0x92A0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32*)(&__MBAR[0x92A4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P64(x) (*(vuint32*)(&__MBAR[0x92A8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32*)(&__MBAR[0x92AC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32*)(&__MBAR[0x92B0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32*)(&__MBAR[0x92B4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P512TO1023(x) (*(vuint32*)(&__MBAR[0x92B8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x92BC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x92C0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32*)(&__MBAR[0x92C4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32*)(&__MBAR[0x92C8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x92CC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32*)(&__MBAR[0x92D0 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32*)(&__MBAR[0x92D4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32*)(&__MBAR[0x92D8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32*)(&__MBAR[0x92DC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x92E0 + ((x)*0x800)]))
/* Bit definitions and macros for MCF_FEC_EIR */
#define MCF_FEC_EIR_RFERR (0x20000)
#define MCF_FEC_EIR_XFERR (0x40000)
#define MCF_FEC_EIR_XFUN (0x80000)
#define MCF_FEC_EIR_RL (0x100000)
#define MCF_FEC_EIR_LC (0x200000)
#define MCF_FEC_EIR_MII (0x800000)
#define MCF_FEC_EIR_TXF (0x8000000)
#define MCF_FEC_EIR_GRA (0x10000000)
#define MCF_FEC_EIR_BABT (0x20000000)
#define MCF_FEC_EIR_BABR (0x40000000)
#define MCF_FEC_EIR_HBERR (0x80000000)
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_EIMR */
#define MCF_FEC_EIMR_RFERR (0x20000)
#define MCF_FEC_EIMR_XFERR (0x40000)
#define MCF_FEC_EIMR_XFUN (0x80000)
#define MCF_FEC_EIMR_RL (0x100000)
#define MCF_FEC_EIMR_LC (0x200000)
#define MCF_FEC_EIMR_MII (0x800000)
#define MCF_FEC_EIMR_TXF (0x8000000)
#define MCF_FEC_EIMR_GRA (0x10000000)
#define MCF_FEC_EIMR_BABT (0x20000000)
#define MCF_FEC_EIMR_BABR (0x40000000)
#define MCF_FEC_EIMR_HBERR (0x80000000)
#define MCF_FEC_EIMR_MASK_ALL (0)
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_ECR */
#define MCF_FEC_ECR_RESET (0x1)
#define MCF_FEC_ECR_ETHER_EN (0x2)
/* Bit definitions and macros for MCF_FEC_MMFR */
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
#define MCF_FEC_MMFR_TA_10 (0x20000)
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
#define MCF_FEC_MMFR_OP_READ (0x20000000)
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
#define MCF_FEC_MMFR_ST_01 (0x40000000)
/* Bit definitions and macros for MCF_FEC_MSCR */
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1)
/* Bit definitions and macros for MCF_FEC_MIBC */
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
/* Bit definitions and macros for MCF_FEC_RCR */
#define MCF_FEC_RCR_LOOP (0x1)
#define MCF_FEC_RCR_DRT (0x2)
#define MCF_FEC_RCR_MII_MODE (0x4)
#define MCF_FEC_RCR_PROM (0x8)
#define MCF_FEC_RCR_BC_REJ (0x10)
#define MCF_FEC_RCR_FCE (0x20)
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
/* Bit definitions and macros for MCF_FEC_RHR */
#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18)
#define MCF_FEC_RHR_MULTCAST (0x40000000)
#define MCF_FEC_RHR_FCE (0x80000000)
/* Bit definitions and macros for MCF_FEC_TCR */
#define MCF_FEC_TCR_GTS (0x1)
#define MCF_FEC_TCR_HBC (0x2)
#define MCF_FEC_TCR_FDEN (0x4)
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
/* Bit definitions and macros for MCF_FEC_PALR */
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_PAHR */
#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_FEC_OPD */
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_FEC_IAUR */
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IALR */
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_GAUR */
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_GALR */
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFWR */
#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0)
#define MCF_FEC_FECTFWR_X_WMRK_64 (0)
#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1)
#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2)
#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3)
#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4)
#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5)
#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6)
#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7)
#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8)
#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9)
#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA)
#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB)
#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC)
#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD)
#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE)
#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF)
/* Bit definitions and macros for MCF_FEC_FECRFDR */
#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFSR */
#define MCF_FEC_FECRFSR_EMT (0x10000)
#define MCF_FEC_FECRFSR_ALARM (0x20000)
#define MCF_FEC_FECRFSR_FU (0x40000)
#define MCF_FEC_FECRFSR_FRMRDY (0x80000)
#define MCF_FEC_FECRFSR_OF (0x100000)
#define MCF_FEC_FECRFSR_UF (0x200000)
#define MCF_FEC_FECRFSR_RXW (0x400000)
#define MCF_FEC_FECRFSR_FAE (0x800000)
#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_FEC_FECRFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECRFCR */
#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_FECRFCR_OF_MSK (0x80000)
#define MCF_FEC_FECRFCR_UF_MSK (0x100000)
#define MCF_FEC_FECRFCR_RXW_MSK (0x200000)
#define MCF_FEC_FECRFCR_FAE_MSK (0x400000)
#define MCF_FEC_FECRFCR_IP_MSK (0x800000)
#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_FEC_FECRFCR_FRMEN (0x8000000)
#define MCF_FEC_FECRFCR_TIMER (0x10000000)
/* Bit definitions and macros for MCF_FEC_FECRLRFP */
#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRLWFP */
#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFAR */
#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFRP */
#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFWP */
#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFDR */
#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFSR */
#define MCF_FEC_FECTFSR_EMT (0x10000)
#define MCF_FEC_FECTFSR_ALARM (0x20000)
#define MCF_FEC_FECTFSR_FU (0x40000)
#define MCF_FEC_FECTFSR_FRMRDY (0x80000)
#define MCF_FEC_FECTFSR_OF (0x100000)
#define MCF_FEC_FECTFSR_UF (0x200000)
#define MCF_FEC_FECTFSR_FAE (0x800000)
#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_FEC_FECTFSR_TXW (0x40000000)
#define MCF_FEC_FECTFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECTFCR */
#define MCF_FEC_FECTFCR_RESERVED (0x200000)
#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000)
#define MCF_FEC_FECTFCR_TXW_MASK (0x240000)
#define MCF_FEC_FECTFCR_OF_MSK (0x280000)
#define MCF_FEC_FECTFCR_UF_MSK (0x300000)
#define MCF_FEC_FECTFCR_FAE_MSK (0x600000)
#define MCF_FEC_FECTFCR_IP_MSK (0xA00000)
#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000)
#define MCF_FEC_FECTFCR_FRMEN (0x8200000)
#define MCF_FEC_FECTFCR_TIMER (0x10200000)
#define MCF_FEC_FECTFCR_WFR (0x20200000)
#define MCF_FEC_FECTFCR_WCTL (0x40200000)
/* Bit definitions and macros for MCF_FEC_FECTLRFP */
#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTLWFP */
#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFAR */
#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFRP */
#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFWP */
#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECFRST */
#define MCF_FEC_FECFRST_RST_CTL (0x1000000)
#define MCF_FEC_FECFRST_SW_RST (0x2000000)
/* Bit definitions and macros for MCF_FEC_FECCTCWR */
#define MCF_FEC_FECCTCWR_TFCW (0x1000000)
#define MCF_FEC_FECCTCWR_CRC (0x2000000)
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF5475_FEC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_GPIO_H__
#define __MCF5475_GPIO_H__
/*********************************************************************
*
* General Purpose I/O (GPIO)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPIO_PODR_FBCTL (*(vuint8 *)(&__MBAR[0xA00]))
#define MCF_GPIO_PDDR_FBCTL (*(vuint8 *)(&__MBAR[0xA10]))
#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8 *)(&__MBAR[0xA20]))
#define MCF_GPIO_PCLRR_FBCTL (*(vuint8 *)(&__MBAR[0xA30]))
#define MCF_GPIO_PODR_FBCS (*(vuint8 *)(&__MBAR[0xA01]))
#define MCF_GPIO_PDDR_FBCS (*(vuint8 *)(&__MBAR[0xA11]))
#define MCF_GPIO_PPDSDR_FBCS (*(vuint8 *)(&__MBAR[0xA21]))
#define MCF_GPIO_PCLRR_FBCS (*(vuint8 *)(&__MBAR[0xA31]))
#define MCF_GPIO_PODR_DMA (*(vuint8 *)(&__MBAR[0xA02]))
#define MCF_GPIO_PDDR_DMA (*(vuint8 *)(&__MBAR[0xA12]))
#define MCF_GPIO_PPDSDR_DMA (*(vuint8 *)(&__MBAR[0xA22]))
#define MCF_GPIO_PCLRR_DMA (*(vuint8 *)(&__MBAR[0xA32]))
#define MCF_GPIO_PODR_FEC0H (*(vuint8 *)(&__MBAR[0xA04]))
#define MCF_GPIO_PDDR_FEC0H (*(vuint8 *)(&__MBAR[0xA14]))
#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8 *)(&__MBAR[0xA24]))
#define MCF_GPIO_PCLRR_FEC0H (*(vuint8 *)(&__MBAR[0xA34]))
#define MCF_GPIO_PODR_FEC0L (*(vuint8 *)(&__MBAR[0xA05]))
#define MCF_GPIO_PDDR_FEC0L (*(vuint8 *)(&__MBAR[0xA15]))
#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8 *)(&__MBAR[0xA25]))
#define MCF_GPIO_PCLRR_FEC0L (*(vuint8 *)(&__MBAR[0xA35]))
#define MCF_GPIO_PODR_FEC1H (*(vuint8 *)(&__MBAR[0xA06]))
#define MCF_GPIO_PDDR_FEC1H (*(vuint8 *)(&__MBAR[0xA16]))
#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8 *)(&__MBAR[0xA26]))
#define MCF_GPIO_PCLRR_FEC1H (*(vuint8 *)(&__MBAR[0xA36]))
#define MCF_GPIO_PODR_FEC1L (*(vuint8 *)(&__MBAR[0xA07]))
#define MCF_GPIO_PDDR_FEC1L (*(vuint8 *)(&__MBAR[0xA17]))
#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8 *)(&__MBAR[0xA27]))
#define MCF_GPIO_PCLRR_FEC1L (*(vuint8 *)(&__MBAR[0xA37]))
#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(&__MBAR[0xA08]))
#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(&__MBAR[0xA18]))
#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(&__MBAR[0xA28]))
#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(&__MBAR[0xA38]))
#define MCF_GPIO_PODR_PCIBG (*(vuint8 *)(&__MBAR[0xA09]))
#define MCF_GPIO_PDDR_PCIBG (*(vuint8 *)(&__MBAR[0xA19]))
#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8 *)(&__MBAR[0xA29]))
#define MCF_GPIO_PCLRR_PCIBG (*(vuint8 *)(&__MBAR[0xA39]))
#define MCF_GPIO_PODR_PCIBR (*(vuint8 *)(&__MBAR[0xA0A]))
#define MCF_GPIO_PDDR_PCIBR (*(vuint8 *)(&__MBAR[0xA1A]))
#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8 *)(&__MBAR[0xA2A]))
#define MCF_GPIO_PCLRR_PCIBR (*(vuint8 *)(&__MBAR[0xA3A]))
#define MCF_GPIO2_PODR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA0C]))
#define MCF_GPIO2_PDDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA1C]))
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA2C]))
#define MCF_GPIO2_PCLRR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA3C]))
#define MCF_GPIO0_PODR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA0D]))
#define MCF_GPIO0_PDDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA1D]))
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA2D]))
#define MCF_GPIO0_PCLRR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA3D]))
#define MCF_GPIO_PODR_DSPI (*(vuint8 *)(&__MBAR[0xA0E]))
#define MCF_GPIO_PDDR_DSPI (*(vuint8 *)(&__MBAR[0xA1E]))
#define MCF_GPIO_PPDSDR_DSPI (*(vuint8 *)(&__MBAR[0xA2E]))
#define MCF_GPIO_PCLRR_DSPI (*(vuint8 *)(&__MBAR[0xA3E]))
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1)
#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2)
#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4)
#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
#endif /* __MCF5475_GPIO_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_GPT_H__
#define __MCF5475_GPT_H__
/*********************************************************************
*
* General Purpose Timers (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPT0_GMS (*(vuint32*)(&__MBAR[0x800]))
#define MCF_GPT0_GCIR (*(vuint32*)(&__MBAR[0x804]))
#define MCF_GPT0_GPWM (*(vuint32*)(&__MBAR[0x808]))
#define MCF_GPT0_GSR (*(vuint32*)(&__MBAR[0x80C]))
#define MCF_GPT1_GMS (*(vuint32*)(&__MBAR[0x810]))
#define MCF_GPT1_GCIR (*(vuint32*)(&__MBAR[0x814]))
#define MCF_GPT1_GPWM (*(vuint32*)(&__MBAR[0x818]))
#define MCF_GPT1_GSR (*(vuint32*)(&__MBAR[0x81C]))
#define MCF_GPT2_GMS (*(vuint32*)(&__MBAR[0x820]))
#define MCF_GPT2_GCIR (*(vuint32*)(&__MBAR[0x824]))
#define MCF_GPT2_GPWM (*(vuint32*)(&__MBAR[0x828]))
#define MCF_GPT2_GSR (*(vuint32*)(&__MBAR[0x82C]))
#define MCF_GPT3_GMS (*(vuint32*)(&__MBAR[0x830]))
#define MCF_GPT3_GCIR (*(vuint32*)(&__MBAR[0x834]))
#define MCF_GPT3_GPWM (*(vuint32*)(&__MBAR[0x838]))
#define MCF_GPT3_GSR (*(vuint32*)(&__MBAR[0x83C]))
#define MCF_GPT_GMS(x) (*(vuint32*)(&__MBAR[0x800 + ((x)*0x10)]))
#define MCF_GPT_GCIR(x) (*(vuint32*)(&__MBAR[0x804 + ((x)*0x10)]))
#define MCF_GPT_GPWM(x) (*(vuint32*)(&__MBAR[0x808 + ((x)*0x10)]))
#define MCF_GPT_GSR(x) (*(vuint32*)(&__MBAR[0x80C + ((x)*0x10)]))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0)
#define MCF_GPT_GMS_TMS_DISABLE (0)
#define MCF_GPT_GMS_TMS_INCAPT (0x1)
#define MCF_GPT_GMS_TMS_OUTCAPT (0x2)
#define MCF_GPT_GMS_TMS_PWM (0x3)
#define MCF_GPT_GMS_TMS_GPIO (0x4)
#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4)
#define MCF_GPT_GMS_GPIO_INPUT (0)
#define MCF_GPT_GMS_GPIO_OUTLO (0x20)
#define MCF_GPT_GMS_GPIO_OUTHI (0x30)
#define MCF_GPT_GMS_IEN (0x100)
#define MCF_GPT_GMS_OD (0x200)
#define MCF_GPT_GMS_SC (0x400)
#define MCF_GPT_GMS_CE (0x1000)
#define MCF_GPT_GMS_WDEN (0x8000)
#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10)
#define MCF_GPT_GMS_ICT_ANY (0)
#define MCF_GPT_GMS_ICT_RISE (0x10000)
#define MCF_GPT_GMS_ICT_FALL (0x20000)
#define MCF_GPT_GMS_ICT_PULSE (0x30000)
#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14)
#define MCF_GPT_GMS_OCT_FRCLOW (0)
#define MCF_GPT_GMS_OCT_PULSEHI (0x100000)
#define MCF_GPT_GMS_OCT_PULSELO (0x200000)
#define MCF_GPT_GMS_OCT_TOGGLE (0x300000)
#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_GPT_GCIR */
#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0)
#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_GPT_GPWM */
#define MCF_GPT_GPWM_LOAD (0x1)
#define MCF_GPT_GPWM_PWMOP (0x100)
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_GPT_GSR */
#define MCF_GPT_GSR_CAPT (0x1)
#define MCF_GPT_GSR_COMP (0x2)
#define MCF_GPT_GSR_PWMP (0x4)
#define MCF_GPT_GSR_TEXP (0x8)
#define MCF_GPT_GSR_PIN (0x100)
#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC)
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10)
#endif /* __MCF5475_GPT_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_I2C_H__
#define __MCF5475_I2C_H__
/*********************************************************************
*
* I2C Module (I2C)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_I2C_I2ADR (*(vuint8 *)(&__MBAR[0x8F00]))
#define MCF_I2C_I2FDR (*(vuint8 *)(&__MBAR[0x8F04]))
#define MCF_I2C_I2CR (*(vuint8 *)(&__MBAR[0x8F08]))
#define MCF_I2C_I2SR (*(vuint8 *)(&__MBAR[0x8F0C]))
#define MCF_I2C_I2DR (*(vuint8 *)(&__MBAR[0x8F10]))
#define MCF_I2C_I2ICR (*(vuint8 *)(&__MBAR[0x8F20]))
/* Bit definitions and macros for MCF_I2C_I2ADR */
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_I2C_I2FDR */
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_I2C_I2CR */
#define MCF_I2C_I2CR_RSTA (0x4)
#define MCF_I2C_I2CR_TXAK (0x8)
#define MCF_I2C_I2CR_MTX (0x10)
#define MCF_I2C_I2CR_MSTA (0x20)
#define MCF_I2C_I2CR_IIEN (0x40)
#define MCF_I2C_I2CR_IEN (0x80)
/* Bit definitions and macros for MCF_I2C_I2SR */
#define MCF_I2C_I2SR_RXAK (0x1)
#define MCF_I2C_I2SR_IIF (0x2)
#define MCF_I2C_I2SR_SRW (0x4)
#define MCF_I2C_I2SR_IAL (0x10)
#define MCF_I2C_I2SR_IBB (0x20)
#define MCF_I2C_I2SR_IAAS (0x40)
#define MCF_I2C_I2SR_ICF (0x80)
/* Bit definitions and macros for MCF_I2C_I2DR */
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_I2C_I2ICR */
#define MCF_I2C_I2ICR_IE (0x1)
#define MCF_I2C_I2ICR_RE (0x2)
#define MCF_I2C_I2ICR_TE (0x4)
#define MCF_I2C_I2ICR_BNBE (0x8)
#endif /* __MCF5475_I2C_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_INTC_H__
#define __MCF5475_INTC_H__
/*********************************************************************
*
* Interrupt Controller (INTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_INTC_IPRH (*(vuint32*)(&__MBAR[0x700]))
#define MCF_INTC_IPRL (*(vuint32*)(&__MBAR[0x704]))
#define MCF_INTC_IMRH (*(vuint32*)(&__MBAR[0x708]))
#define MCF_INTC_IMRL (*(vuint32*)(&__MBAR[0x70C]))
#define MCF_INTC_INTFRCH (*(vuint32*)(&__MBAR[0x710]))
#define MCF_INTC_INTFRCL (*(vuint32*)(&__MBAR[0x714]))
#define MCF_INTC_IRLR (*(vuint8 *)(&__MBAR[0x718]))
#define MCF_INTC_IACKLPR (*(vuint8 *)(&__MBAR[0x719]))
#define MCF_INTC_ICR01 (*(vuint8 *)(&__MBAR[0x741]))
#define MCF_INTC_ICR02 (*(vuint8 *)(&__MBAR[0x742]))
#define MCF_INTC_ICR03 (*(vuint8 *)(&__MBAR[0x743]))
#define MCF_INTC_ICR04 (*(vuint8 *)(&__MBAR[0x744]))
#define MCF_INTC_ICR05 (*(vuint8 *)(&__MBAR[0x745]))
#define MCF_INTC_ICR06 (*(vuint8 *)(&__MBAR[0x746]))
#define MCF_INTC_ICR07 (*(vuint8 *)(&__MBAR[0x747]))
#define MCF_INTC_ICR08 (*(vuint8 *)(&__MBAR[0x748]))
#define MCF_INTC_ICR09 (*(vuint8 *)(&__MBAR[0x749]))
#define MCF_INTC_ICR10 (*(vuint8 *)(&__MBAR[0x74A]))
#define MCF_INTC_ICR11 (*(vuint8 *)(&__MBAR[0x74B]))
#define MCF_INTC_ICR12 (*(vuint8 *)(&__MBAR[0x74C]))
#define MCF_INTC_ICR13 (*(vuint8 *)(&__MBAR[0x74D]))
#define MCF_INTC_ICR14 (*(vuint8 *)(&__MBAR[0x74E]))
#define MCF_INTC_ICR15 (*(vuint8 *)(&__MBAR[0x74F]))
#define MCF_INTC_ICR16 (*(vuint8 *)(&__MBAR[0x750]))
#define MCF_INTC_ICR17 (*(vuint8 *)(&__MBAR[0x751]))
#define MCF_INTC_ICR18 (*(vuint8 *)(&__MBAR[0x752]))
#define MCF_INTC_ICR19 (*(vuint8 *)(&__MBAR[0x753]))
#define MCF_INTC_ICR20 (*(vuint8 *)(&__MBAR[0x754]))
#define MCF_INTC_ICR21 (*(vuint8 *)(&__MBAR[0x755]))
#define MCF_INTC_ICR22 (*(vuint8 *)(&__MBAR[0x756]))
#define MCF_INTC_ICR23 (*(vuint8 *)(&__MBAR[0x757]))
#define MCF_INTC_ICR24 (*(vuint8 *)(&__MBAR[0x758]))
#define MCF_INTC_ICR25 (*(vuint8 *)(&__MBAR[0x759]))
#define MCF_INTC_ICR26 (*(vuint8 *)(&__MBAR[0x75A]))
#define MCF_INTC_ICR27 (*(vuint8 *)(&__MBAR[0x75B]))
#define MCF_INTC_ICR28 (*(vuint8 *)(&__MBAR[0x75C]))
#define MCF_INTC_ICR29 (*(vuint8 *)(&__MBAR[0x75D]))
#define MCF_INTC_ICR30 (*(vuint8 *)(&__MBAR[0x75E]))
#define MCF_INTC_ICR31 (*(vuint8 *)(&__MBAR[0x75F]))
#define MCF_INTC_ICR32 (*(vuint8 *)(&__MBAR[0x760]))
#define MCF_INTC_ICR33 (*(vuint8 *)(&__MBAR[0x761]))
#define MCF_INTC_ICR34 (*(vuint8 *)(&__MBAR[0x762]))
#define MCF_INTC_ICR35 (*(vuint8 *)(&__MBAR[0x763]))
#define MCF_INTC_ICR36 (*(vuint8 *)(&__MBAR[0x764]))
#define MCF_INTC_ICR37 (*(vuint8 *)(&__MBAR[0x765]))
#define MCF_INTC_ICR38 (*(vuint8 *)(&__MBAR[0x766]))
#define MCF_INTC_ICR39 (*(vuint8 *)(&__MBAR[0x767]))
#define MCF_INTC_ICR40 (*(vuint8 *)(&__MBAR[0x768]))
#define MCF_INTC_ICR41 (*(vuint8 *)(&__MBAR[0x769]))
#define MCF_INTC_ICR42 (*(vuint8 *)(&__MBAR[0x76A]))
#define MCF_INTC_ICR43 (*(vuint8 *)(&__MBAR[0x76B]))
#define MCF_INTC_ICR44 (*(vuint8 *)(&__MBAR[0x76C]))
#define MCF_INTC_ICR45 (*(vuint8 *)(&__MBAR[0x76D]))
#define MCF_INTC_ICR46 (*(vuint8 *)(&__MBAR[0x76E]))
#define MCF_INTC_ICR47 (*(vuint8 *)(&__MBAR[0x76F]))
#define MCF_INTC_ICR48 (*(vuint8 *)(&__MBAR[0x770]))
#define MCF_INTC_ICR49 (*(vuint8 *)(&__MBAR[0x771]))
#define MCF_INTC_ICR50 (*(vuint8 *)(&__MBAR[0x772]))
#define MCF_INTC_ICR51 (*(vuint8 *)(&__MBAR[0x773]))
#define MCF_INTC_ICR52 (*(vuint8 *)(&__MBAR[0x774]))
#define MCF_INTC_ICR53 (*(vuint8 *)(&__MBAR[0x775]))
#define MCF_INTC_ICR54 (*(vuint8 *)(&__MBAR[0x776]))
#define MCF_INTC_ICR55 (*(vuint8 *)(&__MBAR[0x777]))
#define MCF_INTC_ICR56 (*(vuint8 *)(&__MBAR[0x778]))
#define MCF_INTC_ICR57 (*(vuint8 *)(&__MBAR[0x779]))
#define MCF_INTC_ICR58 (*(vuint8 *)(&__MBAR[0x77A]))
#define MCF_INTC_ICR59 (*(vuint8 *)(&__MBAR[0x77B]))
#define MCF_INTC_ICR60 (*(vuint8 *)(&__MBAR[0x77C]))
#define MCF_INTC_ICR61 (*(vuint8 *)(&__MBAR[0x77D]))
#define MCF_INTC_ICR62 (*(vuint8 *)(&__MBAR[0x77E]))
#define MCF_INTC_ICR63 (*(vuint8 *)(&__MBAR[0x77F]))
#define MCF_INTC_SWIACK (*(vuint8 *)(&__MBAR[0x7E0]))
#define MCF_INTC_L1IACK (*(vuint8 *)(&__MBAR[0x7E4]))
#define MCF_INTC_L2IACK (*(vuint8 *)(&__MBAR[0x7E8]))
#define MCF_INTC_L3IACK (*(vuint8 *)(&__MBAR[0x7EC]))
#define MCF_INTC_L4IACK (*(vuint8 *)(&__MBAR[0x7F0]))
#define MCF_INTC_L5IACK (*(vuint8 *)(&__MBAR[0x7F4]))
#define MCF_INTC_L6IACK (*(vuint8 *)(&__MBAR[0x7F8]))
#define MCF_INTC_L7IACK (*(vuint8 *)(&__MBAR[0x7FC]))
#define MCF_INTC_ICR(x) (*(vuint8 *)(&__MBAR[0x741 + ((x-1)*0x1)]))
#define MCF_INTC_LIACK(x) (*(vuint8 *)(&__MBAR[0x7E4 + ((x-1)*0x4)]))
/* Bit definitions and macros for MCF_INTC_IPRH */
#define MCF_INTC_IPRH_INT32 (0x1)
#define MCF_INTC_IPRH_INT33 (0x2)
#define MCF_INTC_IPRH_INT34 (0x4)
#define MCF_INTC_IPRH_INT35 (0x8)
#define MCF_INTC_IPRH_INT36 (0x10)
#define MCF_INTC_IPRH_INT37 (0x20)
#define MCF_INTC_IPRH_INT38 (0x40)
#define MCF_INTC_IPRH_INT39 (0x80)
#define MCF_INTC_IPRH_INT40 (0x100)
#define MCF_INTC_IPRH_INT41 (0x200)
#define MCF_INTC_IPRH_INT42 (0x400)
#define MCF_INTC_IPRH_INT43 (0x800)
#define MCF_INTC_IPRH_INT44 (0x1000)
#define MCF_INTC_IPRH_INT45 (0x2000)
#define MCF_INTC_IPRH_INT46 (0x4000)
#define MCF_INTC_IPRH_INT47 (0x8000)
#define MCF_INTC_IPRH_INT48 (0x10000)
#define MCF_INTC_IPRH_INT49 (0x20000)
#define MCF_INTC_IPRH_INT50 (0x40000)
#define MCF_INTC_IPRH_INT51 (0x80000)
#define MCF_INTC_IPRH_INT52 (0x100000)
#define MCF_INTC_IPRH_INT53 (0x200000)
#define MCF_INTC_IPRH_INT54 (0x400000)
#define MCF_INTC_IPRH_INT55 (0x800000)
#define MCF_INTC_IPRH_INT56 (0x1000000)
#define MCF_INTC_IPRH_INT57 (0x2000000)
#define MCF_INTC_IPRH_INT58 (0x4000000)
#define MCF_INTC_IPRH_INT59 (0x8000000)
#define MCF_INTC_IPRH_INT60 (0x10000000)
#define MCF_INTC_IPRH_INT61 (0x20000000)
#define MCF_INTC_IPRH_INT62 (0x40000000)
#define MCF_INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IPRL */
#define MCF_INTC_IPRL_INT1 (0x2)
#define MCF_INTC_IPRL_INT2 (0x4)
#define MCF_INTC_IPRL_INT3 (0x8)
#define MCF_INTC_IPRL_INT4 (0x10)
#define MCF_INTC_IPRL_INT5 (0x20)
#define MCF_INTC_IPRL_INT6 (0x40)
#define MCF_INTC_IPRL_INT7 (0x80)
#define MCF_INTC_IPRL_INT8 (0x100)
#define MCF_INTC_IPRL_INT9 (0x200)
#define MCF_INTC_IPRL_INT10 (0x400)
#define MCF_INTC_IPRL_INT11 (0x800)
#define MCF_INTC_IPRL_INT12 (0x1000)
#define MCF_INTC_IPRL_INT13 (0x2000)
#define MCF_INTC_IPRL_INT14 (0x4000)
#define MCF_INTC_IPRL_INT15 (0x8000)
#define MCF_INTC_IPRL_INT16 (0x10000)
#define MCF_INTC_IPRL_INT17 (0x20000)
#define MCF_INTC_IPRL_INT18 (0x40000)
#define MCF_INTC_IPRL_INT19 (0x80000)
#define MCF_INTC_IPRL_INT20 (0x100000)
#define MCF_INTC_IPRL_INT21 (0x200000)
#define MCF_INTC_IPRL_INT22 (0x400000)
#define MCF_INTC_IPRL_INT23 (0x800000)
#define MCF_INTC_IPRL_INT24 (0x1000000)
#define MCF_INTC_IPRL_INT25 (0x2000000)
#define MCF_INTC_IPRL_INT26 (0x4000000)
#define MCF_INTC_IPRL_INT27 (0x8000000)
#define MCF_INTC_IPRL_INT28 (0x10000000)
#define MCF_INTC_IPRL_INT29 (0x20000000)
#define MCF_INTC_IPRL_INT30 (0x40000000)
#define MCF_INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRH */
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRL */
#define MCF_INTC_IMRL_MASKALL (0x1)
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCH */
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCL */
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IRLR */
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_INTC_IACKLPR */
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
/* Bit definitions and macros for MCF_INTC_ICR */
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
/* Bit definitions and macros for MCF_INTC_SWIACK */
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_INTC_LIACK */
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
#endif /* __MCF5475_INTC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_MMU_H__
#define __MCF5475_MMU_H__
/*********************************************************************
*
* Memory Management Unit (MMU)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_MMU_MMUCR (*(vuint32*)(&__MMUBAR[0]))
#define MCF_MMU_MMUOR (*(vuint32*)(&__MMUBAR[0x4]))
#define MCF_MMU_MMUSR (*(vuint32*)(&__MMUBAR[0x8]))
#define MCF_MMU_MMUAR (*(vuint32*)(&__MMUBAR[0x10]))
#define MCF_MMU_MMUTR (*(vuint32*)(&__MMUBAR[0x14]))
#define MCF_MMU_MMUDR (*(vuint32*)(&__MMUBAR[0x18]))
/* Bit definitions and macros for MCF_MMU_MMUCR */
#define MCF_MMU_MMUCR_EN (0x1)
#define MCF_MMU_MMUCR_ASM (0x2)
/* Bit definitions and macros for MCF_MMU_MMUOR */
#define MCF_MMU_MMUOR_UAA (0x1)
#define MCF_MMU_MMUOR_ACC (0x2)
#define MCF_MMU_MMUOR_RW (0x4)
#define MCF_MMU_MMUOR_ADR (0x8)
#define MCF_MMU_MMUOR_ITLB (0x10)
#define MCF_MMU_MMUOR_CAS (0x20)
#define MCF_MMU_MMUOR_CNL (0x40)
#define MCF_MMU_MMUOR_CA (0x80)
#define MCF_MMU_MMUOR_STLB (0x100)
#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_MMU_MMUSR */
#define MCF_MMU_MMUSR_HIT (0x2)
#define MCF_MMU_MMUSR_WF (0x8)
#define MCF_MMU_MMUSR_RF (0x10)
#define MCF_MMU_MMUSR_SPF (0x20)
/* Bit definitions and macros for MCF_MMU_MMUAR */
#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_MMU_MMUTR */
#define MCF_MMU_MMUTR_V (0x1)
#define MCF_MMU_MMUTR_SG (0x2)
#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2)
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
/* Bit definitions and macros for MCF_MMU_MMUDR */
#define MCF_MMU_MMUDR_LK (0x2)
#define MCF_MMU_MMUDR_X (0x4)
#define MCF_MMU_MMUDR_W (0x8)
#define MCF_MMU_MMUDR_R (0x10)
#define MCF_MMU_MMUDR_SP (0x20)
#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6)
#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8)
#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA)
#endif /* __MCF5475_MMU_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PAD_H__
#define __MCF5475_PAD_H__
/*********************************************************************
*
* Common GPIO
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PAD_PAR_FBCTL (*(vuint16*)(&__MBAR[0xA40]))
#define MCF_PAD_PAR_FBCS (*(vuint8 *)(&__MBAR[0xA42]))
#define MCF_PAD_PAR_DMA (*(vuint8 *)(&__MBAR[0xA43]))
#define MCF_PAD_PAR_FECI2CIRQ (*(vuint16*)(&__MBAR[0xA44]))
#define MCF_PAD_PAR_PCIBG (*(vuint16*)(&__MBAR[0xA48]))
#define MCF_PAD_PAR_PCIBR (*(vuint16*)(&__MBAR[0xA4A]))
#define MCF_PAD_PAR_PSC3 (*(vuint8 *)(&__MBAR[0xA4C]))
#define MCF_PAD_PAR_PSC2 (*(vuint8 *)(&__MBAR[0xA4D]))
#define MCF_PAD_PAR_PSC1 (*(vuint8 *)(&__MBAR[0xA4E]))
#define MCF_PAD_PAR_PSC0 (*(vuint8 *)(&__MBAR[0xA4F]))
#define MCF_PAD_PAR_DSPI (*(vuint16*)(&__MBAR[0xA50]))
#define MCF_PAD_PAR_TIMER (*(vuint8 *)(&__MBAR[0xA52]))
/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3)
#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4)
#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30)
#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40)
#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100)
#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400)
#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000)
#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000)
/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2)
#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4)
#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8)
#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10)
#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20)
/* Bit definitions and macros for MCF_PAD_PAR_DMA */
#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3)
#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC)
#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20)
#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30)
#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80)
#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000)
/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300)
/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300)
/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4)
#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8)
#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30)
#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4)
#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8)
#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30)
#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4)
#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8)
#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30)
#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4)
#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8)
#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30)
#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3)
#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8)
#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC)
#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10)
#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20)
#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30)
#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40)
#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80)
#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0)
#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200)
#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300)
#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA)
#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800)
#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00)
#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000)
/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1)
#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1)
#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4)
#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6)
#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8)
#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20)
#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30)
#endif /* __MCF5475_PAD_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PCI_H__
#define __MCF5475_PCI_H__
/*********************************************************************
*
* PCI Bus Controller (PCI)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PCI_PCIIDR (*(vuint32*)(&__MBAR[0xB00]))
#define MCF_PCI_PCISCR (*(vuint32*)(&__MBAR[0xB04]))
#define MCF_PCI_PCICCRIR (*(vuint32*)(&__MBAR[0xB08]))
#define MCF_PCI_PCICR1 (*(vuint32*)(&__MBAR[0xB0C]))
#define MCF_PCI_PCIBAR0 (*(vuint32*)(&__MBAR[0xB10]))
#define MCF_PCI_PCIBAR1 (*(vuint32*)(&__MBAR[0xB14]))
#define MCF_PCI_PCICCPR (*(vuint32*)(&__MBAR[0xB28]))
#define MCF_PCI_PCISID (*(vuint32*)(&__MBAR[0xB2C]))
#define MCF_PCI_PCICR2 (*(vuint32*)(&__MBAR[0xB3C]))
#define MCF_PCI_PCIGSCR (*(vuint32*)(&__MBAR[0xB60]))
#define MCF_PCI_PCITBATR0 (*(vuint32*)(&__MBAR[0xB64]))
#define MCF_PCI_PCITBATR1 (*(vuint32*)(&__MBAR[0xB68]))
#define MCF_PCI_PCITCR (*(vuint32*)(&__MBAR[0xB6C]))
#define MCF_PCI_PCIIW0BTAR (*(vuint32*)(&__MBAR[0xB70]))
#define MCF_PCI_PCIIW1BTAR (*(vuint32*)(&__MBAR[0xB74]))
#define MCF_PCI_PCIIW2BTAR (*(vuint32*)(&__MBAR[0xB78]))
#define MCF_PCI_PCIIWCR (*(vuint32*)(&__MBAR[0xB80]))
#define MCF_PCI_PCIICR (*(vuint32*)(&__MBAR[0xB84]))
#define MCF_PCI_PCIISR (*(vuint32*)(&__MBAR[0xB88]))
#define MCF_PCI_PCICAR (*(vuint32*)(&__MBAR[0xBF8]))
#define MCF_PCI_PCITPSR (*(vuint32*)(&__MBAR[0x8400]))
#define MCF_PCI_PCITSAR (*(vuint32*)(&__MBAR[0x8404]))
#define MCF_PCI_PCITTCR (*(vuint32*)(&__MBAR[0x8408]))
#define MCF_PCI_PCITER (*(vuint32*)(&__MBAR[0x840C]))
#define MCF_PCI_PCITNAR (*(vuint32*)(&__MBAR[0x8410]))
#define MCF_PCI_PCITLWR (*(vuint32*)(&__MBAR[0x8414]))
#define MCF_PCI_PCITDCR (*(vuint32*)(&__MBAR[0x8418]))
#define MCF_PCI_PCITSR (*(vuint32*)(&__MBAR[0x841C]))
#define MCF_PCI_PCITFDR (*(vuint32*)(&__MBAR[0x8440]))
#define MCF_PCI_PCITFSR (*(vuint32*)(&__MBAR[0x8444]))
#define MCF_PCI_PCITFCR (*(vuint32*)(&__MBAR[0x8448]))
#define MCF_PCI_PCITFAR (*(vuint32*)(&__MBAR[0x844C]))
#define MCF_PCI_PCITFRPR (*(vuint32*)(&__MBAR[0x8450]))
#define MCF_PCI_PCITFWPR (*(vuint32*)(&__MBAR[0x8454]))
#define MCF_PCI_PCIRPSR (*(vuint32*)(&__MBAR[0x8480]))
#define MCF_PCI_PCIRSAR (*(vuint32*)(&__MBAR[0x8484]))
#define MCF_PCI_PCIRTCR (*(vuint32*)(&__MBAR[0x8488]))
#define MCF_PCI_PCIRER (*(vuint32*)(&__MBAR[0x848C]))
#define MCF_PCI_PCIRNAR (*(vuint32*)(&__MBAR[0x8490]))
#define MCF_PCI_PCIRDCR (*(vuint32*)(&__MBAR[0x8498]))
#define MCF_PCI_PCIRSR (*(vuint32*)(&__MBAR[0x849C]))
#define MCF_PCI_PCIRFDR (*(vuint32*)(&__MBAR[0x84C0]))
#define MCF_PCI_PCIRFSR (*(vuint32*)(&__MBAR[0x84C4]))
#define MCF_PCI_PCIRFCR (*(vuint32*)(&__MBAR[0x84C8]))
#define MCF_PCI_PCIRFAR (*(vuint32*)(&__MBAR[0x84CC]))
#define MCF_PCI_PCIRFRPR (*(vuint32*)(&__MBAR[0x84D0]))
#define MCF_PCI_PCIRFWPR (*(vuint32*)(&__MBAR[0x84D4]))
/* Bit definitions and macros for MCF_PCI_PCIIDR */
#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0)
#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCISCR */
#define MCF_PCI_PCISCR_IO (0x1)
#define MCF_PCI_PCISCR_M (0x2)
#define MCF_PCI_PCISCR_B (0x4)
#define MCF_PCI_PCISCR_SP (0x8)
#define MCF_PCI_PCISCR_MW (0x10)
#define MCF_PCI_PCISCR_V (0x20)
#define MCF_PCI_PCISCR_PER (0x40)
#define MCF_PCI_PCISCR_ST (0x80)
#define MCF_PCI_PCISCR_S (0x100)
#define MCF_PCI_PCISCR_F (0x200)
#define MCF_PCI_PCISCR_C (0x100000)
#define MCF_PCI_PCISCR_66M (0x200000)
#define MCF_PCI_PCISCR_R (0x400000)
#define MCF_PCI_PCISCR_FC (0x800000)
#define MCF_PCI_PCISCR_DP (0x1000000)
#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19)
#define MCF_PCI_PCISCR_TS (0x8000000)
#define MCF_PCI_PCISCR_TR (0x10000000)
#define MCF_PCI_PCISCR_MA (0x20000000)
#define MCF_PCI_PCISCR_SE (0x40000000)
#define MCF_PCI_PCISCR_PE (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCICCRIR */
#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8)
/* Bit definitions and macros for MCF_PCI_PCICR1 */
#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
#define MCF_PCI_PCIBAR0_IOM (0x1)
#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1)
#define MCF_PCI_PCIBAR0_PREF (0x8)
#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12)
/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
#define MCF_PCI_PCIBAR1_IOM (0x1)
#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1)
#define MCF_PCI_PCIBAR1_PREF (0x8)
#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_PCI_PCICCPR */
#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCISID */
#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCICR2 */
#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIGSCR */
#define MCF_PCI_PCIGSCR_PR (0x1)
#define MCF_PCI_PCIGSCR_SEE (0x1000)
#define MCF_PCI_PCIGSCR_PEE (0x2000)
#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10)
#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18)
#define MCF_PCI_PCIGSCR_SE (0x10000000)
#define MCF_PCI_PCIGSCR_PE (0x20000000)
/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
#define MCF_PCI_PCITBATR0_EN (0x1)
#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12)
/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
#define MCF_PCI_PCITBATR1_EN (0x1)
#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_PCI_PCITCR */
#define MCF_PCI_PCITCR_P (0x10000)
#define MCF_PCI_PCITCR_LD (0x1000000)
/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8)
#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIIWCR */
#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100)
#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9)
#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800)
#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000)
#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11)
#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000)
#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19)
#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300)
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500)
#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000)
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000)
#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000)
#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000)
/* Bit definitions and macros for MCF_PCI_PCIICR */
#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0)
#define MCF_PCI_PCIICR_TAE (0x1000000)
#define MCF_PCI_PCIICR_IAE (0x2000000)
#define MCF_PCI_PCIICR_REE (0x4000000)
/* Bit definitions and macros for MCF_PCI_PCIISR */
#define MCF_PCI_PCIISR_TA (0x1000000)
#define MCF_PCI_PCIISR_IA (0x2000000)
#define MCF_PCI_PCIISR_RE (0x4000000)
/* Bit definitions and macros for MCF_PCI_PCICAR */
#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2)
#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8)
#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB)
#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCICAR_E (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCITPSR */
#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCITSAR */
#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITTCR */
#define MCF_PCI_PCITTCR_DI (0x1)
#define MCF_PCI_PCITTCR_W (0x10)
#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCITER */
#define MCF_PCI_PCITER_NE (0x10000)
#define MCF_PCI_PCITER_IAE (0x20000)
#define MCF_PCI_PCITER_TAE (0x40000)
#define MCF_PCI_PCITER_RE (0x80000)
#define MCF_PCI_PCITER_SE (0x100000)
#define MCF_PCI_PCITER_FEE (0x200000)
#define MCF_PCI_PCITER_ME (0x1000000)
#define MCF_PCI_PCITER_BE (0x8000000)
#define MCF_PCI_PCITER_CM (0x10000000)
#define MCF_PCI_PCITER_RF (0x40000000)
#define MCF_PCI_PCITER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCITNAR */
#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITLWR */
#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITDCR */
#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCITSR */
#define MCF_PCI_PCITSR_IA (0x10000)
#define MCF_PCI_PCITSR_TA (0x20000)
#define MCF_PCI_PCITSR_RE (0x40000)
#define MCF_PCI_PCITSR_SE (0x80000)
#define MCF_PCI_PCITSR_FE (0x100000)
#define MCF_PCI_PCITSR_BE1 (0x200000)
#define MCF_PCI_PCITSR_BE2 (0x400000)
#define MCF_PCI_PCITSR_BE3 (0x800000)
#define MCF_PCI_PCITSR_NT (0x1000000)
/* Bit definitions and macros for MCF_PCI_PCITFDR */
#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFSR */
#define MCF_PCI_PCITFSR_EMPTY (0x10000)
#define MCF_PCI_PCITFSR_ALARM (0x20000)
#define MCF_PCI_PCITFSR_FULL (0x40000)
#define MCF_PCI_PCITFSR_FR (0x80000)
#define MCF_PCI_PCITFSR_OF (0x100000)
#define MCF_PCI_PCITFSR_UF (0x200000)
#define MCF_PCI_PCITFSR_RXW (0x400000)
#define MCF_PCI_PCITFSR_FAE (0x800000)
#define MCF_PCI_PCITFSR_TXW (0x40000000)
#define MCF_PCI_PCITFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCITFCR */
#define MCF_PCI_PCITFCR_TXW_MASK (0x40000)
#define MCF_PCI_PCITFCR_OF_MASK (0x80000)
#define MCF_PCI_PCITFCR_UF_MASK (0x100000)
#define MCF_PCI_PCITFCR_RXW_MASK (0x200000)
#define MCF_PCI_PCITFCR_FAE_MASK (0x400000)
#define MCF_PCI_PCITFCR_IP_MASK (0x800000)
#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PCI_PCITFCR_WFR (0x20000000)
/* Bit definitions and macros for MCF_PCI_PCITFAR */
#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFRPR */
#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCITFWPR */
#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRPSR */
#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCIRSAR */
#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRTCR */
#define MCF_PCI_PCIRTCR_DI (0x1)
#define MCF_PCI_PCIRTCR_W (0x10)
#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
#define MCF_PCI_PCIRTCR_FB (0x1000)
#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_PCI_PCIRER */
#define MCF_PCI_PCIRER_NE (0x10000)
#define MCF_PCI_PCIRER_IAE (0x20000)
#define MCF_PCI_PCIRER_TAE (0x40000)
#define MCF_PCI_PCIRER_RE (0x80000)
#define MCF_PCI_PCIRER_SE (0x100000)
#define MCF_PCI_PCIRER_FEE (0x200000)
#define MCF_PCI_PCIRER_ME (0x1000000)
#define MCF_PCI_PCIRER_BE (0x8000000)
#define MCF_PCI_PCIRER_CM (0x10000000)
#define MCF_PCI_PCIRER_FE (0x20000000)
#define MCF_PCI_PCIRER_RF (0x40000000)
#define MCF_PCI_PCIRER_RC (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCIRNAR */
#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRDCR */
#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PCI_PCIRSR */
#define MCF_PCI_PCIRSR_IA (0x10000)
#define MCF_PCI_PCIRSR_TA (0x20000)
#define MCF_PCI_PCIRSR_RE (0x40000)
#define MCF_PCI_PCIRSR_SE (0x80000)
#define MCF_PCI_PCIRSR_FE (0x100000)
#define MCF_PCI_PCIRSR_BE1 (0x200000)
#define MCF_PCI_PCIRSR_BE2 (0x400000)
#define MCF_PCI_PCIRSR_BE3 (0x800000)
#define MCF_PCI_PCIRSR_NT (0x1000000)
/* Bit definitions and macros for MCF_PCI_PCIRFDR */
#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFSR */
#define MCF_PCI_PCIRFSR_EMPTY (0x10000)
#define MCF_PCI_PCIRFSR_ALARM (0x20000)
#define MCF_PCI_PCIRFSR_FULL (0x40000)
#define MCF_PCI_PCIRFSR_FR (0x80000)
#define MCF_PCI_PCIRFSR_OF (0x100000)
#define MCF_PCI_PCIRFSR_UF (0x200000)
#define MCF_PCI_PCIRFSR_RXW (0x400000)
#define MCF_PCI_PCIRFSR_FAE (0x800000)
#define MCF_PCI_PCIRFSR_TXW (0x40000000)
#define MCF_PCI_PCIRFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_PCI_PCIRFCR */
#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000)
#define MCF_PCI_PCIRFCR_OF_MASK (0x80000)
#define MCF_PCI_PCIRFCR_UF_MASK (0x100000)
#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000)
#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000)
#define MCF_PCI_PCIRFCR_IP_MASK (0x800000)
#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PCI_PCIRFCR_WFR (0x20000000)
/* Bit definitions and macros for MCF_PCI_PCIRFAR */
#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
#endif /* __MCF5475_PCI_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PCIARB_H__
#define __MCF5475_PCIARB_H__
/*********************************************************************
*
* PCI Bus Arbiter Module (PCIARB)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PCIARB_PACR (*(vuint32*)(&__MBAR[0xC00]))
#define MCF_PCIARB_PASR (*(vuint32*)(&__MBAR[0xC04]))
/* Bit definitions and macros for MCF_PCIARB_PACR */
#define MCF_PCIARB_PACR_INTMPRI (0x1)
#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1)
#define MCF_PCIARB_PACR_INTMINTEN (0x10000)
#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11)
#define MCF_PCIARB_PACR_DS (0x80000000)
/* Bit definitions and macros for MCF_PCIARB_PASR */
#define MCF_PCIARB_PASR_ITLMBK (0x10000)
#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11)
#endif /* __MCF5475_PCIARB_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PSC_H__
#define __MCF5475_PSC_H__
/*********************************************************************
*
* Programmable Serial Controller (PSC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PSC0_PSCMR2 (*(vuint8 *)(&__MBAR[0x8600]))
#define MCF_PSC0_PSCMR1 (*(vuint8 *)(&__MBAR[0x8600]))
#define MCF_PSC0_PSCCSR (*(vuint8 *)(&__MBAR[0x8604]))
#define MCF_PSC0_PSCSR (*(vuint16*)(&__MBAR[0x8604]))
#define MCF_PSC0_PSCCR (*(vuint8 *)(&__MBAR[0x8608]))
#define MCF_PSC0_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCIPCR (*(vuint8 *)(&__MBAR[0x8610]))
#define MCF_PSC0_PSCACR (*(vuint8 *)(&__MBAR[0x8610]))
#define MCF_PSC0_PSCIMR (*(vuint16*)(&__MBAR[0x8614]))
#define MCF_PSC0_PSCISR (*(vuint16*)(&__MBAR[0x8614]))
#define MCF_PSC0_PSCCTUR (*(vuint8 *)(&__MBAR[0x8618]))
#define MCF_PSC0_PSCCTLR (*(vuint8 *)(&__MBAR[0x861C]))
#define MCF_PSC0_PSCIP (*(vuint8 *)(&__MBAR[0x8634]))
#define MCF_PSC0_PSCOPSET (*(vuint8 *)(&__MBAR[0x8638]))
#define MCF_PSC0_PSCOPRESET (*(vuint8 *)(&__MBAR[0x863C]))
#define MCF_PSC0_PSCSICR (*(vuint8 *)(&__MBAR[0x8640]))
#define MCF_PSC0_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8644]))
#define MCF_PSC0_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8648]))
#define MCF_PSC0_PSCIRSDR (*(vuint8 *)(&__MBAR[0x864C]))
#define MCF_PSC0_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8650]))
#define MCF_PSC0_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8654]))
#define MCF_PSC0_PSCRFCNT (*(vuint16*)(&__MBAR[0x8658]))
#define MCF_PSC0_PSCTFCNT (*(vuint16*)(&__MBAR[0x865C]))
#define MCF_PSC0_PSCRFDR (*(vuint32*)(&__MBAR[0x8660]))
#define MCF_PSC0_PSCRFSR (*(vuint16*)(&__MBAR[0x8664]))
#define MCF_PSC0_PSCRFCR (*(vuint32*)(&__MBAR[0x8668]))
#define MCF_PSC0_PSCRFAR (*(vuint16*)(&__MBAR[0x866E]))
#define MCF_PSC0_PSCRFRP (*(vuint16*)(&__MBAR[0x8672]))
#define MCF_PSC0_PSCRFWP (*(vuint16*)(&__MBAR[0x8676]))
#define MCF_PSC0_PSCRLRFP (*(vuint16*)(&__MBAR[0x867A]))
#define MCF_PSC0_PSCRLWFP (*(vuint16*)(&__MBAR[0x867E]))
#define MCF_PSC0_PSCTFDR (*(vuint32*)(&__MBAR[0x8680]))
#define MCF_PSC0_PSCTFSR (*(vuint16*)(&__MBAR[0x8684]))
#define MCF_PSC0_PSCTFCR (*(vuint32*)(&__MBAR[0x8688]))
#define MCF_PSC0_PSCTFAR (*(vuint16*)(&__MBAR[0x868E]))
#define MCF_PSC0_PSCTFRP (*(vuint16*)(&__MBAR[0x8692]))
#define MCF_PSC0_PSCTFWP (*(vuint16*)(&__MBAR[0x8696]))
#define MCF_PSC0_PSCTLRFP (*(vuint16*)(&__MBAR[0x869A]))
#define MCF_PSC0_PSCTLWFP (*(vuint16*)(&__MBAR[0x869E]))
#define MCF_PSC1_PSCMR2 (*(vuint8 *)(&__MBAR[0x8700]))
#define MCF_PSC1_PSCMR1 (*(vuint8 *)(&__MBAR[0x8700]))
#define MCF_PSC1_PSCCSR (*(vuint8 *)(&__MBAR[0x8704]))
#define MCF_PSC1_PSCSR (*(vuint16*)(&__MBAR[0x8704]))
#define MCF_PSC1_PSCCR (*(vuint8 *)(&__MBAR[0x8708]))
#define MCF_PSC1_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCIPCR (*(vuint8 *)(&__MBAR[0x8710]))
#define MCF_PSC1_PSCACR (*(vuint8 *)(&__MBAR[0x8710]))
#define MCF_PSC1_PSCIMR (*(vuint16*)(&__MBAR[0x8714]))
#define MCF_PSC1_PSCISR (*(vuint16*)(&__MBAR[0x8714]))
#define MCF_PSC1_PSCCTUR (*(vuint8 *)(&__MBAR[0x8718]))
#define MCF_PSC1_PSCCTLR (*(vuint8 *)(&__MBAR[0x871C]))
#define MCF_PSC1_PSCIP (*(vuint8 *)(&__MBAR[0x8734]))
#define MCF_PSC1_PSCOPSET (*(vuint8 *)(&__MBAR[0x8738]))
#define MCF_PSC1_PSCOPRESET (*(vuint8 *)(&__MBAR[0x873C]))
#define MCF_PSC1_PSCSICR (*(vuint8 *)(&__MBAR[0x8740]))
#define MCF_PSC1_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8744]))
#define MCF_PSC1_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8748]))
#define MCF_PSC1_PSCIRSDR (*(vuint8 *)(&__MBAR[0x874C]))
#define MCF_PSC1_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8750]))
#define MCF_PSC1_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8754]))
#define MCF_PSC1_PSCRFCNT (*(vuint16*)(&__MBAR[0x8758]))
#define MCF_PSC1_PSCTFCNT (*(vuint16*)(&__MBAR[0x875C]))
#define MCF_PSC1_PSCRFDR (*(vuint32*)(&__MBAR[0x8760]))
#define MCF_PSC1_PSCRFSR (*(vuint16*)(&__MBAR[0x8764]))
#define MCF_PSC1_PSCRFCR (*(vuint32*)(&__MBAR[0x8768]))
#define MCF_PSC1_PSCRFAR (*(vuint16*)(&__MBAR[0x876E]))
#define MCF_PSC1_PSCRFRP (*(vuint16*)(&__MBAR[0x8772]))
#define MCF_PSC1_PSCRFWP (*(vuint16*)(&__MBAR[0x8776]))
#define MCF_PSC1_PSCRLRFP (*(vuint16*)(&__MBAR[0x877A]))
#define MCF_PSC1_PSCRLWFP (*(vuint16*)(&__MBAR[0x877E]))
#define MCF_PSC1_PSCTFDR (*(vuint32*)(&__MBAR[0x8780]))
#define MCF_PSC1_PSCTFSR (*(vuint16*)(&__MBAR[0x8784]))
#define MCF_PSC1_PSCTFCR (*(vuint32*)(&__MBAR[0x8788]))
#define MCF_PSC1_PSCTFAR (*(vuint16*)(&__MBAR[0x878E]))
#define MCF_PSC1_PSCTFRP (*(vuint16*)(&__MBAR[0x8792]))
#define MCF_PSC1_PSCTFWP (*(vuint16*)(&__MBAR[0x8796]))
#define MCF_PSC1_PSCTLRFP (*(vuint16*)(&__MBAR[0x879A]))
#define MCF_PSC1_PSCTLWFP (*(vuint16*)(&__MBAR[0x879E]))
#define MCF_PSC2_PSCMR2 (*(vuint8 *)(&__MBAR[0x8800]))
#define MCF_PSC2_PSCMR1 (*(vuint8 *)(&__MBAR[0x8800]))
#define MCF_PSC2_PSCCSR (*(vuint8 *)(&__MBAR[0x8804]))
#define MCF_PSC2_PSCSR (*(vuint16*)(&__MBAR[0x8804]))
#define MCF_PSC2_PSCCR (*(vuint8 *)(&__MBAR[0x8808]))
#define MCF_PSC2_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCIPCR (*(vuint8 *)(&__MBAR[0x8810]))
#define MCF_PSC2_PSCACR (*(vuint8 *)(&__MBAR[0x8810]))
#define MCF_PSC2_PSCIMR (*(vuint16*)(&__MBAR[0x8814]))
#define MCF_PSC2_PSCISR (*(vuint16*)(&__MBAR[0x8814]))
#define MCF_PSC2_PSCCTUR (*(vuint8 *)(&__MBAR[0x8818]))
#define MCF_PSC2_PSCCTLR (*(vuint8 *)(&__MBAR[0x881C]))
#define MCF_PSC2_PSCIP (*(vuint8 *)(&__MBAR[0x8834]))
#define MCF_PSC2_PSCOPSET (*(vuint8 *)(&__MBAR[0x8838]))
#define MCF_PSC2_PSCOPRESET (*(vuint8 *)(&__MBAR[0x883C]))
#define MCF_PSC2_PSCSICR (*(vuint8 *)(&__MBAR[0x8840]))
#define MCF_PSC2_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8844]))
#define MCF_PSC2_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8848]))
#define MCF_PSC2_PSCIRSDR (*(vuint8 *)(&__MBAR[0x884C]))
#define MCF_PSC2_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8850]))
#define MCF_PSC2_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8854]))
#define MCF_PSC2_PSCRFCNT (*(vuint16*)(&__MBAR[0x8858]))
#define MCF_PSC2_PSCTFCNT (*(vuint16*)(&__MBAR[0x885C]))
#define MCF_PSC2_PSCRFDR (*(vuint32*)(&__MBAR[0x8860]))
#define MCF_PSC2_PSCRFSR (*(vuint16*)(&__MBAR[0x8864]))
#define MCF_PSC2_PSCRFCR (*(vuint32*)(&__MBAR[0x8868]))
#define MCF_PSC2_PSCRFAR (*(vuint16*)(&__MBAR[0x886E]))
#define MCF_PSC2_PSCRFRP (*(vuint16*)(&__MBAR[0x8872]))
#define MCF_PSC2_PSCRFWP (*(vuint16*)(&__MBAR[0x8876]))
#define MCF_PSC2_PSCRLRFP (*(vuint16*)(&__MBAR[0x887A]))
#define MCF_PSC2_PSCRLWFP (*(vuint16*)(&__MBAR[0x887E]))
#define MCF_PSC2_PSCTFDR (*(vuint32*)(&__MBAR[0x8880]))
#define MCF_PSC2_PSCTFSR (*(vuint16*)(&__MBAR[0x8884]))
#define MCF_PSC2_PSCTFCR (*(vuint32*)(&__MBAR[0x8888]))
#define MCF_PSC2_PSCTFAR (*(vuint16*)(&__MBAR[0x888E]))
#define MCF_PSC2_PSCTFRP (*(vuint16*)(&__MBAR[0x8892]))
#define MCF_PSC2_PSCTFWP (*(vuint16*)(&__MBAR[0x8896]))
#define MCF_PSC2_PSCTLRFP (*(vuint16*)(&__MBAR[0x889A]))
#define MCF_PSC2_PSCTLWFP (*(vuint16*)(&__MBAR[0x889E]))
#define MCF_PSC3_PSCMR2 (*(vuint8 *)(&__MBAR[0x8900]))
#define MCF_PSC3_PSCMR1 (*(vuint8 *)(&__MBAR[0x8900]))
#define MCF_PSC3_PSCCSR (*(vuint8 *)(&__MBAR[0x8904]))
#define MCF_PSC3_PSCSR (*(vuint16*)(&__MBAR[0x8904]))
#define MCF_PSC3_PSCCR (*(vuint8 *)(&__MBAR[0x8908]))
#define MCF_PSC3_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCIPCR (*(vuint8 *)(&__MBAR[0x8910]))
#define MCF_PSC3_PSCACR (*(vuint8 *)(&__MBAR[0x8910]))
#define MCF_PSC3_PSCIMR (*(vuint16*)(&__MBAR[0x8914]))
#define MCF_PSC3_PSCISR (*(vuint16*)(&__MBAR[0x8914]))
#define MCF_PSC3_PSCCTUR (*(vuint8 *)(&__MBAR[0x8918]))
#define MCF_PSC3_PSCCTLR (*(vuint8 *)(&__MBAR[0x891C]))
#define MCF_PSC3_PSCIP (*(vuint8 *)(&__MBAR[0x8934]))
#define MCF_PSC3_PSCOPSET (*(vuint8 *)(&__MBAR[0x8938]))
#define MCF_PSC3_PSCOPRESET (*(vuint8 *)(&__MBAR[0x893C]))
#define MCF_PSC3_PSCSICR (*(vuint8 *)(&__MBAR[0x8940]))
#define MCF_PSC3_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8944]))
#define MCF_PSC3_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8948]))
#define MCF_PSC3_PSCIRSDR (*(vuint8 *)(&__MBAR[0x894C]))
#define MCF_PSC3_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8950]))
#define MCF_PSC3_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8954]))
#define MCF_PSC3_PSCRFCNT (*(vuint16*)(&__MBAR[0x8958]))
#define MCF_PSC3_PSCTFCNT (*(vuint16*)(&__MBAR[0x895C]))
#define MCF_PSC3_PSCRFDR (*(vuint32*)(&__MBAR[0x8960]))
#define MCF_PSC3_PSCRFSR (*(vuint16*)(&__MBAR[0x8964]))
#define MCF_PSC3_PSCRFCR (*(vuint32*)(&__MBAR[0x8968]))
#define MCF_PSC3_PSCRFAR (*(vuint16*)(&__MBAR[0x896E]))
#define MCF_PSC3_PSCRFRP (*(vuint16*)(&__MBAR[0x8972]))
#define MCF_PSC3_PSCRFWP (*(vuint16*)(&__MBAR[0x8976]))
#define MCF_PSC3_PSCRLRFP (*(vuint16*)(&__MBAR[0x897A]))
#define MCF_PSC3_PSCRLWFP (*(vuint16*)(&__MBAR[0x897E]))
#define MCF_PSC3_PSCTFDR (*(vuint32*)(&__MBAR[0x8980]))
#define MCF_PSC3_PSCTFSR (*(vuint16*)(&__MBAR[0x8984]))
#define MCF_PSC3_PSCTFCR (*(vuint32*)(&__MBAR[0x8988]))
#define MCF_PSC3_PSCTFAR (*(vuint16*)(&__MBAR[0x898E]))
#define MCF_PSC3_PSCTFRP (*(vuint16*)(&__MBAR[0x8992]))
#define MCF_PSC3_PSCTFWP (*(vuint16*)(&__MBAR[0x8996]))
#define MCF_PSC3_PSCTLRFP (*(vuint16*)(&__MBAR[0x899A]))
#define MCF_PSC3_PSCTLWFP (*(vuint16*)(&__MBAR[0x899E]))
#define MCF_PSC_PSCMR(x) (*(vuint8 *)(&__MBAR[0x8600 + ((x)*0x100)]))
#define MCF_PSC_PSCCSR(x) (*(vuint8 *)(&__MBAR[0x8604 + ((x)*0x100)]))
#define MCF_PSC_PSCSR(x) (*(vuint16*)(&__MBAR[0x8604 + ((x)*0x100)]))
#define MCF_PSC_PSCCR(x) (*(vuint8 *)(&__MBAR[0x8608 + ((x)*0x100)]))
#define MCF_PSC_PSCRB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCRB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCRB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCIPCR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)]))
#define MCF_PSC_PSCACR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)]))
#define MCF_PSC_PSCIMR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)]))
#define MCF_PSC_PSCISR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)]))
#define MCF_PSC_PSCCTUR(x) (*(vuint8 *)(&__MBAR[0x8618 + ((x)*0x100)]))
#define MCF_PSC_PSCCTLR(x) (*(vuint8 *)(&__MBAR[0x861C + ((x)*0x100)]))
#define MCF_PSC_PSCIP(x) (*(vuint8 *)(&__MBAR[0x8634 + ((x)*0x100)]))
#define MCF_PSC_PSCOPSET(x) (*(vuint8 *)(&__MBAR[0x8638 + ((x)*0x100)]))
#define MCF_PSC_PSCOPRESET(x) (*(vuint8 *)(&__MBAR[0x863C + ((x)*0x100)]))
#define MCF_PSC_PSCSICR(x) (*(vuint8 *)(&__MBAR[0x8640 + ((x)*0x100)]))
#define MCF_PSC_PSCIRCR1(x) (*(vuint8 *)(&__MBAR[0x8644 + ((x)*0x100)]))
#define MCF_PSC_PSCIRCR2(x) (*(vuint8 *)(&__MBAR[0x8648 + ((x)*0x100)]))
#define MCF_PSC_PSCIRSDR(x) (*(vuint8 *)(&__MBAR[0x864C + ((x)*0x100)]))
#define MCF_PSC_PSCIRMDR(x) (*(vuint8 *)(&__MBAR[0x8650 + ((x)*0x100)]))
#define MCF_PSC_PSCIRFDR(x) (*(vuint8 *)(&__MBAR[0x8654 + ((x)*0x100)]))
#define MCF_PSC_PSCRFCNT(x) (*(vuint16*)(&__MBAR[0x8658 + ((x)*0x100)]))
#define MCF_PSC_PSCTFCNT(x) (*(vuint16*)(&__MBAR[0x865C + ((x)*0x100)]))
#define MCF_PSC_PSCRFDR(x) (*(vuint32*)(&__MBAR[0x8660 + ((x)*0x100)]))
#define MCF_PSC_PSCRFSR(x) (*(vuint16*)(&__MBAR[0x8664 + ((x)*0x100)]))
#define MCF_PSC_PSCRFCR(x) (*(vuint32*)(&__MBAR[0x8668 + ((x)*0x100)]))
#define MCF_PSC_PSCRFAR(x) (*(vuint16*)(&__MBAR[0x866E + ((x)*0x100)]))
#define MCF_PSC_PSCRFRP(x) (*(vuint16*)(&__MBAR[0x8672 + ((x)*0x100)]))
#define MCF_PSC_PSCRFWP(x) (*(vuint16*)(&__MBAR[0x8676 + ((x)*0x100)]))
#define MCF_PSC_PSCRLRFP(x) (*(vuint16*)(&__MBAR[0x867A + ((x)*0x100)]))
#define MCF_PSC_PSCRLWFP(x) (*(vuint16*)(&__MBAR[0x867E + ((x)*0x100)]))
#define MCF_PSC_PSCTFDR(x) (*(vuint32*)(&__MBAR[0x8680 + ((x)*0x100)]))
#define MCF_PSC_PSCTFSR(x) (*(vuint16*)(&__MBAR[0x8684 + ((x)*0x100)]))
#define MCF_PSC_PSCTFCR(x) (*(vuint32*)(&__MBAR[0x8688 + ((x)*0x100)]))
#define MCF_PSC_PSCTFAR(x) (*(vuint16*)(&__MBAR[0x868E + ((x)*0x100)]))
#define MCF_PSC_PSCTFRP(x) (*(vuint16*)(&__MBAR[0x8692 + ((x)*0x100)]))
#define MCF_PSC_PSCTFWP(x) (*(vuint16*)(&__MBAR[0x8696 + ((x)*0x100)]))
#define MCF_PSC_PSCTLRFP(x) (*(vuint16*)(&__MBAR[0x869A + ((x)*0x100)]))
#define MCF_PSC_PSCTLWFP(x) (*(vuint16*)(&__MBAR[0x869E + ((x)*0x100)]))
/* Bit definitions and macros for MCF_PSC_PSCMR */
#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0)
#define MCF_PSC_PSCMR_TXCTS (0x10)
#define MCF_PSC_PSCMR_TXRTS (0x20)
#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6)
#define MCF_PSC_PSCMR_CM_NORMAL (0)
#define MCF_PSC_PSCMR_CM_ECHO (0x40)
#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80)
#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0)
#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7)
#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8)
#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF)
#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C)
#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18)
#define MCF_PSC_PSCMR_PM_NONE (0x10)
#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC)
#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8)
#define MCF_PSC_PSCMR_PM_ODD (0x4)
#define MCF_PSC_PSCMR_PM_EVEN (0)
#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0)
#define MCF_PSC_PSCMR_BC_5 (0)
#define MCF_PSC_PSCMR_BC_6 (0x1)
#define MCF_PSC_PSCMR_BC_7 (0x2)
#define MCF_PSC_PSCMR_BC_8 (0x3)
#define MCF_PSC_PSCMR_PT (0x4)
#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3)
#define MCF_PSC_PSCMR_ERR (0x20)
#define MCF_PSC_PSCMR_RXIRQ_FU (0x40)
#define MCF_PSC_PSCMR_RXRTS (0x80)
/* Bit definitions and macros for MCF_PSC_PSCCSR */
#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0)
#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4)
#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D)
#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E)
#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F)
#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0)
#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0)
#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0)
/* Bit definitions and macros for MCF_PSC_PSCSR */
#define MCF_PSC_PSCSR_ERR (0x40)
#define MCF_PSC_PSCSR_CDE_DEOF (0x80)
#define MCF_PSC_PSCSR_RXRDY (0x100)
#define MCF_PSC_PSCSR_FU (0x200)
#define MCF_PSC_PSCSR_TXRDY (0x400)
#define MCF_PSC_PSCSR_TXEMP_URERR (0x800)
#define MCF_PSC_PSCSR_OE (0x1000)
#define MCF_PSC_PSCSR_PE_CRCERR (0x2000)
#define MCF_PSC_PSCSR_FE_PHYERR (0x4000)
#define MCF_PSC_PSCSR_RB_NEOF (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCCR */
#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0)
#define MCF_PSC_PSCCR_RX_ENABLED (0x1)
#define MCF_PSC_PSCCR_RX_DISABLED (0x2)
#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2)
#define MCF_PSC_PSCCR_TX_ENABLED (0x4)
#define MCF_PSC_PSCCR_TX_DISABLED (0x8)
#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4)
#define MCF_PSC_PSCCR_NONE (0)
#define MCF_PSC_PSCCR_RESET_MR (0x10)
#define MCF_PSC_PSCCR_RESET_RX (0x20)
#define MCF_PSC_PSCCR_RESET_TX (0x30)
#define MCF_PSC_PSCCR_RESET_ERROR (0x40)
#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50)
#define MCF_PSC_PSCCR_START_BREAK (0x60)
#define MCF_PSC_PSCCR_STOP_BREAK (0x70)
/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0)
#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8)
#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10)
#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0)
#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8)
#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10)
#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
#define MCF_PSC_PSCRB_AC97_SOF (0x800)
#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC)
/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC)
/* Bit definitions and macros for MCF_PSC_PSCIPCR */
#define MCF_PSC_PSCIPCR_RESERVED (0xC)
#define MCF_PSC_PSCIPCR_CTS (0xD)
#define MCF_PSC_PSCIPCR_D_CTS (0x1C)
#define MCF_PSC_PSCIPCR_SYNC (0x8C)
/* Bit definitions and macros for MCF_PSC_PSCACR */
#define MCF_PSC_PSCACR_IEC0 (0x1)
/* Bit definitions and macros for MCF_PSC_PSCIMR */
#define MCF_PSC_PSCIMR_ERR (0x40)
#define MCF_PSC_PSCIMR_DEOF (0x80)
#define MCF_PSC_PSCIMR_TXRDY (0x100)
#define MCF_PSC_PSCIMR_RXRDY_FU (0x200)
#define MCF_PSC_PSCIMR_DB (0x400)
#define MCF_PSC_PSCIMR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCISR */
#define MCF_PSC_PSCISR_ERR (0x40)
#define MCF_PSC_PSCISR_DEOF (0x80)
#define MCF_PSC_PSCISR_TXRDY (0x100)
#define MCF_PSC_PSCISR_RXRDY_FU (0x200)
#define MCF_PSC_PSCISR_DB (0x400)
#define MCF_PSC_PSCISR_IPC (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCCTUR */
#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCCTLR */
#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCIP */
#define MCF_PSC_PSCIP_CTS (0x1)
#define MCF_PSC_PSCIP_TGL (0x40)
#define MCF_PSC_PSCIP_LPWR_B (0x80)
/* Bit definitions and macros for MCF_PSC_PSCOPSET */
#define MCF_PSC_PSCOPSET_RTS (0x1)
/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
#define MCF_PSC_PSCOPRESET_RTS (0x1)
/* Bit definitions and macros for MCF_PSC_PSCSICR */
#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0)
#define MCF_PSC_PSCSICR_SIM_UART (0)
#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1)
#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2)
#define MCF_PSC_PSCSICR_SIM_AC97 (0x3)
#define MCF_PSC_PSCSICR_SIM_SIR (0x4)
#define MCF_PSC_PSCSICR_SIM_MIR (0x5)
#define MCF_PSC_PSCSICR_SIM_FIR (0x6)
#define MCF_PSC_PSCSICR_SHDIR (0x10)
#define MCF_PSC_PSCSICR_DTS1 (0x20)
#define MCF_PSC_PSCSICR_AWR (0x40)
#define MCF_PSC_PSCSICR_ACRB (0x80)
/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
#define MCF_PSC_PSCIRCR1_SPUL (0x1)
#define MCF_PSC_PSCIRCR1_SIPEN (0x2)
#define MCF_PSC_PSCIRCR1_FD (0x4)
/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
#define MCF_PSC_PSCIRCR2_NXTEOF (0x1)
#define MCF_PSC_PSCIRCR2_ABORT (0x2)
#define MCF_PSC_PSCIRCR2_SIPREQ (0x4)
/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0)
#define MCF_PSC_PSCIRMDR_FREQ (0x80)
/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFDR */
#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFSR */
#define MCF_PSC_PSCRFSR_EMT (0x1)
#define MCF_PSC_PSCRFSR_ALARM (0x2)
#define MCF_PSC_PSCRFSR_FU (0x4)
#define MCF_PSC_PSCRFSR_FRMRDY (0x8)
#define MCF_PSC_PSCRFSR_OF (0x10)
#define MCF_PSC_PSCRFSR_UF (0x20)
#define MCF_PSC_PSCRFSR_RXW (0x40)
#define MCF_PSC_PSCRFSR_FAE (0x80)
#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8)
#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800)
#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400)
#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200)
#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100)
#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC)
#define MCF_PSC_PSCRFSR_TXW (0x4000)
#define MCF_PSC_PSCRFSR_IP (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCRFCR */
#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000)
#define MCF_PSC_PSCRFCR_OF_MSK (0x80000)
#define MCF_PSC_PSCRFCR_UF_MSK (0x100000)
#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000)
#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000)
#define MCF_PSC_PSCRFCR_IP_MSK (0x800000)
#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PSC_PSCRFCR_FRMEN (0x8000000)
#define MCF_PSC_PSCRFCR_TIMER (0x10000000)
/* Bit definitions and macros for MCF_PSC_PSCRFAR */
#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFRP */
#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRFWP */
#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFDR */
#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFSR */
#define MCF_PSC_PSCTFSR_EMT (0x1)
#define MCF_PSC_PSCTFSR_ALARM (0x2)
#define MCF_PSC_PSCTFSR_FU (0x4)
#define MCF_PSC_PSCTFSR_FRMRDY (0x8)
#define MCF_PSC_PSCTFSR_OF (0x10)
#define MCF_PSC_PSCTFSR_UF (0x20)
#define MCF_PSC_PSCTFSR_RXW (0x40)
#define MCF_PSC_PSCTFSR_FAE (0x80)
#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8)
#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800)
#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400)
#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200)
#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100)
#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC)
#define MCF_PSC_PSCTFSR_TXW (0x4000)
#define MCF_PSC_PSCTFSR_IP (0x8000)
/* Bit definitions and macros for MCF_PSC_PSCTFCR */
#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0)
#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000)
#define MCF_PSC_PSCTFCR_OF_MSK (0x80000)
#define MCF_PSC_PSCTFCR_UF_MSK (0x100000)
#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000)
#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000)
#define MCF_PSC_PSCTFCR_IP_MSK (0x800000)
#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_PSC_PSCTFCR_FRMEN (0x8000000)
#define MCF_PSC_PSCTFCR_TIMER (0x10000000)
#define MCF_PSC_PSCTFCR_WFR (0x20000000)
/* Bit definitions and macros for MCF_PSC_PSCTFAR */
#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFRP */
#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTFWP */
#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0)
/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0)
#endif /* __MCF5475_PSC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SDRAMC_H__
#define __MCF5475_SDRAMC_H__
/*********************************************************************
*
* Synchronous DRAM Controller (SDRAMC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SDRAMC_SDRAMDS (*(vuint32*)(&__MBAR[0x4]))
#define MCF_SDRAMC_CS0CFG (*(vuint32*)(&__MBAR[0x20]))
#define MCF_SDRAMC_CS1CFG (*(vuint32*)(&__MBAR[0x24]))
#define MCF_SDRAMC_CS2CFG (*(vuint32*)(&__MBAR[0x28]))
#define MCF_SDRAMC_CS3CFG (*(vuint32*)(&__MBAR[0x2C]))
#define MCF_SDRAMC_SDMR (*(vuint32*)(&__MBAR[0x100]))
#define MCF_SDRAMC_SDCR (*(vuint32*)(&__MBAR[0x104]))
#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(&__MBAR[0x108]))
#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(&__MBAR[0x10C]))
#define MCF_SDRAMC_CSCFG(x) (*(vuint32*)(&__MBAR[0x20 + ((x)*0x4)]))
/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0)
#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2)
#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4)
#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6)
#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8)
#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0)
#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1)
#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2)
#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3)
/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0)
#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0)
#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13)
#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14)
#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15)
#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16)
#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17)
#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18)
#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19)
#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A)
#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B)
#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C)
#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D)
#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E)
#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F)
#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14)
#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000)
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
#define MCF_SDRAMC_SDMR_CMD (0x10000)
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12)
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E)
#define MCF_SDRAMC_SDMR_BK_LMR (0)
#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
#define MCF_SDRAMC_SDCR_IPALL (0x2)
#define MCF_SDRAMC_SDCR_IREF (0x4)
#define MCF_SDRAMC_SDCR_BUFF (0x10)
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8)
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10)
#define MCF_SDRAMC_SDCR_DRIVE (0x400000)
#define MCF_SDRAMC_SDCR_AP (0x800000)
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18)
#define MCF_SDRAMC_SDCR_REF (0x10000000)
#define MCF_SDRAMC_SDCR_DDR (0x20000000)
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4)
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8)
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC)
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10)
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14)
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18)
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10)
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14)
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18)
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C)
#endif /* __MCF5475_SDRAMC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SEC_H__
#define __MCF5475_SEC_H__
/*********************************************************************
*
* Integrated Security Engine (SEC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SEC_EUACRH (*(vuint32*)(&__MBAR[0x21000]))
#define MCF_SEC_EUACRL (*(vuint32*)(&__MBAR[0x21004]))
#define MCF_SEC_SIMRH (*(vuint32*)(&__MBAR[0x21008]))
#define MCF_SEC_SIMRL (*(vuint32*)(&__MBAR[0x2100C]))
#define MCF_SEC_SISRH (*(vuint32*)(&__MBAR[0x21010]))
#define MCF_SEC_SISRL (*(vuint32*)(&__MBAR[0x21014]))
#define MCF_SEC_SICRH (*(vuint32*)(&__MBAR[0x21018]))
#define MCF_SEC_SICRL (*(vuint32*)(&__MBAR[0x2101C]))
#define MCF_SEC_SIDR (*(vuint32*)(&__MBAR[0x21020]))
#define MCF_SEC_EUASRH (*(vuint32*)(&__MBAR[0x21028]))
#define MCF_SEC_EUASRL (*(vuint32*)(&__MBAR[0x2102C]))
#define MCF_SEC_SMCR (*(vuint32*)(&__MBAR[0x21030]))
#define MCF_SEC_MEAR (*(vuint32*)(&__MBAR[0x21038]))
#define MCF_SEC_CCCR0 (*(vuint32*)(&__MBAR[0x2200C]))
#define MCF_SEC_CCPSRH0 (*(vuint32*)(&__MBAR[0x22010]))
#define MCF_SEC_CCPSRL0 (*(vuint32*)(&__MBAR[0x22014]))
#define MCF_SEC_CDPR0 (*(vuint32*)(&__MBAR[0x22044]))
#define MCF_SEC_FR0 (*(vuint32*)(&__MBAR[0x2204C]))
#define MCF_SEC_CCCR1 (*(vuint32*)(&__MBAR[0x2300C]))
#define MCF_SEC_CCPSRH1 (*(vuint32*)(&__MBAR[0x23010]))
#define MCF_SEC_CCPSRL1 (*(vuint32*)(&__MBAR[0x23014]))
#define MCF_SEC_CDPR1 (*(vuint32*)(&__MBAR[0x23044]))
#define MCF_SEC_FR1 (*(vuint32*)(&__MBAR[0x2304C]))
#define MCF_SEC_AFRCR (*(vuint32*)(&__MBAR[0x28018]))
#define MCF_SEC_AFSR (*(vuint32*)(&__MBAR[0x28028]))
#define MCF_SEC_AFISR (*(vuint32*)(&__MBAR[0x28030]))
#define MCF_SEC_AFIMR (*(vuint32*)(&__MBAR[0x28038]))
#define MCF_SEC_DRCR (*(vuint32*)(&__MBAR[0x2A018]))
#define MCF_SEC_DSR (*(vuint32*)(&__MBAR[0x2A028]))
#define MCF_SEC_DISR (*(vuint32*)(&__MBAR[0x2A030]))
#define MCF_SEC_DIMR (*(vuint32*)(&__MBAR[0x2A038]))
#define MCF_SEC_MDRCR (*(vuint32*)(&__MBAR[0x2C018]))
#define MCF_SEC_MDSR (*(vuint32*)(&__MBAR[0x2C028]))
#define MCF_SEC_MDISR (*(vuint32*)(&__MBAR[0x2C030]))
#define MCF_SEC_MDIMR (*(vuint32*)(&__MBAR[0x2C038]))
#define MCF_SEC_RNGRCR (*(vuint32*)(&__MBAR[0x2E018]))
#define MCF_SEC_RNGSR (*(vuint32*)(&__MBAR[0x2E028]))
#define MCF_SEC_RNGISR (*(vuint32*)(&__MBAR[0x2E030]))
#define MCF_SEC_RNGIMR (*(vuint32*)(&__MBAR[0x2E038]))
#define MCF_SEC_AESRCR (*(vuint32*)(&__MBAR[0x32018]))
#define MCF_SEC_AESSR (*(vuint32*)(&__MBAR[0x32028]))
#define MCF_SEC_AESISR (*(vuint32*)(&__MBAR[0x32030]))
#define MCF_SEC_AESIMR (*(vuint32*)(&__MBAR[0x32038]))
#define MCF_SEC_CCCRn(x) (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)]))
#define MCF_SEC_CCPSRHn(x) (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)]))
#define MCF_SEC_CCPSRLn(x) (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)]))
#define MCF_SEC_CDPRn(x) (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)]))
#define MCF_SEC_FRn(x) (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)]))
/* Bit definitions and macros for MCF_SEC_EUACRH */
#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0)
#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0)
#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1)
#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2)
#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8)
#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0)
#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100)
#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200)
#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18)
#define MCF_SEC_EUACRH_RNG_NOASSIGN (0)
#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000)
#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000)
/* Bit definitions and macros for MCF_SEC_EUACRL */
#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10)
#define MCF_SEC_EUACRL_AESU_NOASSIGN (0)
#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000)
#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000)
#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SEC_SIMRH */
#define MCF_SEC_SIMRH_AERR (0x8000000)
#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000)
#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000)
#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000)
#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SIMRL */
#define MCF_SEC_SIMRL_TEA (0x40)
#define MCF_SEC_SIMRL_DEU_DN (0x100)
#define MCF_SEC_SIMRL_DEU_ERR (0x200)
#define MCF_SEC_SIMRL_AESU_DN (0x1000)
#define MCF_SEC_SIMRL_AESU_ERR (0x2000)
#define MCF_SEC_SIMRL_MDEU_DN (0x10000)
#define MCF_SEC_SIMRL_MDEU_ERR (0x20000)
#define MCF_SEC_SIMRL_AFEU_DN (0x100000)
#define MCF_SEC_SIMRL_AFEU_ERR (0x200000)
#define MCF_SEC_SIMRL_RNG_DN (0x1000000)
#define MCF_SEC_SIMRL_RNG_ERR (0x2000000)
/* Bit definitions and macros for MCF_SEC_SISRH */
#define MCF_SEC_SISRH_AERR (0x8000000)
#define MCF_SEC_SISRH_CHA_0_DN (0x10000000)
#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000)
#define MCF_SEC_SISRH_CHA_1_DN (0x40000000)
#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SISRL */
#define MCF_SEC_SISRL_TEA (0x40)
#define MCF_SEC_SISRL_DEU_DN (0x100)
#define MCF_SEC_SISRL_DEU_ERR (0x200)
#define MCF_SEC_SISRL_AESU_DN (0x1000)
#define MCF_SEC_SISRL_AESU_ERR (0x2000)
#define MCF_SEC_SISRL_MDEU_DN (0x10000)
#define MCF_SEC_SISRL_MDEU_ERR (0x20000)
#define MCF_SEC_SISRL_AFEU_DN (0x100000)
#define MCF_SEC_SISRL_AFEU_ERR (0x200000)
#define MCF_SEC_SISRL_RNG_DN (0x1000000)
#define MCF_SEC_SISRL_RNG_ERR (0x2000000)
/* Bit definitions and macros for MCF_SEC_SICRH */
#define MCF_SEC_SICRH_AERR (0x8000000)
#define MCF_SEC_SICRH_CHA_0_DN (0x10000000)
#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000)
#define MCF_SEC_SICRH_CHA_1_DN (0x40000000)
#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000)
/* Bit definitions and macros for MCF_SEC_SICRL */
#define MCF_SEC_SICRL_TEA (0x40)
#define MCF_SEC_SICRL_DEU_DN (0x100)
#define MCF_SEC_SICRL_DEU_ERR (0x200)
#define MCF_SEC_SICRL_AESU_DN (0x1000)
#define MCF_SEC_SICRL_AESU_ERR (0x2000)
#define MCF_SEC_SICRL_MDEU_DN (0x10000)
#define MCF_SEC_SICRL_MDEU_ERR (0x20000)
#define MCF_SEC_SICRL_AFEU_DN (0x100000)
#define MCF_SEC_SICRL_AFEU_ERR (0x200000)
#define MCF_SEC_SICRL_RNG_DN (0x1000000)
#define MCF_SEC_SICRL_RNG_ERR (0x2000000)
/* Bit definitions and macros for MCF_SEC_SIDR */
#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_EUASRH */
#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0)
#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8)
#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SEC_EUASRL */
#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10)
#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SEC_SMCR */
#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4)
#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10)
#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20)
#define MCF_SEC_SMCR_SWR (0x1000000)
/* Bit definitions and macros for MCF_SEC_MEAR */
#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_CCCRn */
#define MCF_SEC_CCCRn_RST (0x1)
#define MCF_SEC_CCCRn_CDIE (0x2)
#define MCF_SEC_CCCRn_NT (0x4)
#define MCF_SEC_CCCRn_NE (0x8)
#define MCF_SEC_CCCRn_WE (0x10)
#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8)
#define MCF_SEC_CCCRn_BURST_SIZE_2 (0)
#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100)
#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200)
#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300)
#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400)
#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500)
#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600)
#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700)
/* Bit definitions and macros for MCF_SEC_CCPSRHn */
#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_SEC_CCPSRLn */
#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0)
#define MCF_SEC_CCPSRLn_EUERR (0x100)
#define MCF_SEC_CCPSRLn_SERR (0x200)
#define MCF_SEC_CCPSRLn_DERR (0x400)
#define MCF_SEC_CCPSRLn_PERR (0x1000)
#define MCF_SEC_CCPSRLn_TEA (0x2000)
#define MCF_SEC_CCPSRLn_SD (0x10000)
#define MCF_SEC_CCPSRLn_PD (0x20000)
#define MCF_SEC_CCPSRLn_SRD (0x40000)
#define MCF_SEC_CCPSRLn_PRD (0x80000)
#define MCF_SEC_CCPSRLn_SG (0x100000)
#define MCF_SEC_CCPSRLn_PG (0x200000)
#define MCF_SEC_CCPSRLn_SR (0x400000)
#define MCF_SEC_CCPSRLn_PR (0x800000)
#define MCF_SEC_CCPSRLn_MO (0x1000000)
#define MCF_SEC_CCPSRLn_MI (0x2000000)
#define MCF_SEC_CCPSRLn_STAT (0x4000000)
/* Bit definitions and macros for MCF_SEC_CDPRn */
#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_FRn */
#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SEC_AFRCR */
#define MCF_SEC_AFRCR_SR (0x1000000)
#define MCF_SEC_AFRCR_MI (0x2000000)
#define MCF_SEC_AFRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_AFSR */
#define MCF_SEC_AFSR_RD (0x1000000)
#define MCF_SEC_AFSR_ID (0x2000000)
#define MCF_SEC_AFSR_IE (0x4000000)
#define MCF_SEC_AFSR_OFR (0x8000000)
#define MCF_SEC_AFSR_IFW (0x10000000)
#define MCF_SEC_AFSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_AFISR */
#define MCF_SEC_AFISR_DSE (0x10000)
#define MCF_SEC_AFISR_KSE (0x20000)
#define MCF_SEC_AFISR_CE (0x40000)
#define MCF_SEC_AFISR_ERE (0x80000)
#define MCF_SEC_AFISR_IE (0x100000)
#define MCF_SEC_AFISR_OFU (0x2000000)
#define MCF_SEC_AFISR_IFO (0x4000000)
#define MCF_SEC_AFISR_IFE (0x10000000)
#define MCF_SEC_AFISR_OFE (0x20000000)
#define MCF_SEC_AFISR_AE (0x40000000)
#define MCF_SEC_AFISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AFIMR */
#define MCF_SEC_AFIMR_DSE (0x10000)
#define MCF_SEC_AFIMR_KSE (0x20000)
#define MCF_SEC_AFIMR_CE (0x40000)
#define MCF_SEC_AFIMR_ERE (0x80000)
#define MCF_SEC_AFIMR_IE (0x100000)
#define MCF_SEC_AFIMR_OFU (0x2000000)
#define MCF_SEC_AFIMR_IFO (0x4000000)
#define MCF_SEC_AFIMR_IFE (0x10000000)
#define MCF_SEC_AFIMR_OFE (0x20000000)
#define MCF_SEC_AFIMR_AE (0x40000000)
#define MCF_SEC_AFIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_DRCR */
#define MCF_SEC_DRCR_SR (0x1000000)
#define MCF_SEC_DRCR_MI (0x2000000)
#define MCF_SEC_DRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_DSR */
#define MCF_SEC_DSR_RD (0x1000000)
#define MCF_SEC_DSR_ID (0x2000000)
#define MCF_SEC_DSR_IE (0x4000000)
#define MCF_SEC_DSR_OFR (0x8000000)
#define MCF_SEC_DSR_IFW (0x10000000)
#define MCF_SEC_DSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_DISR */
#define MCF_SEC_DISR_DSE (0x10000)
#define MCF_SEC_DISR_KSE (0x20000)
#define MCF_SEC_DISR_CE (0x40000)
#define MCF_SEC_DISR_ERE (0x80000)
#define MCF_SEC_DISR_IE (0x100000)
#define MCF_SEC_DISR_KPE (0x200000)
#define MCF_SEC_DISR_OFU (0x2000000)
#define MCF_SEC_DISR_IFO (0x4000000)
#define MCF_SEC_DISR_IFE (0x10000000)
#define MCF_SEC_DISR_OFE (0x20000000)
#define MCF_SEC_DISR_AE (0x40000000)
#define MCF_SEC_DISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_DIMR */
#define MCF_SEC_DIMR_DSE (0x10000)
#define MCF_SEC_DIMR_KSE (0x20000)
#define MCF_SEC_DIMR_CE (0x40000)
#define MCF_SEC_DIMR_ERE (0x80000)
#define MCF_SEC_DIMR_IE (0x100000)
#define MCF_SEC_DIMR_KPE (0x200000)
#define MCF_SEC_DIMR_OFU (0x2000000)
#define MCF_SEC_DIMR_IFO (0x4000000)
#define MCF_SEC_DIMR_IFE (0x10000000)
#define MCF_SEC_DIMR_OFE (0x20000000)
#define MCF_SEC_DIMR_AE (0x40000000)
#define MCF_SEC_DIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_MDRCR */
#define MCF_SEC_MDRCR_SR (0x1000000)
#define MCF_SEC_MDRCR_MI (0x2000000)
#define MCF_SEC_MDRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_MDSR */
#define MCF_SEC_MDSR_RD (0x1000000)
#define MCF_SEC_MDSR_ID (0x2000000)
#define MCF_SEC_MDSR_IE (0x4000000)
#define MCF_SEC_MDSR_IFW (0x10000000)
#define MCF_SEC_MDSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_MDISR */
#define MCF_SEC_MDISR_DSE (0x10000)
#define MCF_SEC_MDISR_KSE (0x20000)
#define MCF_SEC_MDISR_CE (0x40000)
#define MCF_SEC_MDISR_ERE (0x80000)
#define MCF_SEC_MDISR_IE (0x100000)
#define MCF_SEC_MDISR_IFO (0x4000000)
#define MCF_SEC_MDISR_AE (0x40000000)
#define MCF_SEC_MDISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_MDIMR */
#define MCF_SEC_MDIMR_DSE (0x10000)
#define MCF_SEC_MDIMR_KSE (0x20000)
#define MCF_SEC_MDIMR_CE (0x40000)
#define MCF_SEC_MDIMR_ERE (0x80000)
#define MCF_SEC_MDIMR_IE (0x100000)
#define MCF_SEC_MDIMR_IFO (0x4000000)
#define MCF_SEC_MDIMR_AE (0x40000000)
#define MCF_SEC_MDIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_RNGRCR */
#define MCF_SEC_RNGRCR_SR (0x1000000)
#define MCF_SEC_RNGRCR_MI (0x2000000)
#define MCF_SEC_RNGRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_RNGSR */
#define MCF_SEC_RNGSR_RD (0x1000000)
#define MCF_SEC_RNGSR_IE (0x4000000)
#define MCF_SEC_RNGSR_OFR (0x8000000)
#define MCF_SEC_RNGSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_RNGISR */
#define MCF_SEC_RNGISR_IE (0x100000)
#define MCF_SEC_RNGISR_OFU (0x2000000)
#define MCF_SEC_RNGISR_AE (0x40000000)
#define MCF_SEC_RNGISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_RNGIMR */
#define MCF_SEC_RNGIMR_IE (0x100000)
#define MCF_SEC_RNGIMR_OFU (0x2000000)
#define MCF_SEC_RNGIMR_AE (0x40000000)
#define MCF_SEC_RNGIMR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AESRCR */
#define MCF_SEC_AESRCR_SR (0x1000000)
#define MCF_SEC_AESRCR_MI (0x2000000)
#define MCF_SEC_AESRCR_RI (0x4000000)
/* Bit definitions and macros for MCF_SEC_AESSR */
#define MCF_SEC_AESSR_RD (0x1000000)
#define MCF_SEC_AESSR_ID (0x2000000)
#define MCF_SEC_AESSR_IE (0x4000000)
#define MCF_SEC_AESSR_OFR (0x8000000)
#define MCF_SEC_AESSR_IFW (0x10000000)
#define MCF_SEC_AESSR_HALT (0x20000000)
/* Bit definitions and macros for MCF_SEC_AESISR */
#define MCF_SEC_AESISR_DSE (0x10000)
#define MCF_SEC_AESISR_KSE (0x20000)
#define MCF_SEC_AESISR_CE (0x40000)
#define MCF_SEC_AESISR_ERE (0x80000)
#define MCF_SEC_AESISR_IE (0x100000)
#define MCF_SEC_AESISR_OFU (0x2000000)
#define MCF_SEC_AESISR_IFO (0x4000000)
#define MCF_SEC_AESISR_IFE (0x10000000)
#define MCF_SEC_AESISR_OFE (0x20000000)
#define MCF_SEC_AESISR_AE (0x40000000)
#define MCF_SEC_AESISR_ME (0x80000000)
/* Bit definitions and macros for MCF_SEC_AESIMR */
#define MCF_SEC_AESIMR_DSE (0x10000)
#define MCF_SEC_AESIMR_KSE (0x20000)
#define MCF_SEC_AESIMR_CE (0x40000)
#define MCF_SEC_AESIMR_ERE (0x80000)
#define MCF_SEC_AESIMR_IE (0x100000)
#define MCF_SEC_AESIMR_OFU (0x2000000)
#define MCF_SEC_AESIMR_IFO (0x4000000)
#define MCF_SEC_AESIMR_IFE (0x10000000)
#define MCF_SEC_AESIMR_OFE (0x20000000)
#define MCF_SEC_AESIMR_AE (0x40000000)
#define MCF_SEC_AESIMR_ME (0x80000000)
#endif /* __MCF5475_SEC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SIU_H__
#define __MCF5475_SIU_H__
/*********************************************************************
*
* System Integration Unit (SIU)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SIU_SBCR (*(vuint32*)(&__MBAR[0x10]))
#define MCF_SIU_SECSACR (*(vuint32*)(&__MBAR[0x38]))
#define MCF_SIU_RSR (*(vuint32*)(&__MBAR[0x44]))
#define MCF_SIU_JTAGID (*(vuint32*)(&__MBAR[0x50]))
/* Bit definitions and macros for MCF_SIU_SBCR */
#define MCF_SIU_SBCR_PIN2DSPI (0x8000000)
#define MCF_SIU_SBCR_DMA2CPU (0x10000000)
#define MCF_SIU_SBCR_CPU2DMA (0x20000000)
#define MCF_SIU_SBCR_PIN2DMA (0x40000000)
#define MCF_SIU_SBCR_PIN2CPU (0x80000000)
/* Bit definitions and macros for MCF_SIU_SECSACR */
#define MCF_SIU_SECSACR_SEQEN (0x1)
/* Bit definitions and macros for MCF_SIU_RSR */
#define MCF_SIU_RSR_RST (0x1)
#define MCF_SIU_RSR_RSTWD (0x2)
#define MCF_SIU_RSR_RSTJTG (0x8)
/* Bit definitions and macros for MCF_SIU_JTAGID */
#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF5475_SIU_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SLT_H__
#define __MCF5475_SLT_H__
/*********************************************************************
*
* Slice Timers (SLT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SLT0_STCNT (*(vuint32*)(&__MBAR[0x900]))
#define MCF_SLT0_SCR (*(vuint32*)(&__MBAR[0x904]))
#define MCF_SLT0_SCNT (*(vuint32*)(&__MBAR[0x908]))
#define MCF_SLT0_SSR (*(vuint32*)(&__MBAR[0x90C]))
#define MCF_SLT1_STCNT (*(vuint32*)(&__MBAR[0x910]))
#define MCF_SLT1_SCR (*(vuint32*)(&__MBAR[0x914]))
#define MCF_SLT1_SCNT (*(vuint32*)(&__MBAR[0x918]))
#define MCF_SLT1_SSR (*(vuint32*)(&__MBAR[0x91C]))
#define MCF_SLT_STCNT(x) (*(vuint32*)(&__MBAR[0x900 + ((x)*0x10)]))
#define MCF_SLT_SCR(x) (*(vuint32*)(&__MBAR[0x904 + ((x)*0x10)]))
#define MCF_SLT_SCNT(x) (*(vuint32*)(&__MBAR[0x908 + ((x)*0x10)]))
#define MCF_SLT_SSR(x) (*(vuint32*)(&__MBAR[0x90C + ((x)*0x10)]))
/* Bit definitions and macros for MCF_SLT_STCNT */
#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SLT_SCR */
#define MCF_SLT_SCR_TEN (0x1000000)
#define MCF_SLT_SCR_IEN (0x2000000)
#define MCF_SLT_SCR_RUN (0x4000000)
/* Bit definitions and macros for MCF_SLT_SCNT */
#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_SLT_SSR */
#define MCF_SLT_SSR_ST (0x1000000)
#define MCF_SLT_SSR_BE (0x2000000)
#endif /* __MCF5475_SLT_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_SRAM_H__
#define __MCF5475_SRAM_H__
/*********************************************************************
*
* System SRAM Module (SRAM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SRAM_SSCR (*(vuint32*)(&__MBAR[0x1FFC0]))
#define MCF_SRAM_TCCR (*(vuint32*)(&__MBAR[0x1FFC4]))
#define MCF_SRAM_TCCRDR (*(vuint32*)(&__MBAR[0x1FFC8]))
#define MCF_SRAM_TCCRDW (*(vuint32*)(&__MBAR[0x1FFCC]))
#define MCF_SRAM_TCCRSEC (*(vuint32*)(&__MBAR[0x1FFD0]))
/* Bit definitions and macros for MCF_SRAM_SSCR */
#define MCF_SRAM_SSCR_INLV (0x10000)
/* Bit definitions and macros for MCF_SRAM_TCCR */
#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SRAM_TCCRDR */
#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SRAM_TCCRDW */
#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18)
/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0)
#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8)
#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10)
#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18)
#endif /* __MCF5475_SRAM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_USB_H__
#define __MCF5475_USB_H__
/*********************************************************************
*
* Universal Serial Bus Interface (USB)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_USB_USBAISR (*(vuint8 *)(&__MBAR[0xB000]))
#define MCF_USB_USBAIMR (*(vuint8 *)(&__MBAR[0xB001]))
#define MCF_USB_EPINFO (*(vuint8 *)(&__MBAR[0xB003]))
#define MCF_USB_CFGR (*(vuint8 *)(&__MBAR[0xB004]))
#define MCF_USB_CFGAR (*(vuint8 *)(&__MBAR[0xB005]))
#define MCF_USB_SPEEDR (*(vuint8 *)(&__MBAR[0xB006]))
#define MCF_USB_FRMNUMR (*(vuint16*)(&__MBAR[0xB00E]))
#define MCF_USB_EPTNR (*(vuint16*)(&__MBAR[0xB010]))
#define MCF_USB_IFUR (*(vuint16*)(&__MBAR[0xB014]))
#define MCF_USB_IFR0 (*(vuint16*)(&__MBAR[0xB040]))
#define MCF_USB_IFR1 (*(vuint16*)(&__MBAR[0xB042]))
#define MCF_USB_IFR2 (*(vuint16*)(&__MBAR[0xB044]))
#define MCF_USB_IFR3 (*(vuint16*)(&__MBAR[0xB046]))
#define MCF_USB_IFR4 (*(vuint16*)(&__MBAR[0xB048]))
#define MCF_USB_IFR5 (*(vuint16*)(&__MBAR[0xB04A]))
#define MCF_USB_IFR6 (*(vuint16*)(&__MBAR[0xB04C]))
#define MCF_USB_IFR7 (*(vuint16*)(&__MBAR[0xB04E]))
#define MCF_USB_IFR8 (*(vuint16*)(&__MBAR[0xB050]))
#define MCF_USB_IFR9 (*(vuint16*)(&__MBAR[0xB052]))
#define MCF_USB_IFR10 (*(vuint16*)(&__MBAR[0xB054]))
#define MCF_USB_IFR11 (*(vuint16*)(&__MBAR[0xB056]))
#define MCF_USB_IFR12 (*(vuint16*)(&__MBAR[0xB058]))
#define MCF_USB_IFR13 (*(vuint16*)(&__MBAR[0xB05A]))
#define MCF_USB_IFR14 (*(vuint16*)(&__MBAR[0xB05C]))
#define MCF_USB_IFR15 (*(vuint16*)(&__MBAR[0xB05E]))
#define MCF_USB_IFR16 (*(vuint16*)(&__MBAR[0xB060]))
#define MCF_USB_IFR17 (*(vuint16*)(&__MBAR[0xB062]))
#define MCF_USB_IFR18 (*(vuint16*)(&__MBAR[0xB064]))
#define MCF_USB_IFR19 (*(vuint16*)(&__MBAR[0xB066]))
#define MCF_USB_IFR20 (*(vuint16*)(&__MBAR[0xB068]))
#define MCF_USB_IFR21 (*(vuint16*)(&__MBAR[0xB06A]))
#define MCF_USB_IFR22 (*(vuint16*)(&__MBAR[0xB06C]))
#define MCF_USB_IFR23 (*(vuint16*)(&__MBAR[0xB06E]))
#define MCF_USB_IFR24 (*(vuint16*)(&__MBAR[0xB070]))
#define MCF_USB_IFR25 (*(vuint16*)(&__MBAR[0xB072]))
#define MCF_USB_IFR26 (*(vuint16*)(&__MBAR[0xB074]))
#define MCF_USB_IFR27 (*(vuint16*)(&__MBAR[0xB076]))
#define MCF_USB_IFR28 (*(vuint16*)(&__MBAR[0xB078]))
#define MCF_USB_IFR29 (*(vuint16*)(&__MBAR[0xB07A]))
#define MCF_USB_IFR30 (*(vuint16*)(&__MBAR[0xB07C]))
#define MCF_USB_IFR31 (*(vuint16*)(&__MBAR[0xB07E]))
#define MCF_USB_PPCNT (*(vuint16*)(&__MBAR[0xB080]))
#define MCF_USB_DPCNT (*(vuint16*)(&__MBAR[0xB082]))
#define MCF_USB_CRCECNT (*(vuint16*)(&__MBAR[0xB084]))
#define MCF_USB_BSECNT (*(vuint16*)(&__MBAR[0xB086]))
#define MCF_USB_PIDECNT (*(vuint16*)(&__MBAR[0xB088]))
#define MCF_USB_FRMECNT (*(vuint16*)(&__MBAR[0xB08A]))
#define MCF_USB_TXPCNT (*(vuint16*)(&__MBAR[0xB08C]))
#define MCF_USB_CNTOVR (*(vuint8 *)(&__MBAR[0xB08E]))
#define MCF_USB_EP0ACR (*(vuint8 *)(&__MBAR[0xB101]))
#define MCF_USB_EP0MPSR (*(vuint16*)(&__MBAR[0xB102]))
#define MCF_USB_EP0IFR (*(vuint8 *)(&__MBAR[0xB104]))
#define MCF_USB_EP0SR (*(vuint8 *)(&__MBAR[0xB105]))
#define MCF_USB_BMRTR (*(vuint8 *)(&__MBAR[0xB106]))
#define MCF_USB_BRTR (*(vuint8 *)(&__MBAR[0xB107]))
#define MCF_USB_WVALUER (*(vuint16*)(&__MBAR[0xB108]))
#define MCF_USB_WINDEXR (*(vuint16*)(&__MBAR[0xB10A]))
#define MCF_USB_WLENGTHR (*(vuint16*)(&__MBAR[0xB10C]))
#define MCF_USB_EP1OUTACR (*(vuint8 *)(&__MBAR[0xB131]))
#define MCF_USB_EP1OUTMPSR (*(vuint16*)(&__MBAR[0xB132]))
#define MCF_USB_EP1OUTIFR (*(vuint8 *)(&__MBAR[0xB134]))
#define MCF_USB_EP1OUTSR (*(vuint8 *)(&__MBAR[0xB135]))
#define MCF_USB_EP1OUTSFR (*(vuint16*)(&__MBAR[0xB13E]))
#define MCF_USB_EP1INACR (*(vuint8 *)(&__MBAR[0xB149]))
#define MCF_USB_EP1INMPSR (*(vuint16*)(&__MBAR[0xB14A]))
#define MCF_USB_EP1INIFR (*(vuint8 *)(&__MBAR[0xB14C]))
#define MCF_USB_EP1INSR (*(vuint8 *)(&__MBAR[0xB14D]))
#define MCF_USB_EP1INSFR (*(vuint16*)(&__MBAR[0xB156]))
#define MCF_USB_EP2OUTACR (*(vuint8 *)(&__MBAR[0xB161]))
#define MCF_USB_EP2OUTMPSR (*(vuint16*)(&__MBAR[0xB162]))
#define MCF_USB_EP2OUTIFR (*(vuint8 *)(&__MBAR[0xB164]))
#define MCF_USB_EP2OUTSR (*(vuint8 *)(&__MBAR[0xB165]))
#define MCF_USB_EP2OUTSFR (*(vuint16*)(&__MBAR[0xB16E]))
#define MCF_USB_EP2INACR (*(vuint8 *)(&__MBAR[0xB179]))
#define MCF_USB_EP2INMPSR (*(vuint16*)(&__MBAR[0xB17A]))
#define MCF_USB_EP2INIFR (*(vuint8 *)(&__MBAR[0xB17C]))
#define MCF_USB_EP2INSR (*(vuint8 *)(&__MBAR[0xB17D]))
#define MCF_USB_EP2INSFR (*(vuint16*)(&__MBAR[0xB186]))
#define MCF_USB_EP3OUTACR (*(vuint8 *)(&__MBAR[0xB191]))
#define MCF_USB_EP3OUTMPSR (*(vuint16*)(&__MBAR[0xB192]))
#define MCF_USB_EP3OUTIFR (*(vuint8 *)(&__MBAR[0xB194]))
#define MCF_USB_EP3OUTSR (*(vuint8 *)(&__MBAR[0xB195]))
#define MCF_USB_EP3OUTSFR (*(vuint16*)(&__MBAR[0xB19E]))
#define MCF_USB_EP3INACR (*(vuint8 *)(&__MBAR[0xB1A9]))
#define MCF_USB_EP3INMPSR (*(vuint16*)(&__MBAR[0xB1AA]))
#define MCF_USB_EP3INIFR (*(vuint8 *)(&__MBAR[0xB1AC]))
#define MCF_USB_EP3INSR (*(vuint8 *)(&__MBAR[0xB1AD]))
#define MCF_USB_EP3INSFR (*(vuint16*)(&__MBAR[0xB1B6]))
#define MCF_USB_EP4OUTACR (*(vuint8 *)(&__MBAR[0xB1C1]))
#define MCF_USB_EP4OUTMPSR (*(vuint16*)(&__MBAR[0xB1C2]))
#define MCF_USB_EP4OUTIFR (*(vuint8 *)(&__MBAR[0xB1C4]))
#define MCF_USB_EP4OUTSR (*(vuint8 *)(&__MBAR[0xB1C5]))
#define MCF_USB_EP4OUTSFR (*(vuint16*)(&__MBAR[0xB1CE]))
#define MCF_USB_EP4INACR (*(vuint8 *)(&__MBAR[0xB1D9]))
#define MCF_USB_EP4INMPSR (*(vuint16*)(&__MBAR[0xB1DA]))
#define MCF_USB_EP4INIFR (*(vuint8 *)(&__MBAR[0xB1DC]))
#define MCF_USB_EP4INSR (*(vuint8 *)(&__MBAR[0xB1DD]))
#define MCF_USB_EP4INSFR (*(vuint16*)(&__MBAR[0xB1E6]))
#define MCF_USB_EP5OUTACR (*(vuint8 *)(&__MBAR[0xB1F1]))
#define MCF_USB_EP5OUTMPSR (*(vuint16*)(&__MBAR[0xB1F2]))
#define MCF_USB_EP5OUTIFR (*(vuint8 *)(&__MBAR[0xB1F4]))
#define MCF_USB_EP5OUTSR (*(vuint8 *)(&__MBAR[0xB1F5]))
#define MCF_USB_EP5OUTSFR (*(vuint16*)(&__MBAR[0xB1FE]))
#define MCF_USB_EP5INACR (*(vuint8 *)(&__MBAR[0xB209]))
#define MCF_USB_EP5INMPSR (*(vuint16*)(&__MBAR[0xB20A]))
#define MCF_USB_EP5INIFR (*(vuint8 *)(&__MBAR[0xB20C]))
#define MCF_USB_EP5INSR (*(vuint8 *)(&__MBAR[0xB20D]))
#define MCF_USB_EP5INSFR (*(vuint16*)(&__MBAR[0xB216]))
#define MCF_USB_EP6OUTACR (*(vuint8 *)(&__MBAR[0xB221]))
#define MCF_USB_EP6OUTMPSR (*(vuint16*)(&__MBAR[0xB222]))
#define MCF_USB_EP6OUTIFR (*(vuint8 *)(&__MBAR[0xB224]))
#define MCF_USB_EP6OUTSR (*(vuint8 *)(&__MBAR[0xB225]))
#define MCF_USB_EP6OUTSFR (*(vuint16*)(&__MBAR[0xB22E]))
#define MCF_USB_EP6INACR (*(vuint8 *)(&__MBAR[0xB239]))
#define MCF_USB_EP6INMPSR (*(vuint16*)(&__MBAR[0xB23A]))
#define MCF_USB_EP6INIFR (*(vuint8 *)(&__MBAR[0xB23C]))
#define MCF_USB_EP6INSR (*(vuint8 *)(&__MBAR[0xB23D]))
#define MCF_USB_EP6INSFR (*(vuint16*)(&__MBAR[0xB246]))
#define MCF_USB_USBSR (*(vuint32*)(&__MBAR[0xB400]))
#define MCF_USB_USBCR (*(vuint32*)(&__MBAR[0xB404]))
#define MCF_USB_DRAMCR (*(vuint32*)(&__MBAR[0xB408]))
#define MCF_USB_DRAMDR (*(vuint32*)(&__MBAR[0xB40C]))
#define MCF_USB_USBISR (*(vuint32*)(&__MBAR[0xB410]))
#define MCF_USB_USBIMR (*(vuint32*)(&__MBAR[0xB414]))
#define MCF_USB_EP0STAT (*(vuint32*)(&__MBAR[0xB440]))
#define MCF_USB_EP0ISR (*(vuint32*)(&__MBAR[0xB444]))
#define MCF_USB_EP0IMR (*(vuint32*)(&__MBAR[0xB448]))
#define MCF_USB_EP0FRCFGR (*(vuint32*)(&__MBAR[0xB44C]))
#define MCF_USB_EP0FDR (*(vuint32*)(&__MBAR[0xB450]))
#define MCF_USB_EP0FSR (*(vuint32*)(&__MBAR[0xB454]))
#define MCF_USB_EP0FCR (*(vuint32*)(&__MBAR[0xB458]))
#define MCF_USB_EP0FAR (*(vuint32*)(&__MBAR[0xB45C]))
#define MCF_USB_EP0FRP (*(vuint32*)(&__MBAR[0xB460]))
#define MCF_USB_EP0FWP (*(vuint32*)(&__MBAR[0xB464]))
#define MCF_USB_EP0LRFP (*(vuint32*)(&__MBAR[0xB468]))
#define MCF_USB_EP0LWFP (*(vuint32*)(&__MBAR[0xB46C]))
#define MCF_USB_EP1STAT (*(vuint32*)(&__MBAR[0xB470]))
#define MCF_USB_EP1ISR (*(vuint32*)(&__MBAR[0xB474]))
#define MCF_USB_EP1IMR (*(vuint32*)(&__MBAR[0xB478]))
#define MCF_USB_EP1FRCFGR (*(vuint32*)(&__MBAR[0xB47C]))
#define MCF_USB_EP1FDR (*(vuint32*)(&__MBAR[0xB480]))
#define MCF_USB_EP1FSR (*(vuint32*)(&__MBAR[0xB484]))
#define MCF_USB_EP1FCR (*(vuint32*)(&__MBAR[0xB488]))
#define MCF_USB_EP1FAR (*(vuint32*)(&__MBAR[0xB48C]))
#define MCF_USB_EP1FRP (*(vuint32*)(&__MBAR[0xB490]))
#define MCF_USB_EP1FWP (*(vuint32*)(&__MBAR[0xB494]))
#define MCF_USB_EP1LRFP (*(vuint32*)(&__MBAR[0xB498]))
#define MCF_USB_EP1LWFP (*(vuint32*)(&__MBAR[0xB49C]))
#define MCF_USB_EP2STAT (*(vuint32*)(&__MBAR[0xB4A0]))
#define MCF_USB_EP2ISR (*(vuint32*)(&__MBAR[0xB4A4]))
#define MCF_USB_EP2IMR (*(vuint32*)(&__MBAR[0xB4A8]))
#define MCF_USB_EP2FRCFGR (*(vuint32*)(&__MBAR[0xB4AC]))
#define MCF_USB_EP2FDR (*(vuint32*)(&__MBAR[0xB4B0]))
#define MCF_USB_EP2FSR (*(vuint32*)(&__MBAR[0xB4B4]))
#define MCF_USB_EP2FCR (*(vuint32*)(&__MBAR[0xB4B8]))
#define MCF_USB_EP2FAR (*(vuint32*)(&__MBAR[0xB4BC]))
#define MCF_USB_EP2FRP (*(vuint32*)(&__MBAR[0xB4C0]))
#define MCF_USB_EP2FWP (*(vuint32*)(&__MBAR[0xB4C4]))
#define MCF_USB_EP2LRFP (*(vuint32*)(&__MBAR[0xB4C8]))
#define MCF_USB_EP2LWFP (*(vuint32*)(&__MBAR[0xB4CC]))
#define MCF_USB_EP3STAT (*(vuint32*)(&__MBAR[0xB4D0]))
#define MCF_USB_EP3ISR (*(vuint32*)(&__MBAR[0xB4D4]))
#define MCF_USB_EP3IMR (*(vuint32*)(&__MBAR[0xB4D8]))
#define MCF_USB_EP3FRCFGR (*(vuint32*)(&__MBAR[0xB4DC]))
#define MCF_USB_EP3FDR (*(vuint32*)(&__MBAR[0xB4E0]))
#define MCF_USB_EP3FSR (*(vuint32*)(&__MBAR[0xB4E4]))
#define MCF_USB_EP3FCR (*(vuint32*)(&__MBAR[0xB4E8]))
#define MCF_USB_EP3FAR (*(vuint32*)(&__MBAR[0xB4EC]))
#define MCF_USB_EP3FRP (*(vuint32*)(&__MBAR[0xB4F0]))
#define MCF_USB_EP3FWP (*(vuint32*)(&__MBAR[0xB4F4]))
#define MCF_USB_EP3LRFP (*(vuint32*)(&__MBAR[0xB4F8]))
#define MCF_USB_EP3LWFP (*(vuint32*)(&__MBAR[0xB4FC]))
#define MCF_USB_EP4STAT (*(vuint32*)(&__MBAR[0xB500]))
#define MCF_USB_EP4ISR (*(vuint32*)(&__MBAR[0xB504]))
#define MCF_USB_EP4IMR (*(vuint32*)(&__MBAR[0xB508]))
#define MCF_USB_EP4FRCFGR (*(vuint32*)(&__MBAR[0xB50C]))
#define MCF_USB_EP4FDR (*(vuint32*)(&__MBAR[0xB510]))
#define MCF_USB_EP4FSR (*(vuint32*)(&__MBAR[0xB514]))
#define MCF_USB_EP4FCR (*(vuint32*)(&__MBAR[0xB518]))
#define MCF_USB_EP4FAR (*(vuint32*)(&__MBAR[0xB51C]))
#define MCF_USB_EP4FRP (*(vuint32*)(&__MBAR[0xB520]))
#define MCF_USB_EP4FWP (*(vuint32*)(&__MBAR[0xB524]))
#define MCF_USB_EP4LRFP (*(vuint32*)(&__MBAR[0xB528]))
#define MCF_USB_EP4LWFP (*(vuint32*)(&__MBAR[0xB52C]))
#define MCF_USB_EP5STAT (*(vuint32*)(&__MBAR[0xB530]))
#define MCF_USB_EP5ISR (*(vuint32*)(&__MBAR[0xB534]))
#define MCF_USB_EP5IMR (*(vuint32*)(&__MBAR[0xB538]))
#define MCF_USB_EP5FRCFGR (*(vuint32*)(&__MBAR[0xB53C]))
#define MCF_USB_EP5FDR (*(vuint32*)(&__MBAR[0xB540]))
#define MCF_USB_EP5FSR (*(vuint32*)(&__MBAR[0xB544]))
#define MCF_USB_EP5FCR (*(vuint32*)(&__MBAR[0xB548]))
#define MCF_USB_EP5FAR (*(vuint32*)(&__MBAR[0xB54C]))
#define MCF_USB_EP5FRP (*(vuint32*)(&__MBAR[0xB550]))
#define MCF_USB_EP5FWP (*(vuint32*)(&__MBAR[0xB554]))
#define MCF_USB_EP5LRFP (*(vuint32*)(&__MBAR[0xB558]))
#define MCF_USB_EP5LWFP (*(vuint32*)(&__MBAR[0xB55C]))
#define MCF_USB_EP6STAT (*(vuint32*)(&__MBAR[0xB560]))
#define MCF_USB_EP6ISR (*(vuint32*)(&__MBAR[0xB564]))
#define MCF_USB_EP6IMR (*(vuint32*)(&__MBAR[0xB568]))
#define MCF_USB_EP6FRCFGR (*(vuint32*)(&__MBAR[0xB56C]))
#define MCF_USB_EP6FDR (*(vuint32*)(&__MBAR[0xB570]))
#define MCF_USB_EP6FSR (*(vuint32*)(&__MBAR[0xB574]))
#define MCF_USB_EP6FCR (*(vuint32*)(&__MBAR[0xB578]))
#define MCF_USB_EP6FAR (*(vuint32*)(&__MBAR[0xB57C]))
#define MCF_USB_EP6FRP (*(vuint32*)(&__MBAR[0xB580]))
#define MCF_USB_EP6FWP (*(vuint32*)(&__MBAR[0xB584]))
#define MCF_USB_EP6LRFP (*(vuint32*)(&__MBAR[0xB588]))
#define MCF_USB_EP6LWFP (*(vuint32*)(&__MBAR[0xB58C]))
#define MCF_USB_IFR(x) (*(vuint16*)(&__MBAR[0xB040 + ((x)*0x2)]))
#define MCF_USB_EPOUTACR(x) (*(vuint8 *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTMPSR(x) (*(vuint16*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTIFR(x) (*(vuint8 *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTSR(x) (*(vuint8 *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTSFR(x) (*(vuint16*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
#define MCF_USB_EPINACR(x) (*(vuint8 *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
#define MCF_USB_EPINMPSR(x) (*(vuint16*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
#define MCF_USB_EPINIFR(x) (*(vuint8 *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
#define MCF_USB_EPINSR(x) (*(vuint8 *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
#define MCF_USB_EPINSFR(x) (*(vuint16*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
#define MCF_USB_EPSTAT(x) (*(vuint32*)(&__MBAR[0xB440 + ((x)*0x30)]))
#define MCF_USB_EPISR(x) (*(vuint32*)(&__MBAR[0xB444 + ((x)*0x30)]))
#define MCF_USB_EPIMR(x) (*(vuint32*)(&__MBAR[0xB448 + ((x)*0x30)]))
#define MCF_USB_EPFRCFGR(x) (*(vuint32*)(&__MBAR[0xB44C + ((x)*0x30)]))
#define MCF_USB_EPFDR(x) (*(vuint32*)(&__MBAR[0xB450 + ((x)*0x30)]))
#define MCF_USB_EPFSR(x) (*(vuint32*)(&__MBAR[0xB454 + ((x)*0x30)]))
#define MCF_USB_EPFCR(x) (*(vuint32*)(&__MBAR[0xB458 + ((x)*0x30)]))
#define MCF_USB_EPFAR(x) (*(vuint32*)(&__MBAR[0xB45C + ((x)*0x30)]))
#define MCF_USB_EPFRP(x) (*(vuint32*)(&__MBAR[0xB460 + ((x)*0x30)]))
#define MCF_USB_EPFWP(x) (*(vuint32*)(&__MBAR[0xB464 + ((x)*0x30)]))
#define MCF_USB_EPLRFP(x) (*(vuint32*)(&__MBAR[0xB468 + ((x)*0x30)]))
#define MCF_USB_EPLWFP(x) (*(vuint32*)(&__MBAR[0xB46C + ((x)*0x30)]))
/* Bit definitions and macros for MCF_USB_USBAISR */
#define MCF_USB_USBAISR_SETUP (0x1)
#define MCF_USB_USBAISR_IN (0x2)
#define MCF_USB_USBAISR_OUT (0x4)
#define MCF_USB_USBAISR_EPHALT (0x8)
#define MCF_USB_USBAISR_TRANSERR (0x10)
#define MCF_USB_USBAISR_ACK (0x20)
#define MCF_USB_USBAISR_CTROVFL (0x40)
#define MCF_USB_USBAISR_EPSTALL (0x80)
/* Bit definitions and macros for MCF_USB_USBAIMR */
#define MCF_USB_USBAIMR_SETUPEN (0x1)
#define MCF_USB_USBAIMR_INEN (0x2)
#define MCF_USB_USBAIMR_OUTEN (0x4)
#define MCF_USB_USBAIMR_EPHALTEN (0x8)
#define MCF_USB_USBAIMR_TRANSERREN (0x10)
#define MCF_USB_USBAIMR_ACKEN (0x20)
#define MCF_USB_USBAIMR_CTROVFLEN (0x40)
#define MCF_USB_USBAIMR_EPSTALLEN (0x80)
/* Bit definitions and macros for MCF_USB_EPINFO */
#define MCF_USB_EPINFO_EPDIR (0x1)
#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1)
/* Bit definitions and macros for MCF_USB_CFGR */
#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_CFGAR */
#define MCF_USB_CFGAR_RESERVED (0xA0)
#define MCF_USB_CFGAR_RMTWKEUP (0xE0)
/* Bit definitions and macros for MCF_USB_SPEEDR */
#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0)
/* Bit definitions and macros for MCF_USB_FRMNUMR */
#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPTNR */
#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0)
#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2)
#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4)
#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6)
#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8)
#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA)
#define MCF_USB_EPTNR_EPnT1 (0)
#define MCF_USB_EPTNR_EPnT2 (0x1)
#define MCF_USB_EPTNR_EPnT3 (0x2)
/* Bit definitions and macros for MCF_USB_IFUR */
#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0)
#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8)
/* Bit definitions and macros for MCF_USB_IFR */
#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0)
#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8)
/* Bit definitions and macros for MCF_USB_PPCNT */
#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_DPCNT */
#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_CRCECNT */
#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_BSECNT */
#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_PIDECNT */
#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_FRMECNT */
#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_TXPCNT */
#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_CNTOVR */
#define MCF_USB_CNTOVR_PPCNT (0x1)
#define MCF_USB_CNTOVR_DPCNT (0x2)
#define MCF_USB_CNTOVR_CRCECNT (0x4)
#define MCF_USB_CNTOVR_BSECNT (0x8)
#define MCF_USB_CNTOVR_PIDECNT (0x10)
#define MCF_USB_CNTOVR_FRMECNT (0x20)
#define MCF_USB_CNTOVR_TXPCNT (0x40)
/* Bit definitions and macros for MCF_USB_EP0ACR */
#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0)
#define MCF_USB_EP0ACR_TTYPE_CTRL (0)
#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1)
#define MCF_USB_EP0ACR_TTYPE_BULK (0x2)
#define MCF_USB_EP0ACR_TTYPE_INT (0x3)
/* Bit definitions and macros for MCF_USB_EP0MPSR */
#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
/* Bit definitions and macros for MCF_USB_EP0IFR */
#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_EP0SR */
#define MCF_USB_EP0SR_HALT (0x1)
#define MCF_USB_EP0SR_ACTIVE (0x2)
#define MCF_USB_EP0SR_PSTALL (0x4)
#define MCF_USB_EP0SR_CCOMP (0x8)
#define MCF_USB_EP0SR_TXZERO (0x20)
#define MCF_USB_EP0SR_INT (0x80)
/* Bit definitions and macros for MCF_USB_BMRTR */
#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0)
#define MCF_USB_BMRTR_REC_DEVICE (0)
#define MCF_USB_BMRTR_REC_INTERFACE (0x1)
#define MCF_USB_BMRTR_REC_ENDPOINT (0x2)
#define MCF_USB_BMRTR_REC_OTHER (0x3)
#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5)
#define MCF_USB_BMRTR_TYPE_STANDARD (0)
#define MCF_USB_BMRTR_TYPE_CLASS (0x20)
#define MCF_USB_BMRTR_TYPE_VENDOR (0x40)
#define MCF_USB_BMRTR_DIR (0x80)
/* Bit definitions and macros for MCF_USB_BRTR */
#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_WVALUER */
#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_WINDEXR */
#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_WLENGTHR */
#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPOUTACR */
#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0)
#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1)
#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2)
#define MCF_USB_EPOUTACR_TTYPE_INT (0x3)
/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
/* Bit definitions and macros for MCF_USB_EPOUTIFR */
#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_EPOUTSR */
#define MCF_USB_EPOUTSR_HALT (0x1)
#define MCF_USB_EPOUTSR_ACTIVE (0x2)
#define MCF_USB_EPOUTSR_PSTALL (0x4)
#define MCF_USB_EPOUTSR_CCOMP (0x8)
#define MCF_USB_EPOUTSR_TXZERO (0x20)
#define MCF_USB_EPOUTSR_INT (0x80)
/* Bit definitions and macros for MCF_USB_EPOUTSFR */
#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0)
/* Bit definitions and macros for MCF_USB_EPINACR */
#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0)
#define MCF_USB_EPINACR_TTYPE_ISOC (0x1)
#define MCF_USB_EPINACR_TTYPE_BULK (0x2)
#define MCF_USB_EPINACR_TTYPE_INT (0x3)
/* Bit definitions and macros for MCF_USB_EPINMPSR */
#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
/* Bit definitions and macros for MCF_USB_EPINIFR */
#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_EPINSR */
#define MCF_USB_EPINSR_HALT (0x1)
#define MCF_USB_EPINSR_ACTIVE (0x2)
#define MCF_USB_EPINSR_PSTALL (0x4)
#define MCF_USB_EPINSR_CCOMP (0x8)
#define MCF_USB_EPINSR_TXZERO (0x20)
#define MCF_USB_EPINSR_INT (0x80)
/* Bit definitions and macros for MCF_USB_EPINSFR */
#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0)
/* Bit definitions and macros for MCF_USB_USBSR */
#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0)
#define MCF_USB_USBSR_SUSP (0x80)
/* Bit definitions and macros for MCF_USB_USBCR */
#define MCF_USB_USBCR_RESUME (0x1)
#define MCF_USB_USBCR_APPLOCK (0x2)
#define MCF_USB_USBCR_RST (0x4)
#define MCF_USB_USBCR_RAMEN (0x8)
#define MCF_USB_USBCR_RAMSPLIT (0x20)
/* Bit definitions and macros for MCF_USB_DRAMCR */
#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0)
#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10)
#define MCF_USB_DRAMCR_BSY (0x40000000)
#define MCF_USB_DRAMCR_START (0x80000000)
/* Bit definitions and macros for MCF_USB_DRAMDR */
#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_USBISR */
#define MCF_USB_USBISR_ISOERR (0x1)
#define MCF_USB_USBISR_FTUNLCK (0x2)
#define MCF_USB_USBISR_SUSP (0x4)
#define MCF_USB_USBISR_RES (0x8)
#define MCF_USB_USBISR_UPDSOF (0x10)
#define MCF_USB_USBISR_RSTSTOP (0x20)
#define MCF_USB_USBISR_SOF (0x40)
#define MCF_USB_USBISR_MSOF (0x80)
/* Bit definitions and macros for MCF_USB_USBIMR */
#define MCF_USB_USBIMR_ISOERR (0x1)
#define MCF_USB_USBIMR_FTUNLCK (0x2)
#define MCF_USB_USBIMR_SUSP (0x4)
#define MCF_USB_USBIMR_RES (0x8)
#define MCF_USB_USBIMR_UPDSOF (0x10)
#define MCF_USB_USBIMR_RSTSTOP (0x20)
#define MCF_USB_USBIMR_SOF (0x40)
#define MCF_USB_USBIMR_MSOF (0x80)
/* Bit definitions and macros for MCF_USB_EPSTAT */
#define MCF_USB_EPSTAT_RST (0x1)
#define MCF_USB_EPSTAT_FLUSH (0x2)
#define MCF_USB_EPSTAT_DIR (0x80)
#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10)
/* Bit definitions and macros for MCF_USB_EPISR */
#define MCF_USB_EPISR_EOF (0x1)
#define MCF_USB_EPISR_EOT (0x4)
#define MCF_USB_EPISR_FIFOLO (0x10)
#define MCF_USB_EPISR_FIFOHI (0x20)
#define MCF_USB_EPISR_ERR (0x40)
#define MCF_USB_EPISR_EMT (0x80)
#define MCF_USB_EPISR_FU (0x100)
/* Bit definitions and macros for MCF_USB_EPIMR */
#define MCF_USB_EPIMR_EOF (0x1)
#define MCF_USB_EPIMR_EOT (0x4)
#define MCF_USB_EPIMR_FIFOLO (0x10)
#define MCF_USB_EPIMR_FIFOHI (0x20)
#define MCF_USB_EPIMR_ERR (0x40)
#define MCF_USB_EPIMR_EMT (0x80)
#define MCF_USB_EPIMR_FU (0x100)
/* Bit definitions and macros for MCF_USB_EPFRCFGR */
#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0)
#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10)
/* Bit definitions and macros for MCF_USB_EPFDR */
#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPFSR */
#define MCF_USB_EPFSR_EMT (0x10000)
#define MCF_USB_EPFSR_ALRM (0x20000)
#define MCF_USB_EPFSR_FU (0x40000)
#define MCF_USB_EPFSR_FR (0x80000)
#define MCF_USB_EPFSR_OF (0x100000)
#define MCF_USB_EPFSR_UF (0x200000)
#define MCF_USB_EPFSR_RXW (0x400000)
#define MCF_USB_EPFSR_FAE (0x800000)
#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_USB_EPFSR_TXW (0x40000000)
#define MCF_USB_EPFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_USB_EPFCR */
#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0)
#define MCF_USB_EPFCR_TXWMSK (0x40000)
#define MCF_USB_EPFCR_OFMSK (0x80000)
#define MCF_USB_EPFCR_UFMSK (0x100000)
#define MCF_USB_EPFCR_RXWMSK (0x200000)
#define MCF_USB_EPFCR_FAEMSK (0x400000)
#define MCF_USB_EPFCR_IPMSK (0x800000)
#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_USB_EPFCR_FRM (0x8000000)
#define MCF_USB_EPFCR_TMR (0x10000000)
#define MCF_USB_EPFCR_WFR (0x20000000)
#define MCF_USB_EPFCR_SHAD (0x80000000)
/* Bit definitions and macros for MCF_USB_EPFAR */
#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPFRP */
#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPFWP */
#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPLRFP */
#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0)
/* Bit definitions and macros for MCF_USB_EPLWFP */
#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0)
#endif /* __MCF5475_USB_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_XLB_H__
#define __MCF5475_XLB_H__
/*********************************************************************
*
* XL Bus Arbiter (XLB)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_XLB_XARB_CFG (*(vuint32*)(&__MBAR[0x240]))
#define MCF_XLB_XARB_VER (*(vuint32*)(&__MBAR[0x244]))
#define MCF_XLB_XARB_SR (*(vuint32*)(&__MBAR[0x248]))
#define MCF_XLB_XARB_IMR (*(vuint32*)(&__MBAR[0x24C]))
#define MCF_XLB_XARB_ADRCAP (*(vuint32*)(&__MBAR[0x250]))
#define MCF_XLB_XARB_SIGCAP (*(vuint32*)(&__MBAR[0x254]))
#define MCF_XLB_XARB_ADRTO (*(vuint32*)(&__MBAR[0x258]))
#define MCF_XLB_XARB_DATTO (*(vuint32*)(&__MBAR[0x25C]))
#define MCF_XLB_XARB_BUSTO (*(vuint32*)(&__MBAR[0x260]))
#define MCF_XLB_XARB_PRIEN (*(vuint32*)(&__MBAR[0x264]))
#define MCF_XLB_XARB_PRI (*(vuint32*)(&__MBAR[0x268]))
/* Bit definitions and macros for MCF_XLB_XARB_CFG */
#define MCF_XLB_XARB_CFG_AT (0x2)
#define MCF_XLB_XARB_CFG_DT (0x4)
#define MCF_XLB_XARB_CFG_BA (0x8)
#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5)
#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8)
#define MCF_XLB_XARB_CFG_PLDIS (0x80000000)
/* Bit definitions and macros for MCF_XLB_XARB_VER */
#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_SR */
#define MCF_XLB_XARB_SR_AT (0x1)
#define MCF_XLB_XARB_SR_DT (0x2)
#define MCF_XLB_XARB_SR_BA (0x4)
#define MCF_XLB_XARB_SR_TTM (0x8)
#define MCF_XLB_XARB_SR_ECW (0x10)
#define MCF_XLB_XARB_SR_TTR (0x20)
#define MCF_XLB_XARB_SR_TTA (0x40)
#define MCF_XLB_XARB_SR_MM (0x80)
#define MCF_XLB_XARB_SR_SEA (0x100)
/* Bit definitions and macros for MCF_XLB_XARB_IMR */
#define MCF_XLB_XARB_IMR_ATE (0x1)
#define MCF_XLB_XARB_IMR_DTE (0x2)
#define MCF_XLB_XARB_IMR_BAE (0x4)
#define MCF_XLB_XARB_IMR_TTME (0x8)
#define MCF_XLB_XARB_IMR_ECWE (0x10)
#define MCF_XLB_XARB_IMR_TTRE (0x20)
#define MCF_XLB_XARB_IMR_TTAE (0x40)
#define MCF_XLB_XARB_IMR_MME (0x80)
#define MCF_XLB_XARB_IMR_SEAE (0x100)
/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0)
#define MCF_XLB_XARB_SIGCAP_TBST (0x20)
#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7)
/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
#define MCF_XLB_XARB_PRIEN_M0 (0x1)
#define MCF_XLB_XARB_PRIEN_M2 (0x4)
#define MCF_XLB_XARB_PRIEN_M3 (0x8)
/* Bit definitions and macros for MCF_XLB_XARB_PRI */
#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0)
#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8)
#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC)
#endif /* __MCF5475_XLB_H__ */

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# Sample Linker Command File for CodeWarrior for ColdFire
KEEP_SECTION {.vectortable}
# Memory ranges
MEMORY {
code (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0
}
SECTIONS {
#BaS Basis adresse
___Bas_base = 0x1FE00000;
# Board Memory map definitions from linker command files:
# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE
# linker symbols must be defined in the linker command file.
#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
___BOOT_FLASH = 0xE0000000;
___BOOT_FLASH_SIZE = 0x00800000;
#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
___SDRAM = 0x00000000;
___SDRAM_SIZE = 0x20000000;
#VIDEO RAM BASIS
___VRAM = 0x60000000;
# MCF5475 Derivative Memory map definitions from linker command files:
# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
# linker symbols must be defined in the linker command file.
# Memory mapped registers
___MBAR = 0xFF000000;
___MMUBAR = 0xFF040000;
# 4KB on-chip Core SRAM0: -> exception table and exception stack
___RAMBAR0 = 0xFF100000;
___RAMBAR0_SIZE = 0x00001000;
___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
# 4KB on-chip Core SRAM1: -> modified code
___RAMBAR1 = 0xFF101000;
___RAMBAR1_SIZE = 0x00001000;
# Systemveriablem:******************************************
# RAMBAR0 0 bis 0x7FF -> exception vectoren
_rt_mod = ___RAMBAR0 + 0x800;
_rt_ssp = ___RAMBAR0 + 0x804;
_rt_usp = ___RAMBAR0 + 0x808;
_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01
_rt_cacr = ___RAMBAR0 + 0x810; # 002
_rt_asid = ___RAMBAR0 + 0x814; # 003
_rt_acr0 = ___RAMBAR0 + 0x818; # 004
_rt_acr1 = ___RAMBAR0 + 0x81c; # 005
_rt_acr2 = ___RAMBAR0 + 0x820; # 006
_rt_acr3 = ___RAMBAR0 + 0x824; # 007
_rt_mmubar = ___RAMBAR0 + 0x828; # 008
_rt_sr = ___RAMBAR0 + 0x82c;
_d0_save = ___RAMBAR0 + 0x830;
_a7_save = ___RAMBAR0 + 0x834;
_video_tlb = ___RAMBAR0 + 0x838;
_video_sbt = ___RAMBAR0 + 0x83C;
_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f
#***********************************************************
# 32KB on-chip System SRAM
___SYS_SRAM = 0xFF010000;
___SYS_SRAM_SIZE = 0x00008000;
.text :
{
startcf.c(.text)
sysinit.c(.text)
BaS.c(.text)
sd_card.c(.text)
mmu.s(.text)
exceptions.s(.text)
supervisor.s(.text)
ewf.s(.text)
illegal_instruction.s(.text)
last.c(.text)
. = ALIGN (0x4);
} > code
}

88
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# Sample Linker Command File for CodeWarrior for ColdFire
KEEP_SECTION {.vectortable}
# Memory ranges
MEMORY {
code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000
}
SECTIONS {
#BaS Basis adresse
___Bas_base = 0x1FE00000;
# Board Memory map definitions from linker command files:
# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE
# linker symbols must be defined in the linker command file.
#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
___BOOT_FLASH = 0xE0000000;
___BOOT_FLASH_SIZE = 0x00800000;
#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
___SDRAM = 0x00000000;
___SDRAM_SIZE = 0x20000000;
#VIDEO RAM BASIS
___VRAM = 0x60000000;
# MCF5475 Derivative Memory map definitions from linker command files:
# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
# linker symbols must be defined in the linker command file.
# Memory mapped registers
___MBAR = 0xFF000000;
___MMUBAR = 0xFF040000;
# 4KB on-chip Core SRAM0: -> exception table and exception stack
___RAMBAR0 = 0xFF100000;
___RAMBAR0_SIZE = 0x00001000;
___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
# 4KB on-chip Core SRAM1: -> modified code
___RAMBAR1 = 0xFF101000;
___RAMBAR1_SIZE = 0x00001000;
# Systemveriablem:******************************************
# RAMBAR0 0 bis 0x7FF -> exception vectoren
_rt_mod = ___RAMBAR0 + 0x800;
_rt_ssp = ___RAMBAR0 + 0x804;
_rt_usp = ___RAMBAR0 + 0x808;
_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01
_rt_cacr = ___RAMBAR0 + 0x810; # 002
_rt_asid = ___RAMBAR0 + 0x814; # 003
_rt_acr0 = ___RAMBAR0 + 0x818; # 004
_rt_acr1 = ___RAMBAR0 + 0x81c; # 005
_rt_acr2 = ___RAMBAR0 + 0x820; # 006
_rt_acr3 = ___RAMBAR0 + 0x824; # 007
_rt_mmubar = ___RAMBAR0 + 0x828; # 008
_rt_sr = ___RAMBAR0 + 0x82c;
_d0_save = ___RAMBAR0 + 0x830;
_a7_save = ___RAMBAR0 + 0x834;
_video_tlb = ___RAMBAR0 + 0x838;
_video_sbt = ___RAMBAR0 + 0x83C;
_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f
#***********************************************************
# 32KB on-chip System SRAM
___SYS_SRAM = 0xFF010000;
___SYS_SRAM_SIZE = 0x00008000;
.code : {} > code
.text :
{
startcf.c(.text)
sysinit.c(.text)
BaS.c(.text)
sd_card.c(.text)
mmu.s(.text)
exceptions.s(.text)
supervisor.s(.text)
ewf.s(.text)
illegal_instruction.s(.text)
last.c(.text)
} >> code
}

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/*
* BaS
*
*/
#include "MCF5475.h"
#include "startcf.h"
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
/* imported routines */
extern int mmu_init();
extern int mmutr_miss();
extern int vec_init();
extern int illegal_table_make();
extern int cf68k_initialize();
/********************************************************************/
/* warte_routinen /*
********************************************************************/
void warte_10ms(void)
{
asm
{
warte_10ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1ms(void)
{
asm
{
warte_1ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_100us(void)
{
asm
{
warte_100us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #13200,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_50us(void)
{
asm
{
warte_50us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #6600,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_10us(void)
{
asm
{
warte_10us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1us(void)
{
asm
{
warte_1us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
/********************************************************************/
void BaS(void)
{
int az_sectors;
int sd_status,i;
az_sectors = sd_card_init();
if(az_sectors>0)
{
sd_card_idle();
}
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq firetos_kopieren
lea MCF_PSC0_PSCTB_8BIT,a6
lea MCF_PSC3_PSCTB_8BIT,a3
lea MCF_PSC3_PSCRB_8BIT,a4
lea MCF_PSC3_PSCRFCNT,a5
move.l #'ACPF',(a3) // SEND SYNC MARKE, MCF BEREIT
bsr warte_10ms
move.l #'PIC ',(a6)
move.b (a4),d0
move.b d0,(a6)
move.b (a4),d1
move.b d1,(a6)
move.b (a4),d2
move.b d2,(a6)
move.l #0x0a0d,(a6)
move.b #0x01,(a3) // RTC DATEN ANFORDERN
// TOS kopieren
lea 0x00e00000,a0
lea 0xe0600000,a1 // default tos
lea 0xe0700000,a2 // 1MB
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
bne cptos_loop
firetos_kopieren:
lea 0x00e00000,a0
lea 0xe0400000,a1
lea 0xe0500000,a2 // 1MB
cptos_loop:
move.l (a1)+,(a0)+
cmp.l a2,a1
blt cptos_loop
/***************************************************************/
/* div inits
/***************************************************************/
div_inits:
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq video_setup
// rtc daten, mmu set, etc nur wenn switch 6 = off
lea 0xffff8961,a0
clr.l d1
moveq #64,d2
move.b (a4),d0
cmp.b #0x81,d0
bne not_rtc
loop_sr:
move.b (a4),d0
move.b d1,(a0)
move.b d0,2(a0)
addq.l #1,d1
cmp.b d1,d2
bne loop_sr
/*
// Set the NVRAM checksum as invalid
move.b #63,(a0)
move.b 2(a0),d0
add #1,d0
move.b d0,2(a0)
*/
not_rtc:
bsr mmu_init
bsr vec_init
bsr illegal_table_make
// interrupts
clr.l 0xf0010004 // disable all interrupts
lea MCF_EPORT_EPPAR,a0
move.w #0xaaa8,(a0) // falling edge all,
// timer 0 on mit int -> video change -------------------------------------------
move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge
move.l d0,MCF_GPT0_GMS
moveq.l #0x3f,d0 // max prority interrutp
move.b d0,MCF_INTC_ICR62 // setzen
// -------------------------------------------------
move.b #0xfe,d0
move.b d0,0xf0010004 // enable int 1-7
nop
lea MCF_EPORT_EPIER,a0
move.b #0xfe,(a0) // int 1-7 on
nop
lea MCF_EPORT_EPFR,a0
move.b #0xff,(a0) // alle pending interrupts l<>schen
nop
lea MCF_INTC_IMRL,a0
move.l #0xFFFFFF00,(a0) // int 1-7 on
lea MCF_INTC_IMRH,a0
move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on
move.l #MCF_MMU_MMUCR_EN,d0
move.l d0,MCF_MMU_MMUCR // mmu on
nop
nop
/********************************************************************/
/* IDE reset
/********************************************************************/
lea 0xffff8802,a0
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
/********************************************************************/
/* video setup
/********************************************************************/
video_setup:
lea 0xf0000410,a0
// 25MHz
move.l #0x032002ba,(a0)+ // horizontal 640x480
move.l #0x020c020a,(a0)+ // vertikal 640x480
move.l #0x0190015d,(a0)+ // horizontal 320x240
move.l #0x020C020A,(a0)+ // vertikal 320x240 */
/*
// 32MHz
move.l #0x037002ba,(a0)+ // horizontal 640x480
move.l #0x020d020a,(a0)+ // vertikal 640x480
move.l #0x02A001e0,(a0)+ // horizontal 320x240
move.l #0x05a00160,(a0)+ // vertikal 320x240
*/
lea -0x20(a0),a0
move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on,
/********************************************************************/
/* memory setup
/********************************************************************/
lea 0x400,a0
lea 0x800,a1
mem_clr_loop:
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
cmp.l a0,a1
bgt mem_clr_loop
moveq #0x48,d0
move.b d0,0xffff8007
// stram
move.l #0xe00000,d0 // ende stram
move.l d0,0x42e
move.l #0x752019f3,d0 // memvalid
move.l d0,0x420
move.l #0x237698aa,d0 // memval2
move.l d0,0x43a
move.l #0x5555aaaa,d0 // memval3
move.l d0,0x51a
// ttram
move.l #__Bas_base,d0 // ende ttram
move.l d0,0x5a4
move.l #0x1357bd13,d0 // ramvalid
move.l d0,0x5a8
// init acia
moveq #3,d0
move.b d0,0xfffffc00
nop
move.b d0,0xfffffc04
nop
moveq #0x96,d0
move.b d0,0xfffffc00
moveq #-1,d0
nop
move.b d0,0xfffffa0f
nop
move.b d0,0xfffffa11
nop
// test auf protect mode ---------------------
move.b DIP_SWITCH,d0
btst #7,d0
beq no_protect // nein->
move.w #0x0700,sr
no_protect:
jmp 0xe00030
}
}

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/********************************************************/
/* exception vectoren intialisieren
/********************************************************/
.include "startcf.h"
.extern ___Bas_base
.extern ___SUP_SP
.extern ___BOOT_FLASH
.extern ___RAMBAR0
.extern _rt_cacr
.extern _rt_mod
.extern _rt_ssp
.extern _rt_usp
.extern _rt_vbr
.extern _illegal_instruction
.extern _privileg_violation
.extern _mmutr_miss
.extern ___MBAR
.extern ___MMUBAR
.extern _video_tlb
.extern _video_sbt
.extern cpusha
/* Register read/write macros */
#define MCF_MMU_MMUCR ___MMUBAR
#define MCF_MMU_MMUOR ___MMUBAR+0x04
#define MCF_MMU_MMUSR ___MMUBAR+0x08
#define MCF_MMU_MMUAR ___MMUBAR+0x10
#define MCF_MMU_MMUTR ___MMUBAR+0x14
#define MCF_MMU_MMUDR ___MMUBAR+0x18
#define MCF_EPORT_EPPAR ___MBAR+0xF00
#define MCF_EPORT_EPDDR ___MBAR+0xF04
#define MCF_EPORT_EPIER ___MBAR+0xF05
#define MCF_EPORT_EPDR ___MBAR+0xF08
#define MCF_EPORT_EPPDR ___MBAR+0xF09
#define MCF_EPORT_EPFR ___MBAR+0xF0C
#define MCF_GPIO_PODR_FEC1L ___MBAR+0xA07
#define MCF_PSC0_PSCTB_8BIT ___MBAR+0x860C
#define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C
#define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C
.public _vec_init
//mmu ---------------------------------------------------
/* Register read/write macros */
#define MCF_MMU_MMUCR ___MMUBAR
#define MCF_MMU_MMUOR ___MMUBAR+0x04
#define MCF_MMU_MMUSR ___MMUBAR+0x08
#define MCF_MMU_MMUAR ___MMUBAR+0x10
#define MCF_MMU_MMUTR ___MMUBAR+0x14
#define MCF_MMU_MMUDR ___MMUBAR+0x18
/* Bit definitions and macros for MCF_MMU_MMUCR */
#define MCF_MMU_MMUCR_EN (0x1)
#define MCF_MMU_MMUCR_ASM (0x2)
/* Bit definitions and macros for MCF_MMU_MMUOR */
#define MCF_MMU_MMUOR_UAA (0x1)
#define MCF_MMU_MMUOR_ACC (0x2)
#define MCF_MMU_MMUOR_RW (0x4)
#define MCF_MMU_MMUOR_ADR (0x8)
#define MCF_MMU_MMUOR_ITLB (0x10)
#define MCF_MMU_MMUOR_CAS (0x20)
#define MCF_MMU_MMUOR_CNL (0x40)
#define MCF_MMU_MMUOR_CA (0x80)
#define MCF_MMU_MMUOR_STLB (0x100)
#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_MMU_MMUSR */
#define MCF_MMU_MMUSR_HIT (0x2)
#define MCF_MMU_MMUSR_WF (0x8)
#define MCF_MMU_MMUSR_RF (0x10)
#define MCF_MMU_MMUSR_SPF (0x20)
/* Bit definitions and macros for MCF_MMU_MMUAR */
#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_MMU_MMUTR */
#define MCF_MMU_MMUTR_V (0x1)
#define MCF_MMU_MMUTR_SG (0x2)
#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2)
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
/* Bit definitions and macros for MCF_MMU_MMUDR */
#define MCF_MMU_MMUDR_LK (0x2)
#define MCF_MMU_MMUDR_X (0x4)
#define MCF_MMU_MMUDR_W (0x8)
#define MCF_MMU_MMUDR_R (0x10)
#define MCF_MMU_MMUDR_SP (0x20)
#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6)
#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8)
#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA)
#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V)
#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
//---------------------------------------------------
/*********************************************************************
*
* General Purpose Timers (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPT0_GMS ___MBAR+0x800
/*********************************************************************
*
* Slice Timers (SLT)
*
*********************************************************************/
#define MCF_SLT0_SCNT ___MBAR+0x908
/**********************************************************/
// macros
/**********************************************************/
irq: .macro vector,int_mask,clr_int
move.w #0x2700,sr // disable interrupt
subq.l #8,a7
movem.l d0/a5,(a7) // register sichern
lea MCF_EPORT_EPFR,a5
move.b #clr_int,(a5) // clear int pending
// test auf protect mode ---------------------
move.b DIP_SWITCHa,d0
btst #7,d0
bne @irq_protect // ja->
// -------------------------------------------
movem.l (a7),d0/a5 // register zur<EFBFBD>ck
addq.l #8,a7
move.l vector,-(a7)
move #0x2\200,sr
rts
@irq_protect:
move.l usp,a5 // usp holen
tst.b _rt_mod // supervisor?
bne @sev_supint // ja ->
mov3q.l #-1,_rt_mod // auf supervisor setzen
move.l a5,_rt_usp // rt_usp speichern
move.l _rt_ssp,a5 // rt_ssp holen
#ifdef cf_stack
move.l 12(a7),-(a5) // pc transferieren
move.l 8(a7),-(a5) // sr,vec
#else
move.w 8(a7),-(a5) // vector nr.
move.l 12(a7),-(a5) // pc verschieben
move.w 10(a7),-(a5) // sr verschieben
#endif
bra @irq_end
@sev_supint:
#ifdef cf_stack
move.l 12(a7),-(a5) // pc transferieren
move.l 8(a7),-(a5) // sr,vec
bset #5,2(a5) // auf super setzen
#else
move.w 8(a7),-(a5) // vector nr.
move.l 12(a7),-(a5) // pc verschieben
move.w 10(a7),-(a5) // sr verschieben
bset #5,(a5) // auf super
#endif
@irq_end:
move.l a5,usp // usp setzen
lea vector,a5
adda.l _rt_vbr,a5
move.l (a5),12(a7) // vectoradresse eintragen
move.b #int_mask,10(a7) // intmaske setzen
movem.l (a7),d0/a5 // register zur<EFBFBD>ck
addq.l #8,a7
rte // und weg
.endm
/*********************************************************/
.text
_vec_init:
mov3q.l #-1,_rt_mod // rt_mod auf super
clr.l _rt_ssp
clr.l _rt_usp
clr.l _rt_vbr
move.l #___RAMBAR0,d0 // sind in rambar0
movec d0,VBR
move.l d0,a0
move.l a0,a2
init_vec:
move.l #256,d0
lea std_exc_vec(pc),a1 // standard vector
init_vec_loop:
move.l a1,(a2)+ // mal standard vector f<EFBFBD>r alle setzen
subq.l #1,d0
bne init_vec_loop
move.l #___SUP_SP,(a0)
lea reset_vector(pc),a1
move.l a1,0x04(a0)
lea acess(pc),a1
move.l a1,0x08(a0)
move.b DIP_SWITCHa,d0 // ++ vr
btst #7,d0
beq no_protect_vectors
lea _illegal_instruction(pc),a1
move.l a1,0x0c(a0)
lea _illegal_instruction(pc),a1
move.l a1,0x10(a0)
lea zero_divide(pc),a1
move.l a1,0x14(a0)
lea _privileg_violation(pc),a1
move.l a1,0x20(a0)
lea linea(pc),a1
move.l a1,0x28(a0)
lea linef(pc),a1
move.l a1,0x2c(a0)
lea format(pc),a1
move.l a1,0x38(a0)
// floating point overflow
lea flpoow(pc),a1
move.l a1,0xc0(a0)
lea flpoow(pc),a1
move.l a1,0xc4(a0)
lea flpoow(pc),a1
move.l a1,0xc8(a0)
lea flpoow(pc),a1
move.l a1,0xcc(a0)
lea flpoow(pc),a1
move.l a1,0xd0(a0)
lea flpoow(pc),a1
move.l a1,0xd4(a0)
lea flpoow(pc),a1
move.l a1,0xd8(a0)
lea flpoow(pc),a1
move.l a1,0xdc(a0)
no_protect_vectors:
// int 1-7
lea irq1(pc),a1
move.l a1,0x104(a0)
lea irq2(pc),a1
move.l a1,0x108(a0)
lea irq3(pc),a1
move.l a1,0x10c(a0)
lea irq4(pc),a1
move.l a1,0x110(a0)
lea irq5(pc),a1
move.l a1,0x114(a0)
lea irq6(pc),a1
move.l a1,0x118(a0)
lea irq7(pc),a1
move.l a1,0x11c(a0)
//psc_vectors
lea psc3(pc),a1
move.l a1,0x180(a0)
//timer 1 vectors
lea timer0(pc),a1
move.l a1,0x1f8(a0)
rts
/********************************************************/
/* exception vector routinen
/********************************************************/
vector_table_start:
std_exc_vec:
move.w #0x2700,sr // disable interrupt
subq.l #8,a7
movem.l d0/a5,(a7) // register sichern
// test auf protect mode -------------------------------
move.b DIP_SWITCHa,d0
btst #7,d0
bne stv_protect // ja->
//------------------------------------------------------
move.w 8(a7),d0 // vector holen
and.l #0x3fc,d0 // vector nummer ausmaskieren
add.l _rt_vbr,d0 // + basis
move.l d0,a5
move.l (a5),d0
move.l 4(a7),a5 // a5 zur<EFBFBD>ck
move.l d0,4(a7)
move.w 10(a7),d0
bset #13,d0 // super
move.w d0,sr // orginal sr wert in super setzen
move.l (a7)+,d0 // d0 zur<EFBFBD>ck
rts
stv_protect:
move.l usp,a5 // usp holen
tst.b _rt_mod // supervisor?
bne sev_sup // ja ->
mov3q.l #-1,_rt_mod // auf supervisor setzen
move.l a5,_rt_usp // rt_usp speichern
move.l _rt_ssp,a5 // rt_ssp holen
#ifdef cf_stack
move.l 12(a7),-(a5) // pc transferieren
move.l 8(a7),d0 // sr holen
move.l d0,-(a5) // sr transferieren
swap d0 // vec -> lw
#else
move.w 8(a7),d0 // vector holen
move.w d0,-(a5) // ablegen
move.l 12(a7),-(a5) // pc transferieren
move.w 10(a7),-(a5) // sr transferieren
#endif
move.l a5,usp // usp setzen
and.l #0x3fc,d0 // vector nummer ausmaskieren
add.l _rt_vbr,d0 // + basis
move.l d0,a5
move.l (a5),12(a7) // hier geht's weiter
movem.l (a7),d0/a5 // register zur<EFBFBD>ck
addq.l #8,a7
rte // und weg
sev_sup:
#ifdef cf_stack
move.l 12(a7),-(a5) // pc transferieren
move.l 8(a7),d0 // sr holen
bset #13,d0 // war aus rt super
move.l d0,-(a5) // sr transferieren
swap d0 // vec -> lw
#else
move.w 8(a7),d0 // vector holen
move.w d0,-(a5) // ablegen
move.l 12(a7),-(a5) // pc transferieren
move.w 10(a7),-(a5) // sr transferieren
bset #5,(a5) // war aus super
#endif
move.l a5,usp // usp setzen
and.l #0x3fc,d0 // vector nummer ausmaskieren
add.l _rt_vbr,d0 // + basis
move.l d0,a5
move.l (a5),12(a7) // hier geht's weiter
movem.l (a7),d0/a5 // register zur<EFBFBD>ck
addq.l #8,a7
rte // und weg
//*******************************************
reset_vector:
move.w #0x2700,sr // disable interrupt
move.l #0x31415926,d0
cmp.l 0x426,d0 // reset vector g<EFBFBD>ltg?
beq std_exc_vec // ja->
jmp ___BOOT_FLASH // sonst kaltstart
acess:
move.w #0x2700,sr // disable interrupt
move.l d0,-(sp) // ++ vr
move.w 4(sp),d0
andi.l #0x0c03,d0
cmpi.l #0x0401,d0
beq access_mmu
cmpi.l #0x0402,d0
beq access_mmu
cmpi.l #0x0802,d0
beq access_mmu
cmpi.l #0x0c02,d0
beq access_mmu
bra bus_error
access_mmu:
move.l MCF_MMU_MMUSR,d0
btst #1,d0
bne bus_error
move.l MCF_MMU_MMUAR,d0
cmp.l #___Bas_base,d0 // max User RAM Bereich
bge bus_error // gr<EFBFBD>sser -> bus error
bra _mmutr_miss
bus_error:
move.l (sp)+,d0
bra std_exc_vec
zero_divide:
move.w #0x2700,sr // disable interrupt
move.l a0,-(a7)
move.l d0,-(a7)
move.l 12(a7),a0 // pc
move.w (a0)+,d0 // befehlscode
btst #7,d0 // long?
beq zd_word // nein->
addq.l #2,a0
zd_word:
and.l 0x3f,d0 // ea ausmaskieren
cmp.w #0x08,d0 // -(ax) oder weniger
ble zd_end
addq.l #2,a0
cmp.w #0x39,d0 // xxx.L
bne zd_nal
addq.l #2,a0
bra zd_end
zd_nal: cmp.w #0x3c,d0 // immediate?
bne zd_end // nein->
btst #7,d0 // long?
beq zd_end // nein
addq.l #2,a0
zd_end:
move.l a0,12(a7)
move.l (a7)+,d0
move.l (a7)+,a0
rte
linea:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
linef:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
format:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
//floating point
flpoow:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
irq1:
irq 0x64,1,0x02
irq2: // hbl
// move.b #3,2(a7)
// rte
irq 0x68,2,0x04
irq3:
irq 0x6c,3,0x08
irq4: // vbl
irq 0x70,4,0x10
irq5: // acp
irq 0x74,5,0x20
irq6: // mfp
move.w #0x2700,sr // disable interrupt
subq.l #8,a7
movem.l d0/a5,(a7) // register sichern
lea MCF_EPORT_EPFR,a5
move.b #0x40,(a5) // clear int6
// test auf timeout screen adr change -------------------------------------------------------
move.l _video_sbt,d0
beq irq6_non_sca // wenn 0 nichts zu tun
sub.l #0x70000000,d0 // 14 sec abz<EFBFBD>hlen
lea MCF_SLT0_SCNT,a5
cmp.l (a5),d0 // aktuelle zeit weg
ble irq6_non_sca // noch nicht abgelaufen
lea -28(a7),a7
movem.l d0-d4/a0-a1,(a7) // register sichern
clr.l d3 // beginn mit 0
bsr cpusha // cache leeren
// eintrag suchen
irq6_next_sca:
move.l d3,d0
move.l d0,MCF_MMU_MMUAR // addresse
move.l #0x106,d4
move.l d4,MCF_MMU_MMUOR // suchen ->
nop
move.l MCF_MMU_MMUOR,d4
clr.w d4
swap d4
move.l d4,MCF_MMU_MMUAR
mvz.w #0x10e,d4
move.l d4,MCF_MMU_MMUOR // eintr<EFBFBD>ge holen aus mmu
nop
move.l MCF_MMU_MMUTR,d4 // ID holen
lsr.l #2,d4 // bit 9 bis 2
cmp.w #sca_page_ID,d4 // ist screen change ID?
bne irq6_sca_pn // nein -> page keine screen area next
// eintrag <EFBFBD>ndern
add.l #std_mmutr,d0
move.l d3,d1 // page 0?
beq irq6_sca_pn0 // ja ->
add.l #cb_mmudr,d1 // sonst page cb
bra irq6_sca_pn1c
irq6_sca_pn0:
add.l #wt_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked
irq6_sca_pn1c:
mvz.w #0x10b,d2 // MMU update
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setze tlb data only
nop
// page copy
move.l d3,a0
add.l #0x60000000,a0
move.l d3,a1
move.l #0x10000,d4 // die ganze page
irq6_vcd0_loop:
move.l (a0)+,(a1)+ // page copy
move.l (a0)+,(a1)+
move.l (a0)+,(a1)+
move.l (a0)+,(a1)+
subq.l #1,d4
bne irq6_vcd0_loop
nop
irq6_sca_pn:
add.l #0x00100000,d3 // next
cmp.l #0x00d00000,d3 // ende?
blt irq6_next_sca // nein->
move.l #0x2000,d0
move.l d0,_video_tlb // anfangszustand wieder herstellen
clr.l _video_sbt // zeit l<EFBFBD>schen
movem.l (a7),d0-d4/a0-a1 // register zur<EFBFBD>ck
lea 28(a7),a7
irq6_non_sca:
// test auf acsi dma -----------------------------------------------------------------
lea 0xfffffa0b,a5
bset #7,-4(a5) // int ena
btst.b #7,(a5) // acsi dma int?
beq non_acsi_dma
bsr acsi_dma
non_acsi_dma:
// ----------------------------------------------------------------------------------
tst.b (a5)
bne irq6_1
tst.b 2(a5)
bne irq6_1
movem.l (a7),d0/a5
addq.l #8,a7
rte
irq6_1:
lea MCF_GPIO_PODR_FEC1L,a5
bclr.b #4,(a5) // led on
lea blinker(pc),a5
addq.l #1,(a5) // +1
move.l (a5),d0
and.l #0x80,d0
bne irq6_2
lea MCF_GPIO_PODR_FEC1L,a5
bset.b #4,(a5) // led off
irq6_2:
// test auf protect mode ---------------------
move.b DIP_SWITCHa,d0
btst #7,d0
bne irq6_3 // ja->
// -------------------------------------------
move.l 0xF0020000,a5 // vector holen
add.l _rt_vbr,a5 // basis
move.l (a5),d0 // vector holen
move.l 4(a7),a5 // a5 zur<EFBFBD>ck
move.l d0,4(a7) // vector eintragen
move.l (a7)+,d0 // d0 zur<EFBFBD>ck
move #0x2600,sr
rts
irq6_3:
move.l usp,a5 // usp holen
tst.b _rt_mod // supervisor?
bne sev_sup6 // ja ->
mov3q.l #-1,_rt_mod // auf supervisor setzen
move.l a5,_rt_usp // rt_usp speichern
move.l _rt_ssp,a5 // rt_ssp holen
#ifdef cf_stack
move.l 12(a7),-(a5) // pc transferieren
move.l 8(a7),-(a5) // sr transferieren
#else
move.w 8(a7),-(a5) // vector transferieren
move.l 12(a7),-(a5) // pc transferieren
move.w 10(a7),-(a5) // sr transferieren
#endif
move.l a5,usp // usp setzen
move.l 0xF0020000,a5 // vector holen: intack routine
add.l _rt_vbr,a5 // virtuelle VBR des Systems
move.l (a5),12(a7) // hier gehts weiter
movem.l (a7),d0/a5 // register zur<EFBFBD>ck
addq.l #8,a7
move.b #6,2(a7) // intmaske setzen
rte // und weg
sev_sup6:
#ifdef cf_stack
move.l 12(a7),-(a5) // pc transferieren
move.l 8(a7),-(a5) // sr,vec
bset #5,2(a5) // auf super setzen
#else
move.w 8(a7),-(a5) // vector nr.
move.l 12(a7),-(a5) // pc verschieben
move.w 10(a7),-(a5) // sr verschieben
bset #5,(a5) // auf super
#endif
move.l a5,usp // usp setzen
move.l 0xF0020000,a5 // vector holen: intack routine
add.l _rt_vbr,a5 // virtuelle VBR des Systems
move.l (a5),12(a7) // hier gehts weiter
movem.l (a7),d0/a5 // register zur<EFBFBD>ck
rts
blinker:.long 0
/**************************************************/
/* pseudo dma */
/**************************************************/
acsi_dma: // atari dma
move.l a1,-(a7)
move.l d1,-(a7)
lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr
move.l #'DMA ',(a1)
move.l #'INT!',(a1)
lea 0xf0020110,a5 // fifo daten
acsi_dma_start:
move.l -12(a5),a1 // dma adresse
move.l -8(a5),d0 // byt counter
ble acsi_dma_end
btst.b #0,-16(a5) // write? (dma modus reg)
bne acsi_dma_wl // ja->
acsi_dma_rl:
tst.b -4(a5) // dma req?
bpl acsi_dma_fertig // nein->
move.l (a5),(a1)+ // read 4 bytes
move.l (a5),(a1)+ // read 4 bytes
move.l (a5),(a1)+ // read 4 bytes
move.l (a5),(a1)+ // read 4 bytes
moveq #'.',d1
move.b d1,MCF_PSC0_PSCTB_8BIT
sub.l #16,d0 // byt counter -16
bpl acsi_dma_rl
bra acsi_dma_fertig
acsi_dma_wl:
tst.b -4(a5) // dma req?
bpl acsi_dma_fertig // nein->
move.l (a1)+,(a5) // write 4 byts
move.l (a1)+,(a5) // write 4 byts
move.l (a1)+,(a5) // write 4 byts
move.l (a1)+,(a5) // write 4 byts
moveq #'.',d1
move.b d1,MCF_PSC0_PSCTB_8BIT
sub.l #16,d0 // byt counter -16
bpl acsi_dma_wl
acsi_dma_fertig:
move.l a1,-12(a5) // adresse zur<EFBFBD>ck
move.l d0,-8(a5) // byt counter zur<EFBFBD>ck
acsi_dma_end:
tst.b -4(a5) // dma req?
bmi acsi_dma_start // ja->
lea 0xfffffa0b,a5
bclr.b #7,4(a5) // clear int in service mfp
bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b
move.w #0x0d0a,d1
move.w d1,MCF_PSC0_PSCTB_8BIT
move.l (a7)+,d1
move.l (a7)+,a1
rts
/**************************************************/
/* irq 7 = pseudo bus error */
/**************************************************/
irq7:
lea -12(sp),sp
movem.l d0/a0,(sp)
move.l ___RAMBAR0+0x008,a0 // Real Access Error handler
move.l a0,8(sp) // This will be the return address for rts
move.w 12(sp),d0 // Format/Vector word
andi.l #0xf000,d0 // Keep only the Format
ori.l #2*4,d0 // Simulate Vector #2, no Fault
move.w d0,12(sp)
// TODO: Inside an interrupt handler, 16(sp) is the return address.
// For an Access Error, it should be the address of the fault instruction instead
lea MCF_EPORT_EPFR,a0
move.b #0x80,(a0) // clear int7
move.l (sp)+,d0
move.l (sp)+,a0
rts // Forward to the Access Error handler
/**************************************************/
/* psc3 com PIC MCF */
/**************************************************/
psc3:
move.w #0x2700,sr // disable interrupt
lea -20(a7),a7
movem.l d0-d2/a0/a3,(a7)
lea MCF_PSC3_PSCRB_8BIT,a3
move.b (a3),d1
cmp.b #2,d1 // anforderung rtc daten?
bne psc3_fertig
lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr
move.l #'PIC ',(a0)
move.l #'INT ',(a0)
move.l #'RTC!',(a0)
move.l #0x0d0a,(a0)
lea 0xffff8961,a0
lea MCF_PSC3_PSCTB_8BIT,a3
clr.l d1
moveq #64,d2
move.b #0x82,(a3) // header: rtcd mcf->pic
loop_sr2:
move.b d1,(a0)
move.b 2(a0),d0
move.b d0,(a3)
addq.l #1,d1
cmp.b d1,d2
bne loop_sr2
psc3_fertig:
movem.l (a7),d0-d2/a0/a3 // register zur<EFBFBD>ck
lea 20(a7),a7
RTE
/**************************************************/
/* timer 0: video change later also others
/**************************************************/
timer0:
move #0x2700,sr
// halt
lea -28(a7),a7
movem.l d0-d4/a0-a1,(a7)
mvz.b 0xffff8201,d0 // l<EFBFBD>schen und high byt
cmp.w #2,d0
blt video_chg_end
cmp.w #0xd0,d0 // normale addresse
blt sca_other // nein->
lea MCF_SLT0_SCNT,a0
move.l (a0),d4
move.l d4,_video_sbt // time sichern
sca_other:
lsl.l #8,d0
move.b 0xffff8203,d0 // mid byt
lsl.l #8,d0
move.b 0xffff820d,d0 // low byt
move.l d0,d3
video_chg_1page:
// test ob page schon gesetzt
moveq #20,d4
move.l d0,d2
lsr.l d4,d2 // neue page
move.l _video_tlb,d4
bset.l d2,d4 // setzen als ge<EFBFBD>ndert
bne video_chg_2page // schon gesetzt gewesen? ja->weg
move.l d4,_video_tlb
bsr cpusha // cache leeren
// daten copieren
video_copy_data:
move.l d4,_video_tlb
and.l #0x00f00000,d0
move.l d0,a0
move.l a0,a1
add.l #0x60000000,a1
move.l #0x10000,d4 // die ganze page
video_copy_data_loop:
move.l (a0)+,(a1)+
move.l (a0)+,(a1)+
move.l (a0)+,(a1)+
move.l (a0)+,(a1)+
subq.l #1,d4
bne video_copy_data_loop
// eintrag suchen
move.l d0,MCF_MMU_MMUAR // addresse
move.l #0x106,d4
move.l d4,MCF_MMU_MMUOR // suchen -> schl<EFBFBD>gt neuen vor wenn keiner
nop
move.l MCF_MMU_MMUOR,d4
clr.w d4
swap d4
move.l d4,MCF_MMU_MMUAR
move.l d0,d1
add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0
add.l #0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1
mvz.w #0x10b,d2 // MMU update
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setzen vidoe maped to 60xxx only data
nop
video_chg_2page:
// test ob evt. anschliessende page gesetzt werden muss
move.l d3,d0
mvz.w 0xffff8210,d4 // byts pro zeile
mvz.w 0xffff82aa,d2 // zeilen ende
mvz.w 0xffff82a8,d1 // zeilenstart
sub.l d1,d2 // differenz = anzahl zeilen
mulu d2,d4 // maximal 480 zeilen
add.l d4,d0 // video gr<EFBFBD>sse
cmp.l #0xe00000,d0 // maximale addresse
bge video_chg_end // wenn gleich oder gr<EFBFBD>sser -> fertig
moveq #20,d4
move.l d0,d2
lsr.l d4,d2 // neue page
move.l _video_tlb,d4
bset.l d2,d4 // setzen als ge<EFBFBD>ndert
beq video_copy_data // nein nochmal
video_chg_end:
// int pending l<EFBFBD>schen
lea MCF_GPT0_GMS,a0
bclr.b #0,3(a0)
nop
bset.b #0,3(a0)
movem.l (a7),d0-d4/a0-a1
lea 28(a7),a7
//--------------------------------------------------------------------------------------------------------
RTE

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//--------------------------------------------------------------------
// add
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// add.b #im,dx
//--------------------------------------------------------------------
addbir_macro:.macro
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
add.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add ea,dx
//--------------------------------------------------------------------
adddd:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add ea,dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddd:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add (ea),dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
adddda:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add (ay)+,dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddai:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add -(ay),dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d16(ay),dx
//--------------------------------------------------------------------
addd16ad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d8(ay,dy),dx
//--------------------------------------------------------------------
addd8ad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add xxx.w,dx
//--------------------------------------------------------------------
addxwd:.macro
#ifdef halten_add
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add xxx.l,dx
//--------------------------------------------------------------------
addxld:.macro
#ifdef halten_add
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d16(pc),dx
//--------------------------------------------------------------------
addd16pcd:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d8(pc,dy),dx
//--------------------------------------------------------------------
addd8pcd:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// add dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // add dx,(ay) (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addeda:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,(ay)+ (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addedai:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,(ay)+
//--------------------------------------------------------------------
addedaid:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,-(ay)
//--------------------------------------------------------------------
addedad:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,-(ay)
//--------------------------------------------------------------------
addedadd:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,d16(ay)
//--------------------------------------------------------------------
adde16ad:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add.w d8(ay,dy),dx
//--------------------------------------------------------------------
adde8ad:.macro
#ifdef halten_add
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,xxx.w
//--------------------------------------------------------------------
addxwe:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,xxx.l
//--------------------------------------------------------------------
addxle:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addaw:.macro
#ifdef halten_add
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
mvs.w \1,d0
adda.l d0,\2
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// add.w ea,usp
//--------------------------------------------------------------------
addawa7:.macro
#ifdef halten_add
halt
#endif
mvs.w \1,d0
move.l usp,a1
add.l d0,a1
move.l a1,usp
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addawu:.macro
#ifdef halten_add
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
move.l a7,_a7_save
move.l usp,a7
move.l \1,d0
adda.l d0,\2
move.l a7,usp
move.l _a7_save,a7
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addawua7:.macro
addawu \1,\2
.endm;
//--------------------------------------------------------------------
// // adda.w d16(ay),ax
//--------------------------------------------------------------------
addawd16a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
adda.l d0,a1
mvs.w (a1),d0
move.l \2,a1
add.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d8(ay,dy),ax
//--------------------------------------------------------------------
addawd8a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
add.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w xxx.w,ax
//--------------------------------------------------------------------
addawxwax:.macro
#ifdef halten_add
halt
#endif
move.w \1,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w xxx.l,ax
//--------------------------------------------------------------------
addawxlax:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d16(pc),ax
//--------------------------------------------------------------------
addawd16pcax:.macro
#ifdef halten_add
halt
#endif
move.w \1,a1
adda.l a0,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d8(pc,dy),ax
//--------------------------------------------------------------------
addawd8pcax:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w #im,ax
//--------------------------------------------------------------------
addawim:.macro
#ifdef halten_add
halt
#endif
mvs.w \1,d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.l d8(ay,dy),ax
//--------------------------------------------------------------------
addald8a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.l d8(pc,dy),ax
//--------------------------------------------------------------------
addakd8pcax:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//*****************************************************************************************
// addx
//*****************************************************************************************
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
adddx:.macro
#ifdef halten_add
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
mvs.\3 \2,d0
mvs.\3 \1,d1
addx.l d0,d1
set_cc0
move.\3 d1,\1
ii_end
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
adddax:.macro
#ifdef halten_add
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
move.l \1,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d0
.endif
move.l \2,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d1
.endif
addx.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------

441
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//--------------------------------------------------------------------
// and
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// and.b #im,dx
//--------------------------------------------------------------------
andbir_macro:.macro
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
and.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea,dx
//--------------------------------------------------------------------
anddd:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
andddd:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and (ea)->dy,dx
//--------------------------------------------------------------------
anddda:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea->ay,(ay)+,dx
//--------------------------------------------------------------------
andddai:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea->ay,-(ay),dx
//--------------------------------------------------------------------
andddad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d16(ay),dx
//--------------------------------------------------------------------
andd16ad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d8(ay,dy),dx
//--------------------------------------------------------------------
andd8ad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and xxx.w,dx
//--------------------------------------------------------------------
andxwd:.macro
#ifdef halten_and
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and xxx.l,dx
//--------------------------------------------------------------------
andxld:.macro
#ifdef halten_and
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d16(pc),dx
//--------------------------------------------------------------------
andd16pcd:.macro
#ifdef halten_and
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d8(pc,dy),dx
//--------------------------------------------------------------------
andd8pcd:.macro
#ifdef halten_and
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// and dx,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // and dx,(ea)->dy
//--------------------------------------------------------------------
andeda:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,(ay)+
//--------------------------------------------------------------------
andedai:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,(ay)+
//--------------------------------------------------------------------
andedaid:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,-(ay)
//--------------------------------------------------------------------
andedad:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,-(ay)
//--------------------------------------------------------------------
andedadd:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,d16(ay)
//--------------------------------------------------------------------
ande16ad:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and.w dx,d8(ay,dy)
//--------------------------------------------------------------------
ande8ad:.macro
#ifdef halten_and
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,xxx.w
//--------------------------------------------------------------------
andxwe:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,xxx.l
//--------------------------------------------------------------------
andxle:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // anda.w ea,ax
//--------------------------------------------------------------------
andaw:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// and.w ea,usp
//--------------------------------------------------------------------
andawa7:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w usp?,ax
//--------------------------------------------------------------------
andawu:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w usp?,usp
//--------------------------------------------------------------------
andawua7:.macro
andawu \1,\2
.endm;
//--------------------------------------------------------------------
// // anda.w d16(ay),ax
//--------------------------------------------------------------------
andawd16a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d8(ay,dy),ax
//--------------------------------------------------------------------
andawd8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w xxx.w,ax
//--------------------------------------------------------------------
andawxwax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w xxx.l,ax
//--------------------------------------------------------------------
andawxlax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d16(pc),ax
//--------------------------------------------------------------------
andawd16pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d8(pc,dy),ax
//--------------------------------------------------------------------
andawd8pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w #im,ax
//--------------------------------------------------------------------
andawim:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.l d8(ay,dy),ax
//--------------------------------------------------------------------
andald8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.l d8(pc,dy),ax
//--------------------------------------------------------------------
andald8pcax:.macro
jmp ii_error
.endm;
//*****************************************************************************************
// spezial addx subx etc.
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
anddx:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
anddax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------

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//--------------------------------------------------------------------
// dbcc,trapcc
//--------------------------------------------------------------------
.text
ii_lset_dbcc:.macro
// dbra
ii_lset_opeau 51,c
ii_lset_opeau 52,c
ii_lset_opeau 53,c
ii_lset_opeau 54,c
ii_lset_opeau 55,c
ii_lset_opeau 56,c
ii_lset_opeau 57,c
ii_lset_opeau 58,c
ii_lset_opeau 59,c
ii_lset_opeau 5a,c
ii_lset_opeau 5b,c
ii_lset_opeau 5c,c
ii_lset_opeau 5d,c
ii_lset_opeau 5e,c
ii_lset_opeau 5f,c
.endm
ii_dbcc_func:.macro
ii_0x51c8:
dbra_macro d0_off+2(a7)
ii_0x51c9:
dbra_macro d1_off+2(a7)
ii_0x51ca:
dbra_macro d2
ii_0x51cb:
dbra_macro d3
ii_0x51cc:
dbra_macro d4
ii_0x51cd:
dbra_macro d5
ii_0x51ce:
dbra_macro d6
ii_0x51cf:
dbra_macro d7
//---------------------------------------------------------------------------------------------
// dbcc dx
//---------------------------------------------------------------------------------------------
ii_dbcc 2,hi
ii_dbcc 3,ls
ii_dbcc 4,cc
ii_dbcc 5,cs
ii_dbcc 6,ne
ii_dbcc 7,eq
ii_dbcc 8,vc
ii_dbcc 9,vs
ii_dbcc a,pl
ii_dbcc b,mi
ii_dbcc c,ge
ii_dbcc d,lt
ii_dbcc e,gt
ii_dbcc f,le
.endm
//---------------------------------------------------------------------------------------------
// dbra dx
//---------------------------------------------------------------------------------------------
dbra_macro:.macro
#ifdef halten_dbcc
halt
#endif
mvz.w \1,d1 // dx holen
subq.l #1,d1 // dx-1
bcc dbra\@ // bra if plus?
addq.l #2,a0 // offset <20>berspringen
move.w d1,\1 // dx sichern
ii_end
dbra\@:
move.w (a0),a1 // offset (wird auf long erweitert)
add.l a1,a0 // dazuadieren
move.w d1,\1 // dx sichern
ii_end
.endm
//---------------------------------------------------------------------------------------------
// dbcc dx
//---------------------------------------------------------------------------------------------
dbcc_macro:.macro
#ifdef halten_dbcc
halt
#endif
b\2 dbncc\@
mvz.w \1,d1 // dx holen
subq.l #1,d1 // dx-1
bcc dbcc\@ // bra if plus?
dbncc\@:
addq.l #2,a0 // offset <20>berspringen
move.w d1,\1 // dx sichern
ii_end
dbcc\@:
move.w (a0),a1 // offset (wird auf long erweitert)
add.l a1,a0 // dazuadieren
move.w d1,\1 // dx sichern
ii_end
.endm
//db
ii_dbcc:.macro
ii_0x5\1c8:
dbcc_macro d0_off+2(a7),\2
ii_0x5\1c9:
dbcc_macro d1_off+2(a7),\2
ii_0x5\1ca:
dbcc_macro d2,\2
ii_0x5\1cb:
dbcc_macro d3,\2
ii_0x5\1cc:
dbcc_macro d4,\2
ii_0x5\1cd:
dbcc_macro d5,\2
ii_0x5\1ce:
dbcc_macro d6,\2
ii_0x5\1cf:
dbcc_macro d7,\2
.endm

181
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//--------------------------------------------------------------------
// extension word format missing
//--------------------------------------------------------------------
.text
ii_ewf_lset:.macro
// pea
ii_lset_opeag 48,7
ii_lset 0x487b
// jmp
ii_lset_opeag 4e,f
ii_lset 0x4efb
// jsr
ii_lset_opeag 4e,b
ii_lset 0x4ebb
// tas
ii_lset_opeag 4a,f
ii_lset 0x4ebb
// tst.b
ii_lset_opeag 4a,3
ii_lset 0x4ebb
// tst.w
ii_lset_opeag 4a,7
ii_lset 0x4ebb
// tst.l
ii_lset_opeag 4a,b
ii_lset 0x4ebb
// clr.b
ii_lset_opeag 42,3
ii_lset 0x423b
// clr.w
ii_lset_opeag 42,7
ii_lset 0x423b
// clr.l
ii_lset_opeag 42,b
ii_lset 0x423b
.endm
//---------------------------------------------------------------------------------------------
ii_ewf_func:.macro
ewf_func_macro pea,487
ewf_func_macro jmp,4ef
ewf_func_macro jsr,4eb
ewf_func_macro tas,4af
ewf_func_macro tstb,4a3
ewf_func_macro tstw,4a7
ewf_func_macro tstl,4ab
ewf_func_macro clrb,423
ewf_func_macro clrw,427
ewf_func_macro clrl,42b
.endm
//---------------------------------------------------------------------------------------------
pea_macro:.macro
jsr ewf
move.l (a1),d0
move.l usp,a1
move.l d0,-(a1)
move.l a1,usp
ii_end
.endm
jmp_macro:.macro
jsr ewf
move.l a1,a0
ii_end
.endm
jsr_macro:.macro
jsr ewf
move.l a1,d0
move.l usp,a1
move.l a0,-(a1)
move.l a1,usp
move.l d0,a0
ii_end
.endm
tas_macro:.macro
jsr ewf
tas (a1)
set_cc0
ii_end
.endm
tstb_macro:.macro
jsr ewf
tst.b (a1)
set_cc0
ii_end
.endm
tstw_macro:.macro
jsr ewf
tst.w (a1)
set_cc0
ii_end
.endm
tstl_macro:.macro
jsr ewf
tst.l (a1)
set_cc0
ii_end
.endm
clrb_macro:.macro
jsr ewf
clr.b (a1)
set_cc0
ii_end
.endm
clrw_macro:.macro
jsr ewf
clr.w (a1)
set_cc0
ii_end
.endm
clrl_macro:.macro
jsr ewf
clr.l (a1)
set_cc0
ii_end
.endm
//--------------------------------------------------------------------
ewf_func_macro:.macro //1=art 2=code
ii_0x\20:
#ifdef halten_ewf
halt
#endif
move.l a0_off(a7),a1
\1_macro
ii_0x\21:
#ifdef halten_ewf
halt
#endif
move.l a1_off(a7),a1
\1_macro
ii_0x\22:
#ifdef halten_ewf
halt
#endif
move.l a2,a1
\1_macro
ii_0x\23:
#ifdef halten_ewf
halt
#endif
move.l a3,a1
\1_macro
ii_0x\24:
#ifdef halten_ewf
halt
#endif
move.l a4,a1
\1_macro
ii_0x\25:
#ifdef halten_ewf
halt
#endif
move.l a5,a1
\1_macro
ii_0x\26:
#ifdef halten_ewf
halt
#endif
move.l a6,a1
\1_macro
ii_0x\27:
#ifdef halten_ewf
halt
#endif
move.l usp,a1
\1_macro
ii_0x\2b:
#ifdef halten_ewf
halt
#endif
move.l a0,a1
\1_macro
.endm

120
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//--------------------------------------------------------------------
// exg
//--------------------------------------------------------------------
.text
ii_exg_lset:.macro
/* ii_lset_dxu c,40 //dx,d0
ii_lset_dxu c,41 //dx,d1
ii_lset_dxu c,42 //dx,d2
ii_lset_dxu c,43 //dx,d3
ii_lset_dxu c,44 //dx,d4
ii_lset_dxu c,45 //dx,d5
ii_lset_dxu c,46 //dx,d6
ii_lset_dxu c,47 //dx,d7
ii_lset_dxu c,48 //ax,a0
ii_lset_dxu c,49 //ax,a1
ii_lset_dxu c,4a //ax,a2
ii_lset_dxu c,4b //ax,a3
ii_lset_dxu c,4c //ax,a4
ii_lset_dxu c,4d //ax,a5
ii_lset_dxu c,4e //ax,a6
ii_lset_dxu c,4f //ax,a7 */ -->setting by "and"
ii_lset_dxu c,88 //dx,a0
ii_lset_dxu c,89 //dx,a1
ii_lset_dxu c,8a //dx,a2
ii_lset_dxu c,8b //dx,a3
ii_lset_dxu c,8c //dx,a4
ii_lset_dxu c,8d //dx,a5
ii_lset_dxu c,8e //dx,a6
ii_lset_dxu c,8f //dx,a7
.endm
//---------------------------------------------------------------------------------------------
ii_exg_func:.macro
// exg dx,dy
ii_exg_dx_dx 14,d0_off(a7)
ii_exg_dx_dx 34,d1_off(a7)
ii_exg_dx_dx 54,d2
ii_exg_dx_dx 74,d3
ii_exg_dx_dx 94,d4
ii_exg_dx_dx b4,d5
ii_exg_dx_dx d4,d6
ii_exg_dx_dx f4,d7
// exg ax,ay
ii_exg_to_ax 14,a0_off(a7)
ii_exg_to_ax 34,a1_off(a7)
ii_exg_to_ax 54,a2
ii_exg_to_ax 74,a3
ii_exg_to_ax 94,a4
ii_exg_to_ax b4,a5
ii_exg_to_ax d4,a6
ii_exg_to_ax f4,usp
// exg dx,ay
ii_exg_to_ax 18,d0_off(a7)
ii_exg_to_ax 38,d1_off(a7)
ii_exg_to_ax 58,d2
ii_exg_to_ax 78,d3
ii_exg_to_ax 98,d4
ii_exg_to_ax b8,d5
ii_exg_to_ax d8,d6
ii_exg_to_ax f8,d7
.endm
//---------------------------------------------------------------------------------------------
exg_macro:.macro
#ifdef halten_exg
halt
#endif
move.l \1,a1
.ifc \2,usp
move.l a1,d0
move.l \2,a1
move.l a1,\1
move.l d0,a1
.else
.ifc \1,usp
move.l a1,d0
move.l \2,a1
move.l a1,\1
move.l d0,a1
.else
move.l \2,\1
.endif
.endif
move.l a1,\2
ii_end
.endm
ii_exg_dx_dx:.macro
ii_0xc\10:
exg_macro \2,d0_off(a7)
ii_0xc\11:
exg_macro \2,d1_off(a7)
ii_0xc\12:
exg_macro \2,d2
ii_0xc\13:
exg_macro \2,d3
ii_0xc\14:
exg_macro \2,d4
ii_0xc\15:
exg_macro \2,d5
ii_0xc\16:
exg_macro \2,d6
ii_0xc\17:
exg_macro \2,d7
.endm
ii_exg_to_ax:.macro
ii_0xc\18:
exg_macro \2,a0_off(a7)
ii_0xc\19:
exg_macro \2,a1_off(a7)
ii_0xc\1a:
exg_macro \2,a2
ii_0xc\1b:
exg_macro \2,a3
ii_0xc\1c:
exg_macro \2,a4
ii_0xc\1d:
exg_macro \2,a5
ii_0xc\1e:
exg_macro \2,a6
ii_0xc\1f:
exg_macro \2,usp
.endm

945
BaS_GNU/BaS_codewarrior/firebeeV1/sources/ii_func.h Normal file
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@@ -0,0 +1,945 @@
//--------------------------------------------------------------------
// functionen macros
//--------------------------------------------------------------------
ii_lset_func:.macro
/******************************************************/
// byt
/******************************************************/
// func.b dy,dx
ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,01
ii_lset_dx \1,02
ii_lset_dx \1,03
ii_lset_dx \1,04
ii_lset_dx \1,05
ii_lset_dx \1,06
ii_lset_dx \1,07
// func.b ax,dx
ii_lset_dxu \1,08
ii_lset_dxu \1,09
ii_lset_dxu \1,0a
ii_lset_dxu \1,0b
ii_lset_dxu \1,0c
ii_lset_dxu \1,0d
ii_lset_dxu \1,0e
ii_lset_dxu \1,0f
// func.b (ax),dx
ii_lset_dx \1,10
ii_lset_dx \1,11
ii_lset_dx \1,12
ii_lset_dx \1,13
ii_lset_dx \1,14
ii_lset_dx \1,15
ii_lset_dx \1,16
ii_lset_dx \1,17
// func.b (ax)+,dx
ii_lset_dx \1,18
ii_lset_dx \1,19
ii_lset_dx \1,1a
ii_lset_dx \1,1b
ii_lset_dx \1,1c
ii_lset_dx \1,1d
ii_lset_dx \1,1e
ii_lset_dx \1,1f
// func.b -(ax),dx
ii_lset_dx \1,20
ii_lset_dx \1,21
ii_lset_dx \1,22
ii_lset_dx \1,23
ii_lset_dx \1,24
ii_lset_dx \1,25
ii_lset_dx \1,26
ii_lset_dx \1,27
// func.b d16(ax),dx
ii_lset_dx \1,28
ii_lset_dx \1,29
ii_lset_dx \1,2a
ii_lset_dx \1,2b
ii_lset_dx \1,2c
ii_lset_dx \1,2d
ii_lset_dx \1,2e
ii_lset_dx \1,2f
// func.b dd8(ax,dy),dx
ii_lset_dx \1,30
ii_lset_dx \1,31
ii_lset_dx \1,32
ii_lset_dx \1,33
ii_lset_dx \1,34
ii_lset_dx \1,35
ii_lset_dx \1,36
ii_lset_dx \1,37
// func.b xxx.w,dx
ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b xxx.l,dx
ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b d16(pc),dx
ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b d8(pc,dy),dx
ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b #im,dx
ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// word
/******************************************************/
// func.w dy,dx
ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,41
ii_lset_dx \1,42
ii_lset_dx \1,43
ii_lset_dx \1,44
ii_lset_dx \1,45
ii_lset_dx \1,46
ii_lset_dx \1,47
// func.w ax,dx
ii_lset_dx \1,48
ii_lset_dx \1,49
ii_lset_dx \1,4a
ii_lset_dx \1,4b
ii_lset_dx \1,4c
ii_lset_dx \1,4d
ii_lset_dx \1,4e
ii_lset_dx \1,4f
// func.w (ax),dx
ii_lset_dx \1,50
ii_lset_dx \1,51
ii_lset_dx \1,52
ii_lset_dx \1,53
ii_lset_dx \1,54
ii_lset_dx \1,55
ii_lset_dx \1,56
ii_lset_dx \1,57
// func.w (ax)+,dx
ii_lset_dx \1,58
ii_lset_dx \1,59
ii_lset_dx \1,5a
ii_lset_dx \1,5b
ii_lset_dx \1,5c
ii_lset_dx \1,5d
ii_lset_dx \1,5e
ii_lset_dx \1,5f
// func.w -(ax),dx
ii_lset_dx \1,60
ii_lset_dx \1,61
ii_lset_dx \1,62
ii_lset_dx \1,63
ii_lset_dx \1,64
ii_lset_dx \1,65
ii_lset_dx \1,66
ii_lset_dx \1,67
// func.w d16(ax),dx
ii_lset_dx \1,68
ii_lset_dx \1,69
ii_lset_dx \1,6a
ii_lset_dx \1,6b
ii_lset_dx \1,6c
ii_lset_dx \1,6d
ii_lset_dx \1,6e
ii_lset_dx \1,6f
// func.w d8(ax,dy),dx
ii_lset_dx \1,70
ii_lset_dx \1,71
ii_lset_dx \1,72
ii_lset_dx \1,73
ii_lset_dx \1,74
ii_lset_dx \1,75
ii_lset_dx \1,76
ii_lset_dx \1,77
// func.w xxx.w,dx
ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w xxx.l,dx
ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w d16(pc),dx
ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w d8(pc,dy),dx
ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w #im,dx
ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// long
/******************************************************/
// func.l ax,dx -> -(ay),-(ax)
ii_lset_dxu \1,c8
ii_lset_dxu \1,c9
ii_lset_dxu \1,ca
ii_lset_dxu \1,cb
ii_lset_dxu \1,cc
ii_lset_dxu \1,cd
ii_lset_dxu \1,ce
ii_lset_dxu \1,cf
// func.w d8(ax,dy),dx
ii_lset_dx \1,b0
ii_lset_dx \1,b1
ii_lset_dx \1,b2
ii_lset_dx \1,b3
ii_lset_dx \1,b4
ii_lset_dx \1,b5
ii_lset_dx \1,b6
ii_lset_dx \1,b7
// func.l d8(pc,dy),dx
ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// adress register
/******************************************************/
//func.w dy,ax
ii_lset_dxg \1,c0
ii_lset_dxg \1,c1
ii_lset_dxg \1,c2
ii_lset_dxg \1,c3
ii_lset_dxg \1,c4
ii_lset_dxg \1,c5
ii_lset_dxg \1,c6
ii_lset_dxg \1,c7
//func.w ay,ax
ii_lset_dxg \1,c8
ii_lset_dxg \1,c9
ii_lset_dxg \1,ca
ii_lset_dxg \1,cb
ii_lset_dxg \1,cc
ii_lset_dxg \1,cd
ii_lset_dxg \1,ce
ii_lset_dxg \1,cf
//func.w (ay),ax
ii_lset_dxg \1,d0
ii_lset_dxg \1,d1
ii_lset_dxg \1,d2
ii_lset_dxg \1,d3
ii_lset_dxg \1,d4
ii_lset_dxg \1,d5
ii_lset_dxg \1,d6
ii_lset_dxg \1,d7
//func.w (ay)+,ax
ii_lset_dxg \1,d8
ii_lset_dxg \1,d9
ii_lset_dxg \1,da
ii_lset_dxg \1,db
ii_lset_dxg \1,dc
ii_lset_dxg \1,dd
ii_lset_dxg \1,de
ii_lset_dxg \1,df
//func.w -(ay),ax
ii_lset_dxg \1,e0
ii_lset_dxg \1,e1
ii_lset_dxg \1,e2
ii_lset_dxg \1,e3
ii_lset_dxg \1,e4
ii_lset_dxg \1,e5
ii_lset_dxg \1,e6
ii_lset_dxg \1,e7
//func.w d16(ay),ax
ii_lset_dxg \1,e8
ii_lset_dxg \1,e9
ii_lset_dxg \1,ea
ii_lset_dxg \1,eb
ii_lset_dxg \1,ec
ii_lset_dxg \1,ed
ii_lset_dxg \1,ee
ii_lset_dxg \1,ef
//func.w d8(ay,dy),ax
ii_lset_dxg \1,f0
ii_lset_dxg \1,f1
ii_lset_dxg \1,f2
ii_lset_dxg \1,f3
ii_lset_dxg \1,f4
ii_lset_dxg \1,f5
ii_lset_dxg \1,f6
ii_lset_dxg \1,f7
// func.w xxx.w,ax
ii_lset_dxg \1,f8
// func.w xxx.l,ax
ii_lset_dxg \1,f9
// func.w d16(pc),ax
ii_lset_dxg \1,fa
// func.w d8(pc,dy),ax
ii_lset_dxg \1,fb
// func.w #im,ax
ii_lset_dxg \1,fc
//--------------------------------------------------------------------
// ende
.endm;
/*****************************************************************************************/
ii_func:.macro
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.b ds,dx
//--------------------------------------------------------------------
funcbeadx \1,00,\2dd,d0_off+3(a7)
funcbeadx \1,01,\2dd,d1_off+3(a7)
funcbeadx \1,02,\2dd,d2
funcbeadx \1,03,\2dd,d3
funcbeadx \1,04,\2dd,d4
funcbeadx \1,05,\2dd,d5
funcbeadx \1,06,\2dd,d6
funcbeadx \1,07,\2dd,d7
//--------------------------------------------------------------------
// func.b (ax),dx
//--------------------------------------------------------------------
funcbeadx \1,10,\2dda,a0_off(a7)
funcbeadx \1,11,\2dda,a1_off(a7)
funcbeadx \1,12,\2dd,(a2)
funcbeadx \1,13,\2dd,(a3)
funcbeadx \1,14,\2dd,(a4)
funcbeadx \1,15,\2dd,(a5)
funcbeadx \1,16,\2dd,(a6)
funcbeadx \1,17,\2dda,usp
//--------------------------------------------------------------------
// func.b (ax)+,dx
//--------------------------------------------------------------------
funcbeadx \1,18,\2ddai,a0_off(a7)
funcbeadx \1,19,\2ddai,a1_off(a7)
funcbeadx \1,1a,\2dd,(a2)+
funcbeadx \1,1b,\2dd,(a3)+
funcbeadx \1,1c,\2dd,(a4)+
funcbeadx \1,1d,\2dd,(a5)+
funcbeadx \1,1e,\2dd,(a6)+
funcbeadx \1,1f,\2ddai,usp
//--------------------------------------------------------------------
// func.b -(ax),dx
//--------------------------------------------------------------------
funcbeadx \1,20,\2ddad,a0_off(a7)
funcbeadx \1,21,\2ddad,a1_off(a7)
funcbeadx \1,22,\2dd,-(a2)
funcbeadx \1,23,\2dd,-(a3)
funcbeadx \1,24,\2dd,-(a4)
funcbeadx \1,25,\2dd,-(a5)
funcbeadx \1,26,\2dd,-(a6)
funcbeadx \1,27,\2ddad,usp
//--------------------------------------------------------------------
// func.b d16(ax),dx
//--------------------------------------------------------------------
funcbeadx \1,28,\2d16ad,a0_off(a7)
funcbeadx \1,29,\2d16ad,a1_off(a7)
funcbeadx \1,2a,\2d16ad,a2
funcbeadx \1,2b,\2d16ad,a3
funcbeadx \1,2c,\2d16ad,a4
funcbeadx \1,2d,\2d16ad,a5
funcbeadx \1,2e,\2d16ad,a6
funcbeadx \1,2f,\2d16ad,usp
//--------------------------------------------------------------------
// func.b d8(ax,dy),dx
//--------------------------------------------------------------------
funcbeadx \1,30,\2d8ad,a0_off(a7)
funcbeadx \1,31,\2d8ad,a1_off(a7)
funcbeadx \1,32,\2d8ad,a2
funcbeadx \1,33,\2d8ad,a3
funcbeadx \1,34,\2d8ad,a4
funcbeadx \1,35,\2d8ad,a5
funcbeadx \1,36,\2d8ad,a6
funcbeadx \1,37,\2d8ad,usp
//--------------------------------------------------------------------
// func.b xxx.w,dx
//--------------------------------------------------------------------
funcbeadx \1,38,\2xwd,(a0)+
//--------------------------------------------------------------------
// func.b xxx.w,dx
//--------------------------------------------------------------------
funcbeadx \1,39,\2xld,(a0)+
//--------------------------------------------------------------------
// func.b d16(pc),dx
//--------------------------------------------------------------------
funcbeadx \1,3a,\2d16pcd,(a0)+
//--------------------------------------------------------------------
// func.b d8(pc,dy),dx
//--------------------------------------------------------------------
funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.b #im,dx
//--------------------------------------------------------------------
funcbeadx \1,3c,\2bir_macro,(a0)+
//--------------------------------------------------------------------
// func.b dy,ea
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.b dx,dd -> addx subx etc. src und dest vertauscht!
//--------------------------------------------------------------------
funcbdxea \1,00,\2dx,d0_off+3(a7)
funcbdxea \1,01,\2dx,d1_off+3(a7)
funcbdxea \1,02,\2dx,d2
funcbdxea \1,03,\2dx,d3
funcbdxea \1,04,\2dx,d4
funcbdxea \1,05,\2dx,d5
funcbdxea \1,06,\2dx,d6
funcbdxea \1,07,\2dx,d7
//--------------------------------------------------------------------
// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht!
//--------------------------------------------------------------------
funcaxay \1,08,\2dax,a0_off(a7),b
funcaxay \1,09,\2dax,a1_off(a7).b
funcaxay \1,0a,\2dax,a2,b
funcaxay \1,0b,\2dax,a3,b
funcaxay \1,0c,\2dax,a4,b
funcaxay \1,0d,\2dax,a5,b
funcaxay \1,0e,\2dax,a6,b
funcaxay \1,0f,\2dax,usp,b
//--------------------------------------------------------------------
// func.b dy,(ax)
//--------------------------------------------------------------------
funcbdxea \1,10,\2eda,a0_off(a7)
funcbdxea \1,11,\2eda,a1_off(a7)
funcbdxea \1,12,\2dd,(a2)
funcbdxea \1,13,\2dd,(a3)
funcbdxea \1,14,\2dd,(a4)
funcbdxea \1,15,\2dd,(a5)
funcbdxea \1,16,\2dd,(a6)
funcbdxea \1,17,\2eda,usp
//--------------------------------------------------------------------
// func.b dy,(ax)+
//--------------------------------------------------------------------
funcbdxea \1,18,\2edai,a0_off(a7)
funcbdxea \1,19,\2edai,a1_off(a7)
funcbdxea \1,1a,\2edaid,(a2)
funcbdxea \1,1b,\2edaid,(a3)
funcbdxea \1,1c,\2edaid,(a4)
funcbdxea \1,1d,\2edaid,(a5)
funcbdxea \1,1e,\2edaid,(a6)
funcbdxea \1,1f,\2edai,usp
//--------------------------------------------------------------------
// func.b dy,-(ax)
//--------------------------------------------------------------------
funcbdxea \1,20,\2edad,a0_off(a7)
funcbdxea \1,21,\2edad,a1_off(a7)
funcbdxea \1,22,\2edadd,(a2)
funcbdxea \1,23,\2edadd,(a3)
funcbdxea \1,24,\2edadd,(a4)
funcbdxea \1,25,\2edadd,(a5)
funcbdxea \1,26,\2edadd,(a6)
funcbdxea \1,27,\2edad,usp
//--------------------------------------------------------------------
// func.b dy,d16(ax)
//--------------------------------------------------------------------
funcbdxea \1,28,\2e16ad,a0_off(a7)
funcbdxea \1,29,\2e16ad,a1_off(a7)
funcbdxea \1,2a,\2e16ad,a2
funcbdxea \1,2b,\2e16ad,a3
funcbdxea \1,2c,\2e16ad,a4
funcbdxea \1,2d,\2e16ad,a5
funcbdxea \1,2e,\2e16ad,a6
funcbdxea \1,2f,\2e16ad,usp
//--------------------------------------------------------------------
// func.b dy,d8(ax,dy)
//--------------------------------------------------------------------
funcbdxea \1,30,\2e8ad,a0_off(a7)
funcbdxea \1,31,\2e8ad,a1_off(a7)
funcbdxea \1,32,\2e8ad,a2
funcbdxea \1,33,\2e8ad,a3
funcbdxea \1,34,\2e8ad,a4
funcbdxea \1,35,\2e8ad,a5
funcbdxea \1,36,\2e8ad,a6
funcbdxea \1,37,\2e8ad,usp
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,38,\2xwe,(a0)+
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,39,\2xld,(a0)+
/*****************************************************************************************/
// word
/*****************************************************************************************/
// func.w ds,dx
//--------------------------------------------------------------------
funcweadx \1,40,\2dd,d0_off+2(a7)
funcweadx \1,41,\2dd,d1_off+2(a7)
funcweadx \1,42,\2dd,d2
funcweadx \1,43,\2dd,d3
funcweadx \1,44,\2dd,d4
funcweadx \1,45,\2dd,d5
funcweadx \1,46,\2dd,d6
funcweadx \1,47,\2dd,d7
//--------------------------------------------------------------------
// func.w ax,dx
//--------------------------------------------------------------------
funcweadx \1,48,\2dd,a0_off+2(a7)
funcweadx \1,49,\2dd,a1_off+2(a7)
funcweadx \1,4a,\2dd,a2
funcweadx \1,4b,\2dd,a3
funcweadx \1,4c,\2dd,a4
funcweadx \1,4d,\2dd,a5
funcweadx \1,4e,\2dd,a6
funcweadx \1,4f,\2ddd,usp
//--------------------------------------------------------------------
// func.w (ax),dx
//--------------------------------------------------------------------
funcweadx \1,50,\2dda,a0_off(a7)
funcweadx \1,51,\2dda,a1_off(a7)
funcweadx \1,52,\2dd,(a2)
funcweadx \1,53,\2dd,(a3)
funcweadx \1,54,\2dd,(a4)
funcweadx \1,55,\2dd,(a5)
funcweadx \1,56,\2dd,(a6)
funcweadx \1,57,\2dda,usp
//--------------------------------------------------------------------
// func.w (ax)+,dx
//--------------------------------------------------------------------
funcweadx \1,58,\2ddai,a0_off(a7)
funcweadx \1,59,\2ddai,a1_off(a7)
funcweadx \1,5a,\2dd,(a2)+
funcweadx \1,5b,\2dd,(a3)+
funcweadx \1,5c,\2dd,(a4)+
funcweadx \1,5d,\2dd,(a5)+
funcweadx \1,5e,\2dd,(a6)+
funcweadx \1,5f,\2ddai,usp
//--------------------------------------------------------------------
// func.w -(ax),dx
//--------------------------------------------------------------------
funcweadx \1,60,\2ddad,a0_off(a7)
funcweadx \1,61,\2ddad,a1_off(a7)
funcweadx \1,62,\2dd,-(a2)
funcweadx \1,63,\2dd,-(a3)
funcweadx \1,64,\2dd,-(a4)
funcweadx \1,65,\2dd,-(a5)
funcweadx \1,66,\2dd,-(a6)
funcweadx \1,67,\2ddad,usp
//--------------------------------------------------------------------
// func.w d16(ax),dx
//--------------------------------------------------------------------
funcweadx \1,68,\2d16ad,a0_off(a7)
funcweadx \1,69,\2d16ad,a1_off(a7)
funcweadx \1,6a,\2d16ad,a2
funcweadx \1,6b,\2d16ad,a3
funcweadx \1,6c,\2d16ad,a4
funcweadx \1,6d,\2d16ad,a5
funcweadx \1,6e,\2d16ad,a6
funcweadx \1,6f,\2d16ad,usp
//--------------------------------------------------------------------
// func.w d8(ax,dy),dx
//--------------------------------------------------------------------
funcweadx \1,70,\2d8ad,a0_off(a7)
funcweadx \1,71,\2d8ad,a1_off(a7)
funcweadx \1,72,\2d8ad,a2
funcweadx \1,73,\2d8ad,a3
funcweadx \1,74,\2d8ad,a4
funcweadx \1,75,\2d8ad,a5
funcweadx \1,76,\2d8ad,a6
funcweadx \1,77,\2d8ad,usp
//--------------------------------------------------------------------
// func.w xxx.w,dx
//--------------------------------------------------------------------
funcweadx \1,78,\2xwd,(a0)+
//--------------------------------------------------------------------
// func.w xxx.w,dx
//--------------------------------------------------------------------
funcweadx \1,79,\2xld,(a0)+
//--------------------------------------------------------------------
// func.w d16(pc),dx
//--------------------------------------------------------------------
funcweadx \1,7a,\2d16pcd,(a0)+
//--------------------------------------------------------------------
// func.w d8(pc,dy),dx
//--------------------------------------------------------------------
funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.w #im,dx
//--------------------------------------------------------------------
funcweadx \1,7c,\2dd,(a0)+
//--------------------------------------------------------------------
// func.w dy,ea
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.w dx,dd -> addx subx etc.
//--------------------------------------------------------------------
.ifnc \2,and //platz f<>r exg
funcwdxea \1,40,\2dx,d0_off+2(a7)
funcwdxea \1,41,\2dx,d1_off+2(a7)
funcwdxea \1,42,\2dx,d2
funcwdxea \1,43,\2dx,d3
funcwdxea \1,44,\2dx,d4
funcwdxea \1,45,\2dx,d5
funcwdxea \1,46,\2dx,d6
funcwdxea \1,47,\2dx,d7
//--------------------------------------------------------------------
// func.w -(ax),-(ay) -> addx,subx
//--------------------------------------------------------------------
funcaxay \1,48,\2dax,a0_off(a7),w
funcaxay \1,49,\2dax,a1_off(a7).w
funcaxay \1,4a,\2dax,a2,w
funcaxay \1,4b,\2dax,a3,w
funcaxay \1,4c,\2dax,a4,w
funcaxay \1,4d,\2dax,a5,w
funcaxay \1,4e,\2dax,a6,w
funcaxay \1,4f,\2dax,usp,w
.endif
//--------------------------------------------------------------------
// func.w dy,(ax)
//--------------------------------------------------------------------
funcwdxea \1,50,\2eda,a0_off(a7)
funcwdxea \1,51,\2eda,a1_off(a7)
funcwdxea \1,52,\2dd,(a2)
funcwdxea \1,53,\2dd,(a3)
funcwdxea \1,54,\2dd,(a4)
funcwdxea \1,55,\2dd,(a5)
funcwdxea \1,56,\2dd,(a6)
funcwdxea \1,57,\2eda,usp
//--------------------------------------------------------------------
// func.w dy,(ax)+
//--------------------------------------------------------------------
funcwdxea \1,58,\2edai,a0_off(a7)
funcwdxea \1,59,\2edai,a1_off(a7)
funcwdxea \1,5a,\2edaid,(a2)
funcwdxea \1,5b,\2edaid,(a3)
funcwdxea \1,5c,\2edaid,(a4)
funcwdxea \1,5d,\2edaid,(a5)
funcwdxea \1,5e,\2edaid,(a6)
funcwdxea \1,5f,\2edai,usp
//--------------------------------------------------------------------
// func.w dy,-(ax)
//--------------------------------------------------------------------
funcwdxea \1,60,\2edad,a0_off(a7)
funcwdxea \1,61,\2edad,a1_off(a7)
funcwdxea \1,62,\2edadd,(a2)
funcwdxea \1,63,\2edadd,(a3)
funcwdxea \1,64,\2edadd,(a4)
funcwdxea \1,65,\2edadd,(a5)
funcwdxea \1,66,\2edadd,(a6)
funcwdxea \1,67,\2edad,usp
//--------------------------------------------------------------------
// func.w dy,d16(ax)
//--------------------------------------------------------------------
funcwdxea \1,68,\2e16ad,a0_off(a7)
funcwdxea \1,69,\2e16ad,a1_off(a7)
funcwdxea \1,6a,\2e16ad,a2
funcwdxea \1,6b,\2e16ad,a3
funcwdxea \1,6c,\2e16ad,a4
funcwdxea \1,6d,\2e16ad,a5
funcwdxea \1,6e,\2e16ad,a6
funcwdxea \1,6f,\2e16ad,usp
//--------------------------------------------------------------------
// func.w dy,d8(ax,dy)
//--------------------------------------------------------------------
funcwdxea \1,70,\2e8ad,a0_off(a7)
funcwdxea \1,71,\2e8ad,a1_off(a7)
funcwdxea \1,72,\2e8ad,a2
funcwdxea \1,73,\2e8ad,a3
funcwdxea \1,74,\2e8ad,a4
funcwdxea \1,75,\2e8ad,a5
funcwdxea \1,76,\2e8ad,a6
funcwdxea \1,77,\2e8ad,usp
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,78,\2xwe,(a0)+
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,79,\2xld,(a0)+
/*****************************************************************************************/
// long
/*****************************************************************************************/
//--------------------------------------------------------------------
// func.l -(ax),-(ay)
//--------------------------------------------------------------------
funcaxay \1,c8,\2dax,a0_off(a7),l
funcaxay \1,c9,\2dax,a1_off(a7).l
funcaxay \1,ca,\2dax,a2,l
funcaxay \1,cb,\2dax,a3,l
funcaxay \1,cc,\2dax,a4,l
funcaxay \1,cd,\2dax,a5,l
funcaxay \1,ce,\2dax,a6,l
funcaxay \1,cf,\2dax,usp,l
//--------------------------------------------------------------------
// func.l d8(ax,dy),dx
//--------------------------------------------------------------------
funcleadx \1,b0,\2d8ad,a0_off(a7)
funcleadx \1,b1,\2d8ad,a1_off(a7)
funcleadx \1,b2,\2d8ad,a2
funcleadx \1,b3,\2d8ad,a3
funcleadx \1,b4,\2d8ad,a4
funcleadx \1,b5,\2d8ad,a5
funcleadx \1,b6,\2d8ad,a6
funcleadx \1,b7,\2d8ad,usp
//--------------------------------------------------------------------
// func.l d8(pc,dy),dx
//--------------------------------------------------------------------
funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.l dy,d8(ax,dy)
//--------------------------------------------------------------------
funcldxea \1,b0,\2e8ad,a0_off(a7)
funcldxea \1,b1,\2e8ad,a1_off(a7)
funcldxea \1,b2,\2e8ad,a2
funcldxea \1,b3,\2e8ad,a3
funcldxea \1,b4,\2e8ad,a4
funcldxea \1,b5,\2e8ad,a5
funcldxea \1,b6,\2e8ad,a6
funcldxea \1,b7,\2e8ad,usp
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// func.w ea,ax
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// func.w dx,ax
//--------------------------------------------------------------------
funcweaax \1,c0,\2aw,d0
funcweaax \1,c1,\2aw,d1
funcweaax \1,c2,\2aw,d2
funcweaax \1,c3,\2aw,d3
funcweaax \1,c4,\2aw,d4
funcweaax \1,c5,\2aw,d5
funcweaax \1,c6,\2aw,d6
funcweaax \1,c7,\2aw,d7
//--------------------------------------------------------------------
// func.w ay,ax
//--------------------------------------------------------------------
funcweaax \1,c8,\2aw,a0
funcweaax \1,c9,\2aw,a1
funcweaax \1,ca,\2aw,a2
funcweaax \1,cb,\2aw,a3
funcweaax \1,cc,\2aw,a4
funcweaax \1,cd,\2aw,a5
funcweaax \1,ce,\2aw,a6
funcweaax \1,cf,\2awu,a7
//--------------------------------------------------------------------
// func.w (ay),ax
//--------------------------------------------------------------------
funcweaax \1,d0,\2aw,(a0)
funcweaax \1,d1,\2aw,(a1)
funcweaax \1,d2,\2aw,(a2)
funcweaax \1,d3,\2aw,(a3)
funcweaax \1,d4,\2aw,(a4)
funcweaax \1,d5,\2aw,(a5)
funcweaax \1,d6,\2aw,(a6)
funcweaax \1,d7,\2awu,(a7)
//--------------------------------------------------------------------
// func.w (ay)+,ax
//--------------------------------------------------------------------
funcweaax \1,d8,\2aw,(a0)+
funcweaax \1,d9,\2aw,(a1)+
funcweaax \1,da,\2aw,(a2)+
funcweaax \1,db,\2aw,(a3)+
funcweaax \1,dc,\2aw,(a4)+
funcweaax \1,dd,\2aw,(a5)+
funcweaax \1,de,\2aw,(a6)+
funcweaax \1,df,\2awu,(a7)+
//--------------------------------------------------------------------
// func.w -(ay),ax
//--------------------------------------------------------------------
funcweaax \1,e0,\2aw,-(a0)
funcweaax \1,e1,\2aw,-(a1)
funcweaax \1,e2,\2aw,-(a2)
funcweaax \1,e3,\2aw,-(a3)
funcweaax \1,e4,\2aw,-(a4)
funcweaax \1,e5,\2aw,-(a5)
funcweaax \1,e6,\2aw,-(a6)
funcweaax \1,e7,\2awu,-(a7)
//--------------------------------------------------------------------
// func.w d16(ay),ax
//--------------------------------------------------------------------
funcweaaxn \1,e8,\2awd16a,a0_off(a7)
funcweaaxn \1,e9,\2awd16a,a1_off(a7)
funcweaaxn \1,ea,\2awd16a,a2
funcweaaxn \1,eb,\2awd16a,a3
funcweaaxn \1,ec,\2awd16a,a4
funcweaaxn \1,ed,\2awd16a,a5
funcweaaxn \1,ee,\2awd16a,a6
funcweaaxn \1,ef,\2awd16a,usp
//--------------------------------------------------------------------
// func.w d8(ay,dy),ax
//--------------------------------------------------------------------
funcweaaxn \1,f0,\2awd8a,a0_off(a7)
funcweaaxn \1,f1,\2awd8a,a1_off(a7)
funcweaaxn \1,f2,\2awd8a,a2
funcweaaxn \1,f3,\2awd8a,a3
funcweaaxn \1,f4,\2awd8a,a4
funcweaaxn \1,f5,\2awd8a,a5
funcweaaxn \1,f6,\2awd8a,a6
funcweaaxn \1,f7,\2awd8a,usp
//--------------------------------------------------------------------
// func.w xxx.w,ax
//--------------------------------------------------------------------
funcweaaxn \1,f8,\2awxwax,(a0)+
//--------------------------------------------------------------------
// func.w xxxlw,ax
//--------------------------------------------------------------------
funcweaaxn \1,f9,\2awxlax,(a0)+
//--------------------------------------------------------------------
// func.w d16(pc),ax
//--------------------------------------------------------------------
funcweaaxn \1,fa,\2awd16pcax,(a0)+
//--------------------------------------------------------------------
// func.w d8(pc,dy),ax
//--------------------------------------------------------------------
funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.w #im,ax
//--------------------------------------------------------------------
funcweaaxn \1,fc,\2awim,(a0)+
//--------------------------------------------------------------------
// ende
.endm;
//--------------------------------------------------------------------
// byt
funcbeadx:.macro // function byt: im,dx
ii_0x\10\2:
\3 \4,d0_off+3(a7),b
ii_0x\12\2:
\3 \4,d1_off+3(a7),b
ii_0x\14\2:
\3 \4,d2,b
ii_0x\16\2:
\3 \4,d3,b
ii_0x\18\2:
\3 \4,d4,b
ii_0x\1a\2:
\3 \4,d5,b
ii_0x\1c\2:
\3 \4,d6,b
ii_0x\1e\2:
\3 \4,d7,b
.endm;
funcbdxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off+3(a7),\4,b
ii_0x\13\2:
\3 d1_off+3(a7),\4,b
ii_0x\15\2:
\3 d2,\4,b
ii_0x\17\2:
\3 d3,\4,b
ii_0x\19\2:
\3 d4,\4,b
ii_0x\1b\2:
\3 d5,\4,b
ii_0x\1d\2:
\3 d6,\4,b
ii_0x\1f\2:
\3 d7,\4,b
.endm;
//--------------------------------------------------------------------
// word
funcweadx:.macro // dx function(\3) ea(\4) -> dx
ii_0x\10\2:
\3 \4,d0_off+2(a7),w
ii_0x\12\2:
\3 \4,d1_off+2(a7),w
ii_0x\14\2:
\3 \4,d2,w
ii_0x\16\2:
\3 \4,d3,w
ii_0x\18\2:
\3 \4,d4,w
ii_0x\1a\2:
\3 \4,d5,w
ii_0x\1c\2:
\3 \4,d6,w
ii_0x\1e\2:
\3 \4,d7,w
.endm;
funcwdxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off+2(a7),\4,w
ii_0x\13\2:
\3 d1_off+2(a7),\4,w
ii_0x\15\2:
\3 d2,\4,w
ii_0x\17\2:
\3 d3,\4,w
ii_0x\19\2:
\3 d4,\4,w
ii_0x\1b\2:
\3 d5,\4,w
ii_0x\1d\2:
\3 d6,\4,w
ii_0x\1f\2:
\3 d7,\4,w
.endm;
//--------------------------------------------------------------------
// long
funcleadx:.macro // dx function(\3) ea(\4) -> dx
ii_0x\10\2:
\3 \4,d0_off(a7),w
ii_0x\12\2:
\3 \4,d1_off(a7),w
ii_0x\14\2:
\3 \4,d2,w
ii_0x\16\2:
\3 \4,d3,w
ii_0x\18\2:
\3 \4,d4,w
ii_0x\1a\2:
\3 \4,d5,w
ii_0x\1c\2:
\3 \4,d6,w
ii_0x\1e\2:
\3 \4,d7,w
.endm;
funcldxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off(a7),\4,w
ii_0x\13\2:
\3 d1_off(a7),\4,w
ii_0x\15\2:
\3 d2,\4,w
ii_0x\17\2:
\3 d3,\4,w
ii_0x\19\2:
\3 d4,\4,w
ii_0x\1b\2:
\3 d5,\4,w
ii_0x\1d\2:
\3 d6,\4,w
ii_0x\1f\2:
\3 d7,\4,w
.endm;
//--------------------------------------------------------------
// address
funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax
ii_0x\10\2:
\3 \4,a0
ii_0x\12\2:
\3 \4,a1
ii_0x\14\2:
\3 \4,a2
ii_0x\16\2:
\3 \4,a3
ii_0x\18\2:
\3 \4,a4
ii_0x\1a\2:
\3 \4,a5
ii_0x\1c\2:
\3 \4,a6
ii_0x\1e\2:
\3a7 \4,a7 // "a7" beachten wegen usp
.endm;
funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax
ii_0x\10\2:
\3 \4,a0_off(a7)
ii_0x\12\2:
\3 \4,a1_off(a7)
ii_0x\14\2:
\3 \4,a2
ii_0x\16\2:
\3 \4,a3
ii_0x\18\2:
\3 \4,a4
ii_0x\1a\2:
\3 \4,a5
ii_0x\1c\2:
\3 \4,a6
ii_0x\1e\2:
\3 \4,usp
.endm;
//--------------------------------------------------------------
// byt, word, long
//--------------------------------------------------------------
funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size
ii_0x\11\2:
\3 a0_off(a7),\4,\5
ii_0x\13\2:
\3 a1_off(a7),\4,\5
ii_0x\15\2:
\3 a2,\4,\5
ii_0x\17\2:
\3 a3,\4,\5
ii_0x\19\2:
\3 a4,\4,\5
ii_0x\1b\2:
\3 a5,\4,\5
ii_0x\1d\2:
\3 a6,\4,\5
ii_0x\1f\2:
\3 usp,\4,\5
.endm;

59
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//--------------------------------------------------------------------
// extension word format missing
//--------------------------------------------------------------------
ii_\1_func:.macro
ii_0x\20:
#ifdef halten_\1
halt
#endif
move.l a0_off(a7),a1
\1_macro
ii_0x\21:
#ifdef halten_\1
halt
#endif
move.l a1_off(a7),a1
\1_macro
ii_0x\22:
#ifdef halten_\1
halt
#endif
move.l a2,a1
\1_macro
ii_0x\23:
#ifdef halten_\1
halt
#endif
move.l a3,a1
\1_macro
ii_0x\24:
#ifdef halten_\1
halt
#endif
move.l a4,a1
\1_macro
ii_0x\25:
#ifdef halten_\1
halt
#endif
move.l a5,a1
\1_macro
ii_0x\26:
#ifdef halten_\1
halt
#endif
move.l a6,a1
\1_macro
ii_0x\27:
#ifdef halten_\1
halt
#endif
move.l usp,a1
\1_macro
ii_0x\2b:
#ifdef halten_\1
halt
#endif
move.l a0,a1
\1_macro
.endm

105
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//-------------------------------------------------------------------
// lea
//-------------------------------------------------------------------
.text
ii_lea_lset:.macro
ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7
ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7
ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7
ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7
ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7
ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7
ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7
ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7
ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7
.endm
//---------------------------------------------------------------------------------------------
// function
//---------------------------------------------------------------------------------------------
ii_lea_sub:.macro
ii_0x4\1\2:
#ifdef halten_lea
halt
#endif
move.l \4,a1
jsr ewf
move.l a1,\3
ii_end
.endm
ii_lea_func:.macro
//lea d8(ax,dy.w),a0-a7
ii_lea_sub 1,f0,a0_off(a7),a0_off(a7)
ii_lea_sub 1,f1,a0_off(a7),a1_off(a7)
ii_lea_sub 1,f2,a0_off(a7),a2
ii_lea_sub 1,f3,a0_off(a7),a3
ii_lea_sub 1,f4,a0_off(a7),a4
ii_lea_sub 1,f5,a0_off(a7),a5
ii_lea_sub 1,f6,a0_off(a7),a6
ii_lea_sub 1,f7,a0_off(a7),usp
ii_lea_sub 3,f0,a1_off(a7),a0_off(a7)
ii_lea_sub 3,f1,a1_off(a7),a1_off(a7)
ii_lea_sub 3,f2,a1_off(a7),a2
ii_lea_sub 3,f3,a1_off(a7),a3
ii_lea_sub 3,f4,a1_off(a7),a4
ii_lea_sub 3,f5,a1_off(a7),a5
ii_lea_sub 3,f6,a1_off(a7),a6
ii_lea_sub 3,f7,a1_off(a7),usp
ii_lea_sub 5,f0,a2,a0_off(a7)
ii_lea_sub 5,f1,a2,a1_off(a7)
ii_lea_sub 5,f2,a2,a2
ii_lea_sub 5,f3,a2,a3
ii_lea_sub 5,f4,a2,a4
ii_lea_sub 5,f5,a2,a5
ii_lea_sub 5,f6,a2,a6
ii_lea_sub 5,f7,a2,usp
ii_lea_sub 7,f0,a3,a0_off(a7)
ii_lea_sub 7,f1,a3,a1_off(a7)
ii_lea_sub 7,f2,a3,a2
ii_lea_sub 7,f3,a3,a3
ii_lea_sub 7,f4,a3,a4
ii_lea_sub 7,f5,a3,a5
ii_lea_sub 7,f6,a3,a6
ii_lea_sub 7,f7,a3,usp
ii_lea_sub 9,f0,a4,a0_off(a7)
ii_lea_sub 9,f1,a4,a1_off(a7)
ii_lea_sub 9,f2,a4,a2
ii_lea_sub 9,f3,a4,a3
ii_lea_sub 9,f4,a4,a4
ii_lea_sub 9,f5,a4,a5
ii_lea_sub 9,f6,a4,a6
ii_lea_sub 9,f7,a4,usp
ii_lea_sub b,f0,a5,a0_off(a7)
ii_lea_sub b,f1,a5,a1_off(a7)
ii_lea_sub b,f2,a5,a2
ii_lea_sub b,f3,a5,a3
ii_lea_sub b,f4,a5,a4
ii_lea_sub b,f5,a5,a5
ii_lea_sub b,f6,a5,a6
ii_lea_sub b,f7,a6,usp
ii_lea_sub d,f0,a6,a0_off(a7)
ii_lea_sub d,f1,a6,a1_off(a7)
ii_lea_sub d,f2,a6,a2
ii_lea_sub d,f3,a6,a3
ii_lea_sub d,f4,a6,a4
ii_lea_sub d,f5,a6,a5
ii_lea_sub d,f6,a6,a6
ii_lea_sub d,f7,a6,usp
ii_lea_sub f,f0,usp,a0_off(a7)
ii_lea_sub f,f1,usp,a1_off(a7)
ii_lea_sub f,f2,usp,a2
ii_lea_sub f,f3,usp,a3
ii_lea_sub f,f4,usp,a4
ii_lea_sub f,f5,usp,a5
ii_lea_sub f,f6,usp,a6
ii_lea_sub f,f7,usp,usp
// lea d8(pc,dy.w),az
ii_lea_sub 1,fb,a0_off(a7),a0
ii_lea_sub 3,fb,a1_off(a7),a0
ii_lea_sub 5,fb,a2,a0
ii_lea_sub 7,fb,a3,a0
ii_lea_sub 9,fb,a4,a0
ii_lea_sub b,fb,a5,a0
ii_lea_sub d,fb,a6,a0
ii_lea_sub f,fb,usp,a0
.endm

144
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/*******************************************************/
// constanten
/*******************************************************/
.extern ___RAMBAR1
.extern _rt_cacr
.extern _rt_mod
.extern _rt_ssp
.extern _rt_usp
.extern _rt_vbr
.extern _d0_save
.extern _a7_save
ii_ss = 16
d0_off = 0
d1_off = 4
a0_off = 8
a1_off = 12
format_off = 16
sr_off = 18
ccr_off = 19
pc_off = 20
#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle
/*******************************************************/
// allgemeine macros
/*******************************************************/
ii_end: .macro
move.l a0,pc_off(a7)
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7
rte
.endm;
set_cc0:.macro
move.w ccr,d0
move.b d0,ccr_off(a7)
.endm;
ii_esr: .macro // geht nicht!!??
movem.l (a7),d0/d1/a0/a1
lea ii_ss+8(a7),a7 // stack erh<72>hen
move.w d0,_d0_save // d0.w sicheren
move.w -6(a7),d0 // sr holen
move.w d0,sr // sr setzen
nop
move.w _d0_save,d0 // d0.w zur<75>ck
.endm;
ii_end_mvm:.macro
move.l a0_off(a7),a0
lea 16(a7),a7
rte
.endm;
ii_endj:.macro
movem.l (a7),d0/d1/a0/a1 // register zur<75>ck
lea ii_ss(a7),a7 // korr
rte // ende
.endm;
set_nzvc:.macro // set ccr bits nzvc
move.w ccr,d1
bclr #4,d1
btst #4,ccr_off(a7)
beq snzvc2\@
bset #4,d1
snzvc2\@:
move.b d1,ccr_off(a7)
.endm;
set_cc1:.macro
move.w ccr,d1
move.b d1,ccr_off(a7)
.endm;
set_cc_b:.macro
move.w ccr,d1
btst #7,d0 // byt negativ?
beq set_cc_b2\@
bset #3,d1 // make negativ
set_cc_b2\@:
move.b d1,ccr_off(a7)
.endm;
set_cc_w:.macro
move.w ccr,d1
btst #15,d0 // byt negativ?
beq set_cc_w2\@
bset #3,d1 // make negativ
set_cc_w2\@:
move.b d1,ccr_off(a7)
.endm;
get_pc: .macro
lea.l (a0),a1
.endm;
//--------------------------------------------------------------------
ii_lset:.macro
lea table+\1*4,a0
move.l #ii_\1,(a0)
.endm;
ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
ii_lset_dxg \1,\2
ii_lset_dxu \1,\2
.endm;
ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
lea table+0x\10\2*4,a0
move.l #ii_0x\10\2,(a0)
lea 0x800(a0),a0 // 4 * 0x200
move.l #ii_0x\12\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\14\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\16\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\18\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1a\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1c\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1e\2,(a0)
.endm;
ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40
lea table+0x\11\2*4,a0
move.l #ii_0x\11\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\13\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\15\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\17\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\19\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1b\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1d\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1f\2,(a0)
.endm;

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//***********************************************************************************/
// movem
//***********************************************************************************/
ii_movem_lset: .macro
// movem.l rx,xxx.L
ii_lset 0x48f9
// movem.l xxx.L,rx
ii_lset 0x4cf9
// movem.w rx,xxx.L
ii_lset 0x48b9
// movem.w xxx.L,rx
ii_lset 0x4cb9
// movem.l rx,-(ax)
ii_lset 0x48e0
ii_lset 0x48e1
ii_lset 0x48e2
ii_lset 0x48e3
ii_lset 0x48e4
ii_lset 0x48e5
ii_lset 0x48e6
ii_lset 0x48e7
// movem.l (ax)+,rx
ii_lset 0x4cd8
ii_lset 0x4cd9
ii_lset 0x4cda
ii_lset 0x4cdb
ii_lset 0x4cdc
ii_lset 0x4cdd
ii_lset 0x4cde
ii_lset 0x4cdf
.endm
//***********************************************************************************/
ii_movem_func: .macro
//-------------------------------------------------------------------
// movem.l
//--------------------------------------------------------------------
// movem.l (ax)+,reg
//--------------------------------------------------------------------
.long 0
az_reg_table:
.byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0
.byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0
//-------------------------------------------------------------------------------
ii_0x48e0: // movem.l reglist,-(a0)
mvm_mem_macro 0x48d0,a0_off(a7),2
ii_0x48e1: // movem.l reglist,-(a1)
mvm_mem_macro 0x48d1,a1_off(a7),2
ii_0x48e2: // movem.l reglist,-(a2)
mvm_mem_macro 0x48d2,a2,2
ii_0x48e3: // movem.l reglist,-(a3)
mvm_mem_macro 0x48d3,a3,2
ii_0x48e4: // movem.l reglist,-(a4)
mvm_mem_macro 0x48d4,a4,2
ii_0x48e5: // movem.l reglist,-(a5)
mvm_mem_macro 0x48d5,a5,2
ii_0x48e6: // movem.l reglist,-(a6)
mvm_mem_macro 0x48d6,a6,2
ii_0x48e7: // movem.l reglist,-(a7)
mvm_mem_macro 0x48d7,usp,2
//-------------------------------------------------------------------------------
ii_0x4cd8: // movem.l (a0)+,reglist
mvm_reg_macro 0x4cd0,0x41e8,2
ii_0x4cd9: // movem.l (a1)+,reglist
mvm_reg_macro 0x4cd1,0x43e9,2
ii_0x4cda: // movem.l (a2)+,reglist
mvm_reg_macro 0x4cd2,0x45ea,2
ii_0x4cdb: // movem.l (a3)+,reglist
mvm_reg_macro 0x4cd3,0x47eb,2
ii_0x4cdc: // movem.l (a4)+,reglist
mvm_reg_macro 0x4cd4,0x49ec,2
ii_0x4cdd: // movem.l (a5)+,reglist
mvm_reg_macro 0x4cd5,0x4bed,2
ii_0x4cde: // movem.l (a6)+,reglist
mvm_reg_macro 0x4cd6,0x4dee,2
ii_0x4cdf: // movem.l (a7)+,reglist
mvm_reg_macro 0x4cd7,0x4fef,2
//----------------------------------------------------------------------------
ii_0x48f9: // movem.l reg,xxx.L
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro l
//---------------------------------------------------------------------------------------------
ii_0x4cf9: // movem.l xxx.L,reg
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro l
//----------------------------------------------------------------------------
ii_0x48b9: // movem.w reg,xxx.L
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro w
//---------------------------------------------------------------------------------------------
ii_0x4cb9: // movem.w xxx.L,reg
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro w
.endm
//==============================================================
mvm_mem_macro:.macro
#ifdef halten_movem
halt
#endif
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lsl.l #\3,d1 // * anzahl byts pro wert
move.l \2,a1
sub.l d1,a1 // ax-anzahl byts
move.l a1,\2
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x reg_list,-(a7)
move.w (a0)+,(a1)+ // register list
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
//---------------------------------------------------------------------------------
mvm_reg_macro:.macro
#ifdef halten_movem
halt
#endif
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x (ax),reg_list
move.w (a0)+,(a1)+ // register list
move.w #\2,(a1)+ // lea 0(ax),ax
lsl.l #\3,d1 // * anzahl byts pro wert
move.w d1,(a1)+ // offset von lea
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
//---------------------------------------------------------------------------------
movemrm_macro:.macro // in d0 register liste, in a1 zieladresse
#ifdef halten_movem
halt
#endif
tst.b d0 // datenregister zu verschieben?
bne mrm_dx\@ // ja->
lsr.l #8,d0 // sonst zu addressregister
jmp mmrm_nd7\@ // ->
mrm_dx\@:
lsr.l #1,d0
bcc mmrm_nd0\@
.ifc 1,l
move.l d0_off(a7),(a1)+
.else
move.w d0_off+2(a7),(a1)+
.endif
mmrm_nd0\@:
lsr.l #1,d0
bcc mmrm_nd1\@
.ifc 1,l
move.l d1_off(a7),(a1)+
.else
move.w d1_off+2(a7),(a1)+
.endif
mmrm_nd1\@:
lsr.l #1,d0
bcc mmrm_nd2\@
move.\1 d2,(a1)+
mmrm_nd2\@:
lsr.l #1,d0
bcc mmrm_nd3\@
move.\1 d3,(a1)+
mmrm_nd3\@:
lsr.l #1,d0
bcc mmrm_nd4\@
move.\1 d4,(a1)+
mmrm_nd4\@:
lsr.l #1,d0
bcc mmrm_nd5\@
move.\1 d5,(a1)+
mmrm_nd5\@:
lsr.l #1,d0
bcc mmrm_nd6\@
move.l d6,(a1)+
mmrm_nd6\@:
lsr.l #1,d0
bcc mmrm_nd7\@
move.\1 d7,(a1)+
mmrm_nd7\@:
tst.b d0 // addressregister zu verschieben?
beq mmrm_na7\@
lsr.l #1,d0
bcc mmrm_na0\@
.ifc 1,l
move.l a0_off(a7),(a1)+
.else
move.w a0_off+2(a7),(a1)+
.endif
mmrm_na0\@:
lsr.l #1,d0
bcc mmrm_na1\@
.ifc 1,l
move.l a1_off(a7),(a1)+
.else
move.w a1_off+2(a7),(a1)+
.endif
mmrm_na1\@:
lsr.l #1,d0
bcc mmrm_na2\@
move.\1 a2,(a1)+
mmrm_na2\@:
lsr.l #1,d0
bcc mmrm_na3\@
move.\1 a3,(a1)+
mmrm_na3\@:
lsr.l #1,d0
bcc mmrm_na4\@
move.\1 a4,(a1)+
mmrm_na4\@:
lsr.l #1,d0
bcc mmrm_na5\@
move.\1 a5,(a1)+
mmrm_na5\@:
lsr.l #1,d0
bcc mmrm_na6\@
move.\1 a6,(a1)+
mmrm_na6\@:
lsr.l #1,d0
bcc mmrm_na7\@
move.l a0,d1 // sichern
move.l usp,a0 // ist ja usp
move.\1 a0,(a1)+ // nach a0
move.l d1,a0 // pc zur<75>ck
mmrm_na7\@:
ii_end
.endm
//---------------------------------------------------------------------------------------------
movemmr_macro:.macro // in d0 register liste, in a1 source adr
#ifdef halten_movem
halt
#endif
tst.b d0 // datenregister zu verschieben?
bne mmr_dx\@ // ja->
lsr.l #8,d0 // sonst zu addressregister
bra mmmr_nd7\@ // ->
mmr_dx\@:
lsr.l #1,d0
bcc mmmr_nd0\@
.ifc 1,l
move.l (a1)+,d0_off(a7)
.else
move.w (a1)+,d0_off+2(a7)
.endif
mmmr_nd0\@:
lsr.l #1,d0
bcc mmmr_nd1\@
.ifc 1,l
move.l (a1)+,d1_off(a7)
.else
move.w (a1)+,d1_off+2(a7)
.endif
mmmr_nd1\@:
lsr.l #1,d0
bcc mmmr_nd2\@
move.\1 (a1)+,d2
mmmr_nd2\@:
lsr.l #1,d0
bcc mmmr_nd3\@
move.\1 (a1)+,d3
mmmr_nd3\@:
lsr.l #1,d0
bcc mmmr_nd4\@
move.\1 (a1)+,d4
mmmr_nd4\@:
lsr.l #1,d0
bcc mmmr_nd5\@
move.\1 (a1)+,d5
mmmr_nd5\@:
lsr.l #1,d0
bcc mmmr_nd6\@
move.\1 (a1)+,d6
mmmr_nd6\@:
lsr.l #1,d0
bcc mmmr_nd7\@
move.\1 (a1)+,d7
mmmr_nd7\@:
tst.b d0 // addressregister zu verschieben?
beq mmmr_na7\@ // nein->
lsr.l #1,d0
bcc mmmr_na0\@
.ifc 1,l
move.l (a1)+,a0_off(a7)
.else
move.w (a1)+,a0_off+2(a7)
.endif
mmmr_na0\@:
lsr.l #1,d0
bcc mmmr_na1\@
.ifc 1,l
move.l (a1)+,a1_off(a7)
.else
move.w (a1)+,a1_off+2(a7)
.endif
mmmr_na1\@:
lsr.l #1,d0
bcc mmmr_na2\@
move.\1 (a1)+,a2
mmmr_na2\@:
lsr.l #1,d0
bcc mmmr_na3\@
move.\1 (a1)+,a3
mmmr_na3\@:
lsr.l #1,d0
bcc mmmr_na4\@
move.\1 (a1)+,a4
mmmr_na4\@:
lsr.l #1,d0
bcc mmmr_na5\@
move.\1 (a1)+,a5
mmmr_na5\@:
lsr.l #1,d0
bcc mmmr_na6\@
move.\1 (a1)+,a6
mmmr_na6\@:
lsr.l #1,d0
bcc mmmr_na7\@
move.\1 (a1)+,a1 // nach a0
move.l a1,usp // war ja usp
mmmr_na7\@:
ii_end
.endm

179
BaS_GNU/BaS_codewarrior/firebeeV1/sources/ii_movep.h Normal file
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//--------------------------------------------------------------------
// movep
//--------------------------------------------------------------------
.text
ii_movep_lset:.macro
ii_lset_opeau 01,0 //movep.w d(a0-7),d0
ii_lset_opeau 03,0 //movep.w d(a0-7),d1
ii_lset_opeau 05,0 //movep.w d(a0-7),d2
ii_lset_opeau 07,0 //movep.w d(a0-7),d3
ii_lset_opeau 09,0 //movep.w d(a0-7),d4
ii_lset_opeau 0b,0 //movep.w d(a0-7),d5
ii_lset_opeau 0d,0 //movep.w d(a0-7),d6
ii_lset_opeau 0f,0 //movep.w d(a0-7),d7
ii_lset_opeau 01,4 //movep.w d0,d(a0-7)
ii_lset_opeau 03,4 //movep.w d1,d(a0-7)
ii_lset_opeau 05,4 //movep.w d2,d(a0-7)
ii_lset_opeau 07,4 //movep.w d3,d(a0-7)
ii_lset_opeau 09,4 //movep.w d4,d(a0-7)
ii_lset_opeau 0b,4 //movep.w d5,d(a0-7)
ii_lset_opeau 0d,4 //movep.w d6,d(a0-7)
ii_lset_opeau 0f,4 //movep.w d7,d(a0-7)
ii_lset_opeau 01,8 //movep.l d(a0-7),d0
ii_lset_opeau 03,8 //movep.l d(a0-7),d1
ii_lset_opeau 05,8 //movep.l d(a0-7),d2
ii_lset_opeau 07,8 //movep.l d(a0-7),d3
ii_lset_opeau 09,8 //movep.l d(a0-7),d4
ii_lset_opeau 0b,8 //movep.l d(a0-7),d5
ii_lset_opeau 0d,8 //movep.l d(a0-7),d6
ii_lset_opeau 0f,8 //movep.l d(a0-7),d7
ii_lset_opeau 01,c //movep.l d0,d(a0-7)
ii_lset_opeau 03,c //movep.l d1,d(a0-7)
ii_lset_opeau 05,c //movep.l d2,d(a0-7)
ii_lset_opeau 07,c //movep.l d3,d(a0-7)
ii_lset_opeau 09,c //movep.l d4,d(a0-7)
ii_lset_opeau 0b,c //movep.l d5,d(a0-7)
ii_lset_opeau 0d,c //movep.l d6,d(a0-7)
ii_lset_opeau 0f,c //movep.l d7,d(a0-7)
.endm
//---------------------------------------------------------------------------------------------
ii_movep_func:.macro
//movep.w d(a0-7),d0-7
ii_movep 010,d0_off(a7),wad
ii_movep 030,d1_off(a7),wad
ii_movep 050,d2,wad
ii_movep 070,d3,wad
ii_movep 090,d4,wad
ii_movep 0b0,d5,wad
ii_movep 0d0,d6,wad
ii_movep 0f0,d7,wad
//movep.w d0-7,d(a0-7)
ii_movep 014,d0_off(a7),wda
ii_movep 034,d1_off(a7),wda
ii_movep 054,d2,wda
ii_movep 074,d3,wda
ii_movep 094,d4,wda
ii_movep 0b4,d5,wda
ii_movep 0d4,d6,wda
ii_movep 0f4,d7,wda
//movep.l d(a0-7),d0-7
ii_movep 018,d0_off(a7),lad
ii_movep 038,d1_off(a7),lad
ii_movep 058,d2,lad
ii_movep 078,d3,lad
ii_movep 098,d4,lad
ii_movep 0b8,d5,lad
ii_movep 0d8,d6,lad
ii_movep 0f8,d7,lad
//movep.l d0-7,d(a0-7)
ii_movep 01c,d0_off(a7),lda
ii_movep 03c,d1_off(a7),lda
ii_movep 05c,d2,lda
ii_movep 07c,d3,lda
ii_movep 09c,d4,lda
ii_movep 0bc,d5,lda
ii_movep 0dc,d6,lda
ii_movep 0fc,d7,lda
.endm
//---------------------------------------------------------------------------------------------
ii_movep:.macro //1=code ziffer 1-3 2=register 3=art
ii_0x\18:
#ifdef halten_movep
halt
#endif
move.l a0_off(a7),a1
ii_movep\3_up1 \2
ii_0x\19:
#ifdef halten_movep
halt
#endif
move.l a1_off(a7),a1
ii_movep\3_up1 \2
ii_0x\1a:
#ifdef halten_movep
halt
#endif
move.l a2,a1
ii_movep\3_up1 \2
ii_0x\1b:
#ifdef halten_movep
halt
#endif
move.l a3,a1
ii_movep\3_up1 \2
ii_0x\1c:
#ifdef halten_movep
halt
#endif
move.l a4,a1
ii_movep\3_up1 \2
ii_0x\1d:
#ifdef halten_movep
halt
#endif
move.l a5,a1
ii_movep\3_up1 \2
ii_0x\1e:
#ifdef halten_movep
halt
#endif
move.l a6,a1
ii_movep\3_up1 \2
ii_0x\1f:
#ifdef halten_movep
halt
#endif
move.l usp,a1
ii_movep\3_up1 \2
.endm
ii_movepwad_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.b (a1),d0
lsl.l #8,d0
move.b 2(a1,d1.l),d0
move.w d0,\1
ii_end
.endm
ii_movepwda_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.w \1,d0
move.b d0,2(a1)
lsr.l #8,d0
move.b d0,(a1)
ii_end
.endm
ii_moveplad_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.b (a1),d0
lsl.l #8,d0
move.b 2(a1),d0
lsl.l #8,d0
move.b 4(a1),d0
lsl.l #8,d0
move.b 6(a1),d0
move.l d0,\1
ii_end
.endm
ii_moveplda_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.l \1,d0
move.b d0,6(a1)
lsr.l #8,d0
move.b d0,4(a1)
lsr.l #8,d0
move.b d0,2(a1)
lsr.l #8,d0
move.b d0,(a1)
ii_end
.endm

661
BaS_GNU/BaS_codewarrior/firebeeV1/sources/ii_op.h Normal file
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@@ -0,0 +1,661 @@
/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_lset_op:.macro
//byt
ii_lset_opea \1,0 // dx,ax
ii_lset_opea \1,1 // (ax), (ax)+
ii_lset_opea \1,2 // -(ax),d16(ax)
ii_lset_opeag \1,3 // d8(ax,dy)
lea table+0x\1\238*4,a0
move.l #ii_0x\138,(a0)+ // xxx.w
move.l #ii_0x\139,(a0)+ // xxx.l
//word
ii_lset_opea \1,4 // dx,ax
ii_lset_opea \1,5 // (ax), (ax)+
ii_lset_opea \1,6 // -(ax),d16(ax)
ii_lset_opeag \1,7 // d8(ax,dy)
lea table+0x\178*4,a0
move.l #ii_0x\178,(a0)+ // xxx.w
move.l #ii_0x\179,(a0)+ // xxx.l
//long
ii_lset_opea \1,8 // dx,ax
ii_lset_opea \1,9 // (ax), (ax)+
ii_lset_opea \1,a // -(ax),d16(ax)
ii_lset_opeag \1,b // d8(ax,dy)
lea table+0x\1b8*4,a0
move.l #ii_0x\1b8,(a0)+ // xxx.w
move.l #ii_0x\1b9,(a0)+ // xxx.l
.endm
ii_lset_opeag:.macro // 0x1120-0x1127
lea table+0x\1\20*4,a0
move.l #ii_0x\1\20,(a0)+
move.l #ii_0x\1\21,(a0)+
move.l #ii_0x\1\22,(a0)+
move.l #ii_0x\1\23,(a0)+
move.l #ii_0x\1\24,(a0)+
move.l #ii_0x\1\25,(a0)+
move.l #ii_0x\1\26,(a0)+
move.l #ii_0x\1\27,(a0)+
.endm;
ii_lset_opeau:.macro // 0x1128-0x112f
lea table+0x\1\28*4,a0
move.l #ii_0x\1\28,(a0)+
move.l #ii_0x\1\29,(a0)+
move.l #ii_0x\1\2a,(a0)+
move.l #ii_0x\1\2b,(a0)+
move.l #ii_0x\1\2c,(a0)+
move.l #ii_0x\1\2d,(a0)+
move.l #ii_0x\1\2e,(a0)+
move.l #ii_0x\1\2f,(a0)+
.endm;
ii_lset_opea:.macro
ii_lset_opeag \1,\2
ii_lset_opeau \1,\2
.endm
/******************************************************/
ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick
// byt
opdx \1,\2,b,0,\3 // dx,ax
opia \1,\2,b,1,\3 // (ax),(ax)+
opdia \1,\2,b,2,\3 // -(ax),d16(ax)
opd8a \1,\2,b,3,\3 // d8(ax),xxx
// word
opdx \1,\2,w,4,\3 // dx,ax
opia \1,\2,w,5,\3 // (ax),(ax)+
opdia \1,\2,w,6,\3 // -(ax),d16(ax)
opd8a \1,\2,w,7,\3 // d8(ax),xxx
// long
opdx \1,\2,l,8,\3 // dx,ax
opia \1,\2,l,9,\3 // (ax),(ax)+
opdia \1,\2,l,a,\3 // -(ax),d16(ax)
opd8a \1,\2,l,b,\3 // d8(ax),xxx
.endm
/******************************************************/
// byt word long
/******************************************************/
opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
.ifc \3,b
op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3
.else
op\5smd \2,d0_off(a7),d0_off(a7),\3
.endif
.endif
ii_0x\1\41:
.ifc \3,b
op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3
.else
op\5smd \2,d1_off(a7),d1_off(a7),\3
.endif
.endif
ii_0x\1\42:
op\5smd \2,d2,d2,\3
ii_0x\1\43:
op\5smd \2,d3,d3,\3
ii_0x\1\44:
op\5smd \2,d4,d4,\3
ii_0x\1\45:
op\5smd \2,d5,d5,\3
ii_0x\1\46:
op\5smd \2,d6,d6,\3
ii_0x\1\47:
op\5smd \2,d7,d7,\3
//ax
ii_0x\1\48:
opa\5smd \2,a0_off(a7),a0_off(a7),\3
ii_0x\1\49:
opa\5smd \2,a1_off(a7),a1_off(a7),\3
ii_0x\1\4a:
opa\5smd \2,a2,a2,\3
ii_0x\1\4b:
opa\5smd \2,a3,a3,\3
ii_0x\1\4c:
opa\5smd \2,a4,a4,\3
ii_0x\1\4d:
opa\5smd \2,a5,a5,\3
ii_0x\1\4e:
opa\5smd \2,a6,a6,\3
ii_0x\1\4f:
opa\5smd \2,usp,usp,\3
.endm;
//-----------------------------------------------
opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
//(ax)
ii_0x\1\40:
op\5sia \2,a0_off(a7),(a1),(a1),\3
ii_0x\1\41:
op\5sia \2,a1_off(a7),(a1),(a1),\3
ii_0x\1\42:
op\5smd \2,(a2),(a2),\3
ii_0x\1\43:
op\5smd \2,(a3),(a3),\3
ii_0x\1\44:
op\5smd \2,(a4),(a4),\3
ii_0x\1\45:
op\5smd \2,(a5),(a5),\3
ii_0x\1\46:
op\5smd \2,(a6),(a6),\3
ii_0x\1\47:
op\5sia \2,usp,(a1),(a1),\3
//(ax)+
ii_0x\1\48:
op\5sia \2,a0_off(a7),(a1),(a1)+,\3
ii_0x\1\49:
op\5sia \2,a1_off(a7),(a1),(a1)+,\3
ii_0x\1\4a:
op\5smd \2,(a2),(a2)+,\3
ii_0x\1\4b:
op\5smd \2,(a3),(a3)+,\3
ii_0x\1\4c:
op\5smd \2,(a4),(a4)+,\3
ii_0x\1\4d:
op\5smd \2,(a5),(a5)+,\3
ii_0x\1\4e:
op\5smd \2,(a6),(a6)+,\3
ii_0x\1\4f:
op\5sia \2,usp,(a1),(a1)+,\3
.endm;
//-----------------------------------------------
opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
op\5sia \2,a0_off(a7),-(a1),(a1),\3
ii_0x\1\41:
op\5sia \2,a1_off(a7),-(a1),(a1),\3
ii_0x\1\42:
op\5smd \2,-(a2),(a2),\3
ii_0x\1\43:
op\5smd \2,-(a3),(a3),\3
ii_0x\1\44:
op\5smd \2,-(a4),(a4),\3
ii_0x\1\45:
op\5smd \2,-(a5),(a5),\3
ii_0x\1\46:
op\5smd \2,-(a6),(a6),\3
ii_0x\1\47:
op\5sia \2,usp,-(a1),(a1),\3
ii_0x\1\48:
op\5sd16a \2,a0_off(a7),\3
ii_0x\1\49:
op\5sd16a \2,a1_off(a7),\3
ii_0x\1\4a:
op\5sd16a \2,a2,\3
ii_0x\1\4b:
op\5sd16a \2,a3,\3
ii_0x\1\4c:
op\5sd16a \2,a4,\3
ii_0x\1\4d:
op\5sd16a \2,a5,\3
ii_0x\1\4e:
op\5sd16a \2,a6,\3
ii_0x\1\4f:
op\5sd16a \2,usp,\3
.endm;
//-----------------------------------------------
opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
op\5sd8a \2,a0_off(a7),\3
ii_0x\1\41:
op\5sd8a \2,a1_off(a7),\3
ii_0x\1\42:
op\5sd8a \2,a2,\3
ii_0x\1\43:
op\5sd8a \2,a3,\3
ii_0x\1\44:
op\5sd8a \2,a4,\3
ii_0x\1\45:
op\5sd8a \2,a5,\3
ii_0x\1\46:
op\5sd8a \2,a6,\3
ii_0x\1\47:
op\5sd8a \2,usp,\3
ii_0x\1\48:
op\5sxx \2,\3,w
ii_0x\1\49:
op\5sxx \2,\3,l
.endm;
//-----------------------------------------------
opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d1
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse
#ifdef halten_op
halt
#endif
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
move.\3 (a0)+,a1
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;
//*******************************************************************************3
opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\4 d1,\3
.endif
ii_end
.endm;
opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d0,d1
.ifnc \1,cmp.l
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
.endif
ii_end
.endm;
opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
.ifc \5,l
move.l (a0)+,d0
.else
.ifc \5,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\5 d1,\4
.endif
ii_end
.endm;
opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
.ifc \3,l
move.l (a0)+,d0
.else
.ifc \3,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\3 d1,(a1)
.endif
ii_end
.endm;
opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
.ifc \3,l
move.l (a0)+,d0
.else
.ifc \3,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\3 d1,(a1)
.endif
ii_end
.endm;
opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse
.ifc \2,l
move.l (a0)+,d0
.else
.ifc \2,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\2 d1,(a1)
.endif
ii_end
.endm;
//*******************************************************************************3
opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 ,d1
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse
#ifdef halten_op
halt
#endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;

263
BaS_GNU/BaS_codewarrior/firebeeV1/sources/ii_opc.h Normal file
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@@ -0,0 +1,263 @@
/*****************************************************************************************/
// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax
// zusammen mit op.h
/*****************************************************************************************/
ii_lset_opc:.macro
ii_lset_opeag \1,c // dx,ax
ii_lset_opea \1,d // (ax), (ax)+
ii_lset_opea \1,e // -(ax),d16(ax)
ii_lset_opeag \1,f // d8(ax,dy)
lea table+0x\1b8*4,a0
move.l #ii_0x\1b8,(a0)+ // xxx.w
move.l #ii_0x\1b9,(a0)+ // xxx.l
.endm
/******************************************************/
ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat
opcdx \1,\2,l,c,\3 // dx,ax
opia \1,\2,l,d,\3 // (ax),(ax)+
opdia \1,\2,l,e,\3 // -(ax),d16(ax)
opd8a \1,\2,l,f,\3 // d8(ax),xxx
.endm
//*******************************************************************************3
/******************************************************/
// byt word long
/******************************************************/
opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
#ifdef halten_opc
halt
#endif
.ifc \3,b
op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3
.else
op\5smd \2,d0_off(a7),d0_off(a7),\3
.endif
.endif
ii_0x\1\41:
.ifc \3,b
op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3
.else
op\5smd \2,d1_off(a7),d1_off(a7),\3
.endif
.endif
ii_0x\1\42:
op\5smd \2,d2,d2,\3
ii_0x\1\43:
op\5smd \2,d3,d3,\3
ii_0x\1\44:
op\5smd \2,d4,d4,\3
ii_0x\1\45:
op\5smd \2,d5,d5,\3
ii_0x\1\46:
op\5smd \2,d6,d6,\3
ii_0x\1\47:
op\5smd \2,d7,d7,\3
.endm
//-----------------------------------------------------
opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d1
set_cc0
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse
#ifdef halten_opc
halt
#endif
.ifc \2,l
move.l (a0)+,d0
.else
.ifc \2,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;

442
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//--------------------------------------------------------------------
// or
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// or.b #im,dx
//--------------------------------------------------------------------
orbir_macro:.macro
#ifdef halten_or
halt
#endif
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
or.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea,dx
//--------------------------------------------------------------------
ordd:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
orddd:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or (ea)->dy,dx
//--------------------------------------------------------------------
ordda:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea->ay,(ay)+,dx
//--------------------------------------------------------------------
orddai:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea->ay,-(ay),dx
//--------------------------------------------------------------------
orddad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d16(ay),dx
//--------------------------------------------------------------------
ord16ad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d8(ay,dy),dx
//--------------------------------------------------------------------
ord8ad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or xxx.w,dx
//--------------------------------------------------------------------
orxwd:.macro
#ifdef halten_or
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or xxx.l,dx
//--------------------------------------------------------------------
orxld:.macro
#ifdef halten_or
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d16(pc),dx
//--------------------------------------------------------------------
ord16pcd:.macro
halt
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d8(pc,dy),dx
//--------------------------------------------------------------------
ord8pcd:.macro
#ifdef halten_or
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// or dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // or (ea)->dy,dx
//--------------------------------------------------------------------
oreda:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,(ay)+
//--------------------------------------------------------------------
oredai:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,(ay)+
//--------------------------------------------------------------------
oredaid:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,-(ay)
//--------------------------------------------------------------------
oredad:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,-(ay)
//--------------------------------------------------------------------
oredadd:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,d16(ay)
//--------------------------------------------------------------------
ore16ad:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or.w dx,d8(ay,dy)
//--------------------------------------------------------------------
ore8ad:.macro
#ifdef halten_or
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,xxx.w
//--------------------------------------------------------------------
orxwe:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,xxx.l
//--------------------------------------------------------------------
orxle:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // ora.w ea,ax
//--------------------------------------------------------------------
oraw:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// or.w ea,usp
//--------------------------------------------------------------------
orawa7:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w usp?,ax
//--------------------------------------------------------------------
orawu:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w usp?,usp
//--------------------------------------------------------------------
orawua7:.macro
orawu \1,\2
.endm;
//--------------------------------------------------------------------
// // ora.w d16(ay),ax
//--------------------------------------------------------------------
orawd16a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d8(ay,dy),ax
//--------------------------------------------------------------------
orawd8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w xxx.w,ax
//--------------------------------------------------------------------
orawxwax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w xxx.l,ax
//--------------------------------------------------------------------
orawxlax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d16(pc),ax
//--------------------------------------------------------------------
orawd16pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d8(pc,dy),ax
//--------------------------------------------------------------------
orawd8pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w #im,ax
//--------------------------------------------------------------------
orawim:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.l d8(ay,dy),ax
//--------------------------------------------------------------------
orald8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.l d8(pc,dy),ax
//--------------------------------------------------------------------
orald8pcax:.macro
jmp ii_error
.endm;
//*****************************************************************************************
// spezial addx subx etc.
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
ordx:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
ordax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------

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//--------------------------------------------------------------------
// pea
//--------------------------------------------------------------------
.text
ii_pea_lset:.macro
ii_lset_opeag 48,7
ii_lset 0x487b
.endm
//---------------------------------------------------------------------------------------------
ii_pea_func:.macro
ii_0x4870:
#ifdef halten_pea
halt
#endif
move.l a0_off(a7),a1
pea_macro
ii_0x4871:
#ifdef halten_pea
halt
#endif
move.l a1_off(a7),a1
pea_macro
ii_0x4872:
#ifdef halten_pea
halt
#endif
move.l a2,a1
pea_macro
ii_0x4873:
#ifdef halten_pea
halt
#endif
move.l a3,a1
pea_macro
ii_0x4874:
#ifdef halten_pea
halt
#endif
move.l a4,a1
pea_macro
ii_0x4875:
#ifdef halten_pea
halt
#endif
move.l a5,a1
pea_macro
ii_0x4876:
#ifdef halten_pea
halt
#endif
move.l a6,a1
pea_macro
ii_0x4877:
#ifdef halten_pea
halt
#endif
move.l usp,a1
pea_macro
ii_0x487b:
#ifdef halten_pea
halt
#endif
move.l a0,a1
pea_macro
.endm
//---------------------------------------------------------------------------------------------
pea_macro:.macro
jsr ewf
move.l (a1),d0
move.l usp,a1
move.l d0,-(a1)
move.l a1,usp
ii_end
.endm

247
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/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_lset_shd:.macro
ii_lset_shdx e0 //r d0
ii_lset_shdx e2 //r d1
ii_lset_shdx e4 //r d2
ii_lset_shdx e6 //r d3
ii_lset_shdx e8 //r d4
ii_lset_shdx ea //r d5
ii_lset_shdx ec //r d6
ii_lset_shdx ee //r d7
ii_lset_shdx e1 //l d0
ii_lset_shdx e3 //l d1
ii_lset_shdx e4 //l d2
ii_lset_shdx e5 //l d3
ii_lset_shdx e9 //l d4
ii_lset_shdx eb //l d5
ii_lset_shdx ed //l d6
ii_lset_shdx ef //l d7
.endm
ii_lset_shdx:.macro
//byt
ii_lset_opea \1,0 // as,ls #im,dx
ii_lset_opea \1,1 // rox,ro #im,dx
ii_lset_opea \1,2 // as,ls dy,dx
ii_lset_opea \1,3 // rox,ro dy,dx
//word
ii_lset_opea \1,4 // as,ls #im,dx
ii_lset_opea \1,5 // rox,ro #im,dx
ii_lset_opea \1,6 // as,ls dy,dx
ii_lset_opea \1,7 // rox,ro dy,dx
//long
// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden
ii_lset_opea \1,9 // rox,ro #im,dx
// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden
ii_lset_opea \1,b // rox,ro dy,dx
.endm
/******************************************************/
ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat
// byt
opdx \1,\2,b,0,\3 // dx
// word
opdx \1,\2,w,4,\3 // dx
// long
opdx \1,\2,l,8,\3 // dx
.endm
/******************************************************/
// byt word long routinen
/******************************************************/
sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvs.\4 \2,d1
sh_shal \1,\2,\3,\4
.endm
sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvz.\4 \2,d1
sh_shal \1,\2,\3,\4
.endm
sh_shal:.macro
move.w \3,d0
\1.l d0,d1
set_cc0
move.\4 d1,\2
.endm
sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvz.\4 \2,d1
.ifc \4,b
byterev.l d1
.else
swap.w d1
.endif
sh_asr \1,\2,\3,\4
.endm
sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
move.\4 \2,d1 /
move.w \3,d0
.ifc \4,b
lsl.l #8,d1
move.b \2,d1
and.l #0x7,d0
lsr.l d0,d1
.else
.ifc \4,w
swap.w d1
move.w \2,d1
and.l #0xf,d0
lsr.l d0,d1
.else
and.l #0x1f,d0
lsr.l d0,d1
move.l d1,a1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsl.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
move.w ccr,d0
and.l #1,d1 // ist auch carry bit
or.l d1,d0
move.b d0,ccr_off(a7)
.endm
sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
move.\4 \2,d1
move.w \3,d0
.ifc \4,b
lsl.l #8,d1
move.b \2,d1
and.l #0x7,d0
lsl.l d0,d1
lsr.l #8,d1
moveq #7,d0
.else
.ifc \4,w
swap.w d1
move.w \2,d1
and.l #0xf,d0
lsr.l d0,d1
swap.w d1
moveq #15,d0
.else
and.l #0x1f,d0
lsl.l d0,d1
move.l d1,a1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsr.l d0,d1
add.l a1,d1
moveq #31,d0
.endif
.endif
move.\4 d1,\2
lsr.l d0,d1 // carry bit schieben
move.w ccr,d0
and.l #1,d1
or.l d1,d0
move.b d0,ccr_off(a7)
.endm
sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
clr.l d0
addx.l d0,d0
ifc \4,b
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
move.b \2,d1
move.w \3,d0
and.l #0x7,d0
lsr.l d0,d1
set_cc0
else
.ifc \4,w
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
lsl.l #8,d1
move.w \2,d1
move.w \3,d0
and.l #0xf,d0
lsr.l d0,d1
set_cc0
.else
bitrev.l d0
move.l \2,d1
lsr.l #1,d1
add.l d0,d1
move.w \3,d0
subq.l #1,d0
and.l #0x1f,d0
lsr.l d0,d1
move.l d1,a1
set_cc1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsl.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
.endm
sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
clr.l d0
addx.l d0,d0
ifc \4,b
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
move.b \2,d1
lsl.l #8,d1
lsl.l #7,d1
move.w \3,d0
and.l #0x7,d0
lsl.l d0,d1
set_cc0
byterev.l d1
else
.ifc \4,w
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
lsl.l #7,d1
mvz.w \2,d0
lsr.l #1,d0
add.l d0,d1
move.w \3,d0
and.l #0xf,d0
lsl.l d0,d1
set_cc0
swap.w d1
.else
move.l \2,d1
lsl.l #1,d1
add.l d0,d1
move.w \3,d0
subq.l #1,d0
and.l #0x1f,d0
lsl.l d0,d1
move.l d1,a1
set_cc1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsr.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
.endm

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/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_shift_lset:.macro
/******************************************************/
// byt
/******************************************************/
// asx.b #,dx
ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,01
ii_lset_dx \1,02
ii_lset_dx \1,03
ii_lset_dx \1,04
ii_lset_dx \1,05
ii_lset_dx \1,06
ii_lset_dx \1,07
// lsx.b #,dx
ii_lset_dxu \1,08
ii_lset_dxu \1,09
ii_lset_dxu \1,0a
ii_lset_dxu \1,0b
ii_lset_dxu \1,0c
ii_lset_dxu \1,0d
ii_lset_dxu \1,0e
ii_lset_dxu \1,0f
// roxx.b #,dx
ii_lset_dx \1,10
ii_lset_dx \1,11
ii_lset_dx \1,12
ii_lset_dx \1,13
ii_lset_dx \1,14
ii_lset_dx \1,15
ii_lset_dx \1,16
ii_lset_dx \1,17
// rox.b #,dx
ii_lset_dx \1,18
ii_lset_dx \1,19
ii_lset_dx \1,1a
ii_lset_dx \1,1b
ii_lset_dx \1,1c
ii_lset_dx \1,1d
ii_lset_dx \1,1e
ii_lset_dx \1,1f
// asx.b dy,dx
ii_lset_dx \1,20
ii_lset_dx \1,21
ii_lset_dx \1,22
ii_lset_dx \1,23
ii_lset_dx \1,24
ii_lset_dx \1,25
ii_lset_dx \1,26
ii_lset_dx \1,27
// lsx.b dy,dx
ii_lset_dx \1,28
ii_lset_dx \1,29
ii_lset_dx \1,2a
ii_lset_dx \1,2b
ii_lset_dx \1,2c
ii_lset_dx \1,2d
ii_lset_dx \1,2e
ii_lset_dx \1,2f
// roxx.dy,dx
ii_lset_dx \1,30
ii_lset_dx \1,31
ii_lset_dx \1,32
ii_lset_dx \1,33
ii_lset_dx \1,34
ii_lset_dx \1,35
ii_lset_dx \1,36
ii_lset_dx \1,37
// rox.b dy,dx
ii_lset_dx \1,38
ii_lset_dx \1,39
ii_lset_dx \1,3a
ii_lset_dx \1,3b
ii_lset_dx \1,3c
ii_lset_dx \1,3d
ii_lset_dx \1,3e
ii_lset_dx \1,3f
/******************************************************/
// word
/******************************************************/
// asx.w #x,dx
ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,41
ii_lset_dx \1,42
ii_lset_dx \1,43
ii_lset_dx \1,44
ii_lset_dx \1,45
ii_lset_dx \1,46
ii_lset_dx \1,47
// lsx.w #,dx
ii_lset_dx \1,48
ii_lset_dx \1,49
ii_lset_dx \1,4a
ii_lset_dx \1,4b
ii_lset_dx \1,4c
ii_lset_dx \1,4d
ii_lset_dx \1,4e
ii_lset_dx \1,4f
// roxx.w #,dx
ii_lset_dx \1,50
ii_lset_dx \1,51
ii_lset_dx \1,52
ii_lset_dx \1,53
ii_lset_dx \1,54
ii_lset_dx \1,55
ii_lset_dx \1,56
ii_lset_dx \1,57
// rox.w #xdx
ii_lset_dx \1,58
ii_lset_dx \1,59
ii_lset_dx \1,5a
ii_lset_dx \1,5b
ii_lset_dx \1,5c
ii_lset_dx \1,5d
ii_lset_dx \1,5e
ii_lset_dx \1,5f
// asx.w dy,dx
ii_lset_dx \1,60
ii_lset_dx \1,61
ii_lset_dx \1,62
ii_lset_dx \1,63
ii_lset_dx \1,64
ii_lset_dx \1,65
ii_lset_dx \1,66
ii_lset_dx \1,67
// lsx.w dy,dx
ii_lset_dx \1,68
ii_lset_dx \1,69
ii_lset_dx \1,6a
ii_lset_dx \1,6b
ii_lset_dx \1,6c
ii_lset_dx \1,6d
ii_lset_dx \1,6e
ii_lset_dx \1,6f
// roxx.w dy,dx
ii_lset_dx \1,70
ii_lset_dx \1,71
ii_lset_dx \1,72
ii_lset_dx \1,73
ii_lset_dx \1,74
ii_lset_dx \1,75
ii_lset_dx \1,76
ii_lset_dx \1,77
// rox.w dy,dx
ii_lset_dx \1,78
ii_lset_dx \1,79
ii_lset_dx \1,7a
ii_lset_dx \1,7b
ii_lset_dx \1,7c
ii_lset_dx \1,7d
ii_lset_dx \1,7e
ii_lset_dx \1,7f
/******************************************************/
// long
/******************************************************/
// roxx.l #,dx
ii_lset_dx \1,90
ii_lset_dx \1,91
ii_lset_dx \1,92
ii_lset_dx \1,93
ii_lset_dx \1,94
ii_lset_dx \1,95
ii_lset_dx \1,96
ii_lset_dx \1,97
// rox.l #xdx
ii_lset_dx \1,98
ii_lset_dx \1,99
ii_lset_dx \1,9a
ii_lset_dx \1,9b
ii_lset_dx \1,9c
ii_lset_dx \1,9d
ii_lset_dx \1,9e
ii_lset_dx \1,9f
// roxx.l dy,dx
ii_lset_dx \1,b0
ii_lset_dx \1,b1
ii_lset_dx \1,b2
ii_lset_dx \1,b3
ii_lset_dx \1,b4
ii_lset_dx \1,b5
ii_lset_dx \1,b6
ii_lset_dx \1,b7
// rox.l dy,dx
ii_lset_dx \1,b8
ii_lset_dx \1,b9
ii_lset_dx \1,ba
ii_lset_dx \1,bb
ii_lset_dx \1,bc
ii_lset_dx \1,bd
ii_lset_dx \1,be
ii_lset_dx \1,bf
//--------------------------------------------------------------------
// asr.w ea
ii_lset_opea \10,d // (ax), (ax)+
ii_lset_opea \10,e // -(ax),d16(ax)
ii_lset_opeag \10,f // d8(ax,dy)
lea table+0x\10\2f8*4,a0
move.l #ii_0x\10f8,(a0)+ // xxx.w
move.l #ii_0x\10f9,(a0)+ // xxx.l
// asl.w ea
ii_lset_opea \11,d // (ax), (ax)+
ii_lset_opea \11,e // -(ax),d16(ax)
ii_lset_opeag \11,f // d8(ax,dy)
lea table+0x\11\2f8*4,a0
move.l #ii_0x\11f8,(a0)+ // xxx.w
move.l #ii_0x\11f9,(a0)+ // xxx.l
// lsr.w ea
ii_lset_opea \12,d // (ax), (ax)+
ii_lset_opea \12,e // -(ax),d16(ax)
ii_lset_opeag \12,f // d8(ax,dy)
lea table+0x\12\2f8*4,a0
move.l #ii_0x\12f8,(a0)+ // xxx.w
move.l #ii_0x\12f9,(a0)+ // xxx.l
// lsr.w ea
ii_lset_opea \13,d // (ax), (ax)+
ii_lset_opea \13,e // -(ax),d16(ax)
ii_lset_opeag \13,f // d8(ax,dy)
lea table+0x\13\2f8*4,a0
move.l #ii_0x\13f8,(a0)+ // xxx.w
move.l #ii_0x\13f9,(a0)+ // xxx.l
// roxr.w ea
ii_lset_opea \14,d // (ax), (ax)+
ii_lset_opea \14,e // -(ax),d16(ax)
ii_lset_opeag \14,f // d8(ax,dy)
lea table+0x\14\2f8*4,a0
move.l #ii_0x\14f8,(a0)+ // xxx.w
move.l #ii_0x\14f9,(a0)+ // xxx.l
// roxl.w ea
ii_lset_opea \15,e // (ax), (ax)+
ii_lset_opea \15,e // -(ax),d16(ax)
ii_lset_opeag \15,f // d8(ax,dy)
lea table+0x\15\2f8*4,a0
move.l #ii_0x\15f8,(a0)+ // xxx.w
move.l #ii_0x\15f9,(a0)+ // xxx.l
// ror.w ea
ii_lset_opea \16,d // (ax), (ax)+
ii_lset_opea \16,e // -(ax),d16(ax)
ii_lset_opeag \16,f // d8(ax,dy)
lea table+0x\16\2f8*4,a0
move.l #ii_0x\16f8,(a0)+ // xxx.w
move.l #ii_0x\16f9,(a0)+ // xxx.l
// rol.w ea
ii_lset_opea \17,d // (ax), (ax)+
ii_lset_opea \17,e // -(ax),d16(ax)
ii_lset_opeag \17,f // d8(ax,dy)
lea table+0x\17\2f8*4,a0
move.l #ii_0x\17f8,(a0)+ // xxx.w
move.l #ii_0x\17f9,(a0)+ // xxx.l
// ende
.endm;
/******************************************************/
ii_shift_op:.macro // 1=code
//byt-------------------------------
//asx.b #x,dx
ii_shift_op2agb 0,as,a
//lsx.b #x,dx
ii_shift_op2aub 0,ls,a
//roxx.b #x,dx
ii_shift_op2agb 1,rox,a
//rox.b #x,dx
ii_shift_op2aub 1,ro,a
//asx.b dy,dx
ii_shift_op2agb 2,as,b
//lsx.b dy,dx
ii_shift_op2aub 2,ls,b
//roxx.b dy,dx
ii_shift_op2agb 3,rox,b
//rox.b dy,dx
ii_shift_op2aub 3,ro,b
// word ---------------------------------------
//asx.w #x,dx
ii_shift_op2agw 4,as,a
//lsx.w #x,dx
ii_shift_op2auw 4,ls,a
//roxx.w #x,dx
ii_shift_op2agw 5,rox,a
//rox.w #x,dx
ii_shift_op2auw 5,ro,a
//asx.w dy,dx
ii_shift_op2agw 6,as,b
//lsx.w dy,dx
ii_shift_op2auw 6,ls,b
//roxx.w dy,dx
ii_shift_op2agw 7,rox,b
//rox.w dy,dx
ii_shift_op2auw 7,ro,b
// long ---------------------------------------
//roxx.l #x,dx
ii_shift_op2agw 9,rox,a
//rox.l #x,dx
ii_shift_op2auw 9,ro,a
//roxx.l dy,dx
ii_shift_op2agw b,rox,b
//rox.l dy,dx
ii_shift_op2auw b,ro,b
// ea ---------------------------------------
//asr.w #1,ea
ii_shift_op2ea 0,asr
//asl.w #1,ea
ii_shift_op2ea 1,asl
//lsr.w #1,ea
ii_shift_op2ea 2,lsr,
//lsl.w #1,ea
ii_shift_op2ea 3,lsl
//roxr.w #1,ea
ii_shift_op2ea 4,roxr
//roxl.w #1,ea
ii_shift_op2ea 5,roxl
//ror.w #1,ea
ii_shift_op2ea 6,ror
//rol.w #1,ea
ii_shift_op2ea 7,rol
.endm
//byt ============================================
ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3b \1,0,\2,d0_off+3(a7)
ii_shift_op1\3b \1,1,\2,d1_off+3(a7)
ii_shift_op1\3b \1,2,\2,d2
ii_shift_op1\3b \1,3,\2,d3
ii_shift_op1\3b \1,4,\2,d4
ii_shift_op1\3b \1,5,\2,d5
ii_shift_op1\3b \1,6,\2,d6
ii_shift_op1\3b \1,7,\2,d7
.endm
ii_shift_op2aub:.macro //byt: 1=code 2=operation
ii_shift_op1\3b \1,8,\2,d0_off+3(a7)
ii_shift_op1\3b \1,9,\2,d1_off+3(a7)
ii_shift_op1\3b \1,a,\2,d2
ii_shift_op1\3b \1,b,\2,d3
ii_shift_op1\3b \1,c,\2,d4
ii_shift_op1\3b \1,d,\2,d5
ii_shift_op1\3b \1,e,\2,d6
ii_shift_op1\3b \1,f,\2,d7
.endm
ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,b,\3r,#8,\4
ii_shift_op0 2\1\2,b,\3r,#1,\4
ii_shift_op0 4\1\2,b,\3r,#2,\4
ii_shift_op0 6\1\2,b,\3r,#3,\4
ii_shift_op0 8\1\2,b,\3r,#4,\4
ii_shift_op0 a\1\2,b,\3r,#5,\4
ii_shift_op0 c\1\2,b,\3r,#6,\4
ii_shift_op0 e\1\2,b,\3r,#7,\4
ii_shift_op0 1\1\2,b,\3l,#8,\4
ii_shift_op0 3\1\2,b,\3l,#1,\4
ii_shift_op0 5\1\2,b,\3l,#2,\4
ii_shift_op0 7\1\2,b,\3l,#3,\4
ii_shift_op0 9\1\2,b,\3l,#4,\4
ii_shift_op0 b\1\2,b,\3l,#5,\4
ii_shift_op0 d\1\2,b,\3l,#6,\4
ii_shift_op0 f\1\2,b,\3l,#7,\4
.endm
ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,b,\3r,d2,\4
ii_shift_op0 6\1\2,b,\3r,d3,\4
ii_shift_op0 8\1\2,b,\3r,d4,\4
ii_shift_op0 a\1\2,b,\3r,d5,\4
ii_shift_op0 c\1\2,b,\3r,d6,\4
ii_shift_op0 e\1\2,b,\3r,d7,\4
ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,b,\3l,d2,\4
ii_shift_op0 7\1\2,b,\3l,d3,\4
ii_shift_op0 9\1\2,b,\3l,d4,\4
ii_shift_op0 b\1\2,b,\3l,d5,\4
ii_shift_op0 d\1\2,b,\3l,d6,\4
ii_shift_op0 f\1\2,b,\3l,d7,\4
.endm
// word ---------------------------------------
ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3w \1,0,\2,d0_off+2(a7)
ii_shift_op1\3w \1,1,\2,d1_off+2(a7)
ii_shift_op1\3w \1,2,\2,d2
ii_shift_op1\3w \1,3,\2,d3
ii_shift_op1\3w \1,4,\2,d4
ii_shift_op1\3w \1,5,\2,d5
ii_shift_op1\3w \1,6,\2,d6
ii_shift_op1\3w \1,7,\2,d7
.endm
ii_shift_op2auw:.macro //byt: 1=code 2=operation
ii_shift_op1\3w \1,8,\2,d0_off+2(a7)
ii_shift_op1\3w \1,9,\2,d1_off+2(a7)
ii_shift_op1\3w \1,a,\2,d2
ii_shift_op1\3w \1,b,\2,d3
ii_shift_op1\3w \1,c,\2,d4
ii_shift_op1\3w \1,d,\2,d5
ii_shift_op1\3w \1,e,\2,d6
ii_shift_op1\3w \1,f,\2,d7
.endm
ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,w,\3r,#8,\4
ii_shift_op0 2\1\2,w,\3r,#1,\4
ii_shift_op0 4\1\2,w,\3r,#2,\4
ii_shift_op0 6\1\2,w,\3r,#3,\4
ii_shift_op0 8\1\2,w,\3r,#4,\4
ii_shift_op0 a\1\2,w,\3r,#5,\4
ii_shift_op0 c\1\2,w,\3r,#6,\4
ii_shift_op0 e\1\2,w,\3r,#7,\4
ii_shift_op0 1\1\2,w,\3l,#8,\4
ii_shift_op0 3\1\2,w,\3l,#1,\4
ii_shift_op0 5\1\2,w,\3l,#2,\4
ii_shift_op0 7\1\2,w,\3l,#3,\4
ii_shift_op0 9\1\2,w,\3l,#4,\4
ii_shift_op0 b\1\2,w,\3l,#5,\4
ii_shift_op0 d\1\2,w,\3l,#6,\4
ii_shift_op0 f\1\2,w,\3l,#7,\4
.endm
ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,w,\3r,d2,\4
ii_shift_op0 6\1\2,w,\3r,d3,\4
ii_shift_op0 8\1\2,w,\3r,d4,\4
ii_shift_op0 a\1\2,w,\3r,d5,\4
ii_shift_op0 c\1\2,w,\3r,d6,\4
ii_shift_op0 e\1\2,w,\3r,d7,\4
ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,w,\3l,d2,\4
ii_shift_op0 7\1\2,w,\3l,d3,\4
ii_shift_op0 9\1\2,w,\3l,d4,\4
ii_shift_op0 b\1\2,w,\3l,d5,\4
ii_shift_op0 d\1\2,w,\3l,d6,\4
ii_shift_op0 f\1\2,w,\3l,d7,\4
.endm
// long ---------------------------------------
ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3l \1,0,\2,d0_off(a7)
ii_shift_op1\3l \1,1,\2,d1_off(a7)
ii_shift_op1\3l \1,2,\2,d2
ii_shift_op1\3l \1,3,\2,d3
ii_shift_op1\3l \1,4,\2,d4
ii_shift_op1\3l \1,5,\2,d5
ii_shift_op1\3l \1,6,\2,d6
ii_shift_op1\3l \1,7,\2,d7
.endm
ii_shift_op2aul:.macro //byt: 1=code 2=operation
ii_shift_op1\3l \1,8,\2,d0_off(a7)
ii_shift_op1\3l \1,9,\2,d1_off(a7)
ii_shift_op1\3l \1,a,\2,d2
ii_shift_op1\3l \1,b,\2,d3
ii_shift_op1\3l \1,c,\2,d4
ii_shift_op1\3l \1,d,\2,d5
ii_shift_op1\3l \1,e,\2,d6
ii_shift_op1\3l \1,f,\2,d7
.endm
ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,l,\3r,#8,\4
ii_shift_op0 2\1\2,l,\3r,#1,\4
ii_shift_op0 4\1\2,l,\3r,#2,\4
ii_shift_op0 6\1\2,l,\3r,#3,\4
ii_shift_op0 8\1\2,l,\3r,#4,\4
ii_shift_op0 a\1\2,l,\3r,#5,\4
ii_shift_op0 c\1\2,l,\3r,#6,\4
ii_shift_op0 e\1\2,l,\3r,#7,\4
ii_shift_op0 1\1\2,l,\3l,#8,\4
ii_shift_op0 3\1\2,l,\3l,#1,\4
ii_shift_op0 5\1\2,l,\3l,#2,\4
ii_shift_op0 7\1\2,l,\3l,#3,\4
ii_shift_op0 9\1\2,l,\3l,#4,\4
ii_shift_op0 b\1\2,l,\3l,#5,\4
ii_shift_op0 d\1\2,l,\3l,#6,\4
ii_shift_op0 f\1\2,l,\3l,#7,\4
.endm
ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,l,\3r,d2,\4
ii_shift_op0 6\1\2,l,\3r,d3,\4
ii_shift_op0 8\1\2,l,\3r,d4,\4
ii_shift_op0 a\1\2,l,\3r,d5,\4
ii_shift_op0 c\1\2,l,\3r,d6,\4
ii_shift_op0 e\1\2,l,\3r,d7,\4
ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,l,\3l,d2,\4
ii_shift_op0 7\1\2,l,\3l,d3,\4
ii_shift_op0 9\1\2,l,\3l,d4,\4
ii_shift_op0 b\1\2,l,\3l,d5,\4
ii_shift_op0 d\1\2,l,\3l,d6,\4
ii_shift_op0 f\1\2,l,\3l,d7,\4
.endm
// .word ea ============================================
ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart
// (a0) bis (a7) ----------------------------
ii_0xe\1d0:
move.l a0_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d1:
move.l a1_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d2:
ii_shift_typ w,\2,#1,(a2),(a2).
ii_0xe\1d3:
ii_shift_typ w,\2,#1,(a3),(a3).
ii_0xe\1d4:
ii_shift_typ w,\2,#1,(a4),(a4).
ii_0xe\1d5:
ii_shift_typ w,\2,#1,(a5),(a5).
ii_0xe\1d6:
ii_shift_typ w,\2,#1,(a6),(a6).
ii_0xe\1d7:
move.l usp,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// (a0)+ bis (a7)+ -----------------------------
ii_0xe\1d8:
move.l a0_off(a7),a1
addq.l #2,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d9:
move.l a1_off(a7),a1
addq.l #2,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1da:
ii_shift_typ w,\2,#1,(a2),(a2)+.
ii_0xe\1db:
ii_shift_typ w,\2,#1,(a3),(a3)+
ii_0xe\1dc:
ii_shift_typ w,\2,#1,(a4),(a4)+
ii_0xe\1dd:
ii_shift_typ w,\2,#1,(a5),(a5)+
ii_0xe\1de:
ii_shift_typ w,\2,#1,(a6),(a6)+
ii_0xe\1df:
move.l usp,a1
addq.l #2,a1
move.l a1,usp
subq.l #2,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// -(a0) bis -(a7) -----------------------------
ii_0xe\1e0:
move.l a0_off(a7),a1
subq.l #2,a1
move.l a1,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e1:
move.l a1_off(a7),a1
subq.l #2,a1
move.l a1,a1_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e2:
ii_shift_typ w,\2,#1,-(a2),(a2).
ii_0xe\1e3:
ii_shift_typ w,\2,#1,-(a3),(a3)
ii_0xe\1e4:
ii_shift_typ w,\2,#1,-(a4),(a4)
ii_0xe\1e5:
ii_shift_typ w,\2,#1,-(a5),(a5)
ii_0xe\1e6:
ii_shift_typ w,\2,#1,-(a6),(a6)
ii_0xe\1e7:
move.l usp,a1
subq.l #2,a1
move.l a1,usp
ii_shift_typ w,\2,#1,(a1),(a1).
// d16(a0) bis d16(a7) -----------------------------
ii_0xe\1e8:
move.w (a0)+,a1
add.l a0_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e9:
move.w (a0)+,a1
add.l a1_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1ea:
move.w (a0)+,a1
add.l a2,a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1eb:
move.w (a0)+,a1
add.l a3,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ec:
move.w (a0)+,a1
add.l a4,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ed:
move.w (a0)+,a1
add.l a5,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ee:
move.w (a0)+,a1
add.l a6,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ef:
mvs.w (a0)+,d0
move.l usp,a1
add.l d0,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// d8(a0,dy) bis d8(a7,dy) -----------------------------
ii_0xe\1f0:
move.l a0_off(a0),a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f1:
move.l a1_off(a0),a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f2:
move.l a2,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f3:
move.l a3,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f4:
move.l a4,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f5:
move.l a5,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f6:
move.l a6,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f7:
move.l usp,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
// xxx.w xxx.l
ii_0xe\1f8:
move.w (a0)+,a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f9:
move.l (a0)+,a1
ii_shift_typ w,\2,#1,(a1),(a1).
.endm
//============================================================================
//subroutine
//------------------------------
ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea
ii_0xe\1:
ii_shift_typ \2,\3,\4,\5,\5
.endm
ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea
ii_0xe\1:
move.l \4,d0
ii_shift_typ \2,\3,d0,\5,\5
.endm
ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest
#ifdef halten
halt
#endif
.ifc asr,\2
mvs.\1 \4,d1
.else
mvz.\1 \4,d1
.endif
.ifc roxr,\2
nop
.else
.ifc roxl,\2
nop
.else
.ifc ror,\2
nop
.else
.ifc rol,\2
nop
.else
\2.l \3,d1
.endif
.endif
.endif
.endif
set_cc0
move.\1 d1,\5
ii_end
.endm

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//--------------------------------------------------------------------
// sub
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// sub.b #im,dx
//--------------------------------------------------------------------
subbir_macro:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
sub.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea,dx
//--------------------------------------------------------------------
subdd:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
subddd:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub (ea)->dy,dx
//--------------------------------------------------------------------
subdda:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea->ay,(ay)+,dx
//--------------------------------------------------------------------
subddai:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea->ay,-(ay),dx
//--------------------------------------------------------------------
subddad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d16(ay),dx
//--------------------------------------------------------------------
subd16ad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d8(ay,dy),dx
//--------------------------------------------------------------------
subd8ad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub xxx.w,dx
//--------------------------------------------------------------------
subxwd:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub xxx.l,dx
//--------------------------------------------------------------------
subxld:.macro
#ifdef halten_sub
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d16(pc),dx
//--------------------------------------------------------------------
subd16pcd:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d8(pc,dy),dx
//--------------------------------------------------------------------
subd8pcd:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// sub dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // sub (ea)->dy,dx
//--------------------------------------------------------------------
subeda:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,(ay)+
//--------------------------------------------------------------------
subedai:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,(ay)+
//--------------------------------------------------------------------
subedaid:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,-(ay)
//--------------------------------------------------------------------
subedad:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,-(ay)
//--------------------------------------------------------------------
subedadd:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,d16(ay)
//--------------------------------------------------------------------
sube16ad:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,d8(ay,dy)
//--------------------------------------------------------------------
sube8ad:.macro
#ifdef halten_sub
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,xxx.w
//--------------------------------------------------------------------
subxwe:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,xxx.l
//--------------------------------------------------------------------
subxle:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// // suba.w ea,ax
//--------------------------------------------------------------------
subaw:.macro
#ifdef halten_sub
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
mvs.w \1,d0
suba.l d0,\2
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// sub.w ea,usp
//--------------------------------------------------------------------
subawa7:.macro
#ifdef halten_sub
halt
#endif
mvs.w \1,d0
move.l usp,a1
sub.l d0,a1
move.l a1,usp
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w usp?,ax
//--------------------------------------------------------------------
subawu:.macro
#ifdef halten_sub
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
move.l a7,_a7_save
move.l usp,a7
move.l \1,d0
suba.l d0,\2
move.l a7,usp
move.l _a7_save,a7
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// // suba.w usp?,usp
//--------------------------------------------------------------------
subawua7:.macro
subawu \1,\2
.endm;
//--------------------------------------------------------------------
// // suba.w d16(ay),ax
//--------------------------------------------------------------------
subawd16a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
adda.l d0,a1
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d8(ay,dy),ax
//--------------------------------------------------------------------
subawd8a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w xxx.w,ax
//--------------------------------------------------------------------
subawxwax:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w xxx.l,ax
//--------------------------------------------------------------------
subawxlax:.macro
#ifdef halten_sub
halt
#endif
move.l (a0)+,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d16(pc),ax
//--------------------------------------------------------------------
subawd16pcax:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
adda.l a0,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d8(pc,dy),ax
//--------------------------------------------------------------------
subawd8pcax:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w #im,ax
//--------------------------------------------------------------------
subawim:.macro
#ifdef halten_sub
halt
#endif
mvs.w \1,d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.l d8(ay,dy),ax
//--------------------------------------------------------------------
subald8a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.l d8(pc,dy),ax
//--------------------------------------------------------------------
subakd8pcax:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//*****************************************************************************************
// subx
//*****************************************************************************************
//--------------------------------------------------------------------
// // subx dy,dx
//--------------------------------------------------------------------
subdx:.macro
#ifdef halten_sub
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
mvs.\3 \2,d0
mvs.\3 \1,d1
subx.l d0,d1
set_cc0
move.\3 d1,\1
ii_end
.endm;
//--------------------------------------------------------------------
// // subx -(ay),-(ax)
//--------------------------------------------------------------------
subdax:.macro
#ifdef halten_sub
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
move.l \1,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d0
.endif
move.l \2,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d1
.endif
subx.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------

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@@ -0,0 +1,328 @@
.public _illegal_instruction
.public _illegal_table_make
.include "startcf.h"
.include "ii_macro.h"
.include "ii_func.h"
.include "ii_op.h"
.include "ii_opc.h"
.include "ii_add.h"
.include "ii_sub.h"
.include "ii_or.h"
.include "ii_and.h"
.include "ii_dbcc.h"
.include "ii_shd.h"
.include "ii_movem.h"
.include "ii_lea.h"
.include "ii_shift.h"
.include "ii_exg.h"
.include "ii_movep.h"
.include "ii_ewf.h"
.include "ii_move.h"
.extern _ii_shift_vec
.extern ewf
/*******************************************************/
.text
ii_error:
nop
halt
nop
nop
_illegal_instruction:
#ifdef ii_on
move.w #0x2700,sr
lea -ii_ss(a7),a7
movem.l d0/d1/a0/a1,(a7)
move.l pc_off(a7),a0 // pc
mvz.w (a0)+,d0 // code
lea table,a1
move.l 0(a1,d0*4),a1
jmp (a1)
/*************************************************************************************************/
#endif
_illegal_table_make:
#ifdef ii_on
lea table,a0
moveq #0,d0
_itm_loop:
move.l #ii_error,(a0)+
addq.l #1,d0
cmp.l #0xF000,d0
bne _itm_loop
//-------------------------------------------------------------------------
ii_ewf_lset // diverse fehlende adressierungn
//-------------------------------------------------------------------------
// 0x0000
// ori
ii_lset_op 00
// andi
ii_lset_op 02
// subi
ii_lset_op 04
// addi
ii_lset_op 06
// eori
ii_lset_op 0a
// cmpi
ii_lset_op 0c
// movep
ii_movep_lset
//-------------------------------------------------------------------------
// 0x1000 move.b
// 0x2000 move.l
// 0x3000 move.w
ii_move_lset
//-------------------------------------------------------------------------
// 0x4000
//-------------------------------------------------------------------------
// negx
ii_lset_op 40
// neg
ii_lset_op 44
// not
ii_lset_op 46
//---------------------------------------------------------------------------------------------
// lea d8(ax,dy.w),az; d8(pc,dy.w),az
//-------------------------------------------------------------------
ii_lea_lset
//-------------------------------------------------------------------
// movem
//-------------------------------------------------------------------
ii_movem_lset
//-------------------------------------------------------------------------
// 0x5000
//-------------------------------------------------------------------------
// addq, subq
ii_lset_op 50
ii_lset_op 51
ii_lset_op 52
ii_lset_op 53
ii_lset_op 54
ii_lset_op 55
ii_lset_op 56
ii_lset_op 57
ii_lset_op 58
ii_lset_op 59
ii_lset_op 5a
ii_lset_op 5b
ii_lset_op 5c
ii_lset_op 5d
ii_lset_op 5e
ii_lset_op 5f
// dbcc
ii_lset_dbcc
// scc
ii_lset_opc 50
ii_lset_opc 51
ii_lset_opc 52
ii_lset_opc 53
ii_lset_opc 54
ii_lset_opc 55
ii_lset_opc 56
ii_lset_opc 57
ii_lset_opc 58
ii_lset_opc 59
ii_lset_opc 5a
ii_lset_opc 5b
ii_lset_opc 5c
ii_lset_opc 5d
ii_lset_opc 5e
ii_lset_opc 5f
//-------------------------------------------------------------------------
// 0x8000 or
//-------------------------------------------------------------------------
ii_lset_func 8
//-------------------------------------------------------------------------
// 0x9000 sub
//-------------------------------------------------------------------------
ii_lset_func 9
//-------------------------------------------------------------------------
// 0xb000
//-------------------------------------------------------------------------
// eor
ii_lset_op b1
ii_lset_op b3
ii_lset_op b5
ii_lset_op b7
ii_lset_op b9
ii_lset_op bb
ii_lset_op bd
ii_lset_op bf
//-------------------------------------------------------------------------
// 0xc000
//-------------------------------------------------------------------------
// and
ii_lset_func c
// exg
ii_exg_lset
//-------------------------------------------------------------------------
// 0xd000 add
//-------------------------------------------------------------------------
ii_lset_func d
//-------------------------------------------------------------------------
// 0xe000
//-------------------------------------------------------------------------
// shift register
ii_shift_lset e
//-------------------------------------------------
// differenz zwischen orginal und gemoved korrigieren
lea ii_error(pc),a1
move.l a1,d1
sub.l #ii_error,d1
lea table,a0
moveq #0,d0
_itkorr_loop:
add.l d1,(a0)+
addq.l #1,d0
cmp.l #0xF000,d0
bne _itkorr_loop
#endif
rts
#ifdef ii_on
//***********************************************************************************/
//-------------------------------------------------------------------------
ii_ewf_func // diverse fehlende adressierungn
//-------------------------------------------------------------------------
//---------------------------------------------------------------------------------------------
// 0x0000
//--------------------------------------------------------------------
// ori 00
ii_op 00,or.l,i
//--------------------------------------------------------------------
// andi 02
ii_op 02,and.l,i
//--------------------------------------------------------------------
// subi 04
ii_op 04,and.l,i
//--------------------------------------------------------------------
// addi 06
ii_op 06,add.l,i
//--------------------------------------------------------------------
// eori 0a
ii_op 0a,eor.l,i
//--------------------------------------------------------------------
// cmpi 0c
ii_op 0c,cmp.l,i
//--------------------------------------------------------------------
// movep
ii_movep_func
///---------------------------------------------------------------------------------------------
// 0x1000 move.b
// 0x2000 move.l
// 0x3000 move.w
ii_move_op
//---------------------------------------------------------------------------------------------
// 0x4000
//---------------------------------------------------------------------------------------------
// neg 0x40..
ii_op 40,negx.l,n
//---------------------------------------------------------------------------------------------
// neg 0x44..
ii_op 44,neg.l,n
//---------------------------------------------------------------------------------------------
// not 0x46..
ii_op 46,not.l,n
//---------------------------------------------------------------------------------------------
// lea d8(ax,dy.w),az; d8(pc,dy.w),az
//-------------------------------------------------------------------
ii_lea_func
//-------------------------------------------------------------------
// movem
//--------------------------------------------------------------------
ii_movem_func
//---------------------------------------------------------------------------------------------
// 0x5000
//---------------------------------------------------------------------------------------------
//dbcc
ii_dbcc_func
// addq 0x5...
ii_op 50,addq.l #8,q
ii_op 52,addq.l #1,q
ii_op 54,addq.l #2,q
ii_op 56,addq.l #3,q
ii_op 58,addq.l #4,q
ii_op 5a,addq.l #5,q
ii_op 5c,addq.l #6,q
ii_op 5e,addq.l #7,q
//---------------------------------------------------------------------------------------------
// subq 0x5...
ii_op 51,subq.l #8,q
ii_op 53,subq.l #1,q
ii_op 55,subq.l #2,q
ii_op 57,subq.l #3,q
ii_op 59,subq.l #4,q
ii_op 5b,subq.l #5,q
ii_op 5d,subq.l #6,q
ii_op 5f,subq.l #7,q
//---------------------------------------------------------------------------------------------
// 0x5... scc
ii_opc 50,st,c
ii_opc 51,sf,c
ii_opc 52,shi,c
ii_opc 53,sls,c
ii_opc 54,scc,c
ii_opc 55,scs,c
ii_opc 56,sne,c
ii_opc 57,seq,c
ii_opc 58,svc,c
ii_opc 59,svs,c
ii_opc 5a,spl,c
ii_opc 5b,smi,c
ii_opc 5c,sge,c
ii_opc 5d,slt,c
ii_opc 5e,sgt,c
ii_opc 5f,sle,c
//---------------------------------------------------------------------------------------------
// 0x6000
//--------------------------------------------------------------------
//---------------------------------------------------------------------------------------------
// 0x7000
//--------------------------------------------------------------------
//---------------------------------------------------------------------------------------------
// 0x8000
//---------------------------------------------------------------------------------------------
// or
ii_func 8,or
//---------------------------------------------------------------------------------------------
// 0x9000
//---------------------------------------------------------------------------------------------
// sub
ii_func 9,sub
//---------------------------------------------------------------------------------------------
// 0xa000
//--------------------------------------------------------------------
//---------------------------------------------------------------------------------------------
// 0xb000
//---------------------------------------------------------------------------------------------
// eor
ii_op b1,eor.l d0,q
ii_op b3,eor.l d1,q
ii_op b5,eor.l d2,q
ii_op b7,eor.l d3,q
ii_op b9,eor.l d4,q
ii_op bb,eor.l d5,q
ii_op bd,eor.l d6,q
ii_op bf,eor.l d7,q
//---------------------------------------------------------------------------------------------
// 0xc000
//---------------------------------------------------------------------------------------------
// and
ii_func c,and
// exg
ii_exg_func
//---------------------------------------------------------------------------------------------
// 0xd000
//---------------------------------------------------------------------------------------------
// add
ii_func d,add
//---------------------------------------------------------------------------------------------
// 0xe000 shift
//--------------------------------------------------------------------
ii_shift_op
//--------------------------------------------------------------------
// 0xf000
//--------------------------------------------------------------------
#endif

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// letztes file der liste
// wichtig als endpunkt des kopierens
void copy_end(void)
{
asm
{
copy_end:
nop
}
}

10
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// letztes file der liste
// wichtig als endpunkt des kopierens
.global copy_end
.text
nop
copy_end:
nop
.asciz 'ende copy';

10
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/*******************************************************/
// allgemeine macros
/*******************************************************/
.text
wait_pll: .macro
wait1_pll\@:
tst.w (a1)
bmi wait1_pll\@
rts
.endm

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/********************************************************************/
/* INIT ACR und MMU /*
/********************************************************************/
.include "startcf.h"
.extern _rt_vbr
.extern _rt_cacr
.extern _rt_asid
.extern _rt_acr0
.extern _rt_acr1
.extern _rt_acr2
.extern _rt_acr3
.extern _rt_mmubar
.extern ___MMUBAR
.extern cpusha
.extern _video_tlb
.extern _video_sbt
/* Register read/write macros */
#define MCF_MMU_MMUCR ___MMUBAR
#define MCF_MMU_MMUOR ___MMUBAR+0x04
#define MCF_MMU_MMUSR ___MMUBAR+0x08
#define MCF_MMU_MMUAR ___MMUBAR+0x10
#define MCF_MMU_MMUTR ___MMUBAR+0x14
#define MCF_MMU_MMUDR ___MMUBAR+0x18
/* Bit definitions and macros for MCF_MMU_MMUCR */
#define MCF_MMU_MMUCR_EN (0x1)
#define MCF_MMU_MMUCR_ASM (0x2)
/* Bit definitions and macros for MCF_MMU_MMUOR */
#define MCF_MMU_MMUOR_UAA (0x1)
#define MCF_MMU_MMUOR_ACC (0x2)
#define MCF_MMU_MMUOR_RW (0x4)
#define MCF_MMU_MMUOR_ADR (0x8)
#define MCF_MMU_MMUOR_ITLB (0x10)
#define MCF_MMU_MMUOR_CAS (0x20)
#define MCF_MMU_MMUOR_CNL (0x40)
#define MCF_MMU_MMUOR_CA (0x80)
#define MCF_MMU_MMUOR_STLB (0x100)
#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_MMU_MMUSR */
#define MCF_MMU_MMUSR_HIT (0x2)
#define MCF_MMU_MMUSR_WF (0x8)
#define MCF_MMU_MMUSR_RF (0x10)
#define MCF_MMU_MMUSR_SPF (0x20)
/* Bit definitions and macros for MCF_MMU_MMUAR */
#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_MMU_MMUTR */
#define MCF_MMU_MMUTR_V (0x1)
#define MCF_MMU_MMUTR_SG (0x2)
#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2)
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
/* Bit definitions and macros for MCF_MMU_MMUDR */
#define MCF_MMU_MMUDR_LK (0x2)
#define MCF_MMU_MMUDR_X (0x4)
#define MCF_MMU_MMUDR_W (0x8)
#define MCF_MMU_MMUDR_R (0x10)
#define MCF_MMU_MMUDR_SP (0x20)
#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6)
#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8)
#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA)
#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V)
#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
.public _mmu_init
.public _mmutr_miss
.text
_mmu_init:
clr.l d0
movec d0,ASID // ASID allways 0
move.l d0,_rt_asid // sichern
movec d0,cacr // cache aus
move.l d0,_rt_cacr // sichern
nop
move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff
movec d0,ACR0
move.l d0,_rt_acr0 // sichern
move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff
movec d0,ACR1
move.l d0,_rt_acr1 // sichern
move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff
movec d0,ACR2
move.l d0,_rt_acr2 // sichern
clr.l d0 // acr3 aus
movec d0,ACR3
move.l d0,_rt_acr3 // sichern
move.l #___MMUBAR+1,d0
movec d0,MMUBAR //mmubar setzen
move.l d0,_rt_mmubar // sichern
nop
move.l #MCF_MMU_MMUOR_CA,d0 // clear all entries,
move.l d0,MCF_MMU_MMUOR
nop
// 0000'0000 locked
moveq.l #0x00000000|std_mmutr,d0
moveq.l #0x00000000|cb_mmudr|MCF_MMU_MMUDR_LK,d1
moveq.l #mmuord_d,d2 // MMU update date
moveq.l #mmuord_i,d3 // MMU update instruction
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // MMU update date
move.l d3,MCF_MMU_MMUOR // MMU update instruction
//---------------------------------------------------------------------------------------
// 00d0'0000 locked ID=6
// video ram: read write execute normal write true
move.l #0x00d00000|MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0
move.l #0x60d00000|wt_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // MMU update date
move.l #0x00d00000|std_mmutr,d0
move.l d3,MCF_MMU_MMUOR // MMU update instruction
move.l #0x2000,d0
move.l d0,_video_tlb // setze page als video page
clr.l _video_sbt // zeit l<EFBFBD>schen
//-------------------------------------------------------------------------------------
// 00e0'0000 locked
move.l #0x00e00000|std_mmutr,d0
move.l #0x00e00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setzen read only ?????? noch nicht
move.l d3,MCF_MMU_MMUOR // setzen
// 00f0'0000 locked
move.l #0x00f00000|std_mmutr,d0
move.l #0xfff00000|nc_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // maped to ffffxxx, precise,
move.l d3,MCF_MMU_MMUOR // maped to ffffxxx, precise,
// 1fe0'0000 locked
move.l #0x1FE00000|std_mmutr,d0
move.l #0x1FE00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setzen data
move.l d3,MCF_MMU_MMUOR // setzen instr
// 1ff0'0000 locked
move.l #0x1FF00000|std_mmutr,d0
move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setzen data
move.l d3,MCF_MMU_MMUOR // setzen instr
// instr 0xFFF0'0000 nach 0x1FF0'0000 umleiten -->> short sprung
/* move.l #0xFFF00000|std_mmutr,d0
move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d3,MCF_MMU_MMUOR // setzen instr
*/
move.l #0xa10ca120,d0
move.l d0,_rt_cacr // sichern
movec d0,cacr
nop
rts
/********************************************************************/
/* MMU table search /*
/********************************************************************/
_mmutr_miss:
bsr cpusha
and.l #0xFFF00000,d0
or.l #std_mmutr,d0
move.l d0,MCF_MMU_MMUTR
and.l #0xFFF00000,d0
or.l #cb_mmudr,d0
move.l d0,MCF_MMU_MMUDR
moveq.l #mmuord_d,d0 // MMU update data
move.l d0,MCF_MMU_MMUOR // setzen
moveq.l #mmuord_i,d0 // MMU update instruction
move.l d0,MCF_MMU_MMUOR // setzen
move.l (sp)+,d0
rte

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// movem
_ii_movem_lset: .macro
// movem rx,xxx.L
ii_lset 0x48f9
// movem rx,-(ax)
// movem (ax)+,rx
ii_lset 0x4cd8
ii_lset 0x4cd9
ii_lset 0x4cda
ii_lset 0x4cdb
ii_lset 0x4cdc
ii_lset 0x4cdd
ii_lset 0x4cde
ii_lset 0x4cdf
// movem xxx.L,rx
ii_lset 0x4cf9
.endm
//***********************************************************************************/
_ii_movem_func: .macro
//-------------------------------------------------------------------
// movem.l
//--------------------------------------------------------------------
// movem.l (ax)+,reg
//--------------------------------------------------------------------
//-------------------------------------------------------------------------------
ii_0x4cd8: // movem.l (a0)+,reglist
mvm_macro 0x4cd0,0x41e8,2
ii_0x4cd9: // movem.l (a1)+,reglist
mvm_macro 0x4cd1,0x43e9,2
ii_0x4cda: // movem.l (a2)+,reglist
mvm_macro 0x4cd2,0x45ea,2
ii_0x4cdb: // movem.l (a3)+,reglist
mvm_macro 0x4cd3,0x47eb,2
ii_0x4cdc: // movem.l (a4)+,reglist
mvm_macro 0x4cd4,0x49ec,2
ii_0x4cdd: // movem.l (a5)+,reglist
mvm_macro 0x4cd5,0x4bed,2
ii_0x4cde: // movem.l (a6)+,reglist
mvm_macro 0x4cd6,0x4dee,2
ii_0x4cdf: // movem.l (a7)+,reglist
mvm_macro 0x4cd7,0x4fef,2
//----------------------------------------------------------------------------
ii_0x48f9: // movem.l reg,xxx.L
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro
ii_end
//---------------------------------------------------------------------------------------------
ii_0x4cf9: // movem.l xxx.L,reg
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro
ii_end
.endm
//==============================================================
mvm_macro:.macro
halt
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x (ax),reg_list
move.w (a0)+,(a1)+ // register list
move.w #\2,(a1)+ // lea 0(ax),ax
lsl.l #\3,d1 // * anzahl byts pro wert
move.w d1,(a1)+ // offset von lea
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
.long 0
az_reg_table:
.byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0
.byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0
//---------------------------------------------------------------------------------
movemrm_macro:.macro // in d0 register liste, in a1 zieladresse
halt
tst.b d0 // datenregister zu verschieben?
bne mrm_dx // ja->
lsr.l #8,d0 // sonst zu addressregister
jmp mmrm_nd7 // ->
mrm_dx:
lsr.l #1,d0
bcc mmrm_nd0
move.l d0_off(a7),(a1)+
mmrm_nd0:
lsr.l #1,d0
bcc mmrm_nd1
move.l d1_off(a7),(a1)+
mmrm_nd1:
lsr.l #1,d0
bcc mmrm_nd2
move.l d2,(a1)+
mmrm_nd2:
lsr.l #1,d0
bcc mmrm_nd3
move.l d3,(a1)+
mmrm_nd3:
lsr.l #1,d0
bcc mmrm_nd4
move.l d4,(a1)+
mmrm_nd4:
lsr.l #1,d0
bcc mmrm_nd5
move.l d5,(a1)+
mmrm_nd5:
lsr.l #1,d0
bcc mmrm_nd6
move.l d6,(a1)+
mmrm_nd6:
lsr.l #1,d0
bcc mmrm_nd7
move.l d7,(a1)+
mmrm_nd7:
tst.b d0 // addressregister zu verschieben?
beq mmrm_na7
lsr.l #1,d0
bcc mmrm_na0
move.l a0_off(a7),(a1)+
mmrm_na0:
lsr.l #1,d0
bcc mmrm_na1
move.l a1_off(a7),(a1)+
mmrm_na1:
lsr.l #1,d0
bcc mmrm_na2
move.l a2,(a1)+
mmrm_na2:
lsr.l #1,d0
bcc mmrm_na3
move.l a3,(a1)+
mmrm_na3:
lsr.l #1,d0
bcc mmrm_na4
move.l a4,(a1)+
mmrm_na4:
lsr.l #1,d0
bcc mmrm_na5
move.l a5,(a1)+
mmrm_na5:
lsr.l #1,d0
bcc mmrm_na6
move.l a6,(a1)+
mmrm_na6:
lsr.l #1,d0
bcc mmrm_na7
move.l a0,d1 // sichern
move.l usp,a0 // ist ja usp
move.l a0,(a1)+ // nach a0
move.l d1,a0 // pc zur<75>ck
mmrm_na7:
.endm
//---------------------------------------------------------------------------------------------
movemmr_macro:.macro // in d0 register liste, in a1 source adr
halt
tst.b d0 // datenregister zu verschieben?
bne mmr_dx // ja->
lsr.l #8,d0 // sonst zu addressregister
bra mmmr_nd7 // ->
mmr_dx:
lsr.l #1,d0
bcc mmmr_nd0
move.l (a1)+,d0_off(a7)
mmmr_nd0:
lsr.l #1,d0
bcc mmmr_nd1
move.l (a1)+,d1_off(a7)
mmmr_nd1:
lsr.l #1,d0
bcc mmmr_nd2
move.l (a1)+,d2
mmmr_nd2:
lsr.l #1,d0
bcc mmmr_nd3
move.l (a1)+,d3
mmmr_nd3:
lsr.l #1,d0
bcc mmmr_nd4
move.l (a1)+,d4
mmmr_nd4:
lsr.l #1,d0
bcc mmmr_nd5
move.l (a1)+,d5
mmmr_nd5:
lsr.l #1,d0
bcc mmmr_nd6
move.l (a1)+,d6
mmmr_nd6:
lsr.l #1,d0
bcc mmmr_nd7
move.l (a1)+,d7
mmmr_nd7:
tst.b d0 // addressregister zu verschieben?
beq mmmr_na7 // nein->
lsr.l #1,d0
bcc mmmr_na0
move.l (a1)+,a0_off(a7)
mmmr_na0:
lsr.l #1,d0
bcc mmmr_na1
move.l (a1)+,a1_off(a7)
mmmr_na1:
lsr.l #1,d0
bcc mmmr_na2
move.l (a1)+,a2
mmmr_na2:
lsr.l #1,d0
bcc mmmr_na3
move.l (a1)+,a3
mmmr_na3:
lsr.l #1,d0
bcc mmmr_na4
move.l (a1)+,a4
mmmr_na4:
lsr.l #1,d0
bcc mmmr_na5
move.l (a1)+,a5
mmmr_na5:
lsr.l #1,d0
bcc mmmr_na6
move.l (a1)+,a6
mmmr_na6:
lsr.l #1,d0
bcc mmmr_na7
move.l a0,d1 // sichern
move.l (a1)+,a0 // nach a0
move.l a0,usp // war ja usp
move.l d1,a0 // pc zur<75>ck
mmmr_na7:
.endm

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/********************************************************************/
// sd card
/********************************************************************/
#define __MBAR 0xff000000
#define MCF_SLT0_SCNT __MBAR + 0x908
#define MCF_PSC0_PSCTB_8BIT __MBAR + 0x860C
#define MCF_PAD_PAR_DSPI __MBAR + 0xA50
#define MCF_DSPI_DMCR __MBAR + 0x8A00 //dspi control
#define dspi_dtar0 0x0c
#define dspi_dsr 0x2c
#define dspi_dtfr 0x34
#define dspi_drfr 0x38
#define time1us 1320
void wait_10ms(void)
{
asm
{
warte_10ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void sd_com(void) // byt senden und holen ---------------------
{
asm
{
move.l d4,dspi_dtfr(a0)
wait_auf_complett:
btst.b #7,dspi_dsr(a0)
beq wait_auf_complett
move.l dspi_drfr(a0),d5
mov3q.l #-1,dspi_dsr(a0) // clr status register
}
}
void sd_get_status(void) // status holen -------------------------------
{
asm
{
sd_get_status:
move.b #0xff,d4
bsr sd_com
cmp.b #0xff,d5
beq sd_get_status
}
}
void sd_rcv_info(void) // daten holen ----------------------------
{
asm
{
moveq #18,d3 // 16 byts + 2 byts crc
move.b #0xff,d4
sd_rcv_rb_w:
bsr sd_get_status
cmp.b #0xfe,d5 // daten bereit?
bne sd_rcv_rb_w // nein->
sd_rcv_rd_rb:
bsr sd_com
move.b d5,(a2)+
subq.l #1,d3
bne sd_rcv_rd_rb
}
}
void sd_card_idle(void)
{
asm
{
// sd idle
// speed =400kHz
move.l #0x082000ff,d4 // tx vorbesetzen
lea MCF_DSPI_DMCR,a0
move.l #0x38558897,d0
move.l d0,dspi_dtar0(a0) // 400kHz
move.b #0xff,d4
bsr sd_com // clocks
move.b #0x40,d4 // cmd idle
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
}
}
int sd_card_init(void)
{
long az_sectors;
asm
{
lea MCF_PSC0_PSCTB_8BIT,a1
move.l #'SD-C',(a1)
move.l #'ard ',(a1)
move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!)
move.l #0x1fffffff,d0 // normal dspi
move.l d0,MCF_PAD_PAR_DSPI
lea MCF_DSPI_DMCR,a0
move.l #0x802d3c00,(a0) // 8 bit cs off clear fifo
move.l #0x38558897,d0
move.l d0,dspi_dtar0(a0) // 400kHz
move.l #0x082000ff,d4 // tx vorbesetzen
move.l d4,dspi_dtfr // und setzen
mov3q.l #-1,dspi_dsr(a0) // status register l<>schen
move.l #0xc00d3c00,(a0) // clock on cs ist on
bsr wait_10ms
move.l #0x802d3c00,(a0) // clock off cs off
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
move.l #0x800d3c00,(a0) // cs on
bsr sd_com
bsr sd_com
move.l #0x802d3c00,(a0) // cs off
bsr sd_com
bsr sd_com
bsr wait_10ms
// sd idle
move.l #100,d6 // 100 versuche
move.l #10,d3 // 10 versuche
sd_idle:
bsr sd_card_idle
move.l #10,d7
move.b #0xff,d4
sd_idle_leeren:
bsr sd_com
cmp.b #0x01,d5
beq idle_end
subq.l #1,d7
bne sd_idle_leeren
subq.l #1,d6
beq sd_not
bra sd_idle
idle_end:
// cdm 8
read_ic:
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x48,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
move.b #0xaa,d4
bsr sd_com
move.b #0x87,d4
bsr sd_com
bsr sd_get_status
cmp.b #5,d5
beq sd_v1
cmp.b #1,d5
bne read_ic
bsr sd_com // 4byts zum wegwerfen
bsr sd_com
bsr sd_com
bsr sd_com
cmp.b #0xaa,d5 // pattern zur<75>ckgekommen?
bne sd_testd3 // nein ->
move.l #'SDHC',(a1)
move.b #' ',(a1)
sd_v1:
// cdm 58
read_ocr:
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x7a,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
bsr sd_get_status
move.l #'Ver1',d6
cmp.b #5,d5
beq read_ocr
cmp.b #1,d5
bne read_ocr
bsr sd_com // 4 byts zum wegwerfen
bsr sd_com
bsr sd_com
bsr sd_com
// acdm 41
move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen
wait_of_aktiv:
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x77,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
bsr sd_get_status
cmp.b #0x05,d5
beq wait_of_aktiv
wait_of_aktiv2:
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x69,d4
bsr sd_com
move.b #0x40,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
bsr sd_get_status
tst.b d5
beq sd_init_ok
cmp.b #0x05,d5
beq wait_of_aktiv2
subq.l #1,d6
bne wait_of_aktiv
sd_testd3:
subq.l #1,d3
bne sd_idle
bra sd_error
sd_init_ok:
// fullspeed
move.l #0x38551120,d0 // 22Mbit/sec
move.l d0,dspi_dtar0(a0) // setzen
// cdm 10
read_cid:
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x4a,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
move.l a5,a2 // adresse setzen
bsr sd_rcv_info
// name ausgeben
lea 1(a5),a2
moveq #7,d7
sd_nam_loop:
move.b (a2)+,(a1)
subq.l #1,d7
bne sd_nam_loop
move.b #' ',(a1)
// cdm 9
read_csd:
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x49,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
move.l a5,a2 // adresse setzen
bsr sd_rcv_info
mvz.b (a5),d0
lsr.l #6,d0
bne sd_csd2 // format v2
move.l 6(a5),d1
moveq #14,d0 // bit 73..62 c_size
lsr.l d0,d1 // bits extrahieren
and.l #0xfff,d1 // 12 bits
addq.l #1,d1
mvz.w 9(a5),d0
lsr.l #7,d0 // bits 49..47
and.l #0x7,d0 // 3 bits
moveq.l #8,d2 // x256 (dif v1 v2)
sub.l d0,d2
lsr.l d2,d1
bra sd_print_size
sd_csd2:
mvz.w 8(a5),d1
addq.l #1,d1
sd_print_size:
swap d1
move.l d1,d3
lsr.l #6,d3 //x65636 /64 -> anzahl sectors
move.l d3,az_sectors
lsl.l #1,d1
bcc sd_16G
move.l #'32GB',(a1)
bra sd_ok
sd_16G:
lsl.l #1,d1
bcc sd_8G
move.l #'16GB',(a1)
bra sd_ok
sd_8G:
lsl.l #1,d1
bcc sd_4G
move.l #' 8GB',(a1)
bra sd_ok
sd_4G:
lsl.l #1,d1
bcc sd_2G
move.l #' 4GB',(a1)
bra sd_ok
sd_2G:
lsl.l #1,d1
bcc sd_1G
move.l #' 2GB',(a1)
bra sd_ok
sd_1G:
lsl.l #1,d1
bcc sd_512M
move.l #' 1GB',(a1)
bra sd_ok
sd_512M:
lsl.l #1,d1
bcc sd_256M
move.b #'5',(a1)
move.l #'12MB',(a1)
bra sd_ok
sd_256M:
lsl.l #1,d1
bcc sd_128M
move.b #'2',(a1)
move.l #'56MB',(a1)
bra sd_ok
sd_128M:
lsl.l #1,d1
bcc sd_64M
move.b #'1',(a1)
move.l #'28MB',(a1)
bra sd_ok
sd_64M:
lsl.l #1,d1
bcc sd_32M
move.l #'64MB',(a1)
bra sd_ok
sd_32M:
lsl.l #1,d1
bcc sd_16M
move.l #'32MB',(a1)
bra sd_ok
sd_16M:
lsl.l #1,d1
bcc sd_8M
move.l #'16MB',(a1)
bra sd_ok
sd_8M:
move.l #'<9MB',(a1)
sd_ok:
move.l #' OK!',(a1)
move.l #0x0a0d,(a1)
bra sd_c_ok
// subs ende -------------------------------
sd_error:
move.l #'Erro',(a1)
move.l #'r!',(a1)
move.l #0x0a0d,(a1)
bra sd_c_error
sd_not:
move.l #'non!',(a1)
move.l #0x0a0d,(a1)
bra sd_c_not
buffer: dc.l 0,0,0,0,0,0,0,0
}
sd_c_ok:
return az_sectors;
sd_c_not:
return -2;
sd_c_error:
return -1;
}
void sd_rcv_sector(void) // 1 sector daten holen ----------------------------
{
asm
{
bsr sd_get_status
cmp.b #0xfe,d5 // daten bereit?
bne sd_rs_end // nein-> error
move.l #512,d3 // sonst 512 byts abholen
sd_rs_loop:
bsr sd_com
move.b d5,(a2)+
subq.l #1,d3
bne sd_rs_loop
// crc holen
bsr sd_com
bsr sd_com
clr.l d5 // alles ok
sd_rs_end:
}
}
int sd_card_sector_read(long sec_nr,long buf_adr)
{
int status ;
asm
{
lea MCF_DSPI_DMCR,a0
move.l #0x082000ff,d4 // tx vorbesetzen
move.l sec_nr,d0
move.l buf_adr,a2
lsl.l #8,d0
add.l d0,d0 // x 512 !
move.l d0,d1 // byts kehren
swap d1
move.l d1,d2
lsr.l #8,d1
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x51,d4
bsr sd_com
move.b d1,d4
bsr sd_com
move.b d2,d4
bsr sd_com
move.l d0,d2
lsr.l #8,d2
move.b d2,d4
bsr sd_com
move.b d0,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
clr.l d5 // alles auf no error
clr.l status
bsr sd_get_status // status holen
tst.b d5
bne sd_csr_end // wenn nicht ok -> weg
// sector holen
bsr sd_rcv_sector
sd_csr_end:
tst.b d5
beq sd_csr_ok
neg.l d5 // wenn nicht ok status auf negativ
move.l d5,status
sd_csr_ok:
}
return status;
}
void sd_send_sector(void) // 1 sector daten senden ----------------------------
{
asm
{
move.l #512,d3
move.b #0xfe,d4 // start token
bsr sd_com // senden
sd_send_wr_wb:
move.b (a2)+,d4 // data
bsr sd_com // senden
subq.l #1,d3
bne sd_send_wr_wb
// send crc
move.b #1,d4
bsr sd_com // crc 1.byt
move.b #1,d4
bsr sd_com // crc 2.byt
sd_send_wr_ww:
bsr sd_get_status
and.l #0x1f,d5
clr.l d6 //status auf OK
cmp.b #5,d5 //data accepted?
beq sd_send_end //ja ->
move.l d5,d6 //sonst status sichern
sd_send_end:
bsr sd_com
tst.b d5 // warte auf geschrieben
beq sd_send_end
move.l d6,d5 // status zur<75>ck
}
}
int sd_card_sector_write(long sec_nr,long buf_adr)
{
int status;
asm
{
lea MCF_DSPI_DMCR,a0
move.l #0x082000ff,d4 // tx vorbesetzen
move.l sec_nr,d0
move.l buf_adr,a2
lsl.l #8,d0
add.l d0,d0 // x 512 !
move.l d0,d1 // byts kehren
swap d1
move.l d1,d2
lsr.l #8,d1
move.b #0xff,d4 // clocks
bsr sd_com
move.b #0x58,d4
bsr sd_com
move.b d1,d4
bsr sd_com
move.b d2,d4
bsr sd_com
move.l d0,d2
lsr.l #8,d2
move.b d2,d4
bsr sd_com
move.b d0,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
clr.l d5 // alles auf no error
clr.l status
bsr sd_get_status // status holen
tst.b d5
bne sd_csw_end // wenn nicht ok -> weg
// sector schreiben
bsr sd_send_sector
sd_csw_end:
tst.b d5
beq sd_csw_ok
neg.l d5 // wenn nicht ok status auf negativ
move.l d5,status
sd_csw_ok:
}
return status;
}

406
BaS_GNU/BaS_codewarrior/firebeeV1/sources/sd_card.s Normal file
View File

@@ -0,0 +1,406 @@
/********************************************************************/
// sd card
/********************************************************************/
#define dspi_dtar0 0x0c
#define dspi_dsr 0x2c
#define dspi_dtfr 0x34
#define dspi_drfr 0x38
.text
sd_test:
lea MCF_PSC0_PSCTB_8BIT,a6
move.l #'SD-C',(a6)
move.l #'ard ',(a6)
move.l #__Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!)
move.l #0x1fffffff,d0 // normal dspi
move.l d0,MCF_PAD_PAR_DSPI
lea MCF_DSPI_DMCR,a0
move.l #0x800d3c00,(a0) // 8 bit cs5 on
move.l #0x38558897,d0
move.l d0,dspi_dtar0(a0) // 400kHz
move.l #0x082000ff,d4 // tx vorbesetzen
mov3q.l #-1,dspi_dsr(a0)
bsr warte_1ms
move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off
bsr warte_10ms
move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off
clr.b d4
bsr sd_com
bsr sd_com
move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on
move.b #0xff,d4
bsr sd_com
bsr sd_com
move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off
bsr warte_10ms
// sd idle
move.l #100,d6 // 100 versuche
move.l #10,d3 // 10 versuche
sd_idle:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x40,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
move.b #0xff,d4 // receive byt
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
subq.l #1,d6
beq sd_not
bra sd_idle
idle_end:
// cdm 8
read_ic:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x48,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
move.b #0xaa,d4
bsr sd_com
move.b #0x87,d4
bsr sd_com
bsr sd_get_status
cmp.b #5,d5
beq sd_v1
cmp.b #1,d5
bne read_ic
move.b #0xff,d4
bsr sd_com
move.b d5,d0
bsr sd_com
move.b d5,d1
bsr sd_com
move.b d5,d2
bsr sd_com
cmp.b #0xaa,d5
bne sd_testd3
move.l #'SDHC',(a6)
move.b #' ',(a6)
sd_v1:
// cdm 58
read_ocr:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x7a,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
bsr sd_get_status
move.l #'Ver1',d6
cmp.b #5,d5
beq read_ocr
cmp.b #1,d5
bne read_ocr
move.b #0xff,d4
bsr sd_com
move.b d5,d0
bsr sd_com
move.b d5,d1
bsr sd_com
move.b d5,d2
bsr sd_com
// acdm 41
move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen
wait_of_aktiv:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x77,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
bsr sd_get_status
cmp.b #0x05,d5
beq wait_of_aktiv
wait_of_aktiv2:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x69,d4
bsr sd_com
move.b #0x40,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
bsr sd_get_status
tst.b d5
beq sd_init_ok
cmp.b #0x05,d5
beq wait_of_aktiv2
subq.l #1,d6
bne wait_of_aktiv
sd_testd3:
subq.l #1,d3
bne sd_idle
bra sd_error
sd_init_ok:
// cdm 10
read_cid:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x4a,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
move.l a5,a4 // adresse setzen
bsr sd_rcv_info
// name ausgeben
lea 1(a5),a4
moveq #7,d7
sd_nam_loop:
move.b (a4)+,(a6)
subq.l #1,d7
bne sd_nam_loop
move.b #' ',(a6)
// cdm 9
read_csd:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x49,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
move.l a5,a4 // adresse setzen
bsr sd_rcv_info
mvz.b (a5),d0
lsr.l #6,d0
bne sd_csd2 // format v2
move.l 6(a5),d1
moveq #14,d0 // bit 73..62 c_size
lsr.l d0,d1 // bits extrahieren
and.l #0xfff,d1 // 12 bits
addq.l #1,d1
mvz.w 9(a5),d0
lsr.l #7,d0 // bits 49..47
and.l #0x7,d0 // 3 bits
moveq.l #8,d2 // x256 (dif v1 v2)
sub.l d0,d2
lsr.l d2,d1
bra sd_print_size
sd_csd2:
mvz.w 8(a5),d1
addq.l #1,d1
sd_print_size:
swap d1
lsl.l #1,d1
bcc sd_16G
move.l #'32GB',(a6)
bra sd_ok
sd_16G:
lsl.l #1,d1
bcc sd_8G
move.l #'16GB',(a6)
bra sd_ok
sd_8G:
lsl.l #1,d1
bcc sd_4G
move.l #' 8GB',(a6)
bra sd_ok
sd_4G:
lsl.l #1,d1
bcc sd_2G
move.l #' 4GB',(a6)
bra sd_ok
sd_2G:
lsl.l #1,d1
bcc sd_1G
move.l #' 2GB',(a6)
bra sd_ok
sd_1G:
lsl.l #1,d1
bcc sd_512M
move.l #' 1GB',(a6)
bra sd_ok
sd_512M:
lsl.l #1,d1
bcc sd_256M
move.b #'5',(a6)
move.l #'12MB',(a6)
bra sd_ok
sd_256M:
lsl.l #1,d1
bcc sd_128M
move.b #'2',(a6)
move.l #'56MB',(a6)
bra sd_ok
sd_128M:
lsl.l #1,d1
bcc sd_64M
move.b #'1',(a6)
move.l #'28MB',(a6)
bra sd_ok
sd_64M:
lsl.l #1,d1
bcc sd_32M
move.l #'64MB',(a6)
bra sd_ok
sd_32M:
lsl.l #1,d1
bcc sd_16M
move.l #'32MB',(a6)
bra sd_ok
sd_16M:
lsl.l #1,d1
bcc sd_8M
move.l #'16MB',(a6)
bra sd_ok
sd_8M:
move.l #'<9MB',(a6)
sd_ok:
move.l #' OK!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
// subs ende -------------------------------
sd_V1:
move.l #'non!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
sd_error:
move.l #'Erro',(a6)
move.l #'r!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
sd_not:
move.l #'non!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
// status holen -------------------------------
sd_get_status:
move.b #0xff,d4
bsr sd_com
cmp.b #0xff,d5
beq sd_get_status
rts
// byt senden und holen ---------------------
sd_com:
move.l d4,dspi_dtfr(a0)
wait_auf_complett:
btst.b #7,dspi_dsr(a0)
beq wait_auf_complett
move.l dspi_drfr(a0),d5
mov3q.l #-1,dspi_dsr(a0) // clr status register
rts
// daten holen ----------------------------
sd_rcv_info:
moveq #18,d3 // 16 byts + 2 byts crc
move.b #0xff,d4
sd_rcv_rb_w:
bsr sd_get_status
cmp.b #0xfe,d5 // daten bereit?
bne sd_rcv_rb_w // nein->
sd_rcv_rd_rb:
bsr sd_com
move.b d5,(a4)+
subq.l #1,d3
bne sd_rcv_rd_rb
rts
/******************************************/

543
BaS_GNU/BaS_codewarrior/firebeeV1/sources/sd_ide.c Normal file
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#include "MCF5475.h"
#include "startcf.h"
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
/* imported routines */
//extern int warten_20ms();
//extern int warten_200us();
//extern int warten_10us();
/********************************************************************/
void asm sd_test(void)
{
clr.w MCF_PAD_PAR_DSPI
lea MCF_GPIO_PPDSDR_DSPI,a2 // data in
lea MCF_GPIO_PODR_DSPI,a1 // data out
move.b #0x00,(a1) // alle auf 0
lea MCF_GPIO_PDDR_DSPI,a0
move.b #0x7d,(a0) // din = input rest output
bsr warten_20ms
move.b #0x7f,(a1) // alle auf 1
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
// sd idle
sd_idle:
bsr sd_16clk
moveq #0x40,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x95,d4
bsr sd_com
bsr sd_receive
cmp.b #0x05,d5
beq sd_test
cmp.b #0x01,d5
beq wait_of_aktiv
cmp.b #0x04,d5
beq sd_init_ok
cmp.b #0x00,d5
beq sd_init_ok
bra sd_idle
// acdm 41
wait_of_aktiv:
bsr sd_16clk
moveq #0x77,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
bsr sd_16clk
move.l #0xff,d6
moveq #0x69,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x02,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x01,d4
bsr sd_com
and d5,d6
bsr sd_receive
cmp.b #0x00,d5
beq sd_init_ok
cmp.b #0x05,d5
beq sd_test
bra wait_of_aktiv
sd_init_ok:
// blockgr<67>sse 512byt
sd_bg:
bsr sd_16clk
moveq #0x50,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #02,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_bg
// read block
sd_rb:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb
lea 0xc00000,a4
move.l #513,d7
rd_rb:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb
// write block
sd_wb:
bsr sd_16clk
moveq #0x58,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_wb
lea 0xc00000,a4
move.l #513,d7
moveq.l #0x66,d4
wr_wb:
bsr sd_com
// subq.l #1,d4
moveq #0x66,d4
subq.l #1,d7
bne wr_wb
bsr sd_receive
wr_wb_el:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
bne wr_wb_el
// read block 2
sd_rb2:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb2
lea 0xc00400,a4
move.l #513,d7
rd_rb2:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb2
nop
nop
rts
sd_receive:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
beq sd_receive
rts
sd_com:
bclr.b #6,(a1)
sd_comb:
bsr warten_10us
moveq #7,d2
clr.l d5
sd_com_loop:
btst d2,d4
beq sd_com2
bset.b #0,(a1)
bra sd_com2_1
sd_com2:
bclr.b #0,(a1)
sd_com2_1:
bsr sd_clk
and.l #0x02,d3
beq sd_com3
bset.b d2,d5
sd_com3:
subq.l #1,d2
bge sd_com_loop
bsr warten_10us
bset.b #6,(a1)
bset.b #0,(a1)
bsr warten_200us
rts
sd_clk:
tst.b 0xfffff700
tst.b 0xfffff700
bset.b #2,(a1)
tst.b 0xfffff700
tst.b 0xfffff700
move.b (a2),d3
tst.b 0xfffff700
bclr.b #2,(a1)
rts
sd_15clk:
move #15,d0
bra sd_16clk
sd_16clk:
moveq #16,d0
sd_16clk1:
bsr sd_clk
subq.l #1,d0
bne sd_16clk1
bsr warten_10us
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
}
/**************************************************/
void asm ide_test(void)
{
lea MCF_PAD_PAR_DSPI,a0
move.w #0x1fff,(a0)
lea MCF_DSPI_DCTAR0,a0
move.l #0x38a644e4,(a0)
lea MCF_DSPI_DMCR,a0
move.l #0x802d3c00,(a0)
clr.l MCF_DSPI_DTCR
bsr warten_20ms
lea MCF_DSPI_DTFR,a0
lea MCF_DSPI_DRFR,a1
moveq #10,d0
sd_reset:
move.l #0x000100ff,(a0)
bsr warten_20ms
and.l (a1),d0
subq.l #1,d0
bne sd_reset
moveq #10,d1
sd_loop1:
bsr warten_20ms
moveq #-1,d0
// cmd 0 set to idle
move.l #0x00200040,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200095,(a0)
bsr warten_20ms
and.l (a1),d0
cmp.w #0x0001,d0
beq sd_loop2
subq.l #1,d1
bne sd_loop1
moveq #10,d1
bra sd_test
sd_loop2:
moveq #-1,d0
// cmd 41
move.l #0x00200069,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200000,(a0)
bsr warten_20ms
and.l (a1),d0
move.l #0x00200001,(a0)
bsr warten_20ms
and.l (a1),d0
tst.w d0
bne sd_loop2
nop
nop
/********************************************************************/
#define cmd_reg (0x1d)
#define status_reg (0x1d)
#define seccnt (0x09)
ide_test:
lea 0xfff00040,a0
lea 0xc00000,a1
move.b #0xec,cmd_reg(a0) //identify devcie cmd
bsr wait_int
bsr ds_rx
// read sector normal
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read cmd
bsr wait_int
bsr ds_rx
// write testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write cmd
bsr drq_wait
// write pattern
move.l #256,d0
ide_test_loop3:
move.w #0xa55a,(a0)
subq.l #1,d0
bne ide_test_loop3
bsr wait_int
// read testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read
bsr wait_int
bsr ds_rx
// sector restauriern
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write
lea -0x400(a1),a1 // vorletzer
bsr drq_wait
bsr ds_tx
bsr wait_int
// fertig und zur<75>ck
nop
rts
// wait auf int
wait_int:
move.b 0xfffffa01,d0
btst.b #5,d0
bne wait_int
move.b status_reg(a0),d0
rts
// wait auf drq
drq_wait:
move.b status_reg(a0),d0
btst #3,d0
beq drq_wait
rts
// 1 sector lesen word
ds_rx:
move.l #256,d0
ds_rx_loop:
move.w (a0),(a1)+
subq.l #1,d0
bne ds_rx_loop
rts
// 1 sector lesen long
ds_rxl:
move.l #128,d0
ds_rxl_loop:
move.l (a0),(a1)+
subq.l #1,d0
bne ds_rxl_loop
rts
// 1 sector schreiben word
ds_tx:
move.l #256,d0
ds_tx_loop:
move.w (a1)+,(a0)
subq.l #1,d0
bne ds_tx_loop
rts
// 1 sector schreiben word
ds_txl:
move.l #128,d0
ds_txl_loop:
move.l (a1)+,(a0)
subq.l #1,d0
bne ds_txl_loop
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
}
/********************************************************************/

458
BaS_GNU/BaS_codewarrior/firebeeV1/sources/sd_ide.s Normal file
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@@ -0,0 +1,458 @@
//.include "startcf.h"
//.extern ___MBAR
//#define MCF_SLT0_SCNT ___MBAR+0x908
//.global ide_test
.text
/*
sd_test:
clr.w MCF_PAD_PAR_DSPI
lea MCF_GPIO_PPDSDR_DSPI,a2 // data in
lea MCF_GPIO_PODR_DSPI,a1 // data out
move.b #0x00,(a1) // alle auf 0
lea MCF_GPIO_PDDR_DSPI,a0
move.b #0x7d,(a0) // din = input rest output
bsr warten_20ms
move.b #0x7f,(a1) // alle auf 1
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
// sd idle
sd_idle:
bsr sd_16clk
moveq #0x40,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x95,d4
bsr sd_com
bsr sd_receive
cmp.b #0x05,d5
beq sd_test
cmp.b #0x01,d5
beq wait_of_aktiv
cmp.b #0x04,d5
beq sd_init_ok
cmp.b #0x00,d5
beq sd_init_ok
bra sd_idle
// acdm 41
wait_of_aktiv:
bsr sd_16clk
moveq #0x77,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
bsr sd_16clk
move.l #0xff,d6
moveq #0x69,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x02,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x01,d4
bsr sd_com
and d5,d6
bsr sd_receive
cmp.b #0x00,d5
beq sd_init_ok
cmp.b #0x05,d5
beq sd_test
bra wait_of_aktiv
sd_init_ok:
// blockgr<EFBFBD>sse 512byt
sd_bg:
bsr sd_16clk
moveq #0x50,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #02,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_bg
// read block
sd_rb:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb
lea 0xc00000,a4
move.l #513,d7
rd_rb:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb
// write block
sd_wb:
bsr sd_16clk
moveq #0x58,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_wb
lea 0xc00000,a4
move.l #513,d7
moveq.l #0x66,d4
wr_wb:
bsr sd_com
// subq.l #1,d4
moveq #0x66,d4
subq.l #1,d7
bne wr_wb
bsr sd_receive
wr_wb_el:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
bne wr_wb_el
// read block 2
sd_rb2:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb2
lea 0xc00400,a4
move.l #513,d7
rd_rb2:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb2
nop
nop
rts
sd_receive:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
beq sd_receive
rts
sd_com:
bclr.b #6,(a1)
sd_comb:
bsr warten_10us
moveq #7,d2
clr.l d5
sd_com_loop:
btst d2,d4
beq sd_com2
bset.b #0,(a1)
bra sd_com2_1
sd_com2:
bclr.b #0,(a1)
sd_com2_1:
bsr sd_clk
and.l #0x02,d3
beq sd_com3
bset.b d2,d5
sd_com3:
subq.l #1,d2
bge sd_com_loop
bsr warten_10us
bset.b #6,(a1)
bset.b #0,(a1)
bsr warten_200us
rts
sd_clk:
tst.b 0xfffff700
tst.b 0xfffff700
bset.b #2,(a1)
tst.b 0xfffff700
tst.b 0xfffff700
move.b (a2),d3
tst.b 0xfffff700
bclr.b #2,(a1)
rts
sd_15clk:
move #15,d0
bra sd_16clk
sd_16clk:
moveq #16,d0
sd_16clk1:
bsr sd_clk
subq.l #1,d0
bne sd_16clk1
bsr warten_10us
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
/********************************************************************/
#define cmd_reg (0x1d)
#define status_reg (0x1d)
#define seccnt (0x09)
ide_test:
lea 0xfff00040,a0
lea 0xc00000,a1
move.b #0xec,cmd_reg(a0) //identify devcie cmd
bsr wait_int
bsr ds_rx
// read sector normal
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read cmd
bsr wait_int
bsr ds_rx
// write testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write cmd
bsr drq_wait
// write pattern
move.l #256,d0
ide_test_loop3:
move.w #0xa55a,(a0)
subq.l #1,d0
bne ide_test_loop3
bsr wait_int
// read testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read
bsr wait_int
bsr ds_rx
// sector restauriern
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write
lea -0x400(a1),a1 // vorletzer
bsr drq_wait
bsr ds_tx
bsr wait_int
// fertig und zur<EFBFBD>ck
nop
rts
// wait auf int
wait_int:
move.b 0xfffffa01,d0
btst #5,d0
bne wait_int
move.b status_reg(a0),d0
rts
// wait auf drq
drq_wait:
move.b status_reg(a0),d0
btst #3,d0
beq drq_wait
rts
// 1 sector lesen word
ds_rx:
move.l #256,d0
ds_rx_loop:
move.w (a0),(a1)+
subq.l #1,d0
bne ds_rx_loop
rts
// 1 sector lesen long
ds_rxl:
move.l #128,d0
ds_rxl_loop:
move.l (a0),(a1)+
subq.l #1,d0
bne ds_rxl_loop
rts
// 1 sector schreiben word
ds_tx:
move.l #256,d0
ds_tx_loop:
move.w (a1)+,(a0)
subq.l #1,d0
bne ds_tx_loop
rts
// 1 sector schreiben word
ds_txl:
move.l #128,d0
ds_txl_loop:
move.l (a1)+,(a0)
subq.l #1,d0
bne ds_txl_loop
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
/********************************************************************/

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/*
* CF_Startup.c - Default init/startup/termination routines for
* Embedded Metrowerks C++
*
* Copyright <20> 1993-1998 Metrowerks, Inc. All Rights Reserved.
* Copyright <20> 2005 Freescale semiConductor Inc. All Rights Reserved.
*
*
* THEORY OF OPERATION
*
* This version of thestartup code is intended for linker relocated
* executables. The startup code will assign the stack pointer to
* __SP_INIT, assign the address of the data relative base address
* to a5, initialize the .bss/.sbss sections to zero, call any
* static C++ initializers and then call main. Upon returning from
* main it will call C++ destructors and call exit to terminate.
*/
#ifdef __cplusplus
#pragma cplusplus off
#endif
#pragma PID off
#pragma PIC off
#include "MCF5475.h"
/* imported data */
extern unsigned long far _SP_INIT, _SDA_BASE;
extern unsigned long far _START_BSS, _END_BSS;
extern unsigned long far _START_SBSS, _END_SBSS;
extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END;
extern unsigned long far __Bas_base;
extern unsigned long far __SUP_SP,__BOOT_FLASH;
extern unsigned long far rt_mbar;
/* imported routines */
extern int BaS(int, char **);
/* exported routines */
extern void __initialize_hardware(void);
extern void init_slt(void);
void _startup(void)
{
asm
{
bra warmstart
jmp __BOOT_FLASH + 8 // ist zugleich reset vector
/* disable interrupts */
warmstart:
// disable interrupts
move.w #0x2700,sr
// Initialize MBAR
MOVE.L #__MBAR,D0
MOVEC D0,MBAR
move.l d0,rt_mbar
// mmu off
move.l #__MMUBAR+1,d0
movec d0,MMUBAR //mmubar setzen
clr.l d0
move.l d0,MCF_MMU_MMUCR // mmu off
/* Initialize RAMBARs: locate SRAM and validate it */ \
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0 // on for all
movec d0,RAMBAR1
// STACKPOINTER AUF ENDE SRAM1
lea __SUP_SP,a7
// instruction cache on
move.l #0x000C8100,d0
movec d0,cacr
nop
// initialize any hardware specific issues
bra __initialize_hardware
}
}

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/******************************************************************************
FILE : startcf.h
PURPOSE : startup code for ColdFire
LANGUAGE: C
Notes:
1) Default entry point is _startup.
. disable interrupts
. the SP is set to __SP_AFTER_RESET
. SP must be initialized to valid memory
in case the memory it points to is not valid using MEMORY_INIT macro
2) __initialize_hardware is called. Here you can initialize memory and some peripherics
at this point global variables are not initialized yet
3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform
needed initialisations for the language (clear memory, data rom copy).
4) void __initialize_system(void); is called
to allow additional hardware initialization (UART, GPIOs, etc...)
5) Jump to main
*/
/********************************************************************************/
#define cf_stack
//#define ii_on
#define halten
#define halten_dbcc
#define halten_and
#define halten_add
#define halten_sub
#define halten_or
#define halten_op
#define halten_opc
#define halten_movem
#define halten_lea
#define halten_shift
#define halten_move
#define halten_exg
#define halten_movep
#define halten_ewf
#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C]))
#define DIP_SWITCHa ___MBAR + 0xA2C
#define sca_page_ID 6

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/********************************************************/
/* user/supervisor handler
/********************************************************/
.include "startcf.h"
.extern _rt_cacr;
.extern _rt_mod;
.extern _rt_ssp;
.extern _rt_usp;
.extern ___MMUBAR
/* Register read/write macros */
#define MCF_MMU_MMUCR ___MMUBAR
#define MCF_MMU_MMUOR ___MMUBAR+0x04
#define MCF_MMU_MMUSR ___MMUBAR+0x08
#define MCF_MMU_MMUAR ___MMUBAR+0x10
#define MCF_MMU_MMUTR ___MMUBAR+0x14
#define MCF_MMU_MMUDR ___MMUBAR+0x18
.public _privileg_violation
.public cpusha
.text
_privileg_violation:
move.w #0x2700,sr
lea -12(a7),a7
movem.l d0/a0/a5,(a7)
#ifndef cf_stack
lea 0x52f0,a0
move.l #0x20,(a0) // set auf 68030
#endif
lea _rt_mod,a0 // zugriff setzen
tst.b (a0) // vom rt_supervisormodus?
bne pv_work // ja->
// tats<EFBFBD>chlich privileg violation
mov3q.l #-1,(a0) // sr_mod setzen
move.l usp,a5 // usp holen
move.l a5,8(a0) // sichern
move.l 4(a0),a5 // rt_ssp holen
#ifdef cf_stack
move.l 16(a7),-(a5) // pc verschieben
move.l 12(a7),-(a5) // sr verschieben
bset #5,2(a5) // auf super setzen
#else
move.w 12(a7),-(a5) // vector nr.
move.l 16(a7),-(a5) // pc verschieben
move.w 14(a7),-(a5) // sr verschieben
bset #5,(a5) // auf super
#endif
move.l a5,usp
move.l 12(a0),a5 // rt_vbr
lea 0x18(a5),a5 // vector
move.l (a5),16(a7) // vector privileg violation
movem.l (a7),d0/a0/a5 // register zur<EFBFBD>ck
lea 12(a7),a7
rte
// privileg violation
pv_work:
move.l 16(a7),a5 // fault pc
move.b (a5),d0 // fault code
cmp.b #0x4e,d0 // 1.byt 0x4e
beq pv_4e // ja->
cmp.b #0x46,d0 // 1.byt 0x46
beq pv_46 // ja->
cmp.b #0x40,d0 // 1.byt 0x40
beq pv_40 // ja->
cmp.b #0xf4,d0 // 0xf4?
beq pv_f4
cmp.b #0xf3,d0 // 0xf3?
beq pv_f3
// hierher sollt man nicht kommen
nop
halt
nop
// code 0x4exx ********************************************
pv_4e:
move.b 1(a5),d0
cmp.b #0x73,d0 //rte?
beq pv_rte //ja->
cmp.b #0x72,d0 //stop?
beq pv_stop //ja->
cmp.b #0x7B,d0 //movec?
beq pv_movec //ja->
// move usp
btst #3,d0 // to or from
bne pv_usp_to_ax // usp -> ax
// move ax->usp
cmp.b #0x60,d0 //movec?
beq pv_a0_usp //ja->
cmp.b #0x61,d0 //movec?
beq pv_a1_usp //ja->
cmp.b #0x62,d0 //movec?
beq pv_a2_usp //ja->
cmp.b #0x63,d0 //movec?
beq pv_a3_usp //ja->
cmp.b #0x64,d0 //movec?
beq pv_a4_usp //ja->
cmp.b #0x65,d0 //movec?
beq pv_a5_usp //ja->
cmp.b #0x66,d0 //movec?
beq pv_a6_usp //ja->
halt
bra pv_a7_usp //ja->
// move usp->ax
pv_usp_to_ax:
move.l 8(a0),a5 //rt_usp holen
cmp.b #0x68,d0 //movec?
beq pv_usp_a0 //ja->
cmp.b #0x69,d0 //movec?
beq pv_usp_a1 //ja->
cmp.b #0x6a,d0 //movec?
beq pv_usp_a2 //ja->
cmp.b #0x6b,d0 //movec?
beq pv_usp_a3 //ja->
cmp.b #0x6c,d0 //movec?
beq pv_usp_a4 //ja->
cmp.b #0x6d,d0 //movec?
beq pv_usp_a5 //ja->
cmp.b #0x6e,d0 //movec?
beq pv_usp_a6 //ja->
// usp->a7
move.l a5,4(a0) // rt usp -> rt ssp
move.l a5,usp // und setzen
bra pv_usp_ax
// a0->usp
pv_a0_usp: move.l 4(a7),a5
bra pv_ax_usp
// a1->usp
pv_a1_usp: move.l a1,a5
bra pv_ax_usp
// a2->usp
pv_a2_usp: move.l a2,a5
bra pv_ax_usp
// a3->usp
pv_a3_usp: move.l a3,a5
bra pv_ax_usp
// a4->usp
pv_a4_usp: move.l a4,a5
bra pv_ax_usp
// a5->usp
pv_a5_usp: move.l 8(a7),a5
bra pv_ax_usp
// a6->usp
pv_a6_usp: move.l a6,a5
bra pv_ax_usp
// a7->usp
pv_a7_usp: move.l 4(a0),a5 // rt_ssp -> a5
pv_ax_usp:
move.l a5,8(a0) // usp -> rt_usp
addq.l #2,16(a7) // next
movem.l (a7),d0/a0/a5 // register zur<EFBFBD>ck
lea 12(a7),a7
rte
// usp->a0
pv_usp_a0:
move.l a5,4(a7)
bra pv_usp_ax
pv_usp_a1:
move.l a5,a1
bra pv_usp_ax
pv_usp_a2:
move.l a5,a2
bra pv_usp_ax
pv_usp_a3:
move.l a5,a3
bra pv_usp_ax
pv_usp_a4:
move.l a5,a4
bra pv_usp_ax
pv_usp_a5:
move.l a5,8(a7)
bra pv_usp_ax
pv_usp_a6:
move.l a5,a6
pv_usp_ax:
addq.l #2,16(a7) // next
movem.l (a7),d0/a0/a5 // register zur<EFBFBD>ck
lea 12(a7),a7
rte
// rte
pv_rte:
move.l usp,a5
#ifdef cf_stack
move.l (a5)+,12(a7) // sr verschieben
move.l (a5)+,16(a7) // pc verschieben
#else
move.w (a5)+,14(a7) // sr verschieben
move.l (a5)+,16(a7) // pc verschieben
move.w (a5)+,12(a7) // vector
#endif
bclr #5,14(a7) // war es von super?
bne pv_rte_sup // ja->
clr.l (a0) // rt_mod auf user
move.l a5,4(a0) // rt_ssp sichern
move.l 8(a0),a5 // rt_usp holen
pv_rte_sup:
move.l a5,usp // usp setzen
movem.l (a7),d0/a0/a5 // register zur<EFBFBD>ck
lea 12(a7),a7
rte
// stop
pv_stop:
move.b 2(a5),d0 // sr wert
and.l #0x0700,d0 // int mask
cmp.w #0x700,d0
beq stop7
cmp.w #0x600,d0
beq stop6
cmp.w #0x500,d0
beq stop5
cmp.w #0x400,d0
beq stop4
cmp.w #0x300,d0
beq stop3
cmp.w #0x200,d0
beq stop2
cmp.w #0x100,d0
beq stop1
stop #0x2000
bra stop_weiter
stop1:
stop #0x2100
bra stop_weiter
stop2:
stop #0x2200
bra stop_weiter
stop3:
stop #0x2300
bra stop_weiter
stop4:
stop #0x2400
bra stop_weiter
stop5:
stop #0x2500
bra stop_weiter
stop6:
stop #0x2600
bra stop_weiter
stop7:
stop #0x2700
stop_weiter:
addq.l #4,16(a7) // next
movem.l (a7),d0/a0/a5 // register zur<EFBFBD>ck
lea 12(a7),a7
rte
// movec ???????
pv_movec:
move.w 2(a5),d0 // 2.word holen
and.l #0xf000,d0
btst #15,d0 // addressregister?
bne pv_movec_ax // ja->
tst.w d0 // d0?
bne pvm_d1 // nein->
move.l (a7),-(a7) // d0 holen und sichern
bra pvm_me
pvm_d1:
cmp.w #0x1000,d0 // d1?
bne pvm_d2 // nein->
move.l d1,-(a7) // d1 holen und sichern
bra pvm_me // fertig machen
pvm_d2:
cmp.w #0x2000,d0 // d1?
bne pvm_d3 // nein->
move.l d2,-(a7) // d2 holen und sichern
bra pvm_me // fertig machen
pvm_d3:
cmp.w #0x3000,d0 // d1?
bne pvm_d4 // nein->
move.l d3,-(a7) // d3 holen und sichern
bra pvm_me // fertig machen
pvm_d4:
cmp.w #0x4000,d0 // d1?
bne pvm_d5 // nein->
move.l d4,-(a7) // d4 holen und sichern
bra pvm_me // fertig machen
pvm_d5:
cmp.w #0x5000,d0 // d1?
bne pvm_d6 // nein->
move.l d5,-(a7) // d5 holen und sichern
bra pvm_me // fertig machen
pvm_d6:
cmp.w #0x6000,d0 // d1?
bne pvm_d7 // nein->
move.l d6,-(a7) // d6 holen und sichern
bra pvm_me // fertig machen
pvm_d7:
move.l d7,-(a7) // d7 holen und sichern
bra pvm_me // fertig machen
pv_movec_ax:
cmp.w #0x8000,d0 // a0?
bne pvm_a1 // nein->
move.l 4(a7),-(a7) // a0 holen und sichern
bra pvm_me // fertig machen
pvm_a1:
cmp.w #0x9000,d0 // a0?
bne pvm_a2 // nein->
move.l a1,-(a7) // a1 holen und sichern
bra pvm_me // fertig machen
pvm_a2:
cmp.w #0xa000,d0 // a0?
bne pvm_a3 // nein->
move.l a2,-(a7) // a2 holen und sichern
bra pvm_me // fertig machen
pvm_a3:
cmp.w #0xb000,d0 // a0?
bne pvm_a4 // nein->
move.l a3,-(a7) // a3 holen und sichern
bra pvm_me // fertig machen
pvm_a4:
cmp.w #0xc000,d0 // a0?
bne pvm_a5 // nein->
move.l a4,-(a7) // a4 holen und sichern
bra pvm_me // fertig machen
pvm_a5:
cmp.w #0xd000,d0 // a0?
bne pvm_a6 // nein->
move.l 8(a7),-(a7) // a5 holen und sichern
bra pvm_me // fertig machen
pvm_a6:
cmp.w #0xe000,d0 // a0?
bne pvm_a7 // nein->
move.l a6,-(a7) // a6 holen und sichern
bra pvm_me // fertig machen
pvm_a7:
move.l 4(a7),-(a7) // a7 holen und sichern
pvm_me:
move.w 2(a5),d0 // 2.word holen
andi.l #0xf,d0 // nur letzte 4 bits
move.l (a7)+,8(a0,d0*4) // start bei +8, *4 weil long
jsr cpusha // gesammten cache flushen
rte
// code 0x46xx *****************************************
pv_46:
move.b 1(a5),d0
cmp.b #0xfc,d0 //#d16->sr
beq im_sr //ja->
//move dx->sr (sr und rt_mod ist supervisor sonst w<EFBFBD>re es privileg violation
cmp.b #0xc0,d0 //d0->sr?
bne d1_sr //nein->
move.w 2(a7),d0 //hier ist d0 gesichert
bra d0_sr
d1_sr:
cmp.b #0xc1,d0 //d1->sr?
bne d2_sr //nein->
move.w d1,d0
bra d0_sr
d2_sr:
cmp.b #0xc2,d0 //d2->sr?
bne d3_sr
move.w d2,d0
bra d0_sr
d3_sr:
cmp.b #0xc3,d0 //d3->sr?
bne d4_sr
move.w d3,d0
bra d0_sr
d4_sr:
cmp.b #0xc4,d0 //d4->sr?
bne d5_sr
move.w d4,d0
bra d0_sr
d5_sr:
cmp.b #0xc5,d0 //d5->sr?
bne d6_sr
move.w d5,d0
bra d0_sr
d6_sr:
cmp.b #0xc6,d0 //d6->sr?
bne d7_sr
move.w d6,d0
bra d0_sr
d7_sr:
move.w d7,d0 // sonst d7->sr
d0_sr:
addq.l #2,16(a7) // next
bra pv_set_sr_end // fertig machen
// move #xxxx,sr
im_sr:
addq.l #4,16(a7) // next
move.w 2(a5),d0 // data
pv_set_sr_end:
bclr #13,d0 // war super?
bne pv_sre2 // ja ->
clr.l (a0)
move.l usp,a5 // usp
move.l a5,4(a0) // rt_ssp speichern
move.l 8(a0),a5 // rt_usp holen
move.l a5,usp // setzen
pv_sre2:
move.w d0,14(a7) // sr setzen
movem.l (a7),d0/a0/a5 // register zur<EFBFBD>ck
lea 12(a7),a7
rte
// code 0x40xx *****************************************
pv_40:
move.b 1(a5),d0 // 2.byt
cmp.b #0xe7,d0
beq pv_strldsr
// move sr->dx
move.l 12(a7),a5 // sr holen
tst.b (a0) // super?
beq pv_40_user // nein?
lea 0x2000(a5),a5 // super zuaddieren
pv_40_user:
cmp.b #0xc0,d0
bne nsr_d1
move.w a5,2(a7)
bra sr_dx_end
nsr_d1:
cmp.b #0xc1,d0
bne nsr_d2
move.w a5,d1
bra sr_dx_end
nsr_d2:
cmp.b #0xc2,d0
bne nsr_d3
move.w a5,d2
bra sr_dx_end
nsr_d3:
cmp.b #0xc3,d0
bne nsr_d4
move.w a5,d3
bra sr_dx_end
nsr_d4:
cmp.b #0xc4,d0
bne nsr_d5
move.w a5,d4
bra sr_dx_end
nsr_d5:
cmp.b #0xc5,d0
bne nsr_d6
move.w a5,d5
bra sr_dx_end
nsr_d6:
cmp.b #0xc6,d0
bne nsr_d7
move.w a5,d6
bra sr_dx_end
nsr_d7:
move.w a5,d7
halt
sr_dx_end:
addq.l #2,16(a7) // next
movem.l (a7),d0/a0/a5 // register zur<EFBFBD>ck
lea 12(a7),a7
rte
// strldsr
pv_strldsr:
nop
halt
nop
// code 0xf4xx ***********************************
pv_f4:
addq.l #2,16(a7) // next instr
move.b 1(a5),d0 // 2.byt
bsr pv_ax_a0 // richtiges register
move.b 1(a5),d0 // 2.byt
cmp.b #0x30,d0 // >0xf430
blo pv_intouch
// cpushl
cpushl bc,(a0)
movem.l (a7),d0/a0/a5
lea 12(a7),a7
rte
pv_intouch:
intouch (a0)
movem.l (a7),d0/a0/a5
lea 12(a7),a7
rte
// subroutine register ax->a0
pv_ax_a0:
and.l #0x7,d0 // nur register nummer
subq.l #1,d0
bmi pv_a0_a0
subq.l #1,d0
bmi pv_a1_a0
subq.l #1,d0
bmi pv_a2_a0
subq.l #1,d0
bmi pv_a3_a0
subq.l #1,d0
bmi pv_a4_a0
subq.l #1,d0
bmi pv_a5_a0
subq.l #1,d0
bmi pv_a6_a0
move.l a7,a0
rts
pv_a0_a0:
move.l 8(a7),a0
rts
pv_a1_a0:
move.l a1,a0
rts
pv_a2_a0:
move.l a2,a0
rts
pv_a3_a0:
move.l a3,a0
rts
pv_a4_a0:
move.l a4,a0
rts
pv_a5_a0:
move.l 12(a7),a0
rts
pv_a6_a0:
move.l a6,a0
rts
// code 0xf4xx ***********************************
pv_f3:
addq.l #2,16(a7) // next instr
move.b 1(a5),d0 // 2. byt
cmp.b #0x40,d0
bgt pv_frestore
//fsave (ax) oder d16(ax)
jsr pv_ax_a0 // richtiges register holen
move.b 1(a5),d0
cmp.b #0x20,d0
// +d16
blt pv_f3_ax
addq.l #2,16(a7) // next instr
clr.l d0
move.w 2(a0),d0 // d16
add.l d0,a0
pv_f3_ax:
fsave (a0)
movem.l (a7),d0/a0/a5
lea 12(a7),a7
rte
pv_frestore:
cmp.b #0x7a,d0
beq pv_f_d16pc
// frestore (ax) oder d16(ax)
jsr pv_ax_a0 // richtiges register holen
move.b 1(a5),d0
cmp.b #0x60,d0
blt pv_frestore_ax
pv_fend:
addq.l #2,16(a7) // next instr
clr.l d0
move.w 2(a0),d0 // d16
add.l d0,a0
pv_frestore_ax:
frestore (a0)
movem.l (a7),d0/a0/a5
lea 12(a7),a7
rte
// frestore d16(pc)
pv_f_d16pc:
move.l 16(a7),a0 // pc holen
bra pv_fend
//*****************************************************
cpusha:
lea -16(a7),a7
movem.l d0-d2/a0,(a7) // register sichern
move sr,d2
nop
move #0x2700,sr // no interrupts
clr.l d0
clr.l d1
move.l d0,a0
cfa_setloop:
cpushl bc,(a0) // flush
lea 0x10(a0),a0 // index+1
addq.l #1,d1 // index+1
cmpi.w #512,d1 // alle sets?
bne cfa_setloop // nein->
clr.l d1
addq.l #1,d0
move.l d0,a0
cmpi.w #4,d0 // all ways?
bne cfa_setloop // nein->
nop
move.l _rt_cacr,d0 // holen
movec d0,cacr // setzen
move.w d2,sr // alte interrupt maske
movem.l (a7),d0-d2/a0 // register zur<EFBFBD>ck
lea 16(a7),a7
rts
//*******************************************************33

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/*
* File: sysinit.c
* Purpose: Power-on Reset configuration of the COLDARI board.
*
* Notes:
*
*/
#include "MCF5475.h"
#include "startcf.h"
extern unsigned long far __VRAM;
extern unsigned long far __Bas_base;
extern unsigned long far BaS;
extern unsigned long far __BOOT_FLASH[];
extern int copy_end();
extern int warte_10us();
extern int warte_1ms();
extern int warte_10ms();
extern int warte_50us();
extern unsigned long far rt_cacr;
/********************************************************************/
// init SLICE TIMER 0
// all = 32.538 sec = 30.736mHz
// BYT0 = 127.1ms/tick = 7.876Hz offset 0
// BYT1 = 496.5us/tick = 2.014kHz offset 1
// BYT2 = 1.939us/tick = 515.6kHz offset 2
// BYT3 = 7.576ns/tick = 132.00MHz offset 3
// count down!!! 132MHz!!!
/********************************************************************/
void init_slt(void)
{
asm
{
lea MCF_SLT0_STCNT,a0
move.l #0xffffffff,(a0)
lea MCF_SLT0_SCR,a0
move.b #0x05,(a0)
}
MCF_PSC0_PSCTB_8BIT = 'SLT ';
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
// init GPIO ETC.
/********************************************************************/
void init_gpio(void)
{
// PAD REGISTER P.S.:FBCTL UND FBCS WERDEN RICHTIG GESETZT BEIM RESET
MCF_PAD_PAR_DMA = 0b11111111; // NORMAL ALS DREQ DACK
MCF_PAD_PAR_FECI2CIRQ = 0b1111001111001111; // FEC0 NORMAL, FEC1 ALS I/O, I2C, #INT5..6
MCF_PAD_PAR_PCIBG = 0b0000001000111111; // #PCI_BG4=#TBST,#PIC_BG3=I/O,#PCI_BG2..0=NORMAL
MCF_PAD_PAR_PCIBR = 0b0000001000111111; // #PCI_BR4=#INT4,#PIC_BR3=INPUT,#PCI_BR2..0=NORMAL
MCF_PAD_PAR_PSC3 = 0b00001100; // PSC3=TX,RX CTS+RTS=I/O
MCF_PAD_PAR_PSC1 = 0b11111100; // PSC1 NORMAL SERIELL
MCF_PAD_PAR_PSC0 = 0b11111100; // PSC0 NORMAL SERIELL
MCF_PAD_PAR_DSPI = 0b0001111111111111; // DSPI NORMAL
MCF_PAD_PAR_TIMER = 0b00101101; // TIN3..2=#IRQ3..2;TOUT3..2=NORMAL
// ALLE OUTPUTS NORMAL LOW
// ALLE DIR NORMAL INPUT = 0
MCF_GPIO_PDDR_FEC1L = 0b00011110; // OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA)
}
/********************************************************************/
// init seriel
/********************************************************************/
void init_seriel(void)
{
// PSC0: SER1 ----------
MCF_PSC0_PSCSICR = 0; // UART
MCF_PSC0_PSCCSR = 0xDD;
MCF_PSC0_PSCCTUR = 0x00;
MCF_PSC0_PSCCTLR = 36; // BAUD RATE = 115200
MCF_PSC0_PSCCR = 0x20;
MCF_PSC0_PSCCR = 0x30;
MCF_PSC0_PSCCR = 0x40;
MCF_PSC0_PSCCR = 0x50;
MCF_PSC0_PSCCR = 0x10;
MCF_PSC0_PSCIMR = 0x8700;
MCF_PSC0_PSCACR = 0x03;
MCF_PSC0_PSCMR1= 0xb3;
MCF_PSC0_PSCMR2= 0x07;
MCF_PSC0_PSCRFCR = 0x0F;
MCF_PSC0_PSCTFCR = 0x0F;
MCF_PSC0_PSCRFAR = 0x00F0;
MCF_PSC0_PSCTFAR = 0x00F0;
MCF_PSC0_PSCOPSET = 0x01;
MCF_PSC0_PSCCR = 0x05;
// PSC3: PIC ----------
MCF_PSC3_PSCSICR = 0; // UART
MCF_PSC3_PSCCSR = 0xDD;
MCF_PSC3_PSCCTUR = 0x00;
MCF_PSC3_PSCCTLR = 36; // BAUD RATE = 115200
MCF_PSC3_PSCCR = 0x20;
MCF_PSC3_PSCCR = 0x30;
MCF_PSC3_PSCCR = 0x40;
MCF_PSC3_PSCCR = 0x50;
MCF_PSC3_PSCCR = 0x10;
MCF_PSC3_PSCIMR = 0x0200; // receiver interrupt enable
MCF_PSC3_PSCACR = 0x03;
MCF_PSC3_PSCMR1= 0xb3;
MCF_PSC3_PSCMR2= 0x07;
MCF_PSC3_PSCRFCR = 0x0F;
MCF_PSC3_PSCTFCR = 0x0F;
MCF_PSC3_PSCRFAR = 0x00F0;
MCF_PSC3_PSCTFAR = 0x00F0;
MCF_PSC3_PSCOPSET = 0x01;
MCF_PSC3_PSCCR = 0x05;
MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 'SERI';
MCF_PSC0_PSCTB_8BIT = 'AL O';
MCF_PSC0_PSCTB_8BIT = 'K! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* Initialize DDR DIMMs on the EVB board */
/********************************************************************/
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
void init_ddram(void)
{
MCF_PSC0_PSCTB_8BIT = 'DDRA';
if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
{
/* Basic configuration and initialization */
MCF_SDRAMC_SDRAMDS = 0x000002AA; // SDRAMDS configuration
MCF_SDRAMC_CS0CFG = 0x0000001A; // SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
MCF_SDRAMC_CS1CFG = 0x0800001A; // SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
MCF_SDRAMC_CS2CFG = 0x1000001A; // SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
MCF_SDRAMC_CS3CFG = 0x1800001A; // SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
// MCF_SDRAMC_SDCFG1 = 0x53722938; // SDCFG1
MCF_SDRAMC_SDCFG1 = 0x73622830; // SDCFG1
// MCF_SDRAMC_SDCFG2 = 0x24330000; // SDCFG2
MCF_SDRAMC_SDCFG2 = 0x46770000; // SDCFG2
// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL
MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL
MCF_SDRAMC_SDMR = 0x40010000; // SDMR (write to LEMR)
// MCF_SDRAMC_SDMR = 0x05890000; // SDRM (write to LMR)
MCF_SDRAMC_SDMR = 0x048D0000; // SDRM (write to LMR)
// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL
MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL
// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (first refresh)
MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (first refresh)
// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (second refresh)
MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (second refresh)
/// MCF_SDRAMC_SDMR = 0x01890000; // SDMR (write to LMR)
MCF_SDRAMC_SDMR = 0x008D0000; // SDMR (write to LMR)
// MCF_SDRAMC_SDCR = 0x710F0F00; // SDCR (lock SDMR and enable refresh)
MCF_SDRAMC_SDCR = 0x710D0F00; // SDCR (lock SDMR and enable refresh)
}
MCF_PSC0_PSCTB_8BIT = 'M OK';
MCF_PSC0_PSCTB_8BIT = '! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* init FB_CSx /*
/********************************************************************/
void init_fbcs()
{
MCF_PSC0_PSCTB_8BIT = 'FBCS';
/* Flash */
MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS
MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa
MCF_FBCS0_CSMR = 0x007F0001; // 8MB on
MCF_FBCS1_CSAR = 0xFFF00000; // ATARI I/O ADRESS
MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_1M
| MCF_FBCS_CSMR_V);
MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BEN<45>TZT, DECODE DIREKT AUF DEM FPGA
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE
| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE
MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF
| MCF_FBCS_CSMR_V);
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* FPGA LADEN /*
/********************************************************************/
void init_fpga(void)
{
MCF_PSC0_PSCTB_8BIT = 'FPGA';
asm
{
lea MCF_GPIO_PODR_FEC1L,a1 // register adresse:write
lea MCF_GPIO_PPDSDR_FEC1L,a2 // reads
bclr #1,(a1) // clk auf low
bclr #2,(a1) // #config=low
test_nSTATUS:
btst #0,(a2) // nSTATUS==0
bne test_nSTATUS // nein->
btst #5,(a2) // conf done==0
bne test_nSTATUS // nein->
jsr warte_10us // warten
bset #2,(a1) // #config=high
jsr warte_10us // warten
test_STATUS:
btst #0,(a2) // status high?
beq test_STATUS // nein->
jsr warte_10us // warten
lea 0xE0700000,a0 // startadresse fpga daten
word_send_loop:
cmp.l #0xE0800000,a0
bgt fpga_error
move.b (a0)+,d0 // 32 bit holen
moveq #8,d1 // 32 bit ausgeben
bit_send_loop:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_1
bclr #3,(a1)
bra bit_send
bit_is_1:
bset #3,(a1)
bit_send:
bset #1,(a1) // clock=high
bclr #1,(a1) // clock=low
subq.l #1,d1
bne bit_send_loop // wiederholen bis fertig
btst #5,(a2) // fpga fertig, conf_done=high?
beq word_send_loop // nein, next word->
move.l #4000,d1
overclk:
bset #1,(a1) // clock=high
nop
bclr #1,(a1) // clock=low
subq.l #1,d1
bne overclk // weiter bis fertig
bra init_fpga_end
//---------------------------------------------------------
wait_pll:
lea MCF_SLT0_SCNT,a3
move.l (a3),d0
move.l #100000,d6 // ca 1ms
wait_pll_loop:
tst.w (a1)
bpl wait_pll_ok
move.l (a3),d1
sub.l d0,d1
add.l d6,d1
bpl wait_pll_loop
wait_pll_ok:
rts
// fertig
fpga_error:
}
MCF_PSC0_PSCTB_8BIT = ' NOT';
init_fpga_end:
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
// init pll
MCF_PSC0_PSCTB_8BIT = 'PLL ';
asm
{
lea 0xf0000600,a0
lea 0xf0000800,a1
bsr wait_pll
move.w #27,0x48(a0) // loopfilter r
bsr wait_pll
move.w #1,0x08(a0) // charge pump I
bsr wait_pll
move.w #12,0x0(a0) // N counter high = 12
bsr wait_pll
move.w #12,0x40(a0) // N counter low = 12
bsr wait_pll
move.w #1,0x114(a0) // ck1 bypass
bsr wait_pll
move.w #1,0x118(a0) // ck2 bypass
bsr wait_pll
move.w #1,0x11c(a0) // ck3 bypass
bsr wait_pll
move.w #1,0x10(a0) // ck0 high = 1
bsr wait_pll
move.w #1,0x50(a0) // ck0 low = 1
bsr wait_pll
move.w #1,0x144(a0) // M odd division
bsr wait_pll
move.w #1,0x44(a0) // M low = 1
bsr wait_pll
move.w #145,0x04(a0) // M high = 145 = 146MHz
bsr wait_pll
clr.b (a1) // set
}
MCF_PSC0_PSCTB_8BIT = 'SET!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* INIT VIDEO DDR RAM /*
/********************************************************************/
void init_video_ddr(void)
{
asm
{
// init video ram
moveq.l #0xB,d0
move.w d0,0xF0000400 //set cke=1, cs=1 config=1
nop
lea __VRAM,a0 //zeiger auf video ram
nop
move.l #0x00050400,(a0) //IPALL
nop
move.l #0x00072000,(a0) //load EMR pll on
nop
move.l #0x00070122,(a0) //load MR: reset pll, cl=2 BURST=4lw
nop
move.l #0x00050400,(a0) //IPALL
nop
move.l #0x00060000,(a0) //auto refresh
nop
move.l #0x00060000,(a0) //auto refresh
nop
move.l #0000070022,(a0) //load MR dll on
nop
move.l #0x01070002,d0 // fifo on, refresh on, ddrcs und cke on, video dac on,
move.l d0,0xf0000400
}
}
/********************************************************************/
/* video mit aufl<66>sung 1280x1000 137MHz /*
/********************************************************************/
void video_1280_1024(void)
{
extern int wait_pll;
asm
{
// SPEICHER F<>LLEM
//testmuster 1
lea __VRAM,a2
lea __VRAM+0x600000,a3
clr.l d0
move.l #0x1000102,d1
loop5: move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
add.l d1,d0
flo6: cmp.l a2,a3
bgt loop5
// screen setzen
//horizontal 1280
lea 0xffff8282,a0
move.w #1800,(a0)+
move.w #1380,(a0)+
move.w #99,(a0)+
move.w #100,(a0)+
move.w #1379,(a0)+
move.w #1500,(a0)
//vertical 1024
lea 0xffff82a2,a0
move.w #1150,(a0)+
move.w #1074,(a0)+
move.w #49,(a0)+
move.w #50,(a0)+
move.w #1073,(a0)+
move.w #1100,(a0)+
// acp video on
move.l #0x01070207,d0
move.l d0,0xf0000400
// clut setzen
lea 0xf0000000,a0
move.l #0xffffffff,(a0)+
move.l #0xff,(a0)+
move.l #0xff00,(a0)+
move.l #0xff0000,(a0)
// halt
}
}
/********************************************************************/
/* INIT PCI /*
/********************************************************************/
#define PCI_MEMORY_OFFSET (0x80000000)
#define PCI_MEMORY_SIZE (0x40000000)
#define PCI_IO_OFFSET (0xD0000000)
#define PCI_IO_SIZE (0x10000000)
void init_PCI(void)
{
MCF_PSC0_PSCTB_8BIT = 'PCI ';
asm
{
// Setup the arbiter
move.l #MCF_PCIARB_PACR_INTMPRI \
+ MCF_PCIARB_PACR_EXTMPRI(0x1F) \
+ MCF_PCIARB_PACR_INTMINTEN \
+ MCF_PCIARB_PACR_EXTMINTEN(0x1F),D0
move.l D0,MCF_PCIARB_PACR
// Setup burst parameters
move.l #MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32),D0
move.l D0,MCF_PCI_PCICR1
move.l #MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16),D0
move.l D0,MCF_PCI_PCICR2
// Turn on error signaling
move.l #MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_IAE + MCF_PCI_PCIICR_REE + 32,D0
move.l D0,MCF_PCI_PCIICR
move.l #MCF_PCI_PCIGSCR_SEE,D0
or.l D0,MCF_PCI_PCIGSCR
// Configure Initiator Windows */
move.l #PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8),D0
clr.w D0
move.l D0,MCF_PCI_PCIIW0BTAR // Initiator Window 0 Base / Translation Address Register
move.l #PCI_IO_OFFSET+((PCI_IO_SIZE-1)>>8),D0
clr.w D0
move.l D0,MCF_PCI_PCIIW1BTAR // Initiator Window 1 Base / Translation Address Register
clr.l MCF_PCI_PCIIW2BTAR // not used
move.l #MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO,D0
move.l D0,MCF_PCI_PCIIWCR // Initiator Window Configuration Register
/* Clear PCI Reset and wait for devices to reset */
move.l #~MCF_PCI_PCIGSCR_PR,D0
and.l D0,MCF_PCI_PCIGSCR
}
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* test UPC720101 (USB) /*
/********************************************************************/
void test_upd720101(void)
{
MCF_PSC0_PSCTB_8BIT = 'NEC ';
asm
{
// SELECT UPD720101 AD17
MOVE.L #MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(0),D0
MOVE.L D0,MCF_PCI_PCICAR
LEA PCI_IO_OFFSET,A0
MOVE.L (A0),D1
move.l #0x33103500,d0
cmp.l d0,d1
beq nec_ok
}
MCF_PSC0_PSCTB_8BIT = 'NOT ';
goto nec_not_ok;
nec_ok:
asm
{
MOVE.L #MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
MOVE.L D0,MCF_PCI_PCICAR
move.b #0x20,(a0)
}
nec_not_ok:
asm
{
MOVE.L #MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
MOVE.L D0,MCF_PCI_PCICAR
}
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* TFP410 (vdi) einschalten /*
/********************************************************************/
void vdi_on(void)
{
uint8 RBYT, DBYT;
int versuche, startzeit;
MCF_PSC0_PSCTB_8BIT = 'DVI ';
MCF_I2C_I2FDR = 0x3c; // 100kHz standard
versuche = 0;
loop_i2c:
if (versuche++>10) goto next;
MCF_I2C_I2ICR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2CR = 0xA;
RBYT = MCF_I2C_I2DR;
MCF_I2C_I2SR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2ICR = 0x01;
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7a; // ADRESSE TFP410
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
tpf_410_ACK_OK:
MCF_I2C_I2DR = 0x00; // SUB ADRESS 0
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x08; // txak=1
RBYT = MCF_I2C_I2DR;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
if (RBYT!=0x4c) goto loop_i2c;
i2c_ok:
MCF_I2C_I2CR = 0x0; // stop
MCF_I2C_I2SR = 0x0; // clear sr
while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free
MCF_I2C_I2CR = 0xb0; // on tx master
MCF_I2C_I2DR = 0x7A;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2SR = 0x0; // clear sr
while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7A;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x08; // txak=1
warte_50us();
RBYT = MCF_I2C_I2DR;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
if (RBYT!=0xbf) goto loop_i2c;
goto dvi_ok;
next:
MCF_PSC0_PSCTB_8BIT = 'NOT ';
dvi_ok:
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_I2C_I2CR = 0x0; // i2c off
}
/********************************************************************/
/* AC97 /*
/********************************************************************/
void init_ac97(void)
{
// PSC2: AC97 ----------
int i,k,zm,x,va,vb,vc;
MCF_PSC0_PSCTB_8BIT = 'AC97';
MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97
| MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
| MCF_PAD_PAR_PSC2_PAR_TXD2
| MCF_PAD_PAR_PSC2_PAR_RXD2;
MCF_PSC2_PSCMR1 = 0x0;
MCF_PSC2_PSCMR2 = 0x0;
MCF_PSC2_PSCIMR = 0x0300;
MCF_PSC2_PSCSICR = 0x03; //AC97
MCF_PSC2_PSCRFCR = 0x0f000000;
MCF_PSC2_PSCTFCR = 0x0f000000;
MCF_PSC2_PSCRFAR = 0x00F0;
MCF_PSC2_PSCTFAR = 0x00F0;
for ( zm = 0; zm<100000; zm++) // wiederholen bis synchron
{
MCF_PSC2_PSCCR = 0x20;
MCF_PSC2_PSCCR = 0x30;
MCF_PSC2_PSCCR = 0x40;
MCF_PSC2_PSCCR = 0x05;
// MASTER VOLUME -0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// read register
MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0
}
warte_50us();
va = MCF_PSC2_PSCTB_AC97;
if ((va & 0x80000fff)==0x80000800)
{
vb = MCF_PSC2_PSCTB_AC97;
vc = MCF_PSC2_PSCTB_AC97;
if ((va & 0xE0000fff)==0xE0000800 & vb==0x02000000 & vc==0x00000000)
{
goto livo;
}
}
}
MCF_PSC0_PSCTB_8BIT = ' NOT';
livo:
// AUX VOLUME ->-0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16
MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME
for ( i = 3; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// line in VOLUME +12dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// cd in VOLUME 0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// mono out VOLUME 0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 3; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF
MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data
ac97_end:
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
void __initialize_hardware(void)
{
_init_hardware:
asm
{
// instruction cache on
move.l #0x000C8120,d0
move.l d0,rt_cacr
movec d0,cacr
nop
}
init_gpio();
init_seriel();
init_slt();
init_fbcs();
init_ddram();
// Ports nicht initialisieren wenn DIP Switch 5 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq not_init_ports
}
init_PCI(); //pci braucht zeit
not_init_ports:
init_fpga();
init_video_ddr();
vdi_on();
// Ports nicht initialisieren wenn DIP Switch 5 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq not_init_ports2
}
test_upd720101();
// video_1280_1024();
init_ac97();
not_init_ports2:
asm
{
/*****************************************************/
/* BaS kopieren
/*****************************************************/
lea copy_start,a0
lea BaS,a1
sub.l a0,a1
move.l #__Bas_base,a2
move.l a2,a3
add.l a1,a3
lea copy_end,a4
BaS_kopieren_loop: // immer 16 bytes
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
cmp.l a4,a0
blt BaS_kopieren_loop
/*****************************************************/
jmp (a3)
copy_start:
/********************************************************************/
}
}

87
BaS_GNU/BaS_codewarrior/firebeeV1/sources/sysinit.h Normal file
View File

@@ -0,0 +1,87 @@
/*
* File: sysinit.h
* Purpose: COLDARI Power-on Reset configuration
*
* Notes:
*
*/
#ifndef __SYSINIT_H__
#define __SYSINIT_H__
#ifdef __cplusplus
extern "C" {
#endif
#if ENABLE_UART_SUPPORT==1
/*
* System Bus Clock Info
*/
// 5475EVB has 133Mhz system clock
#define SYSTEM_CLOCK_KHZ 133000 /* system bus frequency in kHz */
/***
* Serial Port Info
* The baud rate to be : 19200
* Data bits : 8
* Parity : None
* Stop Bits : 1
* Flow Control : None
*/
#define TERMINAL_PORT (0) /* PSC channel used as terminal */
#define TERMINAL_BAUD kBaud19200 /* 115200 */
#undef HARDWARE_FLOW_CONTROL /* Flow control ON or OFF */
#endif
/***
* Board Memory map definitions from linker command files:
* __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker
* symbols must be defined in the linker command file.
*/
extern __declspec(system) uint8 __BOOT_FLASH[];
extern __declspec(system) uint8 __BOOT_FLASH_SIZE[];
extern __declspec(system) uint8 __SDRAM[];
extern __declspec(system) uint8 __SDRAM_SIZE[];
#define BOOT_FLASH_ADDRESS (uint32)__BOOT_FLASH
#define BOOT_FLASH_SIZE (uint32)__BOOT_FLASH_SIZE
#define SDRAM_ADDRESS (uint32)__SDRAM
#define SDRAM_SIZE (uint32)__SDRAM_SIZE
/********************************************************************/
/* __initialize_hardware Startup code routine
*
* __initialize_hardware is called by the startup code right after reset,
* with interrupt disabled and SP pre-set to a valid memory area.
* Here you should initialize memory and some peripherics;
* at this point global variables are not initialized yet.
* The startup code will initialize SP on return of this function.
*/
void __initialize_hardware(void);
/********************************************************************/
/* __initialize_system Startup code routine
*
* __initialize_system is called by the startup code when all languages
* specific initialization are done to allow additional hardware setup.
*/
void __initialize_system(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSINIT_H__ */

413
BaS_GNU/BaS_codewarrior/workspace.cww Normal file
View File

@@ -0,0 +1,413 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<?codewarrior exportversion="1.0" ideversion="5.9.0" success="y" ?>
<!DOCTYPE MWIDEWORKSPACE [
<!ELEMENT MWIDEWORKSPACE (WINDOW*, COMWINDOW*)>
<!ELEMENT WINDOW (SESSION, EDOCTYPE, PATH, FRAMELOC, FRAMESIZE, DOCKINFO)>
<!ELEMENT COMWINDOW (SESSION, CLSID, OWNERPROJECT, DATA, FRAMELOC, FRAMESIZE, DOCKINFO)>
<!ELEMENT SESSION (#PCDATA)>
<!ELEMENT EDOCTYPE (#PCDATA)>
<!ELEMENT DEFAULT (#PCDATA)>
<!ELEMENT MAXIMIZED (#PCDATA)>
<!ELEMENT PATH (#PCDATA)>
<!ATTLIST PATH USERELATIVEPATHS (true | false) "true">
<!ELEMENT FRAMELOC (X, Y)>
<!ELEMENT X (#PCDATA)>
<!ELEMENT Y (#PCDATA)>
<!ELEMENT FRAMESIZE (W, H)>
<!ELEMENT W (#PCDATA)>
<!ELEMENT H (#PCDATA)>
<!ELEMENT DOCKINFO (STATUS, ROW, COLUMN, DOCKBARID, PCTWIDTH, HGT, GROUPID)>
<!ELEMENT STATUS (#PCDATA)>
<!ELEMENT ROW (#PCDATA)>
<!ELEMENT COLUMN (#PCDATA)>
<!ELEMENT DOCKBARID (#PCDATA)>
<!ELEMENT PCTWIDTH (#PCDATA)>
<!ELEMENT HGT (#PCDATA)>
<!ELEMENT GROUPID (GIDHIGHPART, GIDLOWPART)>
<!ELEMENT GIDHIGHPART (#PCDATA)>
<!ELEMENT GIDLOWPART (#PCDATA)>
<!ELEMENT CLSID (#PCDATA)>
<!ELEMENT OWNERPROJECT (#PCDATA)>
<!ATTLIST OWNERPROJECT USERELATIVEPATHS (true | false) "true">
<!ELEMENT DATA (#PCDATA)>
<!ATTLIST DATA BINARYFORMAT (true | false) "true">
]>
<MWIDEWORKSPACE>
<WINDOW>
<SESSION>-1</SESSION>
<EDOCTYPE>0</EDOCTYPE>
<DEFAULT>true</DEFAULT>
<PATH USERELATIVEPATHS = "true">firebeeV1\firebeeV1.mcp</PATH>
<FRAMELOC>
<X>938</X>
<Y>306</Y>
</FRAMELOC>
<FRAMESIZE>
<W>392</W>
<H>338</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>1</STATUS>
<ROW>0</ROW>
<COLUMN>0</COLUMN>
<DOCKBARID>59420</DOCKBARID>
<PCTWIDTH>1.000000</PCTWIDTH>
<HGT>378</HGT>
<GROUPID>
<GIDHIGHPART>0</GIDHIGHPART>
<GIDLOWPART>0</GIDLOWPART>
</GROUPID>
</DOCKINFO>
</WINDOW>
<WINDOW>
<SESSION>-1</SESSION>
<EDOCTYPE>1</EDOCTYPE>
<PATH USERELATIVEPATHS = "true">firebeeV1\sources\exceptions.s</PATH>
<FRAMELOC>
<X>8</X>
<Y>34</Y>
</FRAMELOC>
<FRAMESIZE>
<W>549</W>
<H>895</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>0</STATUS>
<ROW></ROW>
<COLUMN></COLUMN>
<DOCKBARID></DOCKBARID>
<PCTWIDTH></PCTWIDTH>
<HGT></HGT>
<GROUPID>
<GIDHIGHPART></GIDHIGHPART>
<GIDLOWPART></GIDLOWPART>
</GROUPID>
</DOCKINFO>
</WINDOW>
<WINDOW>
<SESSION>1073741824</SESSION>
<EDOCTYPE>35</EDOCTYPE>
<FRAMELOC>
<X>60</X>
<Y>205</Y>
</FRAMELOC>
<FRAMESIZE>
<W>582</W>
<H>392</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>0</STATUS>
<ROW></ROW>
<COLUMN></COLUMN>
<DOCKBARID></DOCKBARID>
<PCTWIDTH></PCTWIDTH>
<HGT></HGT>
<GROUPID>
<GIDHIGHPART></GIDHIGHPART>
<GIDLOWPART></GIDLOWPART>
</GROUPID>
</DOCKINFO>
<DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
<DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
<MEMORYWININDEX>2</MEMORYWININDEX>
<MEMORYWINSETTINGS EXPRSTRING = "0xf0000600" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "1" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
</WINDOW>
<WINDOW>
<SESSION>1073741824</SESSION>
<EDOCTYPE>35</EDOCTYPE>
<FRAMELOC>
<X>1586</X>
<Y>31</Y>
</FRAMELOC>
<FRAMESIZE>
<W>484</W>
<H>907</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>0</STATUS>
<ROW></ROW>
<COLUMN></COLUMN>
<DOCKBARID></DOCKBARID>
<PCTWIDTH></PCTWIDTH>
<HGT></HGT>
<GROUPID>
<GIDHIGHPART></GIDHIGHPART>
<GIDLOWPART></GIDLOWPART>
</GROUPID>
</DOCKINFO>
<DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
<DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
<MEMORYWININDEX>4</MEMORYWININDEX>
<MEMORYWINSETTINGS EXPRSTRING = "0x1009626" SPACEINDEX = "1" VIEWINDEX = "4" WORDSIZE = "2" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
</WINDOW>
<WINDOW>
<SESSION>1073741824</SESSION>
<EDOCTYPE>35</EDOCTYPE>
<FRAMELOC>
<X>1185</X>
<Y>39</Y>
</FRAMELOC>
<FRAMESIZE>
<W>481</W>
<H>225</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>0</STATUS>
<ROW></ROW>
<COLUMN></COLUMN>
<DOCKBARID></DOCKBARID>
<PCTWIDTH></PCTWIDTH>
<HGT></HGT>
<GROUPID>
<GIDHIGHPART></GIDHIGHPART>
<GIDLOWPART></GIDLOWPART>
</GROUPID>
</DOCKINFO>
<DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
<DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
<MEMORYWININDEX>5</MEMORYWININDEX>
<MEMORYWINSETTINGS EXPRSTRING = "0xF" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "3" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
</WINDOW>
<WINDOW>
<SESSION>1073741824</SESSION>
<EDOCTYPE>35</EDOCTYPE>
<FRAMELOC>
<X>1100</X>
<Y>691</Y>
</FRAMELOC>
<FRAMESIZE>
<W>481</W>
<H>225</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>0</STATUS>
<ROW></ROW>
<COLUMN></COLUMN>
<DOCKBARID></DOCKBARID>
<PCTWIDTH></PCTWIDTH>
<HGT></HGT>
<GROUPID>
<GIDHIGHPART></GIDHIGHPART>
<GIDLOWPART></GIDLOWPART>
</GROUPID>
</DOCKINFO>
<DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
<DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
<MEMORYWININDEX>3</MEMORYWININDEX>
<MEMORYWINSETTINGS EXPRSTRING = "0x010077e2" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "3" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
</WINDOW>
<WINDOW>
<SESSION>1073741824</SESSION>
<EDOCTYPE>35</EDOCTYPE>
<FRAMELOC>
<X>645</X>
<Y>600</Y>
</FRAMELOC>
<FRAMESIZE>
<W>481</W>
<H>225</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>0</STATUS>
<ROW></ROW>
<COLUMN></COLUMN>
<DOCKBARID></DOCKBARID>
<PCTWIDTH></PCTWIDTH>
<HGT></HGT>
<GROUPID>
<GIDHIGHPART></GIDHIGHPART>
<GIDLOWPART></GIDLOWPART>
</GROUPID>
</DOCKINFO>
<DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
<DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
<MEMORYWININDEX>1</MEMORYWININDEX>
<MEMORYWINSETTINGS EXPRSTRING = "0xfffffa" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "1" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
</WINDOW>
<WINDOW>
<SESSION>-2147483648</SESSION>
<EDOCTYPE>24</EDOCTYPE>
<FRAMELOC>
<X>13</X>
<Y>33</Y>
</FRAMELOC>
<FRAMESIZE>
<W>591</W>
<H>742</H>
</FRAMESIZE>
<DOCKINFO>
<STATUS>0</STATUS>
<ROW></ROW>
<COLUMN></COLUMN>
<DOCKBARID></DOCKBARID>
<PCTWIDTH></PCTWIDTH>
<HGT></HGT>
<GROUPID>
<GIDHIGHPART></GIDHIGHPART>
<GIDLOWPART></GIDLOWPART>
</GROUPID>
</DOCKINFO>
</WINDOW>
<WINDOW>
<SESSION>-2147483648</SESSION>
<EDOCTYPE>28</EDOCTYPE>
<FRAMELOC>
<X>652</X>
<Y>33</Y>
</FRAMELOC>
<FRAMESIZE>
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362
BaS_GNU/Binaries/BaS_15_12_10.S19 Normal file
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BIN
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45217
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 222 10/21/2009 SJ Web Edition
# Date created = 12:11:46 March 06, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Coldari1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY Coldari1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:46 MARCH 06, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION 9.1

79
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Tue Sep 08 16:24:57 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY DSP IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
CLK33M : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
nFB_BURST : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nRSTO : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
nSRCS : INOUT STD_LOGIC;
nSRBLE : OUT STD_LOGIC;
nSRBHE : OUT STD_LOGIC;
nSRWE : OUT STD_LOGIC;
nSROE : OUT STD_LOGIC;
DSP_INT : OUT STD_LOGIC;
DSP_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END DSP;
-- Architecture Body
ARCHITECTURE DSP_architecture OF DSP IS
BEGIN
nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3;
nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
DSP_INT <= '0';
DSP_TA <= '0';
IO(17 downto 0) <= FB_ADR(18 downto 1);
SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
END DSP_architecture;

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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Tue Sep 08 16:24:57 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY DSP IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
CLK33M : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
nFB_BURST : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nRSTO : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
nSRCS : OUT STD_LOGIC;
nSRBLE : OUT STD_LOGIC;
nSRBHE : OUT STD_LOGIC;
nSRWE : OUT STD_LOGIC;
nSROE : OUT STD_LOGIC;
DSP_INT : OUT STD_LOGIC;
DSP_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END DSP;
-- Architecture Body
ARCHITECTURE DSP_architecture OF DSP IS
BEGIN
nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3;
nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
DSP_INT <= '0';
DSP_TA <= '0';
IO(17 downto 0) <= FB_ADR(18 downto 1);
SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
END DSP_architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity adgen_stage is port(
activate_adgen : in std_logic;
activate_x_mem : in std_logic;
activate_y_mem : in std_logic;
activate_l_mem : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
optional_ea_word : in std_logic_vector(23 downto 0);
register_file : in register_file_type;
adgen_mode_a : in adgen_mode_type;
adgen_mode_b : in adgen_mode_type;
address_out_x : out unsigned(BW_ADDRESS-1 downto 0);
address_out_y : out unsigned(BW_ADDRESS-1 downto 0);
wr_R_port_A_valid : out std_logic;
wr_R_port_A : out addr_wr_port_type;
wr_R_port_B_valid : out std_logic;
wr_R_port_B : out addr_wr_port_type
);
end entity;
architecture rtl of adgen_stage is
signal address_out_x_int : unsigned(BW_ADDRESS-1 downto 0);
begin
address_out_x <= address_out_x_int;
address_generator_X: process(activate_adgen, instr_word, register_file, adgen_mode_a) is
variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0);
variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0);
variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0);
variable op1 : unsigned(BW_ADDRESS-1 downto 0);
variable op2 : unsigned(BW_ADDRESS-1 downto 0);
variable addr_mod : unsigned(BW_ADDRESS-1 downto 0);
variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0);
variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0);
variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0);
variable bit_set : std_logic;
begin
r_reg_local := register_file.addr_r(to_integer(unsigned(instr_word(10 downto 8))));
n_reg_local := register_file.addr_n(to_integer(unsigned(instr_word(10 downto 8))));
m_reg_local := register_file.addr_m(to_integer(unsigned(instr_word(10 downto 8))));
-- select the operands for the calculation
case adgen_mode_a is
-- (Rn) - Nn
when POST_MIN_N => addr_mod := unsigned(- signed(n_reg_local));
-- (Rn) + Nn
when POST_PLUS_N => addr_mod := n_reg_local;
-- (Rn)-
when POST_MIN_1 => addr_mod := (others => '1'); -- -1
-- (Rn)+
when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS);
-- (Rn)
when NOP => addr_mod := (others => '0');
-- (Rn + Nn)
when INDEXED_N => addr_mod := n_reg_local;
-- -(Rn)
when PRE_MIN_1 => addr_mod := (others => '1'); -- - 1
-- absolute address (appended to instruction word)
when ABSOLUTE => addr_mod := (others => '0');
when IMMEDIATE => addr_mod := (others => '0');
end case;
op1 := r_reg_local;
op2 := addr_mod;
-- linear addressing
if m_reg_local = 2**BW_ADDRESS-1 then
op1 := r_reg_local;
op2 := addr_mod;
-- bit reverse operation
elsif m_reg_local = 0 then
-- reverse the input to the adder bit wise
-- so we just need to use a single adder
for i in 0 to BW_ADDRESS-1 loop
op1(BW_ADDRESS - 1 - i) := r_reg_local(i);
op2(BW_ADDRESS - 1 - i) := addr_mod(i);
end loop;
-- modulo arithmetic
else
bit_set := '0';
for i in BW_ADDRESS-1 downto 0 loop
if m_reg_local(i) = '1' then
bit_set := '1';
end if;
if bit_set = '1' then
modulo_bitmask(i) := '0';
else
modulo_bitmask(i) := '1';
end if;
end loop;
end if;
new_r_reg_interm := op1 + op2;
new_r_reg := new_r_reg_interm;
-- linear addressing
if m_reg_local = 2**BW_ADDRESS-1 then
new_r_reg := new_r_reg_interm;
-- bit reverse operation
elsif m_reg_local = 0 then
for i in 0 to BW_ADDRESS-1 loop
new_r_reg(BW_ADDRESS - 1 - i) := new_r_reg_interm(i);
end loop;
else
end if;
-- store the updated register in the global register file
-- do not store when we do nothing or there is nothing to update
-- LUA instructions DO NOT UPDATE the source register!!
if (adgen_mode_a = NOP or adgen_mode_a = ABSOLUTE or adgen_mode_a = IMMEDIATE or instr_array = INSTR_LUA) then
wr_R_port_A_valid <= '0';
else
wr_R_port_A_valid <= '1';
end if;
wr_R_port_A.reg_number <= unsigned(instr_word(10 downto 8));
wr_R_port_A.reg_value <= new_r_reg;
-- select the output of the AGU
case adgen_mode_a is
-- (Rn) - Nn
when POST_MIN_N => address_out_x_int <= r_reg_local;
-- (Rn) + Nn
when POST_PLUS_N => address_out_x_int <= r_reg_local;
-- (Rn)-
when POST_MIN_1 => address_out_x_int <= r_reg_local;
-- (Rn)+
when POST_PLUS_1 => address_out_x_int <= r_reg_local;
-- (Rn)
when NOP => address_out_x_int <= r_reg_local;
-- (Rn + Nn)
when INDEXED_N => address_out_x_int <= new_r_reg;
-- -(Rn)
when PRE_MIN_1 => address_out_x_int <= new_r_reg;
-- absolute address (appended to instruction word)
when ABSOLUTE => address_out_x_int <= unsigned(optional_ea_word(BW_ADDRESS-1 downto 0));
when IMMEDIATE => address_out_x_int <= r_reg_local; -- Done externally, value never used
end case;
-- LUA instructions only use the updated address!
if instr_array = INSTR_LUA then
address_out_x_int <= new_r_reg;
end if;
end process address_generator_X;
address_generator_Y: process(activate_adgen, activate_x_mem, activate_y_mem, activate_l_mem, instr_word,
register_file, adgen_mode_b, address_out_x_int) is
variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0);
variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0);
variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0);
variable op2 : unsigned(BW_ADDRESS-1 downto 0);
variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0);
begin
r_reg_local := register_file.addr_r(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
n_reg_local := register_file.addr_n(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
m_reg_local := register_file.addr_m(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
-- select the operands for the calculation
case adgen_mode_b is
-- (Rn) + Nn
when POST_PLUS_N => op2 := n_reg_local;
-- (Rn)-
when POST_MIN_1 => op2 := (others => '1'); -- -1
-- (Rn)+
when POST_PLUS_1 => op2 := to_unsigned(1, BW_ADDRESS);
-- (Rn)
when others => op2 := (others => '0');
end case;
new_r_reg := r_reg_local + op2;
-- TODO: USE modifier register!
-- store the updated register in the global register file
-- do not store when we do nothing or there is nothing to update
if adgen_mode_b = NOP then
wr_R_port_B_valid <= '0';
else
wr_R_port_B_valid <= '1';
end if;
wr_R_port_B.reg_number <= unsigned((not instr_word(10)) & instr_word(14 downto 13));
wr_R_port_B.reg_value <= new_r_reg;
-- the address for the y memory is calculated in the first AGU if the x memory is not accessed!
-- so use the other output as address output for the y memory!
-- Furthermore, use the same address for L memory accesses (X and Y memory access the same address!)
if (activate_y_mem = '1' and activate_x_mem = '0') or activate_l_mem = '1' then
address_out_y <= address_out_x_int;
-- in any other case use the locally computed value
else
-- select the output of the AGU
case adgen_mode_b is
-- (Rn) + Nn
when POST_PLUS_N => address_out_y <= r_reg_local;
-- (Rn)-
when POST_MIN_1 => address_out_y <= r_reg_local;
-- (Rn)+
when POST_PLUS_1 => address_out_y <= r_reg_local;
-- (Rn)
when others => address_out_y <= r_reg_local;
end case;
end if;
end process address_generator_Y;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
package constants_pkg is
-------------------------
-- Flags in CCR register
-------------------------
constant C_FLAG : natural := 0;
constant V_FLAG : natural := 1;
constant Z_FLAG : natural := 2;
constant N_FLAG : natural := 3;
constant U_FLAG : natural := 4;
constant E_FLAG : natural := 5;
constant L_FLAG : natural := 6;
constant S_FLAG : natural := 7;
-------------------
-- Pipeline stages
-------------------
constant ST_FETCH : natural := 0;
constant ST_FETCH2 : natural := 1;
constant ST_DECODE : natural := 2;
constant ST_ADGEN : natural := 3;
constant ST_EXEC : natural := 4;
----------------------
-- Activation signals
----------------------
constant ACT_ADGEN : natural := 0; -- Run the address generator
constant ACT_ALU : natural := 1; -- Activation of ALU results in modification of the status register
constant ACT_EXEC_BRA : natural := 2; -- Branch (in execute stage)
constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage)
constant ACT_EXEC_LOOP : natural := 4; -- Loop instruction (REP, DO)
constant ACT_X_MEM_RD : natural := 5; -- Init read from X memory
constant ACT_Y_MEM_RD : natural := 6; -- Init read from Y memory
constant ACT_P_MEM_RD : natural := 7; -- Init read from P memory
constant ACT_X_MEM_WR : natural := 8; -- Init write to X memory
constant ACT_Y_MEM_WR : natural := 9; -- Init write to Y memory
constant ACT_P_MEM_WR : natural := 10; -- Init write to P memory
constant ACT_REG_RD : natural := 11; -- Read from register (6 bit addressing)
constant ACT_REG_WR : natural := 12; -- Write to register (6 bit addressing)
constant ACT_IMM_8BIT : natural := 13; -- 8 bit immediate operand (in instruction word)
constant ACT_IMM_12BIT : natural := 14; -- 12 bit immediate operand (in instruction word)
constant ACT_IMM_LONG : natural := 15; -- 24 bit immediate operant (in optional instruction word)
constant ACT_X_BUS_RD : natural := 16; -- Read data via X-bus (from x0,x1,a,b)
constant ACT_X_BUS_WR : natural := 17; -- Write data via X-bus (to x0,x1,a,b)
constant ACT_Y_BUS_RD : natural := 18; -- Read data via Y-bus (from y0,y1,a,b)
constant ACT_Y_BUS_WR : natural := 19; -- Write data via Y-bus (to y0,y1,a,b)
constant ACT_L_BUS_RD : natural := 20; -- Read data via L-bus (from a10, b10,x,y,a,b,ab,ba)
constant ACT_L_BUS_WR : natural := 21; -- Write data via L-bus (to a10, b10,x,y,a,b,ab,ba)
constant ACT_BIT_MOD_WR : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG)
constant ACT_REG_WR_CC : natural := 23; -- Write to register file conditionally (Tcc)
constant ACT_ALU_WR_CC : natural := 24; -- Write ALU result conditionally (Tcc)
constant ACT_NORM : natural := 25; -- NORM instruction needs special handling
end package constants_pkg;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity exec_stage_alu is port(
alu_activate : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
alu_ctrl : in alu_ctrl_type;
register_file : in register_file_type;
addr_r_in : in unsigned(BW_ADDRESS-1 downto 0);
addr_r_out : out unsigned(BW_ADDRESS-1 downto 0);
modify_accu : out std_logic;
dst_accu : out std_logic;
modified_accu : out signed(55 downto 0);
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of exec_stage_alu is
signal alu_shifter_out : signed(55 downto 0);
signal alu_shifter_carry_out : std_logic;
signal alu_shifter_overflow_out : std_logic;
signal alu_logic_conj : signed(55 downto 0);
signal alu_multiplier_out : signed(55 downto 0);
signal alu_src_op : signed(55 downto 0);
signal alu_add_result : signed(56 downto 0);
signal alu_add_carry_out : std_logic;
signal alu_post_adder_result : signed(56 downto 0);
signal scaling_mode : std_logic_vector(1 downto 0);
signal modified_accu_int : signed(55 downto 0);
signal norm_instr_asl : std_logic;
signal norm_instr_asr : std_logic;
signal norm_instr_nop : std_logic;
signal norm_update_ccr : std_logic;
begin
-- store calculated value?
modify_accu <= alu_ctrl.store_result;
modified_accu <= modified_accu_int;
-- for the norm instruction we first need to determine whether we have to
-- update the CCR register or not
modify_sr <= alu_activate when alu_ctrl.norm_instr = '0' else
norm_update_ccr;
dst_accu <= alu_ctrl.dst_accu;
scaling_mode <= register_file.sr(11 downto 10);
calcule_ccr_flags: process(register_file, alu_ctrl, alu_shifter_carry_out,
alu_post_adder_result, modified_accu_int, alu_add_carry_out) is
begin
-- by default do not modify the flags in the status register
modified_sr <= register_file.sr;
-- Carry flag generation
-------------------------
case alu_ctrl.ccr_flags_ctrl(C_FLAG) is
when CLEAR => modified_sr(C_FLAG) <= '0';
when SET => modified_sr(C_FLAG) <= '1';
when MODIFY =>
-- the carry flag can stem from the shifter or from the post adder
-- in case we shift and add only a zero to the shift result (ASL, ASR, LSL, LSR, ROL, ROR)
-- take the carry flag from the shifter, else from the post adder
if (alu_ctrl.shift_mode = SHIFT_LEFT or alu_ctrl.shift_mode = SHIFT_RIGHT) and
alu_ctrl.add_src_stage_2 = "00" then -- add zero after shifting?
modified_sr(C_FLAG) <= alu_shifter_carry_out;
elsif alu_ctrl.div_instr = '1' then
modified_sr(C_FLAG) <= not std_logic(alu_post_adder_result(55));
else
-- modified_sr(C_FLAG) <= std_logic(alu_post_adder_result(57));
modified_sr(C_FLAG) <= alu_add_carry_out;
end if;
when others => -- Don't touch
end case;
-- Overflow flag generation
----------------------------
case alu_ctrl.ccr_flags_ctrl(V_FLAG) is
when CLEAR => modified_sr(V_FLAG) <= '0';
when SET => modified_sr(V_FLAG) <= '1';
when MODIFY =>
-- There are two sources for the overflow flag:
-- 1)
-- in case the result cannot be represented using 56 bits set
-- the overflow flag. this is the case when the two MSBs of
-- the 57 bit result are different
-- 2)
-- The shifter circuit performs a 56 bit left shift. In case the
-- two MSBs of the operand are different set the overflow flag as well
if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
(alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and
alu_shifter_overflow_out = '1' ) then
modified_sr(V_FLAG) <= '1';
else
modified_sr(V_FLAG) <= '0';
end if;
when others => -- Don't touch
end case;
-- Zero flag generation
----------------------------
case alu_ctrl.ccr_flags_ctrl(Z_FLAG) is
when CLEAR => modified_sr(Z_FLAG) <= '0';
when SET => modified_sr(Z_FLAG) <= '1';
when MODIFY =>
-- in case the result is zero set this flag
-- distinguish between 24 bit and 56 bit ALU operations
-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
if (alu_ctrl.word_24_update = '1' and modified_accu_int(47 downto 24) = 0) or
(alu_ctrl.word_24_update = '0' and modified_accu_int(55 downto 0) = 0) then
modified_sr(Z_FLAG) <= '1';
else
modified_sr(Z_FLAG) <= '0';
end if;
when others => -- Don't touch
end case;
-- Negative flag generation
----------------------------
case alu_ctrl.ccr_flags_ctrl(N_FLAG) is
when CLEAR => modified_sr(N_FLAG) <= '0';
when SET => modified_sr(N_FLAG) <= '1';
when MODIFY =>
-- in case the result is negative set this flag
-- distinguish between 24 bit and 56 bit ALU operations
-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
if alu_ctrl.word_24_update = '1' then
modified_sr(N_FLAG) <= std_logic(modified_accu_int(47));
else
modified_sr(N_FLAG) <= std_logic(modified_accu_int(55));
end if;
when others => -- Don't touch
end case;
-- Unnormalized flag generation
----------------------------
case alu_ctrl.ccr_flags_ctrl(U_FLAG) is
when CLEAR => modified_sr(U_FLAG) <= '0';
when SET => modified_sr(U_FLAG) <= '1';
when MODIFY =>
-- Set unnormalized bit according to the scaling mode
if (scaling_mode = "00" and alu_post_adder_result(47) = alu_post_adder_result(46)) or
(scaling_mode = "01" and alu_post_adder_result(48) = alu_post_adder_result(47)) or
(scaling_mode = "10" and alu_post_adder_result(46) = alu_post_adder_result(45)) then
modified_sr(U_FLAG) <= '1';
else
modified_sr(U_FLAG) <= '0';
end if;
when others => -- Don't touch
end case;
-- Extension flag generation
----------------------------
case alu_ctrl.ccr_flags_ctrl(E_FLAG) is
when CLEAR => modified_sr(E_FLAG) <= '0';
when SET => modified_sr(E_FLAG) <= '1';
when MODIFY =>
-- Set extension flag by default
modified_sr(E_FLAG) <= '1';
-- Clear extension flag according to the scaling mode
case scaling_mode is
when "00" =>
if alu_post_adder_result(55 downto 47) = "111111111" or alu_post_adder_result(55 downto 47) = "000000000" then
modified_sr(E_FLAG) <= '0';
end if;
when "01" =>
if alu_post_adder_result(55 downto 48) = "11111111" or alu_post_adder_result(55 downto 48) = "00000000" then
modified_sr(E_FLAG) <= '0';
end if;
when "10" =>
if alu_post_adder_result(55 downto 46) = "1111111111" or alu_post_adder_result(55 downto 46) = "0000000000" then
modified_sr(E_FLAG) <= '0';
end if;
when others =>
modified_sr(E_FLAG) <= '0';
end case;
when others => -- Don't touch
end case;
-- Limit flag generation (equals overflow flag generaton!)
-- Clearing of the Limit flag has to be done by the user!
-----------------------------------------------------------
case alu_ctrl.ccr_flags_ctrl(L_FLAG) is
when CLEAR => modified_sr(L_FLAG) <= '0';
when SET => modified_sr(L_FLAG) <= '1';
when MODIFY =>
-- There are two sources for the overflow flag:
-- 1)
-- in case the result cannot be represented using 56 bits set
-- the overflow flag. this is the case when the two MSBs of
-- the 57 bit result are different
-- 2)
-- The shifter circuit performs a 56 bit left shift. In case the
-- two MSBs of the operand are different set the overflow flag as well
if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
(alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and
alu_shifter_overflow_out = '1' ) then
modified_sr(L_FLAG) <= '1';
end if;
when others => -- Don't touch
end case;
-- Scaling flag generation (DSP56002 and up)
--------------------------------------------
-- Scaling flag is not generated in the ALU, but when A or B are read to the XDB or YDB
end process;
src_operand_select: process(register_file, alu_ctrl) is
begin
-- decoding according similar to JJJ representation
case alu_ctrl.add_src_stage_1 is
when "000" =>
-- select depending on destination accu
if alu_ctrl.dst_accu = '0' then
alu_src_op <= register_file.a;
else
alu_src_op <= register_file.b;
end if;
when "001" => -- A,B or B,A
-- select depending on destination accu
if alu_ctrl.dst_accu = '0' then
alu_src_op <= register_file.b;
else
alu_src_op <= register_file.a;
end if;
when "010" => -- X
alu_src_op(55 downto 48) <= (others => register_file.x1(23));
alu_src_op(47 downto 0) <= register_file.x1 & register_file.x0;
when "011" => -- Y
alu_src_op(55 downto 48) <= (others => register_file.y1(23));
alu_src_op(47 downto 0) <= register_file.y1 & register_file.y0;
when "100" => -- x0
alu_src_op(55 downto 48) <= (others => register_file.x0(23));
alu_src_op(47 downto 24) <= register_file.x0;
alu_src_op(23 downto 0) <= (others => '0');
when "101" => -- y0
alu_src_op(55 downto 48) <= (others => register_file.y0(23));
alu_src_op(47 downto 24) <= register_file.y0;
alu_src_op(23 downto 0) <= (others => '0');
when "110" => -- x1
alu_src_op(55 downto 48) <= (others => register_file.x1(23));
alu_src_op(47 downto 24) <= register_file.x1;
alu_src_op(23 downto 0) <= (others => '0');
when "111" => -- y1
alu_src_op(55 downto 48) <= (others => register_file.y1(23));
alu_src_op(47 downto 24) <= register_file.y1;
alu_src_op(23 downto 0) <= (others => '0');
when others =>
end case;
end process;
alu_logical_functions: process(alu_ctrl, alu_src_op, alu_shifter_out) is
begin
alu_logic_conj <= alu_shifter_out;
case alu_ctrl.logic_function is
when "110" =>
alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) and alu_src_op(47 downto 24);
when "010" =>
alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) or alu_src_op(47 downto 24);
when "011" =>
alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) xor alu_src_op(47 downto 24);
when "111" =>
alu_logic_conj(47 downto 24) <= not alu_shifter_out(47 downto 24);
when others =>
end case;
end process;
alu_adder : process(alu_ctrl, alu_src_op, alu_multiplier_out, alu_shifter_out) is
variable add_src_op_1 : signed(56 downto 0);
variable add_src_op_2 : signed(56 downto 0);
variable carry_const : signed(56 downto 0);
variable alu_shifter_out_57 : signed(56 downto 0);
variable alu_add_result_58 : signed(57 downto 0);
variable alu_add_result_interm : signed(56 downto 0);
variable invert_carry_flag : std_logic;
begin
-- by default do not invert the carry
invert_carry_flag := '0';
-- determine whether to use multiplier output, the operand defined above, or zeros!
-- resizing is done here already. Like that we can see whether an overflow
-- occurs due to negating the source operand
case alu_ctrl.add_src_stage_2 is
when "00" => add_src_op_1 := (others => '0');
when "10" => add_src_op_1 := resize(alu_multiplier_out, 57);
when others => add_src_op_1 := resize(alu_src_op, 57);
end case;
-- determine the sign for the 1st operand!
case alu_ctrl.add_src_sign is
-- normal operation
when "00" => add_src_op_1 := add_src_op_1;
-- negative sign
when "01" => add_src_op_1 := - add_src_op_1;
invert_carry_flag := not invert_carry_flag;
-- change according to sign
-- performs - | accu | for the CMPM instruction
when "10" =>
-- we subtract in any case, so invert the carry!
invert_carry_flag := not invert_carry_flag;
if add_src_op_1(55) = '0' then
add_src_op_1 := - add_src_op_1;
else
add_src_op_1 := add_src_op_1;
end if;
-- div instruction!
-- sign dependant of D[55] XOR S[23], if 1 => positive , if 0 => negative
-- add_src_op_1 holds S[23] (sign extension!)
when others =>
if (alu_ctrl.shift_src = '0' and add_src_op_1(55) /= register_file.a(55)) or
(alu_ctrl.shift_src = '1' and add_src_op_1(55) /= register_file.b(55)) then
add_src_op_1 := add_src_op_1;
else
add_src_op_1 := - add_src_op_1;
-- invert_carry_flag := not invert_carry_flag;
end if;
end case;
alu_shifter_out_57 := resize(alu_shifter_out, 57);
-- determine the sign for the 2nd operand (coming from the shifter)!
case alu_ctrl.shift_src_sign is
-- negative sign
when "01" =>
add_src_op_2 := - alu_shifter_out_57;
-- change according to sign
-- this allows to build the magnitude (ABS, CMPM)
when "10" =>
if alu_shifter_out(55) = '1' then
add_src_op_2 := - alu_shifter_out_57;
else
add_src_op_2 := alu_shifter_out_57;
end if;
when others =>
add_src_op_2 := alu_shifter_out_57;
end case;
-- determine whether carry flag has to be added or subtracted
if alu_ctrl.rounding_used = "10" then
-- add carry flag
carry_const(0) := register_file.sr(C_FLAG);
elsif alu_ctrl.rounding_used = "11" then
-- subtract carry flag
carry_const := (others => register_file.sr(0)); -- carry flag
else
carry_const := (others => '0');
end if;
-- add the values and calculate the carry bit
alu_add_result_interm := ('0' & add_src_op_1(55 downto 0)) +
('0' & add_src_op_2(55 downto 0)) +
('0' & carry_const(55 downto 0));
-- here pops the new carry out of the adder
if invert_carry_flag = '0' then
alu_add_carry_out <= alu_add_result_interm(56);
else
alu_add_carry_out <= not alu_add_result_interm(56);
end if;
-- calculate the last bit (56), in order to test for overflow later on
alu_add_result(55 downto 0) <= alu_add_result_interm(55 downto 0);
-- alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) xor alu_add_result_interm(56);
alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56)
xor carry_const(56) xor alu_add_result_interm(56);
end process alu_adder;
-- Adder after the normal arithmetic adder
-- This adder is responsible for
-- -- 1) carry addition
-- -- 2) carry subtration
-- 3) convergent rounding
alu_post_adder: process(alu_add_result, scaling_mode, alu_ctrl) is
variable post_adder_constant : signed(56 downto 0);
variable testing_constant : signed(24 downto 0);
begin
-- by default add nothing
post_adder_constant := (others => '0');
case alu_ctrl.rounding_used is
-- rounding dependant on scaling bits
when "01" =>
case scaling_mode is
-- no scaling
when "00" => testing_constant := alu_add_result(23 downto 0) & '0';
-- scale down
when "01" => testing_constant := alu_add_result(24 downto 0);
-- scale up
when "10" => testing_constant := alu_add_result(22 downto 0) & "00";
when others =>
testing_constant := alu_add_result(23 downto 0) & '0';
end case;
-- Special case!
if testing_constant(24) = '1' and testing_constant(23 downto 0) = X"000000" then
-- add depending on bit left to the rounding position
case scaling_mode is
-- no scaling
when "00" => post_adder_constant(23) := alu_add_result(24);
-- scale down
when "01" => post_adder_constant(24) := alu_add_result(25);
-- scale up
when "10" => post_adder_constant(22) := alu_add_result(23);
when others =>
end case;
else -- testing_constant /= X"1000000"
-- add rounding constant depending on scaling mode
-- results in round up if MSB of testing constant is set, else nothing happens
case scaling_mode is
-- no scaling
when "00" => post_adder_constant(23) := '1';
-- scale down
when "01" => post_adder_constant(24) := '1';
-- scale up
when "10" => post_adder_constant(22) := '1';
when others =>
end case;
end if;
-- no rounding
when others =>
post_adder_constant := (others => '0');
end case;
-- Add the result of the first adder to the constant (e.g., carry flag)
alu_post_adder_result <= alu_add_result + post_adder_constant;
-- When rounding is used set 24 LSBs to zero!
if alu_ctrl.rounding_used = "01" then
alu_post_adder_result(23 downto 0) <= (others => '0');
end if;
end process;
alu_select_new_accu: process(alu_post_adder_result, alu_logic_conj, alu_ctrl) is
begin
if alu_ctrl.logic_function /= "000" then
modified_accu_int <= alu_logic_conj;
else
modified_accu_int <= alu_post_adder_result(55 downto 0);
end if;
end process;
-- contains the 24*24 bit fractional multiplier
alu_multiplier : process(register_file, alu_ctrl) is
variable src_op1: signed(23 downto 0);
variable src_op2: signed(23 downto 0);
variable mul_result_interm : signed(47 downto 0);
begin
-- select source operands for multiplication
case alu_ctrl.mul_op1 is
when "00" => src_op1 := register_file.x0;
when "01" => src_op1 := register_file.x1;
when "10" => src_op1 := register_file.y0;
when others => src_op1 := register_file.y1;
end case;
case alu_ctrl.mul_op2 is
when "00" => src_op2 := register_file.x0;
when "01" => src_op2 := register_file.x1;
when "10" => src_op2 := register_file.y0;
when others => src_op2 := register_file.y1;
end case;
-- perform integer multiplication
mul_result_interm := src_op1 * src_op2;
-- sign extension of result
alu_multiplier_out(55 downto 48) <= (others => mul_result_interm(47));
-- convert from two's complement representation to fractional format
-- signed integer multiplication delivers twice the sign bit, but only one is needed for the
-- fractional multiplication, so remove one and append a zero to the result
alu_multiplier_out(47 downto 0) <= mul_result_interm(46 downto 0) & '0';
end process alu_multiplier;
-- contains the data shifter
alu_shifter: process(register_file, alu_ctrl, norm_instr_asl, norm_instr_asr) is
variable src_accu : signed(55 downto 0);
variable shift_to_perform : alu_shift_mode;
begin
-- read source accumulator
if alu_ctrl.shift_src = '0' then
src_accu := register_file.a;
else
src_accu := register_file.b;
end if;
alu_shifter_carry_out <= '0';
alu_shifter_overflow_out <= '0';
-- NORM instruction determines the shift value just
-- in time, so overwrite the flag from the alu_ctrl
-- for this instruction by the calculated value
if alu_ctrl.norm_instr = '0' then
shift_to_perform := alu_ctrl.shift_mode;
else
if norm_instr_asl = '1' then
shift_to_perform := SHIFT_LEFT;
elsif norm_instr_asr = '1' then
shift_to_perform := SHIFT_RIGHT;
else
shift_to_perform := NO_SHIFT;
end if;
end if;
case shift_to_perform is
when NO_SHIFT =>
alu_shifter_out <= src_accu;
when SHIFT_LEFT =>
-- ASL, ADDL, DIV?
if alu_ctrl.word_24_update = '0' then
-- special handling for div instruction required
if alu_ctrl.div_instr = '1' then
alu_shifter_out <= src_accu(54 downto 0) & register_file.sr(C_FLAG);
else
alu_shifter_out <= src_accu(54 downto 0) & '0';
end if;
alu_shifter_carry_out <= src_accu(55);
-- detect overflow that results from left shifting
-- Needed for ASL, ADDL, DIV instructions
if src_accu(55) /= src_accu(54) then
alu_shifter_overflow_out <= '1';
end if;
-- LSL/ROL?
elsif alu_ctrl.word_24_update = '1' then
alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
alu_shifter_out(23 downto 0) <= src_accu(23 downto 0);
alu_shifter_carry_out <= src_accu(47);
if alu_ctrl.rotate = '0' then -- LSL ?
alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & '0';
else -- ROL ?
alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & register_file.sr(C_FLAG);
end if;
end if;
when SHIFT_RIGHT =>
-- ASR?
if alu_ctrl.word_24_update = '0' then
alu_shifter_out <= src_accu(55) & src_accu(55 downto 1);
alu_shifter_carry_out <= src_accu(0);
-- LSR/ROR?
elsif alu_ctrl.word_24_update = '1' then
alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
alu_shifter_out(23 downto 0) <= src_accu(23 downto 0);
alu_shifter_carry_out <= src_accu(24);
if alu_ctrl.rotate = '0' then -- LSR
alu_shifter_out(47 downto 24) <= '0' & src_accu(47 downto 25);
else -- ROR
alu_shifter_out(47 downto 24) <= register_file.sr(C_FLAG) & src_accu(47 downto 25);
end if;
end if;
when ZEROS =>
alu_shifter_out <= (others => '0');
end case;
end process alu_shifter;
-- Special handling for NORM instruction
-- Determine which case occurs (see User's Manual for more information)
norm_instr_logic: process(register_file, addr_r_in) is
begin
norm_instr_asl <= '0';
norm_instr_asr <= '0';
-- Either left shift
if register_file.sr(E_FLAG) = '0' and
register_file.sr(U_FLAG) = '1' and
register_file.sr(Z_FLAG) = '0' then
norm_instr_asl <= '1';
norm_update_ccr <= '1';
addr_r_out <= addr_r_in - 1;
-- Or right shift
elsif register_file.sr(E_FLAG) = '1' then
norm_instr_asr <= '1';
norm_update_ccr <= '1';
addr_r_out <= addr_r_in + 1;
-- Or do nothing!
else
norm_update_ccr <= '0';
addr_r_out <= addr_r_in;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity exec_stage_bit_modify is port(
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
src_operand : in std_logic_vector(23 downto 0);
register_file : in register_file_type;
dst_operand : out std_logic_vector(23 downto 0);
bit_cond_met : out std_logic;
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of exec_stage_bit_modify is
signal operand_bit : std_logic;
signal src_operand_32 : std_logic_vector(31 downto 0);
begin
-- this is just a helper signal to prevent the simulator
-- to stop when accessing a bit > 23.
src_operand_32 <= "00000000" & src_operand;
-- read the bit we want to test (and modify)
operand_bit <= src_operand_32(to_integer(unsigned(instr_word(4 downto 0))));
-- modify the Carry flag only for the bit modify instructions!
modify_sr <= '1' when instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG or instr_array = INSTR_BTST else '0';
modified_sr <= register_file.sr(15 downto 1) & operand_bit;
bit_operation: process(instr_word, instr_array, src_operand, operand_bit) is
variable new_bit : std_logic;
begin
-- do nothing by default!
dst_operand <= src_operand;
bit_cond_met <= '0';
-- determine which bit to write
if instr_array = INSTR_BCLR then
new_bit := '0';
elsif instr_array = INSTR_BSET then
new_bit := '1';
else -- BCHG
new_bit := not operand_bit;
end if;
if instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG then
dst_operand(to_integer(unsigned(instr_word(4 downto 0)))) <= new_bit;
end if;
-- check for the jump instructions whether condition is met or not!
if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR then
if operand_bit = '0' then
bit_cond_met <= '1';
else
bit_cond_met <= '0';
end if;
end if;
if instr_array = INSTR_JSET or instr_array = INSTR_JSSET then
if operand_bit = '0' then
bit_cond_met <= '0';
else
bit_cond_met <= '1';
end if;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity exec_stage_branch is port(
activate_exec_bra : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
register_file : in register_file_type;
jump_address : in unsigned(BW_ADDRESS-1 downto 0);
bit_cond_met : in std_logic;
cc_flag_set : in std_logic;
push_stack : out push_stack_type;
pop_stack : out pop_stack_type;
modify_pc : out std_logic;
modified_pc : out unsigned(BW_ADDRESS-1 downto 0);
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of exec_stage_branch is
signal branch_condition_met : std_logic;
signal modify_pc_int : std_logic;
begin
modify_pc_int <= '1' when activate_exec_bra = '1' and branch_condition_met = '1' else '0';
modify_pc <= modify_pc_int;
calculate_branch_condition : process(instr_word, instr_array, register_file, bit_cond_met)
begin
branch_condition_met <= '0';
-- unconditional jumps
if instr_array = INSTR_JMP or
instr_array = INSTR_JSR or
instr_array = INSTR_RTI or
instr_array = INSTR_RTS then
-- jump always
branch_condition_met <= '1';
end if;
-- then see whether the branch condition is satisfied
if instr_array = INSTR_JCC or instr_array = INSTR_JSCC then
branch_condition_met <= cc_flag_set;
end if;
-- jmp that is executed according to a certain bit condition
if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR or
instr_array = INSTR_JSET or instr_array = INSTR_JSSET then
branch_condition_met <= bit_cond_met;
end if;
end process calculate_branch_condition;
calculate_branch_target : process(instr_array, instr_word, jump_address)
begin
modified_pc <= jump_address;
-- address calculation is the same for the following instructions
if instr_array = INSTR_JMP or
instr_array = INSTR_JCC or
instr_array = INSTR_JSCC or
instr_array = INSTR_JSR then
if instr_word(18) = '1' then
-- short jump address included in opcode (bits 11 downto 0)
modified_pc(11 downto 0) <= unsigned(instr_word(11 downto 0));
elsif instr_word(18) = '0' then
-- effective address defined by opcode and coming from address generator unit
modified_pc <= jump_address;
end if;
end if;
-- jump address contains the obligatory address of the second
-- instruction word
if instr_array = INSTR_JCLR or
instr_array = INSTR_JSET or
instr_array = INSTR_JSCLR or
instr_array = INSTR_JSSET then
modified_pc <= jump_address;
end if;
-- target address is stored on the stack
if instr_array = INSTR_RTS or
instr_array = INSTR_RTI then
modified_pc <= unsigned(register_file.current_ssh);
end if;
end process calculate_branch_target;
-- Subroutine functions need to store PC and SR on the stack
push_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_JSCC or instr_array = INSTR_JSR or
instr_array = INSTR_JSCLR or instr_array = INSTR_JSSET) else '0';
push_stack.content <= PC_AND_SR;
-- pc is set externally!
push_stack.pc <= (others => '0');
-- RTI/RTS instructions need to read from the stack
pop_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_RTI or instr_array = INSTR_RTS) else '0';
-- some instructions require to set the SR
calculate_status_register : process(instr_array)
begin
modify_sr <= '0';
modified_sr <= (others => '0');
if instr_array = INSTR_RTI then
modify_sr <= '1';
modified_sr <= register_file.current_ssl;
end if;
end process calculate_status_register;
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity exec_stage_cc_flag_calc is port(
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
register_file : in register_file_type;
cc_flag_set : out std_logic
);
end entity;
architecture rtl of exec_stage_cc_flag_calc is
begin
calculate_cc_flag : process(instr_word, instr_array, register_file)
variable cc_select : std_logic_vector(3 downto 0);
procedure calculate_cc_flag(cc: std_logic_vector(3 downto 0)) is
variable c_flag : std_logic := register_file.ccr(0);
variable v_flag : std_logic := register_file.ccr(1);
variable z_flag : std_logic := register_file.ccr(2);
variable n_flag : std_logic := register_file.ccr(3);
variable u_flag : std_logic := register_file.ccr(4);
variable e_flag : std_logic := register_file.ccr(5);
variable l_flag : std_logic := register_file.ccr(6);
begin
if (cc = "0000" and c_flag = '0') or -- CC: carry clear
(cc = "1000" and c_flag = '1') or -- CS: carry set
(cc = "0101" and e_flag = '0') or -- EC: extension clear
(cc = "1010" and z_flag = '1') or -- EQ: equal
(cc = "1101" and e_flag = '1') or -- ES: extension set
(cc = "0001" and (n_flag = v_flag)) or -- GE: greater than or equal
(cc = "0001" and ((n_flag xor v_flag) or z_flag) = '0') or -- GT: greater than
(cc = "0110" and l_flag = '0') or -- LC: limit clear
(cc = "1111" and ((n_flag xor v_flag) or z_flag ) = '1') or -- LE: less or equal
(cc = "1110" and l_flag = '1') or -- LS: limit set
(cc = "1001" and (n_flag /= v_flag)) or -- LT: less than
(cc = "1011" and n_flag = '1') or -- MI: minus
(cc = "0010" and z_flag = '0') or -- NE: not equal
(cc = "1100" and (( not u_flag and not e_flag) or z_flag) = '1') or -- NR: normalized
(cc = "0011" and n_flag = '0') or -- PL: plus
(cc = "0100" and (( not u_flag and not e_flag ) or z_flag) = '0') -- NN: not normalized
then
cc_flag_set <= '1';
end if;
end procedure;
begin
cc_flag_set <= '0';
-- Rip the flags we have to test for from the instruction word
if (instr_array = INSTR_JCC and instr_word(18) = '0') or
(instr_array = INSTR_JSCC) then
cc_select := instr_word(3 downto 0);
else
cc_select := instr_word(15 downto 12);
end if;
calculate_cc_flag(cc_select);
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity exec_stage_cr_mod is port (
activate_exec_cr_mod : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
register_file : in register_file_type;
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0);
modify_omr : out std_logic;
modified_omr : out std_logic_vector(7 downto 0)
);
end exec_stage_cr_mod;
architecture rtl of exec_stage_cr_mod is
begin
process(activate_exec_cr_mod, instr_word, instr_array, register_file) is
variable imm8 : std_logic_vector(7 downto 0);
variable op8 : std_logic_vector(7 downto 0);
variable res8 : std_logic_vector(7 downto 0);
begin
modify_sr <= '0';
modify_omr <= '0';
modified_sr <= (others => '0');
modified_omr <= (others => '0');
imm8 := instr_word(15 downto 8);
if instr_word(1 downto 0) = "00" then
-- read MR
op8 := register_file.mr;
elsif instr_word(1 downto 0) = "01" then
-- read CCR
op8 := register_file.ccr;
else -- instr_word(1 downto 0) = "10"
-- read OMR
op8 := register_file.omr;
end if;
if instr_array = INSTR_ANDI then
res8 := imm8 and op8;
else -- instr_array = INSTR_ORI
res8 := imm8 or op8;
end if;
-- only write the result when activated
if activate_exec_cr_mod = '1' then
if instr_word(1 downto 0) = "00" then
-- update MR
modify_sr <= '1';
modified_sr <= res8 & register_file.ccr;
elsif instr_word(1 downto 0) = "01" then
-- update CCR
modify_sr <= '1';
modified_sr <= register_file.mr & res8;
elsif instr_word(1 downto 0) = "10" then
-- update OMR
modify_omr <= '1';
modified_omr <= res8;
end if;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity exec_stage_loop is port(
clk, rst : in std_logic;
activate_exec_loop : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
loop_iterations : in unsigned(15 downto 0);
loop_address : in unsigned(BW_ADDRESS-1 downto 0);
loop_start_address: in unsigned(BW_ADDRESS-1 downto 0);
register_file : in register_file_type;
fetch_perform_enddo: in std_logic;
memory_stall : in std_logic;
push_stack : out push_stack_type;
pop_stack : out pop_stack_type;
stall_rep : out std_logic;
stall_do : out std_logic;
decrement_lc : out std_logic;
modify_lc : out std_logic;
modified_lc : out unsigned(15 downto 0);
modify_la : out std_logic;
modified_la : out unsigned(15 downto 0);
modify_pc : out std_logic;
modified_pc : out unsigned(BW_ADDRESS-1 downto 0);
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of exec_stage_loop is
signal rep_loop_polling : std_logic;
signal do_loop_polling : std_logic;
signal enddo_polling : std_logic;
signal lc_temp : unsigned(15 downto 0);
signal rf_lc_eq_1 : std_logic;
signal memory_stall_t : std_logic;
begin
modified_pc <= loop_start_address;
-- loop counter in register file equal to 1?
rf_lc_eq_1 <= '1' when register_file.lc = 1 else '0';
process(activate_exec_loop, instr_array, register_file, fetch_perform_enddo,
rep_loop_polling, loop_iterations, rf_lc_eq_1, loop_start_address) is
begin
stall_rep <= '0';
stall_do <= '0';
modify_la <= '0';
modify_lc <= '0';
modify_pc <= '0';
modify_sr <= '0';
modified_la <= loop_address;
modified_lc <= loop_iterations; -- default
-- set the loop flag LF (bit 15) of Status register
modified_sr(15) <= '1';
modified_sr(14 downto 0) <= register_file.sr(14 downto 0);
push_stack.valid <= '0'; -- push PC and SR on the stack
push_stack.pc <= loop_start_address;
push_stack.content <= LA_AND_LC;
pop_stack.valid <= '0';
decrement_lc <= '0';
------------------
-- DO instruction
------------------
if activate_exec_loop = '1' and instr_array = INSTR_DO then
-- first instruction of the do loop instruction?
if do_loop_polling = '0' then
stall_do <= '1';
modify_lc <= '1'; -- store the new loop counter
modify_la <= '1'; -- store the new loop address
push_stack.valid <= '1'; -- push LA and LC on the stack
push_stack.content <= LA_AND_LC;
else -- second clock cycle of the do loop instruction ?
push_stack.valid <= '1'; -- push PC and SR on the stack
push_stack.pc <= loop_start_address;
push_stack.content <= PC_AND_SR;
-- set the PC to the first instruction of the loop
-- the already fetched instruction are flushed from the pipeline
-- this prevents problems, when the loop consists of only one or two instructions
modify_pc <= '1';
-- set the loop flag
modify_sr <= '1';
end if;
end if;
-----------------------------------------------
-- ENDDO instruction / loop end in fetch stage
-----------------------------------------------
if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' or enddo_polling = '1' then
pop_stack.valid <= '1';
if enddo_polling = '0' then
-- only restore the LF from the stack
modified_sr(15) <= register_file.current_ssl(15);
modify_sr <= '1';
stall_do <= '1'; -- stall one clock cycle
else
-- restore loop counter and loop address in second clock cycle
modified_lc <= unsigned(register_file.current_ssl);
modify_lc <= '1';
modified_la <= unsigned(register_file.current_ssh);
modify_la <= '1';
end if;
end if;
-------------------
-- REP instruction
-------------------
if activate_exec_loop = '1' and instr_array = INSTR_REP then
-- only do something when there are more than 1 iterations
-- the first execution is already on the way
if loop_iterations /= 1 then
stall_rep <= '1'; -- stall the fetch and decode stages
modify_lc <= '1'; -- store the loop counter
modified_lc <= loop_iterations - 1;
end if;
end if;
-- keep processing the single instruction
if rep_loop_polling = '1' then
stall_rep <= '1';
-- if the REP instruction cause a stall do not modify the lc!
if memory_stall_t = '0' then
if rf_lc_eq_1 = '0' then
decrement_lc <= '1';
-- when the instruction to repeat caused a memory stall
-- do not continue!
else
-- finish the REP instruction by restoring the LC
stall_rep <= '0';
modify_lc <= '1';
modified_lc <= lc_temp;
end if;
end if;
end if;
end process;
-- process that allows to remember that we are processing a REP/DO instruction
-- even though the REP instruction is not available in the pipeline anymore
-- also store the old loop counter
process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
rep_loop_polling <= '0';
do_loop_polling <= '0';
enddo_polling <= '0';
lc_temp <= (others => '0');
memory_stall_t <= '0';
else
memory_stall_t <= memory_stall;
if activate_exec_loop = '1' and instr_array = INSTR_REP then
-- only do something when there are more than 1 iterations
-- the first execution is already on the way
if loop_iterations /= 1 then
rep_loop_polling <= '1';
lc_temp <= register_file.lc;
end if;
end if;
-- test whether the REP instruction has been executed
if rep_loop_polling = '1' and rf_lc_eq_1 = '1' and memory_stall_t = '0' then
rep_loop_polling <= '0';
end if;
-- do loop execution takes two clock cycles
-- in the first clock cycle we store loop address and loop counter on the stack
-- in the second clock cycle we store programm counter and status register on the stack
if activate_exec_loop = '1' and instr_array = INSTR_DO then
do_loop_polling <= '1';
end if;
-- clear the flag immediately again (only two cycles execution time!)
if do_loop_polling = '1' then
do_loop_polling <= '0';
end if;
-- ENDDO instructions take two clock cycles as well!
if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' then
enddo_polling <= '1';
end if;
if enddo_polling = '1' then
enddo_polling <= '0';
end if;
end if;
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
entity fetch_stage is port(
pc_old : in unsigned(BW_ADDRESS-1 downto 0);
pc_new : out unsigned(BW_ADDRESS-1 downto 0);
modify_pc : in std_logic;
modified_pc : in unsigned(BW_ADDRESS-1 downto 0);
register_file : in register_file_type;
decrement_lc : out std_logic;
perform_enddo : out std_logic
);
end fetch_stage;
architecture rtl of fetch_stage is
begin
pc_calculation: process(pc_old, modify_pc, modified_pc, register_file) is
begin
decrement_lc <= '0';
perform_enddo <= '0';
-- by default increment pc by one
pc_new <= pc_old + 1;
if modify_pc = '1' then
pc_new <= modified_pc;
end if;
-- Loop Flag set?
if register_file.sr(15) = '1' then
if register_file.la = pc_old then
-- Loop not finished?
-- => start from the beginning if necessary
if register_file.lc /= 1 then
-- if the last address was LA and the loop is not finished yet, we have to
-- read now from the beginning of the loop again
pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0));
-- decrement loop counter
decrement_lc <= '1';
else
-- loop done!
-- => tell the loop controller in the exec stage to perform the enddo operation
-- (without flushing of the pipeline!)
perform_enddo <= '1';
end if;
end if;
end if;
end process pc_calculation;
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity memory_management is port (
clk, rst : in std_logic;
stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0);
memory_stall : out std_logic;
data_rom_enable: in std_logic;
pmem_ctrl_in : in mem_ctrl_type_in;
pmem_ctrl_out : out mem_ctrl_type_out;
xmem_ctrl_in : in mem_ctrl_type_in;
xmem_ctrl_out : out mem_ctrl_type_out;
ymem_ctrl_in : in mem_ctrl_type_in;
ymem_ctrl_out : out mem_ctrl_type_out
);
end memory_management;
architecture rtl of memory_management is
component mem_control is
generic(
mem_type : memory_type
);
port(
clk, rst : in std_logic;
rd_addr : in unsigned(BW_ADDRESS-1 downto 0);
rd_en : in std_logic;
data_out : out std_logic_vector(23 downto 0);
data_out_valid : out std_logic;
wr_addr : in unsigned(BW_ADDRESS-1 downto 0);
wr_en : in std_logic;
wr_accomplished : out std_logic;
data_in : in std_logic_vector(23 downto 0)
);
end component mem_control;
signal pmem_data_out : std_logic_vector(23 downto 0);
signal pmem_data_out_valid : std_logic;
signal pmem_rd_addr : unsigned(BW_ADDRESS-1 downto 0);
signal pmem_rd_en : std_logic;
signal xmem_rd_en : std_logic;
signal xmem_data_out : std_logic_vector(23 downto 0);
signal xmem_data_out_valid : std_logic;
signal xmem_rd_polling : std_logic;
signal ymem_rd_en : std_logic;
signal ymem_data_out : std_logic_vector(23 downto 0);
signal ymem_data_out_valid : std_logic;
signal ymem_rd_polling : std_logic;
signal pmem_stall_buffer : std_logic_vector(23 downto 0);
signal pmem_stall_buffer_valid : std_logic;
signal xmem_stall_buffer : std_logic_vector(23 downto 0);
signal ymem_stall_buffer : std_logic_vector(23 downto 0);
signal stall_flags_d : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
begin
-- here it is necessary to store the output of the pmem/xmem/ymem when the pipeline enters a stall
-- when the pipeline wakes up, this temporal result is inserted into the pipeline
stall_buffer: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
pmem_stall_buffer <= (others => '0');
pmem_stall_buffer_valid <= '0';
xmem_stall_buffer <= (others => '0');
ymem_stall_buffer <= (others => '0');
stall_flags_d <= (others => '0');
else
stall_flags_d <= stall_flags;
if stall_flags(ST_FETCH2) = '1' and stall_flags_d(ST_FETCH2) = '0' then
if pmem_data_out_valid = '1' then
pmem_stall_buffer <= pmem_data_out;
pmem_stall_buffer_valid <= '1';
end if;
end if;
if stall_flags(ST_FETCH2) = '0' and stall_flags_d(ST_FETCH2) = '1' then
pmem_stall_buffer_valid <= '0';
end if;
end if;
end if;
end process stall_buffer;
memory_stall <= '1' when ( xmem_rd_en = '1' or (xmem_rd_polling = '1' and xmem_data_out_valid = '0') ) or
( ymem_rd_en = '1' or (ymem_rd_polling = '1' and ymem_data_out_valid = '0') ) else
'0';
-------------------------------
-- PMEM CONTROLLER
-------------------------------
inst_pmem_ctrl : mem_control
generic map(
mem_type => P_MEM
)
port map(
clk => clk,
rst => rst,
rd_addr => pmem_ctrl_in.rd_addr,
rd_en => pmem_ctrl_in.rd_en,
data_out => pmem_data_out,
data_out_valid => pmem_data_out_valid,
wr_addr => pmem_ctrl_in.wr_addr,
wr_en => pmem_ctrl_in.wr_en,
data_in => pmem_ctrl_in.data_in
);
-- In case we wake up from a stall use the buffered value
pmem_ctrl_out.data_out <= pmem_stall_buffer when stall_flags(ST_FETCH2) = '0' and
stall_flags_d(ST_FETCH2) = '1' and
pmem_stall_buffer_valid = '1' else
pmem_data_out;
pmem_ctrl_out.data_out_valid <= pmem_stall_buffer_valid when stall_flags(ST_FETCH2) = '0' and
stall_flags_d(ST_FETCH2) = '1' else
'0' when stall_flags(ST_FETCH2) = '1' else
pmem_data_out_valid;
-------------------------------
-- XMEM CONTROLLER
-------------------------------
inst_xmem_ctrl : mem_control
generic map(
mem_type => X_MEM
)
port map(
clk => clk,
rst => rst,
rd_addr => xmem_ctrl_in.rd_addr,
rd_en => xmem_rd_en,
data_out => xmem_data_out,
data_out_valid => xmem_data_out_valid,
wr_addr => xmem_ctrl_in.wr_addr,
wr_en => xmem_ctrl_in.wr_en,
data_in => xmem_ctrl_in.data_in
);
xmem_rd_en <= '1' when xmem_rd_polling = '0' and xmem_ctrl_in.rd_en = '1' else '0';
xmem_ctrl_out.data_out <= xmem_data_out;
xmem_ctrl_out.data_out_valid <= xmem_data_out_valid;
-------------------------------
-- YMEM CONTROLLER
-------------------------------
inst_ymem_ctrl : mem_control
generic map(
mem_type => Y_MEM
)
port map(
clk => clk,
rst => rst,
rd_addr => ymem_ctrl_in.rd_addr,
rd_en => ymem_rd_en,
data_out => ymem_data_out,
data_out_valid => ymem_data_out_valid,
wr_addr => ymem_ctrl_in.wr_addr,
wr_en => ymem_ctrl_in.wr_en,
data_in => ymem_ctrl_in.data_in
);
ymem_rd_en <= '1' when ymem_rd_polling = '0' and ymem_ctrl_in.rd_en = '1' else '0';
ymem_ctrl_out.data_out <= ymem_data_out;
ymem_ctrl_out.data_out_valid <= ymem_data_out_valid;
mem_stall_control: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
xmem_rd_polling <= '0';
ymem_rd_polling <= '0';
else
if xmem_rd_en = '1' then
xmem_rd_polling <= '1';
end if;
if xmem_data_out_valid = '1' then
xmem_rd_polling <= '0';
end if;
if ymem_rd_en = '1' then
ymem_rd_polling <= '1';
end if;
if ymem_data_out_valid = '1' then
ymem_rd_polling <= '0';
end if;
end if;
end if;
end process;
end architecture;

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package parameter_pkg is
constant BW_ADDRESS : natural := 16;
constant PIPELINE_DEPTH : natural := 5;
constant NUM_ACT_SIGNALS : natural := 26;
end package;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity pipeline is port (
clk, rst : in std_logic;
register_file_out : out register_file_type
);
end pipeline;
-- TODOs:
-- External memory accesses
-- ROM tables
-- Reading from SSH flag has to modify stack pointer
-- Memory access (x,y,p) and talling accordingly
-- Address Generator: ring buffers are not yet supported
-- List of BUGS:
-- - Reading from address one clock cycle after writing to the same address might result in corrupted data!!
-- - SBC instruction has errorneous carry flag calculation
-- List of probable issues:
-- - Reading from XMEM/YMEM with stalls probably results in corrupted data
-- - ENDDO instruction probably has to flush the pipeline afterwards
-- - Writing to memory occurs twice, when stalls occur
-- Things to optimize:
-- - RTS/RTI could be executed in the ADGEN Stage already
-- - DO loops always flush the pipeline. This is necessary in case we have a very short loop.
-- The single instruction of the loop then has passed the fetch stage already without the branch
architecture rtl of pipeline is
signal pipeline_regs : pipeline_type;
signal stall_flags : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
component fetch_stage is port(
pc_old : in unsigned(BW_ADDRESS-1 downto 0);
pc_new : out unsigned(BW_ADDRESS-1 downto 0);
modify_pc : in std_logic;
modified_pc : in unsigned(BW_ADDRESS-1 downto 0);
register_file : in register_file_type;
decrement_lc : out std_logic;
perform_enddo : out std_logic
);
end component fetch_stage;
signal pc_old, pc_new : unsigned(BW_ADDRESS-1 downto 0);
signal fetch_modify_pc : std_logic;
signal fetch_modified_pc : unsigned(BW_ADDRESS-1 downto 0);
signal fetch_perform_enddo: std_logic;
signal fetch_decrement_lc: std_logic;
component decode_stage is port(
activate_dec : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
dble_word_instr : out std_logic;
instr_array : out instructions_type;
act_array : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
reg_wr_addr : out std_logic_vector(5 downto 0);
reg_rd_addr : out std_logic_vector(5 downto 0);
x_bus_rd_addr : out std_logic_vector(1 downto 0);
x_bus_wr_addr : out std_logic_vector(1 downto 0);
y_bus_rd_addr : out std_logic_vector(1 downto 0);
y_bus_wr_addr : out std_logic_vector(1 downto 0);
l_bus_addr : out std_logic_vector(2 downto 0);
adgen_mode_a : out adgen_mode_type;
adgen_mode_b : out adgen_mode_type;
alu_ctrl : out alu_ctrl_type
);
end component decode_stage;
signal dec_activate : std_logic;
signal dec_instr_word : std_logic_vector(23 downto 0);
signal dec_dble_word_instr : std_logic;
signal dec_instr_array : instructions_type;
signal dec_act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
signal dec_reg_wr_addr : std_logic_vector(5 downto 0);
signal dec_reg_rd_addr : std_logic_vector(5 downto 0);
signal dec_x_bus_wr_addr : std_logic_vector(1 downto 0);
signal dec_x_bus_rd_addr : std_logic_vector(1 downto 0);
signal dec_y_bus_wr_addr : std_logic_vector(1 downto 0);
signal dec_y_bus_rd_addr : std_logic_vector(1 downto 0);
signal dec_l_bus_addr : std_logic_vector(2 downto 0);
signal dec_adgen_mode_a : adgen_mode_type;
signal dec_adgen_mode_b : adgen_mode_type;
signal dec_alu_ctrl : alu_ctrl_type;
component adgen_stage is port(
activate_adgen : in std_logic;
activate_x_mem : in std_logic;
activate_y_mem : in std_logic;
activate_l_mem : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
optional_ea_word : in std_logic_vector(23 downto 0);
register_file : in register_file_type;
adgen_mode_a : in adgen_mode_type;
adgen_mode_b : in adgen_mode_type;
address_out_x : out unsigned(BW_ADDRESS-1 downto 0);
address_out_y : out unsigned(BW_ADDRESS-1 downto 0);
wr_R_port_A_valid : out std_logic;
wr_R_port_A : out addr_wr_port_type;
wr_R_port_B_valid : out std_logic;
wr_R_port_B : out addr_wr_port_type
);
end component adgen_stage;
signal adgen_activate : std_logic;
signal adgen_activate_x_mem : std_logic;
signal adgen_activate_y_mem : std_logic;
signal adgen_activate_l_mem : std_logic;
signal adgen_instr_word : std_logic_vector(23 downto 0);
signal adgen_instr_array : instructions_type;
signal adgen_optional_ea_word : std_logic_vector(23 downto 0);
signal adgen_register_file : register_file_type;
signal adgen_mode_a : adgen_mode_type;
signal adgen_mode_b : adgen_mode_type;
signal adgen_address_out_x : unsigned(BW_ADDRESS-1 downto 0);
signal adgen_address_out_y : unsigned(BW_ADDRESS-1 downto 0);
signal adgen_wr_R_port_A_valid : std_logic;
signal adgen_wr_R_port_A : addr_wr_port_type;
signal adgen_wr_R_port_B_valid : std_logic;
signal adgen_wr_R_port_B : addr_wr_port_type;
component exec_stage_bit_modify is port(
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
src_operand : in std_logic_vector(23 downto 0);
register_file : in register_file_type;
dst_operand : out std_logic_vector(23 downto 0);
bit_cond_met : out std_logic;
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end component exec_stage_bit_modify;
signal exec_bit_modify_instr_word : std_logic_vector(23 downto 0);
signal exec_bit_modify_instr_array : instructions_type;
signal exec_bit_modify_src_operand : std_logic_vector(23 downto 0);
signal exec_bit_modify_dst_operand : std_logic_vector(23 downto 0);
signal exec_bit_modify_bit_cond_met : std_logic;
signal exec_bit_modify_modify_sr : std_logic;
signal exec_bit_modify_modified_sr : std_logic_vector(15 downto 0);
component exec_stage_branch is port(
activate_exec_bra : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
register_file : in register_file_type;
jump_address : in unsigned(BW_ADDRESS-1 downto 0);
bit_cond_met : in std_logic;
cc_flag_set : in std_logic;
push_stack : out push_stack_type;
pop_stack : out pop_stack_type;
modify_pc : out std_logic;
modified_pc : out unsigned(BW_ADDRESS-1 downto 0);
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end component exec_stage_branch;
signal exec_bra_activate : std_logic;
signal exec_bra_instr_word : std_logic_vector(23 downto 0);
signal exec_bra_instr_array : instructions_type;
signal exec_bra_jump_address : unsigned(BW_ADDRESS-1 downto 0);
signal exec_bra_bit_cond_met : std_logic;
signal exec_bra_push_stack : push_stack_type;
signal exec_bra_pop_stack : pop_stack_type;
signal exec_bra_modify_pc : std_logic;
signal exec_bra_modified_pc : unsigned(BW_ADDRESS-1 downto 0);
signal exec_bra_modify_sr : std_logic;
signal exec_bra_modified_sr : std_logic_vector(15 downto 0);
component exec_stage_cr_mod is port(
activate_exec_cr_mod : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
register_file : in register_file_type;
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0);
modify_omr : out std_logic;
modified_omr : out std_logic_vector(7 downto 0)
);
end component exec_stage_cr_mod;
signal exec_cr_mod_activate : std_logic;
signal exec_cr_mod_instr_word : std_logic_vector(23 downto 0);
signal exec_cr_mod_instr_array : instructions_type;
signal exec_cr_mod_modify_sr : std_logic;
signal exec_cr_mod_modified_sr : std_logic_vector(15 downto 0);
signal exec_cr_mod_modify_omr : std_logic;
signal exec_cr_mod_modified_omr : std_logic_vector(7 downto 0);
component exec_stage_loop is port(
clk, rst : in std_logic;
activate_exec_loop : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
loop_iterations : in unsigned(15 downto 0);
loop_address : in unsigned(BW_ADDRESS-1 downto 0);
loop_start_address: in unsigned(BW_ADDRESS-1 downto 0);
register_file : in register_file_type;
fetch_perform_enddo: in std_logic;
memory_stall : in std_logic;
push_stack : out push_stack_type;
pop_stack : out pop_stack_type;
stall_rep : out std_logic;
stall_do : out std_logic;
decrement_lc : out std_logic;
modify_lc : out std_logic;
modified_lc : out unsigned(15 downto 0);
modify_la : out std_logic;
modified_la : out unsigned(15 downto 0);
modify_pc : out std_logic;
modified_pc : out unsigned(BW_ADDRESS-1 downto 0);
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end component exec_stage_loop;
signal exec_loop_activate : std_logic;
signal exec_loop_instr_word : std_logic_vector(23 downto 0);
signal exec_loop_instr_array : instructions_type;
signal exec_loop_iterations : unsigned(15 downto 0);
signal exec_loop_address : unsigned(BW_ADDRESS-1 downto 0);
signal exec_loop_start_address : unsigned(BW_ADDRESS-1 downto 0);
signal exec_loop_register_file : register_file_type;
signal exec_loop_push_stack : push_stack_type;
signal exec_loop_pop_stack : pop_stack_type;
signal exec_loop_stall_rep : std_logic;
signal exec_loop_stall_do : std_logic;
signal exec_loop_decrement_lc : std_logic;
signal exec_loop_modify_lc : std_logic;
signal exec_loop_modified_lc : unsigned(15 downto 0);
signal exec_loop_modify_la : std_logic;
signal exec_loop_modified_la : unsigned(BW_ADDRESS-1 downto 0);
signal exec_loop_modify_pc : std_logic;
signal exec_loop_modified_pc : unsigned(BW_ADDRESS-1 downto 0);
signal exec_loop_modify_sr : std_logic;
signal exec_loop_modified_sr : std_logic_vector(BW_ADDRESS-1 downto 0);
component exec_stage_alu is port(
alu_activate : in std_logic;
instr_word : in std_logic_vector(23 downto 0);
alu_ctrl : in alu_ctrl_type;
register_file : in register_file_type;
addr_r_in : in unsigned(BW_ADDRESS-1 downto 0);
addr_r_out : out unsigned(BW_ADDRESS-1 downto 0);
modify_accu : out std_logic;
dst_accu : out std_logic;
modified_accu : out signed(55 downto 0);
modify_sr : out std_logic;
modified_sr : out std_logic_vector(15 downto 0)
);
end component exec_stage_alu;
signal exec_alu_activate : std_logic;
signal exec_alu_instr_word : std_logic_vector(23 downto 0);
signal exec_alu_ctrl : alu_ctrl_type;
signal exec_alu_addr_r_in : unsigned(BW_ADDRESS-1 downto 0);
signal exec_alu_addr_r_out : unsigned(BW_ADDRESS-1 downto 0);
signal exec_alu_modify_accu : std_logic;
signal exec_alu_dst_accu : std_logic;
signal exec_alu_modified_accu : signed(55 downto 0);
signal exec_alu_modify_sr : std_logic;
signal exec_alu_modified_sr : std_logic_vector(15 downto 0);
signal exec_imm_8bit : std_logic_vector(23 downto 0);
signal exec_imm_12bit : std_logic_vector(23 downto 0);
signal exec_src_operand : std_logic_vector(23 downto 0);
signal exec_dst_operand : std_logic_vector(23 downto 0);
component exec_stage_cc_flag_calc is port(
instr_word : in std_logic_vector(23 downto 0);
instr_array : in instructions_type;
register_file : in register_file_type;
cc_flag_set : out std_logic
);
end component exec_stage_cc_flag_calc;
signal exec_cc_flag_calc_instr_word : std_logic_vector(23 downto 0);
signal exec_cc_flag_calc_instr_array : instructions_type;
signal exec_cc_flag_set : std_logic;
component reg_file is port(
clk, rst : in std_logic;
register_file : out register_file_type;
wr_R_port_A_valid : in std_logic;
wr_R_port_A : in addr_wr_port_type;
wr_R_port_B_valid : in std_logic;
wr_R_port_B : in addr_wr_port_type;
alu_wr_valid : in std_logic;
alu_wr_addr : in std_logic;
alu_wr_data : in signed(55 downto 0);
reg_wr_addr : in std_logic_vector(5 downto 0);
reg_wr_addr_valid : in std_logic;
reg_wr_data : in std_Logic_vector(23 downto 0);
reg_rd_addr : in std_logic_vector(5 downto 0);
reg_rd_data : out std_Logic_vector(23 downto 0);
X_bus_rd_addr : in std_logic_vector(1 downto 0);
X_bus_data_out : out std_logic_vector(23 downto 0);
X_bus_wr_addr : in std_logic_vector(1 downto 0);
X_bus_wr_valid : in std_logic;
X_bus_data_in : in std_logic_vector(23 downto 0);
Y_bus_rd_addr : in std_logic_vector(1 downto 0);
Y_bus_data_out : out std_logic_vector(23 downto 0);
Y_bus_wr_addr : in std_logic_vector(1 downto 0);
Y_bus_wr_valid : in std_logic;
Y_bus_data_in : in std_logic_vector(23 downto 0);
L_bus_rd_addr : in std_logic_vector(2 downto 0);
L_bus_rd_valid : in std_logic;
L_bus_wr_addr : in std_logic_vector(2 downto 0);
L_bus_wr_valid : in std_logic;
push_stack : in push_stack_type;
pop_stack : in pop_stack_type;
set_sr : in std_logic;
new_sr : in std_logic_vector(15 downto 0);
set_omr : in std_logic;
new_omr : in std_logic_vector(7 downto 0);
set_lc : in std_logic;
new_lc : in unsigned(15 downto 0);
dec_lc : in std_logic;
set_la : in std_logic;
new_la : in unsigned(BW_ADDRESS-1 downto 0)
);
end component reg_file;
signal register_file : register_file_type;
signal rf_wr_R_port_A_valid : std_logic;
signal rf_wr_R_port_B_valid : std_logic;
signal rf_reg_wr_addr : std_logic_vector(5 downto 0);
signal rf_reg_wr_addr_valid : std_logic;
signal rf_reg_wr_data : std_logic_vector(23 downto 0);
signal rf_reg_rd_addr : std_logic_vector(5 downto 0);
signal rf_reg_rd_data : std_logic_vector(23 downto 0);
signal rf_X_bus_rd_addr : std_logic_vector(1 downto 0);
signal rf_X_bus_data_out : std_logic_vector(23 downto 0);
signal rf_X_bus_wr_addr : std_logic_vector(1 downto 0);
signal rf_X_bus_wr_valid : std_logic;
signal rf_X_bus_data_in : std_logic_vector(23 downto 0);
signal rf_Y_bus_rd_addr : std_logic_vector(1 downto 0);
signal rf_Y_bus_data_out : std_logic_vector(23 downto 0);
signal rf_Y_bus_wr_addr : std_logic_vector(1 downto 0);
signal rf_Y_bus_wr_valid : std_logic;
signal rf_Y_bus_data_in : std_logic_vector(23 downto 0);
signal rf_L_bus_rd_addr : std_logic_vector(2 downto 0);
signal rf_L_bus_rd_valid : std_logic;
signal rf_L_bus_wr_addr : std_logic_vector(2 downto 0);
signal rf_L_bus_wr_valid : std_logic;
signal push_stack : push_stack_type;
signal pop_stack : pop_stack_type;
signal rf_set_sr : std_logic;
signal rf_new_sr : std_logic_vector(15 downto 0);
signal rf_set_omr : std_logic;
signal rf_new_omr : std_logic_vector(7 downto 0);
signal rf_dec_lc : std_logic;
signal rf_set_lc : std_logic;
signal rf_new_lc : unsigned(15 downto 0);
signal rf_set_la : std_logic;
signal rf_new_la : unsigned(BW_ADDRESS-1 downto 0);
signal rf_alu_wr_valid : std_logic;
component memory_management is port (
clk, rst : in std_logic;
stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0);
memory_stall : out std_logic;
data_rom_enable: in std_logic;
pmem_ctrl_in : in mem_ctrl_type_in;
pmem_ctrl_out : out mem_ctrl_type_out;
xmem_ctrl_in : in mem_ctrl_type_in;
xmem_ctrl_out : out mem_ctrl_type_out;
ymem_ctrl_in : in mem_ctrl_type_in;
ymem_ctrl_out : out mem_ctrl_type_out
);
end component memory_management;
signal memory_stall : std_logic;
signal pmem_ctrl_in : mem_ctrl_type_in;
signal pmem_ctrl_out : mem_ctrl_type_out;
signal xmem_ctrl_in : mem_ctrl_type_in;
signal xmem_ctrl_out : mem_ctrl_type_out;
signal ymem_ctrl_in : mem_ctrl_type_in;
signal ymem_ctrl_out : mem_ctrl_type_out;
signal pmem_data_out : std_logic_vector(23 downto 0);
signal pmem_data_out_valid : std_logic;
signal xmem_data_out : std_logic_vector(23 downto 0);
signal xmem_data_out_valid : std_logic;
signal ymem_data_out : std_logic_vector(23 downto 0);
signal ymem_data_out_valid : std_logic;
begin
register_file_out <= register_file;
-- merge all stall sources
stall_flags(ST_FETCH) <= '1' when exec_loop_stall_rep = '1' or
memory_stall = '1' or
exec_loop_stall_do = '1' else '0';
stall_flags(ST_FETCH2) <= '1' when exec_loop_stall_rep = '1' or
memory_stall = '1' or
exec_loop_stall_do = '1' else '0';
stall_flags(ST_DECODE) <= '1' when exec_loop_stall_rep = '1' or
memory_stall = '1' or
exec_loop_stall_do = '1' else '0';
stall_flags(ST_ADGEN) <= exec_loop_stall_do;
-- stall_flags(ST_ADGEN) <= '1' when memory_stall = '1' or
-- exec_loop_stall_do = '1' else '0';
-- stall_flags(ST_EXEC) <= '0';
stall_flags(ST_EXEC) <= exec_loop_stall_do;
-- stall_flags(ST_EXEC) <= '1' when memory_stall = '1' or
-- exec_loop_stall_do = '1' else '0';
shift_pipeline: process(clk, rst) is
procedure flush_pipeline_stage(stage: natural) is
begin
pipeline_regs(stage).pc <= (others => '1');
pipeline_regs(stage).instr_word <= (others => '0');
pipeline_regs(stage).act_array <= (others => '0');
pipeline_regs(stage).instr_array <= INSTR_NOP;
pipeline_regs(stage).dble_word_instr <= '0';
pipeline_regs(stage).dec_activate <= '0';
pipeline_regs(stage).adgen_mode_a <= NOP;
pipeline_regs(stage).adgen_mode_b <= NOP;
pipeline_regs(stage).reg_wr_addr <= (others => '0');
pipeline_regs(stage).reg_rd_addr <= (others => '0');
pipeline_regs(stage).x_bus_rd_addr <= (others => '0');
pipeline_regs(stage).x_bus_wr_addr <= (others => '0');
pipeline_regs(stage).y_bus_rd_addr <= (others => '0');
pipeline_regs(stage).y_bus_wr_addr <= (others => '0');
pipeline_regs(stage).l_bus_addr <= (others => '0');
pipeline_regs(stage).adgen_address_x <= (others => '0');
pipeline_regs(stage).adgen_address_y <= (others => '0');
pipeline_regs(stage).RAM_out_x <= (others => '0');
pipeline_regs(stage).RAM_out_y <= (others => '0');
pipeline_regs(stage).alu_ctrl.store_result <= '0';
end procedure flush_pipeline_stage;
begin
if rising_edge(clk) then
if rst = '1' then
for i in 0 to PIPELINE_DEPTH-1 loop
flush_pipeline_stage(i);
end loop;
else
-- shift the pipeline registers when no stall applies
for i in 1 to PIPELINE_DEPTH-1 loop
if stall_flags(i) = '0' then
-- do not copy the pipeline registers from a stalled pipeline stage
-- for REP we do not flush
-- if stall_flags(i-1) = '1' then
if (stall_flags(i-1) = '1' and exec_loop_stall_rep = '0') or
(i = ST_ADGEN and memory_stall = '1' and exec_loop_stall_rep = '1') then
flush_pipeline_stage(i);
else
pipeline_regs(i) <= pipeline_regs(i-1);
end if;
end if;
end loop;
-- FETCH Pipeline Registers
if stall_flags(ST_FETCH) = '0' then
pipeline_regs(ST_FETCH).pc <= pc_new;
pipeline_regs(ST_FETCH).dec_activate <= '1';
end if;
-- FETCH2 Pipeline Registers
if stall_flags(ST_FETCH2) = '0' then
-- Normal pipeline operation?
-- Buffering of RAM output when stalling is performed in the memory management
if pmem_data_out_valid = '1' then
pipeline_regs(ST_FETCH2).instr_word <= pmem_data_out;
end if;
end if;
-- DECODE Pipeline registers
if stall_flags(ST_DECODE) = '0' then
pipeline_regs(ST_DECODE).act_array <= dec_act_array;
pipeline_regs(ST_DECODE).instr_array <= dec_instr_array;
pipeline_regs(ST_DECODE).dble_word_instr <= dec_dble_word_instr;
pipeline_regs(ST_DECODE).reg_wr_addr <= dec_reg_wr_addr;
pipeline_regs(ST_DECODE).reg_rd_addr <= dec_reg_rd_addr;
pipeline_regs(ST_DECODE).x_bus_wr_addr <= dec_x_bus_wr_addr;
pipeline_regs(ST_DECODE).x_bus_rd_addr <= dec_x_bus_rd_addr;
pipeline_regs(ST_DECODE).y_bus_wr_addr <= dec_y_bus_wr_addr;
pipeline_regs(ST_DECODE).y_bus_rd_addr <= dec_y_bus_rd_addr;
pipeline_regs(ST_DECODE).l_bus_addr <= dec_l_bus_addr;
pipeline_regs(ST_DECODE).adgen_mode_a <= dec_adgen_mode_a;
pipeline_regs(ST_DECODE).adgen_mode_b <= dec_adgen_mode_b;
pipeline_regs(ST_DECODE).alu_ctrl <= dec_alu_ctrl;
end if;
-- ADGEN Pipeline registers
if stall_flags(ST_ADGEN) = '0' then
pipeline_regs(ST_ADGEN).adgen_address_x <= adgen_address_out_x;
pipeline_regs(ST_ADGEN).adgen_address_y <= adgen_address_out_y;
end if;
if xmem_data_out_valid = '1' then
pipeline_regs(ST_ADGEN).RAM_out_x <= xmem_data_out;
end if;
if ymem_data_out_valid = '1' then
pipeline_regs(ST_ADGEN).RAM_out_y <= ymem_data_out;
end if;
-- EXEC Pipeline stuff
if exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' then
-- clear the following pipeline stages,
-- since we modified the pc.
-- Do not flush ST_FETCH - it will hold the correct pc.
flush_pipeline_stage(ST_FETCH2);
flush_pipeline_stage(ST_DECODE);
flush_pipeline_stage(ST_ADGEN);
end if;
end if;
end if;
end process shift_pipeline;
-------------------------------
-- FETCH STAGE INSTANTIATION
-------------------------------
inst_fetch_stage: fetch_stage port map(
pc_old => pc_old,
pc_new => pc_new,
modify_pc => fetch_modify_pc,
modified_pc => fetch_modified_pc,
register_file => register_file,
decrement_lc => fetch_decrement_lc,
perform_enddo => fetch_perform_enddo
);
pc_old <= pipeline_regs(ST_FETCH).pc;
fetch_modify_pc <= '1' when exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' else '0';
fetch_modified_pc <= exec_bra_modified_pc when exec_bra_modify_pc = '1' else
exec_loop_modified_pc;
-------------------------------
-- DECODE STAGE INSTANTIATION
-------------------------------
inst_decode_stage : decode_stage port map(
activate_dec => dec_activate,
instr_word => dec_instr_word,
dble_word_instr => dec_dble_word_instr,
instr_array => dec_instr_array,
act_array => dec_act_array,
reg_wr_addr => dec_reg_wr_addr,
reg_rd_addr => dec_reg_rd_addr,
x_bus_wr_addr => dec_x_bus_wr_addr,
x_bus_rd_addr => dec_x_bus_rd_addr,
y_bus_wr_addr => dec_y_bus_wr_addr,
y_bus_rd_addr => dec_y_bus_rd_addr,
l_bus_addr => dec_l_bus_addr,
adgen_mode_a => dec_adgen_mode_a,
adgen_mode_b => dec_adgen_mode_b,
alu_ctrl => dec_alu_ctrl
);
dec_instr_word <= pipeline_regs(ST_DECODE-1).instr_word;
-- do not decode, when we have no valid instruction. This can happen when
-- 1) the pipeline just started its operation
-- 2) the pipeline was flushed due to a jump
-- 3) we are processing a instruction that consists of two words
dec_activate <= '1' when pipeline_regs(ST_DECODE-1).dec_activate = '1' and pipeline_regs(ST_DECODE).dble_word_instr = '0' else '0';
-------------------------------
-- AGU STAGE INSTANTIATION
-------------------------------
inst_adgen_stage: adgen_stage port map(
activate_adgen => adgen_activate,
activate_x_mem => adgen_activate_x_mem,
activate_y_mem => adgen_activate_y_mem,
activate_l_mem => adgen_activate_l_mem,
instr_word => adgen_instr_word,
instr_array => adgen_instr_array,
optional_ea_word => adgen_optional_ea_word,
register_file => register_file,
adgen_mode_a => adgen_mode_a,
adgen_mode_b => adgen_mode_b,
address_out_x => adgen_address_out_x,
address_out_y => adgen_address_out_y,
wr_R_port_A_valid => adgen_wr_R_port_A_valid,
wr_R_port_A => adgen_wr_R_port_A,
wr_R_port_B_valid => adgen_wr_R_port_B_valid,
wr_R_port_B => adgen_wr_R_port_B
);
adgen_activate <= pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN);
adgen_activate_x_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' or
pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_WR) = '1' else '0';
adgen_activate_y_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' or
pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_WR) = '1' else '0';
adgen_activate_l_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_RD) = '1' or
pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_WR) = '1' else '0';
adgen_instr_word <= pipeline_regs(ST_ADGEN-1).instr_word;
adgen_instr_array <= pipeline_regs(ST_ADGEN-1).instr_array;
adgen_optional_ea_word <= pipeline_regs(ST_ADGEN-2).instr_word;
adgen_mode_a <= pipeline_regs(ST_ADGEN-1).adgen_mode_a;
adgen_mode_b <= pipeline_regs(ST_ADGEN-1).adgen_mode_b;
-------------------------------
-- EXECUTE STAGE INSTANTIATIONS
-------------------------------
inst_exec_stage_alu: exec_stage_alu port map(
alu_activate => exec_alu_activate,
instr_word => exec_alu_instr_word,
alu_ctrl => exec_alu_ctrl,
register_file => register_file,
addr_r_in => exec_alu_addr_r_in,
addr_r_out => exec_alu_addr_r_out,
modify_accu => exec_alu_modify_accu,
dst_accu => exec_alu_dst_accu,
modified_accu => exec_alu_modified_accu,
modify_sr => exec_alu_modify_sr,
modified_sr => exec_alu_modified_sr
);
exec_alu_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_ALU);
exec_alu_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
exec_alu_ctrl <= pipeline_regs(ST_EXEC-1).alu_ctrl;
exec_alu_addr_r_in <= unsigned(rf_reg_rd_data(BW_ADDRESS-1 downto 0));
inst_exec_stage_bit_modify: exec_stage_bit_modify port map(
instr_word => exec_bit_modify_instr_word,
instr_array => exec_bit_modify_instr_array,
src_operand => exec_bit_modify_src_operand,
register_file => register_file,
dst_operand => exec_bit_modify_dst_operand,
bit_cond_met => exec_bit_modify_bit_cond_met,
modify_sr => exec_bit_modify_modify_sr,
modified_sr => exec_bit_modify_modified_sr
);
exec_bit_modify_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
exec_bit_modify_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
exec_bit_modify_src_operand <= exec_src_operand;
-- Writing to the register file using the 6 bit addressing scheme
-- sources are:
-- 1) X-RAM output
-- 2) Y-RAM output
-- 3) register file itself
-- 4) short immediate value (8 bit stored in instruction word)
-- 5) long immediate value (from optional effective address extension)
-- 5) address generated by the address generation unit (LUA instr)
exec_src_operand <= pipeline_regs(ST_EXEC-1).RAM_out_x when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else
pipeline_regs(ST_EXEC-1).RAM_out_y when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else
rf_reg_rd_data when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else
exec_imm_8bit when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_8BIT) = '1' else
exec_imm_12bit when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_12BIT) = '1' else
pipeline_regs(ST_EXEC-2).instr_word when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_LONG) = '1' else
std_logic_vector(resize(pipeline_regs(ST_EXEC-1).adgen_address_x, 24)); -- for LUA instr.
-- Destination for the register file using the 6 bit addressing scheme.
-- Either read the bit modified version of the read value
-- or use the modified Rn in case of a NORM instruction
-- exec_dst_operand <= exec_bit_modify_dst_operand;
exec_dst_operand <= exec_bit_modify_dst_operand when pipeline_regs(ST_EXEC-1).act_array(ACT_NORM) = '0' else
std_logic_vector(resize(exec_alu_addr_r_out,24));
-- Unit to check whether cc (in Jcc, JScc, Tcc, ...) is true
inst_exec_stage_cc_flag_calc: exec_stage_cc_flag_calc port map(
instr_word => exec_cc_flag_calc_instr_word,
instr_array => exec_cc_flag_calc_instr_array,
register_file => register_file,
cc_flag_set => exec_cc_flag_set
);
exec_cc_flag_calc_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
exec_cc_flag_calc_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
inst_exec_stage_branch : exec_stage_branch port map(
activate_exec_bra => exec_bra_activate,
instr_word => exec_bra_instr_word,
instr_array => exec_bra_instr_array,
register_file => register_file,
jump_address => exec_bra_jump_address,
bit_cond_met => exec_bra_bit_cond_met,
cc_flag_set => exec_cc_flag_set,
push_stack => exec_bra_push_stack,
pop_stack => exec_bra_pop_stack,
modify_pc => exec_bra_modify_pc,
modified_pc => exec_bra_modified_pc,
modify_sr => exec_bra_modify_sr,
modified_sr => exec_bra_modified_sr
);
exec_bra_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_BRA);
exec_bra_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
exec_bra_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
exec_bra_jump_address <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else
unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0));
exec_bra_bit_cond_met <= exec_bit_modify_bit_cond_met;
inst_exec_stage_cr_mod : exec_stage_cr_mod port map(
activate_exec_cr_mod => exec_cr_mod_activate,
instr_word => exec_cr_mod_instr_word,
instr_array => exec_cr_mod_instr_array,
register_file => register_file,
modify_sr => exec_cr_mod_modify_sr,
modified_sr => exec_cr_mod_modified_sr,
modify_omr => exec_cr_mod_modify_omr,
modified_omr => exec_cr_mod_modified_omr
);
exec_cr_mod_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_CR_MOD);
exec_cr_mod_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
exec_cr_mod_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
inst_exec_stage_loop: exec_stage_loop port map(
clk => clk,
rst => rst,
activate_exec_loop => exec_loop_activate,
instr_word => exec_loop_instr_word,
instr_array => exec_loop_instr_array,
loop_iterations => exec_loop_iterations,
loop_address => exec_loop_address,
loop_start_address => exec_loop_start_address,
register_file => register_file,
fetch_perform_enddo=> fetch_perform_enddo,
memory_stall => memory_stall,
push_stack => exec_loop_push_stack,
pop_stack => exec_loop_pop_stack,
stall_rep => exec_loop_stall_rep,
stall_do => exec_loop_stall_do,
modify_lc => exec_loop_modify_lc,
decrement_lc => exec_loop_decrement_lc,
modified_lc => exec_loop_modified_lc,
modify_la => exec_loop_modify_la,
modified_la => exec_loop_modified_la,
modify_pc => exec_loop_modify_pc,
modified_pc => exec_loop_modified_pc,
modify_sr => exec_loop_modify_sr,
modified_sr => exec_loop_modified_sr
);
exec_loop_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_LOOP);
exec_loop_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
exec_loop_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
exec_loop_iterations <= unsigned(exec_src_operand(15 downto 0));
-- from which source is our operand?
-- - XMEM
-- - YMEM
-- - Any register
-- - Immediate (from instruction word)
-- exec_src_operand <= unsigned(pipeline_regs(ST_EXEC-1).RAM_out_x(BW_ADDRESS-1 downto 0)) when
-- pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else
-- unsigned(pipeline_regs(ST_EXEC-1).RAM_out_y(BW_ADDRESS-1 downto 0)) when
-- pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else
-- unsigned(rf_reg_rd_data(15 downto 0)) when
-- pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else
-- "00000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(15 downto 8));
-- Loop address is given by the second instruction word of the DO instruction.
-- This address is available one previous stage within the pipeline
exec_loop_address <= unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0)) - 1;
-- one more stage before we find the programm counter of the first instruction to be executed in a DO loop
exec_loop_start_address <= unsigned(pipeline_regs(ST_EXEC-3).pc);
-- For the 8 bit immediate is can be either a fractional (registers x0,x1,y0,y1,a,b) or an unsigned (the rest)
exec_imm_8bit(23 downto 16) <= (others => '0') when rf_reg_wr_addr(5 downto 2) /= "0001" and rf_reg_wr_addr(5 downto 1) /= "00111" else
pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
exec_imm_8bit(15 downto 8) <= (others => '0');
exec_imm_8bit( 7 downto 0) <= (others => '0') when rf_reg_wr_addr(5 downto 2) = "0001" or rf_reg_wr_addr(5 downto 1) = "00111" else
pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
-- The 12 bit immediate stems from the instruction word
exec_imm_12bit(23 downto 12) <= (others => '0');
exec_imm_12bit(11 downto 0) <= pipeline_regs(ST_EXEC-1).instr_word(3 downto 0) & pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
-----------------
-- REGISTER FILE
-----------------
inst_reg_file: reg_file port map(
clk => clk,
rst => rst,
register_file => register_file,
wr_R_port_A_valid => rf_wr_R_port_A_valid,
wr_R_port_A => adgen_wr_R_port_A,
wr_R_port_B_valid => rf_wr_R_port_B_valid,
wr_R_port_B => adgen_wr_R_port_B,
reg_wr_addr => rf_reg_wr_addr,
reg_wr_addr_valid => rf_reg_wr_addr_valid,
reg_wr_data => rf_reg_wr_data,
reg_rd_addr => rf_reg_rd_addr,
reg_rd_data => rf_reg_rd_data,
alu_wr_valid => rf_alu_wr_valid,
alu_wr_addr => exec_alu_dst_accu,
alu_wr_data => exec_alu_modified_accu,
X_bus_rd_addr => rf_X_bus_rd_addr,
X_bus_data_out => rf_X_bus_data_out,
X_bus_wr_addr => rf_X_bus_wr_addr ,
X_bus_wr_valid => rf_X_bus_wr_valid,
X_bus_data_in => rf_X_bus_data_in ,
Y_bus_rd_addr => rf_Y_bus_rd_addr ,
Y_bus_data_out => rf_Y_bus_data_out,
Y_bus_wr_addr => rf_Y_bus_wr_addr ,
Y_bus_wr_valid => rf_Y_bus_wr_valid,
Y_bus_data_in => rf_Y_bus_data_in ,
L_bus_rd_addr => rf_L_bus_rd_addr ,
L_bus_rd_valid => rf_L_bus_rd_valid,
L_bus_wr_addr => rf_L_bus_wr_addr ,
L_bus_wr_valid => rf_L_bus_wr_valid,
push_stack => push_stack,
pop_stack => pop_stack,
set_sr => rf_set_sr,
new_sr => rf_new_sr,
set_omr => rf_set_omr,
new_omr => rf_new_omr,
set_la => rf_set_la,
new_la => rf_new_la,
dec_lc => rf_dec_lc,
set_lc => rf_set_lc,
new_lc => rf_new_lc
);
-----------------
-- BUSES (X,Y,L)
-----------------
rf_X_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_WR);
rf_X_bus_wr_addr <= pipeline_regs(ST_EXEC-1).x_bus_wr_addr;
rf_X_bus_rd_addr <= pipeline_regs(ST_EXEC-1).x_bus_rd_addr;
rf_X_bus_data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' else
pipeline_regs(ST_EXEC-1).RAM_out_x; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else
rf_Y_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_WR);
rf_Y_bus_wr_addr <= pipeline_regs(ST_EXEC-1).y_bus_wr_addr;
rf_Y_bus_rd_addr <= pipeline_regs(ST_EXEC-1).y_bus_rd_addr;
rf_Y_bus_data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' else
pipeline_regs(ST_EXEC-1).RAM_out_y; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else
rf_L_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_WR);
rf_L_bus_rd_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD);
rf_L_bus_wr_addr <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- equal to bits in instruction word
rf_L_bus_rd_addr <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- could be simplified by taking these bits..
-- writing to the R registers within the ADGEN stage has to be prevented when
-- 1) a jump is currently being executed (which is detected in the exec stage)
-- 2) stall cycles occur. In this case the write will happen in the last cycle, when we stop stalling.
-- 3) a memory access results in a stall (e.g. caused by the instruction to REP)
rf_wr_R_port_A_valid <= '0' when stall_flags(ST_ADGEN) = '1' or
exec_bra_modify_pc = '1' or
memory_stall = '1' else
adgen_wr_R_port_A_valid;
rf_wr_R_port_B_valid <= '0' when stall_flags(ST_ADGEN) = '1' or
exec_bra_modify_pc = '1' or
memory_stall = '1' else
adgen_wr_R_port_B_valid;
rf_reg_wr_addr <= pipeline_regs(ST_EXEC-1).reg_wr_addr;
-- can be set due to
-- 1) normal write operation (e.g., move)
-- 2) conditional move (Tcc)
rf_reg_wr_addr_valid <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR) = '1' else
exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR_CC) = '1' else '0';
rf_reg_wr_data <= exec_dst_operand;
rf_reg_rd_addr <= pipeline_regs(ST_EXEC-1).reg_rd_addr;
-- Writing from the ALU can depend on the condition code (Tcc) instruction
rf_alu_wr_valid <= exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_ALU_WR_CC) = '1' else
exec_alu_modify_accu;
push_stack.valid <= '1' when exec_bra_push_stack.valid = '1' or exec_loop_push_stack.valid = '1' else '0';
push_stack.content <= exec_bra_push_stack.content when exec_bra_push_stack.valid = '1' else
exec_loop_push_stack.content;
-- for jump to subroutine store the pc of the subsequent instruction
push_stack.pc <= pipeline_regs(ST_EXEC-2).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else
pipeline_regs(ST_EXEC-3).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '1' else
exec_loop_push_stack.pc when exec_loop_push_stack.valid = '1' else
(others => '0');
pop_stack.valid <= '1' when exec_bra_pop_stack.valid = '1' or exec_loop_pop_stack.valid = '1' else '0';
rf_set_sr <= '1' when exec_bra_modify_sr = '1' or
exec_cr_mod_modify_sr = '1' or
exec_loop_modify_sr = '1' or
exec_alu_modify_sr = '1' or
exec_bit_modify_modify_sr = '1' else '0';
rf_new_sr <= exec_bra_modified_sr when exec_bra_modify_sr = '1' else
exec_cr_mod_modified_sr when exec_cr_mod_modify_sr = '1' else
exec_loop_modified_sr when exec_loop_modify_sr = '1' else
exec_alu_modified_sr when exec_alu_modify_sr = '1' else
exec_bit_modify_modified_sr; -- when exec_bit_modify_modify_sr = '1' else
rf_set_omr <= exec_cr_mod_modify_omr;
rf_new_omr <= exec_cr_mod_modified_omr;
rf_set_lc <= exec_loop_modify_lc;
rf_new_lc <= exec_loop_modified_lc;
rf_set_la <= exec_loop_modify_la;
rf_new_la <= exec_loop_modified_la;
rf_dec_lc <= '1' when exec_loop_decrement_lc = '1' or fetch_decrement_lc = '1' else '0';
---------------------
-- MEMORY MANAGEMENT
---------------------
MMU_inst: memory_management port map (
clk => clk,
rst => rst,
stall_flags => stall_flags,
memory_stall => memory_stall,
data_rom_enable => register_file.omr(2),
pmem_ctrl_in => pmem_ctrl_in,
pmem_ctrl_out => pmem_ctrl_out,
xmem_ctrl_in => xmem_ctrl_in,
xmem_ctrl_out => xmem_ctrl_out,
ymem_ctrl_in => ymem_ctrl_in,
ymem_ctrl_out => ymem_ctrl_out
);
------------------
-- Program Memory
------------------
pmem_ctrl_in.rd_addr <= pc_new;
pmem_ctrl_in.rd_en <= '1' when stall_flags(ST_FETCH) = '0' else '0';
-- TODO: Writing to PMEM!
pmem_ctrl_in.wr_addr <= (others => '0');
pmem_ctrl_in.wr_en <= '0';
pmem_ctrl_in.data_in <= (others => '0');
pmem_data_out <= pmem_ctrl_out.data_out;
pmem_data_out_valid <= pmem_ctrl_out.data_out_valid;
------------------
-- X Memory
------------------
-- Either take the result of the AGU or use the short absolute value stored in the instruction word
xmem_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else
"0000000000" & unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8));
xmem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' else '0';
-- Either take the result of the AGU or use the absolute value stored in the instruction word
xmem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else
"0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8));
xmem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_WR) = '1' else '0';
xmem_ctrl_in.data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' or
pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1' else
exec_dst_operand;
xmem_data_out <= xmem_ctrl_out.data_out;
xmem_data_out_valid <= xmem_ctrl_out.data_out_valid;
------------------
-- Y Memory
------------------
-- Either take the result of the AGU or use the absolute value stored in the instruction word
ymem_ctrl_in.rd_addr <= adgen_address_out_y when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else
"0000000000" & unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8));
ymem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' else '0';
-- Either take the result of the AGU or use the absolute value stored in the instruction word
ymem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_y when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else
"0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8));
ymem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_WR) = '1' else '0';
ymem_ctrl_in.data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' or
pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1' else
exec_dst_operand;
ymem_data_out <= ymem_ctrl_out.data_out;
ymem_data_out_valid <= ymem_ctrl_out.data_out_valid;
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
use work.types_pkg.all;
use work.constants_pkg.all;
entity reg_file is port(
clk, rst : in std_logic;
register_file : out register_file_type;
wr_R_port_A_valid : in std_logic;
wr_R_port_A : in addr_wr_port_type;
wr_R_port_B_valid : in std_logic;
wr_R_port_B : in addr_wr_port_type;
alu_wr_valid : in std_logic;
alu_wr_addr : in std_logic;
alu_wr_data : in signed(55 downto 0);
reg_wr_addr : in std_logic_vector(5 downto 0);
reg_wr_addr_valid : in std_logic;
reg_wr_data : in std_Logic_vector(23 downto 0);
reg_rd_addr : in std_logic_vector(5 downto 0);
reg_rd_data : out std_Logic_vector(23 downto 0);
X_bus_rd_addr : in std_logic_vector(1 downto 0);
X_bus_data_out : out std_logic_vector(23 downto 0);
X_bus_wr_addr : in std_logic_vector(1 downto 0);
X_bus_wr_valid : in std_logic;
X_bus_data_in : in std_logic_vector(23 downto 0);
Y_bus_rd_addr : in std_logic_vector(1 downto 0);
Y_bus_data_out : out std_logic_vector(23 downto 0);
Y_bus_wr_addr : in std_logic_vector(1 downto 0);
Y_bus_wr_valid : in std_logic;
Y_bus_data_in : in std_logic_vector(23 downto 0);
L_bus_rd_addr : in std_logic_vector(2 downto 0);
L_bus_rd_valid : in std_logic;
L_bus_wr_addr : in std_logic_vector(2 downto 0);
L_bus_wr_valid : in std_logic;
push_stack : in push_stack_type;
pop_stack : in pop_stack_type;
set_sr : in std_logic;
new_sr : in std_logic_vector(15 downto 0);
set_omr : in std_logic;
new_omr : in std_logic_vector(7 downto 0);
dec_lc : in std_logic;
set_lc : in std_logic;
new_lc : in unsigned(15 downto 0);
set_la : in std_logic;
new_la : in unsigned(BW_ADDRESS-1 downto 0)
);
end entity;
architecture rtl of reg_file is
signal addr_r : addr_array;
signal addr_m : addr_array;
signal addr_n : addr_array;
signal loop_address : unsigned(BW_ADDRESS-1 downto 0);
signal loop_counter : unsigned(15 downto 0);
-- condition code register
signal ccr : std_logic_vector(7 downto 0);
-- mode register
signal mr : std_logic_vector(7 downto 0);
-- status register = mode register + condition code register
signal sr : std_logic_vector(15 downto 0);
-- operation mode register
signal omr : std_logic_vector(7 downto 0);
signal stack_pointer : unsigned(5 downto 0);
signal system_stack_ssh : stack_array_type;
signal system_stack_ssl : stack_array_type;
signal x0 : signed(23 downto 0);
signal x1 : signed(23 downto 0);
signal y0 : signed(23 downto 0);
signal y1 : signed(23 downto 0);
signal a0 : signed(23 downto 0);
signal a1 : signed(23 downto 0);
signal a2 : signed(7 downto 0);
signal b0 : signed(23 downto 0);
signal b1 : signed(23 downto 0);
signal b2 : signed(7 downto 0);
signal limited_a1 : signed(23 downto 0);
signal limited_b1 : signed(23 downto 0);
signal limited_a0 : signed(23 downto 0);
signal limited_b0 : signed(23 downto 0);
signal set_limiting_flag : std_logic;
signal X_bus_rd_limited_a : std_logic;
signal X_bus_rd_limited_b : std_logic;
signal Y_bus_rd_limited_a : std_logic;
signal Y_bus_rd_limited_b : std_logic;
signal reg_rd_limited_a : std_logic;
signal reg_rd_limited_b : std_logic;
signal rd_limited_a : std_logic;
signal rd_limited_b : std_logic;
begin
sr <= mr & ccr;
register_file.addr_r <= addr_r;
register_file.addr_n <= addr_n;
register_file.addr_m <= addr_m;
register_file.lc <= loop_counter;
register_file.la <= loop_address;
register_file.ccr <= ccr;
register_file.mr <= mr;
register_file.sr <= sr;
register_file.omr <= omr;
register_file.stack_pointer <= stack_pointer;
register_file.current_ssh <= system_stack_ssh(to_integer(stack_pointer(3 downto 0)));
register_file.current_ssl <= system_stack_ssl(to_integer(stack_pointer(3 downto 0)));
register_file.a <= a2 & a1 & a0;
register_file.b <= b2 & b1 & b0;
register_file.x0 <= x0;
register_file.x1 <= x1;
register_file.y0 <= y0;
register_file.y1 <= y1;
global_register_file: process(clk) is
variable stack_pointer_plus_1 : unsigned(3 downto 0);
variable reg_addr : integer range 0 to 7;
begin
if rising_edge(clk) then
if rst = '1' then
addr_r <= (others => (others => '0'));
addr_n <= (others => (others => '0'));
addr_m <= (others => (others => '1'));
ccr <= (others => '0');
mr <= (others => '0');
omr <= (others => '0');
system_stack_ssl <= (others => (others => '0'));
system_stack_ssh <= (others => (others => '0'));
stack_pointer <= (others => '0');
loop_counter <= (others => '0');
loop_address <= (others => '0');
x0 <= (others => '0');
x1 <= (others => '0');
y0 <= (others => '0');
y1 <= (others => '0');
a0 <= (others => '0');
a1 <= (others => '0');
a2 <= (others => '0');
b0 <= (others => '0');
b1 <= (others => '0');
b2 <= (others => '0');
else
reg_addr := to_integer(unsigned(reg_wr_addr(2 downto 0)));
-----------------------------------------------------------------------
-- General write port to register file using 6 bit addressing scheme
-----------------------------------------------------------------------
if reg_wr_addr_valid = '1' then
case reg_wr_addr(5 downto 3) is
-- X0, X1, Y0, Y1
when "000" =>
case reg_wr_addr(2 downto 0) is
when "100" =>
x0 <= signed(reg_wr_data);
when "101" =>
x1 <= signed(reg_wr_data);
when "110" =>
y0 <= signed(reg_wr_data);
when "111" =>
y1 <= signed(reg_wr_data);
when others =>
end case;
-- A0, B0, A2, B2, A1, B1, A, B
when "001" =>
case reg_wr_addr(2 downto 0) is
when "000" =>
a0 <= signed(reg_wr_data);
when "001" =>
b0 <= signed(reg_wr_data);
when "010" =>
a2 <= signed(reg_wr_data(7 downto 0));
when "011" =>
b2 <= signed(reg_wr_data(7 downto 0));
when "100" =>
a1 <= signed(reg_wr_data);
when "101" =>
b1 <= signed(reg_wr_data);
when "110" =>
a2 <= (others => reg_wr_data(23));
a1 <= signed(reg_wr_data);
a0 <= (others => '0');
when "111" =>
b2 <= (others => reg_wr_data(23));
b1 <= signed(reg_wr_data);
b0 <= (others => '0');
when others =>
end case;
-- R0-R7
when "010" =>
addr_r(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
-- N0-N7
when "011" =>
addr_n(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
-- M0-M7
when "100" =>
addr_m(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
-- SR, OMR, SP, SSH, SSL, LA, LC
when "111" =>
case reg_wr_addr(2 downto 0) is
-- SR
when "001" =>
mr <= reg_wr_data(15 downto 8);
ccr <= reg_wr_data( 7 downto 0);
-- OMR
when "010" =>
omr <= reg_wr_data(7 downto 0);
-- SP
when "011" =>
stack_pointer <= unsigned(reg_wr_data(5 downto 0));
-- SSH
when "100" =>
system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
-- increase stack after writing
stack_pointer(3 downto 0) <= stack_pointer_plus_1;
-- test whether stack is full, if so set the stack error flag (SE)
if stack_pointer(3 downto 0) = "1111" then
stack_pointer(4) <= '1';
end if;
-- SSL
when "101" =>
system_stack_ssl(to_integer(stack_pointer)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
-- LA
when "110" =>
loop_address <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
-- LC
when "111" =>
loop_counter <= unsigned(reg_wr_data(15 downto 0));
when others =>
end case;
when others =>
end case;
end if;
----------------
-- X BUS Write
----------------
if X_bus_wr_valid = '1' then
case X_bus_wr_addr is
when "00" =>
x0 <= signed(X_bus_data_in);
when "01" =>
x1 <= signed(X_bus_data_in);
when "10" =>
a2 <= (others => X_bus_data_in(23));
a1 <= signed(X_bus_data_in);
a0 <= (others => '0');
when others =>
b2 <= (others => X_bus_data_in(23));
b1 <= signed(X_bus_data_in);
b0 <= (others => '0');
end case;
end if;
----------------
-- Y BUS Write
----------------
if Y_bus_wr_valid = '1' then
case Y_bus_wr_addr is
when "00" =>
y0 <= signed(Y_bus_data_in);
when "01" =>
y1 <= signed(Y_bus_data_in);
when "10" =>
a2 <= (others => Y_bus_data_in(23));
a1 <= signed(Y_bus_data_in);
a0 <= (others => '0');
when others =>
b2 <= (others => Y_bus_data_in(23));
b1 <= signed(Y_bus_data_in);
b0 <= (others => '0');
end case;
end if;
------------------
-- L BUS Write
------------------
if L_bus_wr_valid = '1' then
case L_bus_wr_addr is
-- A10
when "000" =>
a1 <= signed(X_bus_data_in);
a0 <= signed(Y_bus_data_in);
-- B10
when "001" =>
b1 <= signed(X_bus_data_in);
b0 <= signed(Y_bus_data_in);
-- X
when "010" =>
x1 <= signed(X_bus_data_in);
x0 <= signed(Y_bus_data_in);
-- Y
when "011" =>
y1 <= signed(X_bus_data_in);
y0 <= signed(Y_bus_data_in);
-- A
when "100" =>
a2 <= (others => X_bus_data_in(23));
a1 <= signed(X_bus_data_in);
a0 <= signed(Y_bus_data_in);
-- B
when "101" =>
b2 <= (others => X_bus_data_in(23));
b1 <= signed(X_bus_data_in);
b0 <= signed(Y_bus_data_in);
-- AB
when "110" =>
a2 <= (others => X_bus_data_in(23));
a1 <= signed(X_bus_data_in);
a0 <= (others => '0');
b2 <= (others => Y_bus_data_in(23));
b1 <= signed(Y_bus_data_in);
b0 <= (others => '0');
-- BA
when others =>
a2 <= (others => Y_bus_data_in(23));
a1 <= signed(Y_bus_data_in);
a0 <= (others => '0');
b2 <= (others => X_bus_data_in(23));
b1 <= signed(X_bus_data_in);
b0 <= (others => '0');
end case;
end if;
---------------------
-- STATUS REGISTERS
---------------------
if set_sr = '1' then
ccr <= new_sr( 7 downto 0);
mr <= new_sr(15 downto 8);
end if;
if set_omr = '1' then
omr <= new_omr;
end if;
-- data limiter active?
-- listing this statement after the set_sr test results
-- in the correct behaviour for ALU operations with parallel move
if set_limiting_flag = '1' then
ccr(6) <= '1';
end if;
--------------------
-- LOOP REGISTERS
--------------------
if set_la = '1' then
loop_address <= new_la;
end if;
if set_lc = '1' then
loop_counter <= new_lc;
end if;
if dec_lc = '1' then
loop_counter <= loop_counter - 1;
end if;
---------------------
-- ADDRESS REGISTER
---------------------
if wr_R_port_A_valid = '1' then
addr_r(to_integer(wr_R_port_A.reg_number)) <= wr_R_port_A.reg_value;
end if;
if wr_R_port_B_valid = '1' then
addr_r(to_integer(wr_R_port_B.reg_number)) <= wr_R_port_B.reg_value;
end if;
-------------------------
-- ALU ACCUMULATOR WRITE
-------------------------
if alu_wr_valid = '1' then
if alu_wr_addr = '0' then
a2 <= alu_wr_data(55 downto 48);
a1 <= alu_wr_data(47 downto 24);
a0 <= alu_wr_data(23 downto 0);
else
b2 <= alu_wr_data(55 downto 48);
b1 <= alu_wr_data(47 downto 24);
b0 <= alu_wr_data(23 downto 0);
end if;
end if;
---------------------
-- STACK CONTROLLER
---------------------
stack_pointer_plus_1 := stack_pointer(3 downto 0) + 1;
if push_stack.valid = '1' then
-- increase stack after writing
stack_pointer(3 downto 0) <= stack_pointer_plus_1;
-- test whether stack is full, if so set the stack error flag (SE)
if stack_pointer(3 downto 0) = "1111" then
stack_pointer(4) <= '1';
end if;
case push_stack.content is
when PC =>
system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
when PC_AND_SR =>
system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
system_stack_ssl(to_integer(stack_pointer_plus_1)) <= SR;
when LA_AND_LC =>
system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_address);
system_stack_ssl(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_counter);
end case;
end if;
-- decrease stack pointer
if pop_stack.valid = '1' then
stack_pointer(3 downto 0) <= stack_pointer(3 downto 0) - 1;
-- if stack is empty set the underflow flag (bit 5, UF) and the stack error flag (bit 4, SE)
if stack_pointer(3 downto 0) = "0000" then
stack_pointer(5) <= '1';
stack_pointer(4) <= '1';
end if;
end if;
end if;
end if;
end process;
x_bus_rd_port: process(X_bus_rd_addr,x0,x1,a1,b1,limited_a1,limited_b1,
L_bus_rd_addr,L_bus_rd_valid,y1) is
begin
X_bus_rd_limited_a <= '0';
X_bus_rd_limited_b <= '0';
case X_bus_rd_addr is
when "00" => X_bus_data_out <= std_logic_vector(x0);
when "01" => X_bus_data_out <= std_logic_vector(x1);
when "10" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
end case;
if L_bus_rd_valid = '1' then
case L_bus_rd_addr is
when "000" => X_bus_data_out <= std_logic_vector(a1);
when "001" => X_bus_data_out <= std_logic_vector(b1);
when "010" => X_bus_data_out <= std_logic_vector(x1);
when "011" => X_bus_data_out <= std_logic_vector(y1);
when "100" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
when "101" => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
when "110" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
end case;
end if;
end process x_bus_rd_port;
y_bus_rd_port: process(Y_bus_rd_addr,y0,y1,a1,b1,limited_a1,limited_b1,
L_bus_rd_addr,L_bus_rd_valid,a0,b0,x0,limited_a0,limited_b0) is
begin
Y_bus_rd_limited_a <= '0';
Y_bus_rd_limited_b <= '0';
case Y_bus_rd_addr is
when "00" => Y_bus_data_out <= std_logic_vector(y0);
when "01" => Y_bus_data_out <= std_logic_vector(y1);
when "10" => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
when others => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
end case;
if L_bus_rd_valid = '1' then
case L_bus_rd_addr is
when "000" => Y_bus_data_out <= std_logic_vector(a0);
when "001" => Y_bus_data_out <= std_logic_vector(b0);
when "010" => Y_bus_data_out <= std_logic_vector(x0);
when "011" => Y_bus_data_out <= std_logic_vector(y0);
when "100" => Y_bus_data_out <= std_logic_vector(limited_a0); Y_bus_rd_limited_a <= '1';
when "101" => Y_bus_data_out <= std_logic_vector(limited_b0); Y_bus_rd_limited_b <= '1';
when "110" => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
when others => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
end case;
end if;
end process y_bus_rd_port;
reg_rd_port: process(reg_rd_addr, x0,x1,y0,y1,a0,a1,a2,b0,b1,b2,
omr,ccr,mr,addr_r,addr_n,addr_m,stack_pointer,
loop_address,loop_counter,system_stack_ssl,system_stack_ssh) is
variable reg_addr : integer range 0 to 7;
begin
reg_addr := to_integer(unsigned(reg_rd_addr(2 downto 0)));
reg_rd_data <= (others => '0');
reg_rd_limited_a <= '0';
reg_rd_limited_b <= '0';
case reg_rd_addr(5 downto 3) is
-- X0, X1, Y0, Y1
when "000" =>
case reg_rd_addr(2 downto 0) is
when "100" =>
reg_rd_data <= std_logic_vector(x0);
when "101" =>
reg_rd_data <= std_logic_vector(x1);
when "110" =>
reg_rd_data <= std_logic_vector(y0);
when "111" =>
reg_rd_data <= std_logic_vector(y1);
when others =>
end case;
-- A0, B0, A2, B2, A1, B1, A, B
when "001" =>
case reg_rd_addr(2 downto 0) is
when "000" =>
reg_rd_data <= std_logic_vector(a0);
when "001" =>
reg_rd_data <= std_logic_vector(b0);
when "010" =>
-- MSBs are read as zero!
reg_rd_data(23 downto 8) <= (others => '0');
reg_rd_data(7 downto 0) <= std_logic_vector(a2);
when "011" =>
-- MSBs are read as zero!
reg_rd_data(23 downto 8) <= (others => '0');
reg_rd_data(7 downto 0) <= std_logic_vector(b2);
when "100" =>
reg_rd_data <= std_logic_vector(a1);
when "101" =>
reg_rd_data <= std_logic_vector(b1);
when "110" =>
reg_rd_data <= std_logic_vector(limited_a1);
reg_rd_limited_a <= '1';
when "111" =>
reg_rd_data <= std_logic_vector(limited_b1);
reg_rd_limited_b <= '1';
when others =>
end case;
-- R0-R7
when "010" =>
reg_rd_data <= std_logic_vector(resize(addr_r(reg_addr), 24));
-- N0-N7
when "011" =>
reg_rd_data <= std_logic_vector(resize(addr_n(reg_addr), 24));
-- M0-M7
when "100" =>
reg_rd_data <= std_logic_vector(resize(addr_m(reg_addr), 24));
-- SR, OMR, SP, SSH, SSL, LA, LC
when "111" =>
case reg_wr_addr(2 downto 0) is
-- SR
when "001" =>
reg_rd_data(23 downto 16) <= (others => '0');
reg_rd_data(15 downto 0) <= mr & ccr;
-- OMR
when "010" =>
reg_rd_data(23 downto 8) <= (others => '0');
reg_rd_data( 7 downto 0) <= omr;
-- SP
when "011" =>
reg_rd_data(23 downto 6) <= (others => '0');
reg_rd_data(5 downto 0) <= std_logic_vector(stack_pointer);
-- SSH
when "100" =>
-- TODO!
-- system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
-- -- increase stack after writing
-- stack_pointer(3 downto 0) <= stack_pointer_plus_1;
-- -- test whether stack is full, if so set the stack error flag (SE)
-- if stack_pointer(3 downto 0) = "1111" then
-- stack_pointer(4) <= '1';
-- end if;
-- SSL
when "101" =>
reg_rd_data <= (others => '0');
reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(system_stack_ssl(to_integer(stack_pointer)));
-- LA
when "110" =>
reg_rd_data <= (others => '0');
reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(loop_address);
-- LC
when "111" =>
reg_rd_data <= (others => '0');
reg_rd_data(15 downto 0) <= std_logic_vector(loop_counter);
when others =>
end case;
when others =>
end case;
end process;
rd_limited_a <= '1' when reg_rd_limited_a = '1' or X_bus_rd_limited_a = '1' or Y_bus_rd_limited_a = '1' else '0';
rd_limited_b <= '1' when reg_rd_limited_b = '1' or X_bus_rd_limited_b = '1' or Y_bus_rd_limited_b = '1' else '0';
data_shifter_limiter: process(a2,a1,a0,b2,b1,b0,sr,rd_limited_a,rd_limited_b) is
variable scaled_a : signed(55 downto 0);
variable scaled_b : signed(55 downto 0);
begin
set_limiting_flag <= '0';
-----------------
-- DATA SCALING
-----------------
-- test against scaling bits S1, S0
case sr(11 downto 10) is
-- scale down (right shift)
when "01" =>
scaled_a := a2(7) & a2 & a1 & a0(23 downto 1);
scaled_b := b2(7) & b2 & b1 & b0(23 downto 1);
-- scale up (arithmetic left shift)
when "10" =>
scaled_a := a2(6 downto 0) & a1 & a0 & '0';
scaled_b := b2(6 downto 0) & b1 & b0 & '0';
-- "00" do not scale!
when others =>
scaled_a := a2 & a1 & a0;
scaled_b := b2 & b1 & b0;
end case;
-- only sign extension stored in a2?
-- Yes: No limiting needed!
if scaled_a(55 downto 47) = "111111111" or scaled_a(55 downto 47) = "000000000" then
limited_a1 <= scaled_a(47 downto 24);
limited_a0 <= scaled_a(23 downto 0);
else
-- positive value in a?
if scaled_a(55) = '0' then
limited_a1 <= X"7FFFFF";
limited_a0 <= X"FFFFFF";
-- negative value in a?
else
limited_a1 <= X"800000";
limited_a0 <= X"000000";
end if;
-- set the limit flag in the status register
if rd_limited_a = '1' then
set_limiting_flag <= '1';
end if;
end if;
-- only sign extension stored in b2?
-- Yes: No limiting needed!
if scaled_b(55 downto 47) = "111111111" or scaled_b(55 downto 47) = "000000000" then
limited_b1 <= scaled_b(47 downto 24);
limited_b0 <= scaled_b(23 downto 0);
else
-- positive value in b?
if scaled_b(55) = '0' then
limited_b1 <= X"7FFFFF";
limited_b0 <= X"FFFFFF";
-- negative value in b?
else
limited_b1 <= X"800000";
limited_b0 <= X"000000";
end if;
-- set the limit flag in the status register
if rd_limited_b = '1' then
set_limiting_flag <= '1';
end if;
end if;
end process;
end architecture rtl;

167
BaS_GNU/FPGA_quartus/DSP/src/types_pkg.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.parameter_pkg.all;
package types_pkg is
-- the different addressing modes
type adgen_mode_type is (NOP, POST_MIN_N, POST_PLUS_N, POST_MIN_1, POST_PLUS_1, INDEXED_N, PRE_MIN_1, ABSOLUTE, IMMEDIATE);
------------------------
-- Decoded instructions
------------------------
type instructions_type is (
INSTR_NOP ,
INSTR_RTI ,
INSTR_ILLEGAL ,
INSTR_SWI ,
INSTR_RTS ,
INSTR_RESET ,
INSTR_WAIT ,
INSTR_STOP ,
INSTR_ENDDO ,
INSTR_ANDI ,
INSTR_ORI ,
INSTR_DIV ,
INSTR_NORM ,
INSTR_LUA ,
INSTR_MOVEC ,
INSTR_REP ,
INSTR_DO ,
INSTR_MOVEM ,
INSTR_MOVEP ,
INSTR_PM_MOVEM,
INSTR_BCLR ,
INSTR_BSET ,
INSTR_JCLR ,
INSTR_JSET ,
INSTR_JMP ,
INSTR_JCC ,
INSTR_BCHG ,
INSTR_BTST ,
INSTR_JSCLR ,
INSTR_JSSET ,
INSTR_JSR ,
INSTR_JSCC );
type addr_array is array(0 to 7) of unsigned(BW_ADDRESS-1 downto 0);
type alu_shift_mode is (NO_SHIFT, SHIFT_LEFT, SHIFT_RIGHT, ZEROS);
type alu_ccr_flag is (DONT_TOUCH, CLEAR, MODIFY, SET);
type alu_ccr_flag_array is array(7 downto 0) of alu_ccr_flag;
type alu_ctrl_type is record
mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
shift_src : std_logic; -- a,b
shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
shift_mode : alu_shift_mode;
rotate : std_logic; -- 0: logical shift, 1: rotate shift
add_src_stage_1 : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b
add_src_stage_2 : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved
add_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
logic_function : std_logic_vector(2 downto 0); -- 000: none, 001: and, 010: or, 011: eor, 100: not
word_24_update : std_logic; -- only accumulator bits 47 downto 24 affected?
rounding_used : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry
store_result : std_logic; -- 0: do not update accumulator, 1: update accumulator
dst_accu : std_logic; -- 0: a, 1: b
div_instr : std_logic; -- DIV instruction? Special ALU operations needed!
norm_instr : std_logic; -- NORM instruction? Special ALU operations needed!
ccr_flags_ctrl : alu_ccr_flag_array;
end record;
type pipeline_signals is record
instr_word: std_logic_vector(23 downto 0);
pc : unsigned(BW_ADDRESS-1 downto 0);
dble_word_instr : std_logic;
instr_array : instructions_type;
act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
dec_activate : std_logic;
adgen_mode_a : adgen_mode_type;
adgen_mode_b : adgen_mode_type;
reg_wr_addr : std_logic_vector(5 downto 0);
reg_rd_addr : std_logic_vector(5 downto 0);
x_bus_rd_addr : std_logic_vector(1 downto 0);
x_bus_wr_addr : std_logic_vector(1 downto 0);
y_bus_rd_addr : std_logic_vector(1 downto 0);
y_bus_wr_addr : std_logic_vector(1 downto 0);
l_bus_addr : std_logic_vector(2 downto 0);
adgen_address_x : unsigned(BW_ADDRESS-1 downto 0);
adgen_address_y : unsigned(BW_ADDRESS-1 downto 0);
RAM_out_x : std_logic_vector(23 downto 0);
RAM_out_y : std_logic_vector(23 downto 0);
alu_ctrl : alu_ctrl_type;
end record;
type pipeline_type is array(0 to PIPELINE_DEPTH-1) of pipeline_signals;
type register_file_type is record
a : signed(55 downto 0);
b : signed(55 downto 0);
x0 : signed(23 downto 0);
x1 : signed(23 downto 0);
y0 : signed(23 downto 0);
y1 : signed(23 downto 0);
la : unsigned(BW_ADDRESS-1 downto 0);
lc : unsigned(15 downto 0);
addr_r : addr_array;
addr_n : addr_array;
addr_m : addr_array;
ccr : std_logic_vector(7 downto 0);
mr : std_logic_vector(7 downto 0);
sr : std_logic_vector(15 downto 0);
omr : std_logic_vector(7 downto 0);
stack_pointer : unsigned(5 downto 0);
-- system_stack_ssh : stack_array_type;
-- system_stack_ssl : stack_array_type;
current_ssh : std_logic_vector(BW_ADDRESS-1 downto 0);
current_ssl : std_logic_vector(BW_ADDRESS-1 downto 0);
end record;
type addr_wr_port_type is record
-- write_valid : std_logic;
reg_number : unsigned(2 downto 0);
reg_value : unsigned(15 downto 0);
end record;
type mem_ctrl_type_in is record
rd_addr : unsigned(BW_ADDRESS-1 downto 0);
rd_en : std_logic;
wr_addr : unsigned(BW_ADDRESS-1 downto 0);
wr_en : std_logic;
data_in : std_logic_vector(23 downto 0);
end record;
type mem_ctrl_type_out is record
data_out : std_logic_vector(23 downto 0);
data_out_valid : std_logic;
end record;
type memory_type is (X_MEM, Y_MEM, P_MEM);
---------------
-- STACK TYPES
---------------
type stack_array_type is array(0 to 15) of std_logic_vector(BW_ADDRESS-1 downto 0);
type push_stack_content_type is (PC, PC_AND_SR, LA_AND_LC);
type push_stack_type is record
valid : std_logic;
pc : unsigned(BW_ADDRESS-1 downto 0);
content : push_stack_content_type;
end record;
-- type pop_stack_content_type is (PC, PC_AND_SR, SR, LA_AND_LC);
-- type pop_stack_type is std_logic;
type pop_stack_type is record
valid : std_logic;
-- content : pop_stack_content_type;
end record;
end package types_pkg;

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BaS_GNU/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd Normal file
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Tue Sep 08 16:24:20 2009
library work;
use work.FalconIO_SDCard_IDE_CF_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Entity Declaration
-- Entity Declaration
ENTITY FalconIO_SDCard_IDE_CF IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
CLK33M : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
CLK2M : IN STD_LOGIC;
CLK500k : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
nFB_BURST : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
LP_BUSY : IN STD_LOGIC;
nACSI_DRQ : IN STD_LOGIC;
nACSI_INT : IN STD_LOGIC;
nSCSI_DRQ : IN STD_LOGIC;
nSCSI_MSG : IN STD_LOGIC;
MIDI_IN : IN STD_LOGIC;
RxD : IN STD_LOGIC;
CTS : IN STD_LOGIC;
RI : IN STD_LOGIC;
DCD : IN STD_LOGIC;
AMKB_RX : IN STD_LOGIC;
PIC_AMKB_RX : IN STD_LOGIC;
IDE_RDY : IN STD_LOGIC;
IDE_INT : IN STD_LOGIC;
WP_CS_CARD : IN STD_LOGIC;
nINDEX : IN STD_LOGIC;
TRACK00 : IN STD_LOGIC;
nRD_DATA : IN STD_LOGIC;
nDCHG : IN STD_LOGIC;
SD_DATA0 : IN STD_LOGIC;
SD_DATA1 : IN STD_LOGIC;
SD_DATA2 : IN STD_LOGIC;
SD_CARD_DEDECT : IN STD_LOGIC;
SD_WP : IN STD_LOGIC;
nDACK0 : IN STD_LOGIC;
nFB_WR : INOUT STD_LOGIC;
WP_CF_CARD : IN STD_LOGIC;
nWP : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nRSTO : IN STD_LOGIC;
HD_DD : IN STD_LOGIC;
nSCSI_C_D : IN STD_LOGIC;
nSCSI_I_O : IN STD_LOGIC;
CLK2M4576 : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
VSYNC : IN STD_LOGIC;
HSYNC : IN STD_LOGIC;
DSP_INT : IN STD_LOGIC;
nBLANK : IN STD_LOGIC;
FDC_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
nIDE_CS1 : OUT STD_LOGIC;
nIDE_CS0 : OUT STD_LOGIC;
LP_STR : OUT STD_LOGIC;
LP_DIR : OUT STD_LOGIC;
nACSI_ACK : OUT STD_LOGIC;
nACSI_RESET : OUT STD_LOGIC;
nACSI_CS : OUT STD_LOGIC;
ACSI_DIR : OUT STD_LOGIC;
ACSI_A1 : OUT STD_LOGIC;
nSCSI_ACK : OUT STD_LOGIC;
nSCSI_ATN : OUT STD_LOGIC;
SCSI_DIR : OUT STD_LOGIC;
SD_CLK : OUT STD_LOGIC;
YM_QA : OUT STD_LOGIC;
YM_QC : OUT STD_LOGIC;
YM_QB : OUT STD_LOGIC;
nSDSEL : OUT STD_LOGIC;
STEP : OUT STD_LOGIC;
MOT_ON : OUT STD_LOGIC;
nRP_LDS : OUT STD_LOGIC;
nRP_UDS : OUT STD_LOGIC;
nROM4 : OUT STD_LOGIC;
nROM3 : OUT STD_LOGIC;
nCF_CS1 : OUT STD_LOGIC;
nCF_CS0 : OUT STD_LOGIC;
nIDE_RD : INOUT STD_LOGIC;
nIDE_WR : INOUT STD_LOGIC;
AMKB_TX : OUT STD_LOGIC;
IDE_RES : OUT STD_LOGIC;
DTR : OUT STD_LOGIC;
RTS : OUT STD_LOGIC;
TxD : OUT STD_LOGIC;
MIDI_OLR : OUT STD_LOGIC;
MIDI_TLR : OUT STD_LOGIC;
nDREQ0 : OUT STD_LOGIC;
DSA_D : OUT STD_LOGIC;
nMFP_INT : OUT STD_LOGIC;
FALCON_IO_TA : OUT STD_LOGIC;
STEP_DIR : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC;
WR_GATE : OUT STD_LOGIC;
DMA_DRQ : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_PAR : INOUT STD_LOGIC;
nSCSI_SEL : INOUT STD_LOGIC;
nSCSI_BUSY : INOUT STD_LOGIC;
nSCSI_RST : INOUT STD_LOGIC;
SD_CD_DATA3 : INOUT STD_LOGIC;
SD_CDM_D1 : INOUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END FalconIO_SDCard_IDE_CF;
-- Architecture Body
ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
-- system
signal SYS_CLK : STD_LOGIC;
signal RESETn : STD_LOGIC;
signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS
signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS
signal BYT : STD_LOGIC; -- WENN BYT -> 1
signal LONG : STD_LOGIC; -- WENN -> 1
-- KEYBOARD MIDI
signal ACIA_CS_I : STD_LOGIC;
signal IRQ_KEYBDn : STD_LOGIC;
signal IRQ_MIDIn : STD_LOGIC;
signal KEYB_RxD : STD_LOGIC;
signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0);
signal MIDI_OUT : STD_LOGIC;
signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0);
signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0);
-- MFP
signal MFP_CS : STD_LOGIC;
signal MFP_INTACK : STD_LOGIC;
signal LDS : STD_LOGIC;
signal DTACK_OUT_MFPn : STD_LOGIC;
signal IRQ_ACIAn : STD_LOGIC;
signal DINTn : STD_LOGIC;
signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0);
signal TDO : STD_LOGIC;
-- SOUND
signal SNDCS : STD_LOGIC;
signal SNDCS_I : STD_LOGIC;
signal SNDIR_I : STD_LOGIC;
signal LP_DIR_X : STD_LOGIC;
signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0);
signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0);
-- DIV
signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE
signal ROM_CS : STD_LOGIC;
-- DMA UND FLOPPY
signal DMA_DATEN_CS : STD_LOGIC;
signal DMA_MODUS_CS : STD_LOGIC;
signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0);
signal WDC_BSL_CS : STD_LOGIC;
signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal HD_DD_OUT : STD_LOGIC;
signal FDCS_In : STD_LOGIC;
signal CA0 : STD_LOGIC;
signal CA1 : STD_LOGIC;
signal CA2 : STD_LOGIC;
signal FDINT : STD_LOGIC;
signal FDRQ : STD_LOGIC;
signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0);
signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_TOP_CS : STD_LOGIC;
signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_HIGH_CS : STD_LOGIC;
signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_MID_CS : STD_LOGIC;
signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_LOW_CS : STD_LOGIC;
signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_DIRM_CS : STD_LOGIC;
signal DMA_ADR_CS : STD_LOGIC;
signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0);
signal DMA_DIR_OLD : STD_LOGIC;
signal DMA_BYT_CNT_CS : STD_LOGIC;
signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0);
signal CLR_FIFO : STD_LOGIC;
signal DMA_DRQ_I : STD_LOGIC;
signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0);
signal DMA_DRQQ : STD_LOGIC;
signal DMA_DRQ_Q : STD_LOGIC;
signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0);
signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0);
signal RDF_RDE : STD_LOGIC;
signal RDF_WRE : STD_LOGIC;
signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0);
signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0);
signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0);
signal WRF_RDE : STD_LOGIC;
signal WRF_WRE : STD_LOGIC;
signal nFDC_WR : STD_LOGIC;
type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
signal FCF_STATE : FCF_STATES;
signal NEXT_FCF_STATE : FCF_STATES;
signal DMA_REQ : STD_LOGIC;
signal FDC_CS : STD_LOGIC;
signal FCF_CS : STD_LOGIC;
signal FCF_APH : STD_LOGIC;
signal DMA_AZ_CS : STD_LOGIC;
signal DMA_ACTIV : STD_LOGIC;
signal DMA_ACTIV_NEW : STD_LOGIC;
signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0);
-- SCSI
signal SCSI_CS : STD_LOGIC;
signal SCSI_CSn : STD_LOGIC;
signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0);
signal nSCSI_DACK : STD_LOGIC;
signal SCSI_DRQ : STD_LOGIC;
signal SCSI_INT : STD_LOGIC;
signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0);
signal DB_EN : STD_LOGIC;
signal DBP_OUTn : STD_LOGIC;
signal DBP_EN : STD_LOGIC;
signal RST_OUTn : STD_LOGIC;
signal RST_EN : STD_LOGIC;
signal BSY_OUTn : STD_LOGIC;
signal BSY_EN : STD_LOGIC;
signal SEL_OUTn : STD_LOGIC;
signal SEL_EN : STD_LOGIC;
-- IDE
signal nnIDE_RES : STD_LOGIC;
signal IDE_CF_CS : STD_LOGIC;
signal IDE_CF_TA : STD_LOGIC;
signal NEXT_nIDE_RD : STD_LOGIC;
signal NEXT_nIDE_WR : STD_LOGIC;
type CMD_STATES is( IDLE, T1, T6, T7);
signal CMD_STATE : CMD_STATES;
signal NEXT_CMD_STATE : CMD_STATES;
BEGIN
LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
'1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
'1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1';
nDREQ0 <= '0';
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
SD_CLK <= 'Z';
SD_CD_DATA3 <= 'Z';
SD_CDM_D1 <= 'Z';
----------------------------------------------------------------------------
-- IDE
----------------------------------------------------------------------------
CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
begin
if nRSTO = '0' then
CMD_STATE <= IDLE;
elsif rising_edge(MAIN_CLK) then
CMD_STATE <= NEXT_CMD_STATE; -- go to next
nIDE_RD <= NEXT_nIDE_RD; -- go to next
nIDE_WR <= NEXT_nIDE_WR; -- go to next
else
CMD_STATE <= CMD_STATE; -- halten
nIDE_RD <= nIDE_RD; -- halten
nIDE_WR <= nIDE_WR; -- halten
end if;
end process CMD_REG;
CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
begin
case CMD_STATE is
when IDLE =>
IDE_CF_TA <= '0';
if IDE_CF_CS = '1' then
NEXT_nIDE_RD <= not nFB_WR;
NEXT_nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T1;
else
NEXT_nIDE_RD <= '1';
NEXT_nIDE_WR <= '1';
NEXT_CMD_STATE <= IDLE;
end if;
when T1 =>
IDE_CF_TA <= '0';
NEXT_nIDE_RD <= not nFB_WR;
NEXT_nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T6;
when T6 =>
IF IDE_RDY = '1' then
IDE_CF_TA <= '1';
NEXT_nIDE_RD <= '1';
NEXT_nIDE_WR <= '1';
NEXT_CMD_STATE <= T7;
else
IDE_CF_TA <= '0';
NEXT_nIDE_RD <= not nFB_WR;
NEXT_nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T6;
end if;
when T7 =>
IDE_CF_TA <= '0';
NEXT_nIDE_RD <= '1';
NEXT_nIDE_WR <= '1';
NEXT_CMD_STATE <= IDLE;
end case;
end process CMD_DECODER;
IDE_RES <= not nnIDE_RES and nRSTO;
IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80
nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F
'0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F
nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F
'0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F
nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F
'0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F
nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F
'0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F
-----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772
-------------------------------------------------------------------------------------------------------------------------------------------
-- daten read fifo
RDF: dcfifo0
port map(
aclr => CLR_FIFO,
data => RDF_DIN,
rdclk => MAIN_CLK,
rdreq => RDF_RDE,
wrclk => FDC_CLK,
wrreq => RDF_WRE,
q => RDF_DOUT,
wrusedw => RDF_AZ
);
FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY
FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
-- daten write fifo
WRF: dcfifo1
port map(
aclr => CLR_FIFO,
data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
rdclk => FDC_CLK,
rdreq => WRF_RDE,
wrclk => MAIN_CLK,
wrreq => WRF_WRE,
q => WRF_DOUT,
rdusedw => WRF_AZ
);
CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
-- FIFO WRITE: GENAU 1 MAIN_CLK -------------------------------------------------------------------------
process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
begin
if nRSTO = '0' THEN
WRF_WRE <= '0';
elsif rising_edge(MAIN_CLK) then
IF FCF_APH = '1' and nFB_WR = '0' then
WRF_WRE <= '1';
else
WRF_WRE <= '0';
end if;
else
WRF_WRE <= WRF_WRE;
end if;
END PROCESS;
FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
begin
if nRSTO = '0' then
FCF_STATE <= FCF_IDLE;
DMA_ACTIV <= '0';
elsif rising_edge(FDC_CLK) then
FCF_STATE <= NEXT_FCF_STATE; -- go to next
DMA_ACTIV <= DMA_ACTIV_NEW;
else
FCF_STATE <= FCF_STATE; -- halten
DMA_ACTIV <= DMA_ACTIV;
end if;
end process FCF_REG;
FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
begin
if nRSTO = '0' then
FDC_OUT <= x"00";
elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
FDC_OUT <= CD_OUT_FDC; -- set
else
FDC_OUT <= FDC_OUT; -- halten
end if;
end process FDC_REG;
DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
begin
case FCF_STATE is
when FCF_IDLE =>
SCSI_CSn <= '1';
FDCS_In <= '1';
RDF_WRE <= '0';
WRF_RDE <= '0';
nSCSI_DACK <= '1';
if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then
DMA_ACTIV_NEW <= DMA_REQ;
NEXT_FCF_STATE <= FCF_T0;
else
DMA_ACTIV_NEW <= '0';
NEXT_FCF_STATE <= FCF_IDLE;
end if;
when FCF_T0 =>
SCSI_CSn <= '1';
FDCS_In <= '1';
RDF_WRE <= '0';
nSCSI_DACK <= '1';
DMA_ACTIV_NEW <= DMA_REQ;
WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO
if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike?
NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start
else
NEXT_FCF_STATE <= FCF_T1;
end if;
when FCF_T1 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T2;
when FCF_T2 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T3;
when FCF_T3 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T6;
when FCF_T6 =>
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO
NEXT_FCF_STATE <= FCF_T7;
when FCF_T7 =>
SCSI_CSn <= '1';
FDCS_In <= '1';
RDF_WRE <= '0';
WRF_RDE <= '0';
nSCSI_DACK <= '1';
DMA_ACTIV_NEW <= '0';
if FDC_CS = '1' and DMA_REQ = '0' then
NEXT_FCF_STATE <= FCF_T7;
else
NEXT_FCF_STATE <= FCF_IDLE;
end if;
end case;
end process FCF_DECODER;
I_FDC: WF1772IP_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
CSn => FDCS_In,
RWn => nFDC_WR,
A1 => CA2,
A0 => CA1,
DATA_IN => CD_IN_FDC,
DATA_OUT => CD_OUT_FDC,
-- DATA_EN => CD_EN_FDC,
RDn => nRD_DATA,
TR00n => TRACK00,
IPn => nINDEX,
WPRTn => nWP,
DDEn => '0', -- Fixed to MFM.
HDTYPE => HD_DD_OUT,
MO => MOT_ON,
WG => WR_GATE,
WD => WR_DATA,
STEP => STEP,
DIRC => STEP_DIR,
DRQ => DMA_DRQ_I,
INTRQ => FDINT
);
DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2
DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2
WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2
HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else
DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
--- WDC BSL REGISTER -------------------------------------------------------
process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
begin
if nRSTO = '0' THEN
WDC_BSL <= "00";
elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
IF FB_B0 = '1' THEN
WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
else
WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
end if;
end if;
END PROCESS;
--- DMA MODUS REGISTER -------------------------------------------------------
process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
begin
if nRSTO = '0' THEN
DMA_MODUS <= x"0000";
elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
IF FB_B0 = '1' THEN
DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
else
DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
end if;
IF FB_B1 = '1' THEN
DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
else
DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
end if;
else
DMA_MODUS <= DMA_MODUS;
end if;
END PROCESS;
-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
begin
if nRSTO = '0' or CLR_FIFO = '1' THEN
DMA_BYT_CNT <= x"00000000";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
DMA_BYT_CNT(31 downto 17) <= "000000000000000";
DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
DMA_BYT_CNT(8 downto 0) <= "000000000";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
DMA_BYT_CNT <= FB_AD;
else
DMA_BYT_CNT <= DMA_BYT_CNT;
end if;
END PROCESS;
--------------------------------------------------------------------
FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
DMA_STATUS(0) <= '1'; -- DMA OK
DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0';
DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else
'1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------
process(FDC_CLK, nRSTO, DMA_DRQ_REG)
begin
if nRSTO = '0' THEN
DMA_DRQ_REG <= "00";
elsif rising_edge(FDC_CLK) then
DMA_DRQ_REG(0) <= DMA_DRQQ;
DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
else
DMA_DRQ_REG <= DMA_DRQ_REG;
end if;
END PROCESS;
-- DMA ADRESSE ------------------------------------------------------
process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
begin
if nRSTO = '0' THEN
DMA_TOP <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
DMA_TOP <= FB_AD(31 downto 24);
else
DMA_TOP <= DMA_TOP;
end if;
END PROCESS;
process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
begin
if nRSTO = '0' THEN
DMA_HIGH <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
DMA_HIGH <= FB_AD(23 downto 16);
else
DMA_HIGH <= DMA_HIGH;
end if;
END PROCESS;
process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
begin
DMA_MID <= DMA_MID;
if nRSTO = '0' THEN
DMA_MID <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
if DMA_MID_CS = '1' then
DMA_MID <= FB_AD(23 downto 16);
elsif DMA_ADR_CS = '1' then
DMA_MID <= FB_AD(15 downto 8);
end if;
end if;
END PROCESS;
process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
begin
DMA_LOW <= DMA_LOW;
if nRSTO = '0' THEN
DMA_LOW <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
if DMA_LOW_CS = '1'then
DMA_LOW <= FB_AD(23 downto 16);
elsif DMA_ADR_CS = '1' then
DMA_LOW <= FB_AD(7 downto 0);
end if;
end if;
END PROCESS;
--------------------------------------------------------------------------------------------
DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2
DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2
DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2
DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2
FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-- DIRECTZUGRIFF
DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG
DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- DMA RW TOGGLE ------------------------------------------
process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
begin
if nRSTO = '0' THEN
DMA_DIR_OLD <= '0';
elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then
DMA_DIR_OLD <= DMA_MODUS(8);
else
DMA_DIR_OLD <= DMA_DIR_OLD;
end if;
END PROCESS;
CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
-- SCSI ----------------------------------------------------------------------------------
I_SCSI: WF5380_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
ADR => CA2 & CA1 & CA0,
DATA_IN => CD_IN_FDC,
DATA_OUT => SCSI_DOUT,
--DATA_EN : out bit;
-- Bus and DMA controls:
CSn => '1', --SCSI_CSn, ABGESCHALTET
RDn => (not nFDC_WR) or (not SCSI_CS),
WRn => nFDC_WR or (not SCSI_CS),
EOPn => '1',
DACKn => nSCSI_DACK,
DRQ => SCSI_DRQ,
INT => SCSI_INT,
-- READY =>
-- SCSI bus:
DB_INn => SCSI_D,
DB_OUTn => DB_OUTn,
DB_EN => DB_EN,
DBP_INn => SCSI_PAR,
DBP_OUTn => DBP_OUTn,
DBP_EN => DBP_EN, -- wenn 1 dann output
RST_INn => nSCSI_RST,
RST_OUTn => RST_OUTn,
RST_EN => RST_EN,
BSY_INn => nSCSI_BUSY,
BSY_OUTn => BSY_OUTn,
BSY_EN => BSY_EN,
SEL_INn => nSCSI_SEL,
SEL_OUTn => SEL_OUTn,
SEL_EN => SEL_EN,
ACK_INn => '1',
ACK_OUTn => nSCSI_ACK,
-- ACK_EN => ACK_EN,
ATN_INn => '1',
ATN_OUTn => nSCSI_ATN,
-- ATN_EN => ATN_EN,
REQ_INn => nSCSI_DRQ,
-- REQ_OUTn => REQ_OUTn,
-- REQ_EN => REQ_EN,
IOn_IN => nSCSI_I_O,
-- IOn_OUT => IOn_OUT,
-- IO_EN => IO_EN,
CDn_IN => nSCSI_C_D,
-- CDn_OUT => CDn_OUT,
-- CD_EN => CD_EN,
MSG_INn => nSCSI_MSG
-- MSG_OUTn => MSG_OUTn,
-- MSG_EN => MSG_EN
);
-- SCSI ACSI ---------------------------------------------------------------
SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET
SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
ACSI_DIR <= '0';
ACSI_D <= "ZZZZZZZZ";
nACSI_CS <= '1';
ACSI_A1 <= CA1;
nACSI_RESET <= nRSTO;
nACSI_ACK <= '1';
----------------------------------------------------------------------------
-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
----------------------------------------------------------------------------
ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000
nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
----------------------------------------------------------------------------
-- ACIA KEYBOARD
----------------------------------------------------------------------------
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
CS2n => FB_ADR(2),
CS1 => '1',
CS0 => ACIA_CS_I,
E => ACIA_CS_I,
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_OUT => DATA_OUT_ACIA_I,
-- DATA_EN => DATA_EN_ACIA_I,
TXCLK => CLK500k,
RXCLK => CLK500k,
RXDATA => KEYB_RxD,
CTSn => '0',
DCDn => '0',
IRQn => IRQ_KEYBDn,
TXDATA => AMKB_TX
--RTSn => -- Not used.
);
ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8
KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------
process(CLK2M, AMKB_RX, AMKB_REG)
begin
if rising_edge(CLK2M) then
IF AMKB_RX = '0' THEN
IF AMKB_REG < 16 THEN
AMKB_REG <= "00000";
ELSE
AMKB_REG <= AMKB_REG - 1;
END IF;
ELSE
IF AMKB_REG > 15 THEN
AMKB_REG <= "11111";
ELSE
AMKB_REG <= AMKB_REG + 1;
END IF;
END IF;
ELSE
AMKB_REG <= AMKB_REG;
end if;
END PROCESS;
----------------------------------------------------------------------------
-- ACIA MIDI
----------------------------------------------------------------------------
I_ACIA_MIDI: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
CS2n => '0',
CS1 => FB_ADR(2),
CS0 => ACIA_CS_I,
E => ACIA_CS_I,
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_OUT => DATA_OUT_ACIA_II,
-- DATA_EN => DATA_EN_ACIA_II,
TXCLK => CLK500k,
RXCLK => CLK500k,
RXDATA => MIDI_IN,
CTSn => '0',
DCDn => '0',
IRQn => IRQ_MIDIn,
TXDATA => MIDI_OUT
--RTSn => -- Not used.
);
MIDI_TLR <= MIDI_OUT;
MIDI_OLR <= MIDI_OUT;
FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
----------------------------------------------------------------------------
-- MFP
----------------------------------------------------------------------------
I_MFP: WF68901IP_TOP_SOC
port map(
-- System control:
CLK => MAIN_CLK,
RESETn => nRSTO,
-- Asynchronous bus control:
DSn => not LDS,
CSn => not MFP_CS,
RWn => nFB_WR,
DTACKn => DTACK_OUT_MFPn,
-- Data and Adresses:
RS => FB_ADR(5 downto 1),
DATA_IN => FB_AD(23 downto 16),
DATA_OUT => DATA_OUT_MFP,
-- DATA_EN => DATA_EN_MFP,
GPIP_IN(7) => not DMA_DRQ_Q,
GPIP_IN(6) => not RI,
GPIP_IN(5) => DINTn,
GPIP_IN(4) => IRQ_ACIAn,
GPIP_IN(3) => DSP_INT,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY,
-- GPIP_OUT =>, -- Not used; all GPIPs are direction input.
-- GPIP_EN =>, -- Not used; all GPIPs are direction input.
-- Interrupt control:
IACKn => not MFP_INTACK,
IEIn => '0',
-- IEOn =>, -- Not used.
IRQn => nMFP_INT,
-- Timers and timer control:
XTAL1 => CLK2M4576,
TAI => '0',
TBI => nBLANK,
-- TAO =>,
-- TBO =>,
-- TCO =>,
TDO => TDO,
-- Serial I/O control:
RC => TDO,
TC => TDO,
SI => RxD,
SO => TxD
-- SO_EN => MFP_SO_EN
-- DMA control:
-- RRn =>,
-- TRn =>
);
MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40
MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000
LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
'0' when FDINT = '1' else
'0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------
process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
begin
if nRSTO = '0' THEN
IRQ_ACIAn <= '1';
elsif rising_edge(MAIN_CLK) then
IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
else
IRQ_ACIAn <= IRQ_ACIAn;
end if;
END PROCESS;
----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
I_SOUND: WF2149IP_TOP_SOC
port map(
SYS_CLK => MAIN_CLK,
RESETn => nRSTO,
WAV_CLK => CLK2M,
SELn => '1',
BDIR => SNDIR_I,
BC2 => '1',
BC1 => SNDCS_I,
A9n => '0',
A8 => '1',
DA_IN => FB_AD(31 downto 24),
DA_OUT => DA_OUT_X,
IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => LP_STR,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
IO_A_OUT(1) => DSA_D,
IO_A_OUT(0) => nSDSEL,
-- IO_A_EN =>, -- Not required.
IO_B_IN => LP_D,
IO_B_OUT => LP_D_X,
-- IO_B_EN => IO_B_EN,
OUT_A => YM_QA,
OUT_B => YM_QB,
OUT_C => YM_QC
);
SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4
SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;
END FalconIO_SDCard_IDE_CF_architecture;

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@@ -0,0 +1,971 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Tue Sep 08 16:24:20 2009
library work;
use work.FalconIO_SDCard_IDE_CF_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Entity Declaration
-- Entity Declaration
ENTITY FalconIO_SDCard_IDE_CF IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
CLK33M : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
CLK2M : IN STD_LOGIC;
CLK500k : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
nFB_BURST : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
LP_BUSY : IN STD_LOGIC;
nACSI_DRQ : IN STD_LOGIC;
nACSI_INT : IN STD_LOGIC;
nSCSI_DRQ : IN STD_LOGIC;
nSCSI_MSG : IN STD_LOGIC;
MIDI_IN : IN STD_LOGIC;
RxD : IN STD_LOGIC;
CTS : IN STD_LOGIC;
RI : IN STD_LOGIC;
DCD : IN STD_LOGIC;
AMKB_RX : IN STD_LOGIC;
PIC_AMKB_RX : IN STD_LOGIC;
IDE_RDY : IN STD_LOGIC;
IDE_INT : IN STD_LOGIC;
WP_CS_CARD : IN STD_LOGIC;
nINDEX : IN STD_LOGIC;
TRACK00 : IN STD_LOGIC;
nRD_DATA : IN STD_LOGIC;
nDCHG : IN STD_LOGIC;
SD_DATA0 : IN STD_LOGIC;
SD_DATA1 : IN STD_LOGIC;
SD_DATA2 : IN STD_LOGIC;
SD_CARD_DEDECT : IN STD_LOGIC;
SD_WP : IN STD_LOGIC;
nDACK0 : IN STD_LOGIC;
nFB_WR : INOUT STD_LOGIC;
WP_CF_CARD : IN STD_LOGIC;
nWP : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nRSTO : IN STD_LOGIC;
HD_DD : IN STD_LOGIC;
nSCSI_C_D : IN STD_LOGIC;
nSCSI_I_O : IN STD_LOGIC;
CLK2M4576 : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
VSYNC : IN STD_LOGIC;
HSYNC : IN STD_LOGIC;
DSP_INT : IN STD_LOGIC;
nBLANK : IN STD_LOGIC;
FDC_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
nIDE_CS1 : OUT STD_LOGIC;
nIDE_CS0 : OUT STD_LOGIC;
LP_STR : OUT STD_LOGIC;
LP_DIR : OUT STD_LOGIC;
nACSI_ACK : OUT STD_LOGIC;
nACSI_RESET : OUT STD_LOGIC;
nACSI_CS : OUT STD_LOGIC;
ACSI_DIR : OUT STD_LOGIC;
ACSI_A1 : OUT STD_LOGIC;
nSCSI_ACK : OUT STD_LOGIC;
nSCSI_ATN : OUT STD_LOGIC;
SCSI_DIR : OUT STD_LOGIC;
SD_CLK : OUT STD_LOGIC;
YM_QA : OUT STD_LOGIC;
YM_QC : OUT STD_LOGIC;
YM_QB : OUT STD_LOGIC;
nSDSEL : OUT STD_LOGIC;
STEP : OUT STD_LOGIC;
MOT_ON : OUT STD_LOGIC;
nRP_LDS : OUT STD_LOGIC;
nRP_UDS : OUT STD_LOGIC;
nROM4 : OUT STD_LOGIC;
nROM3 : OUT STD_LOGIC;
nCF_CS1 : OUT STD_LOGIC;
nCF_CS0 : OUT STD_LOGIC;
nIDE_RD : INOUT STD_LOGIC;
nIDE_WR : INOUT STD_LOGIC;
AMKB_TX : OUT STD_LOGIC;
IDE_RES : OUT STD_LOGIC;
DTR : OUT STD_LOGIC;
RTS : OUT STD_LOGIC;
TxD : OUT STD_LOGIC;
MIDI_OLR : OUT STD_LOGIC;
MIDI_TLR : OUT STD_LOGIC;
nDREQ0 : OUT STD_LOGIC;
DSA_D : OUT STD_LOGIC;
nMFP_INT : OUT STD_LOGIC;
FALCON_IO_TA : OUT STD_LOGIC;
STEP_DIR : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC;
WR_GATE : OUT STD_LOGIC;
DMA_DRQ : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_PAR : INOUT STD_LOGIC;
nSCSI_SEL : INOUT STD_LOGIC;
nSCSI_BUSY : INOUT STD_LOGIC;
nSCSI_RST : INOUT STD_LOGIC;
SD_CD_DATA3 : INOUT STD_LOGIC;
SD_CDM_D1 : INOUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END FalconIO_SDCard_IDE_CF;
-- Architecture Body
ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
-- system
signal SYS_CLK : STD_LOGIC;
signal RESETn : STD_LOGIC;
signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS
signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS
signal BYT : STD_LOGIC; -- WENN BYT -> 1
signal LONG : STD_LOGIC; -- WENN -> 1
-- KEYBOARD MIDI
signal ACIA_CS_I : STD_LOGIC;
signal IRQ_KEYBDn : STD_LOGIC;
signal IRQ_MIDIn : STD_LOGIC;
signal KEYB_RxD : STD_LOGIC;
signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0);
signal MIDI_OUT : STD_LOGIC;
signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0);
signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0);
-- MFP
signal MFP_CS : STD_LOGIC;
signal MFP_INTACK : STD_LOGIC;
signal LDS : STD_LOGIC;
signal DTACK_OUT_MFPn : STD_LOGIC;
signal IRQ_ACIAn : STD_LOGIC;
signal DINTn : STD_LOGIC;
signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0);
signal TDO : STD_LOGIC;
-- SOUND
signal SNDCS : STD_LOGIC;
signal SNDCS_I : STD_LOGIC;
signal SNDIR_I : STD_LOGIC;
signal LP_DIR_X : STD_LOGIC;
signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0);
signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0);
-- DIV
signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE
signal ROM_CS : STD_LOGIC;
-- DMA UND FLOPPY
signal DMA_DATEN_CS : STD_LOGIC;
signal DMA_MODUS_CS : STD_LOGIC;
signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0);
signal WDC_BSL_CS : STD_LOGIC;
signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal HD_DD_OUT : STD_LOGIC;
signal FDCS_In : STD_LOGIC;
signal CA0 : STD_LOGIC;
signal CA1 : STD_LOGIC;
signal CA2 : STD_LOGIC;
signal FDINT : STD_LOGIC;
signal FDRQ : STD_LOGIC;
signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0);
signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_TOP_CS : STD_LOGIC;
signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_HIGH_CS : STD_LOGIC;
signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_MID_CS : STD_LOGIC;
signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_LOW_CS : STD_LOGIC;
signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0);
signal DMA_DIRM_CS : STD_LOGIC;
signal DMA_ADR_CS : STD_LOGIC;
signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0);
signal DMA_DIR_OLD : STD_LOGIC;
signal DMA_BYT_CNT_CS : STD_LOGIC;
signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0);
signal CLR_FIFO : STD_LOGIC;
signal DMA_DRQ_I : STD_LOGIC;
signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0);
signal DMA_DRQQ : STD_LOGIC;
signal DMA_DRQ_Q : STD_LOGIC;
signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0);
signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0);
signal RDF_RDE : STD_LOGIC;
signal RDF_WRE : STD_LOGIC;
signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0);
signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0);
signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0);
signal WRF_RDE : STD_LOGIC;
signal WRF_WRE : STD_LOGIC;
signal nFDC_WR : STD_LOGIC;
type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
signal FCF_STATE : FCF_STATES;
signal NEXT_FCF_STATE : FCF_STATES;
signal DMA_REQ : STD_LOGIC;
signal FDC_CS : STD_LOGIC;
signal FCF_CS : STD_LOGIC;
signal FCF_APH : STD_LOGIC;
signal DMA_AZ_CS : STD_LOGIC;
signal DMA_ACTIV : STD_LOGIC;
signal DMA_ACTIV_NEW : STD_LOGIC;
signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0);
-- SCSI
signal SCSI_CS : STD_LOGIC;
signal SCSI_CSn : STD_LOGIC;
signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0);
signal nSCSI_DACK : STD_LOGIC;
signal SCSI_DRQ : STD_LOGIC;
signal SCSI_INT : STD_LOGIC;
signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0);
signal DB_EN : STD_LOGIC;
signal DBP_OUTn : STD_LOGIC;
signal DBP_EN : STD_LOGIC;
signal RST_OUTn : STD_LOGIC;
signal RST_EN : STD_LOGIC;
signal BSY_OUTn : STD_LOGIC;
signal BSY_EN : STD_LOGIC;
signal SEL_OUTn : STD_LOGIC;
signal SEL_EN : STD_LOGIC;
-- IDE
signal nnIDE_RES : STD_LOGIC;
signal IDE_CF_CS : STD_LOGIC;
signal IDE_CF_TA : STD_LOGIC;
signal NEXT_nIDE_RD : STD_LOGIC;
signal NEXT_nIDE_WR : STD_LOGIC;
type CMD_STATES is( IDLE, T1, T6, T7);
signal CMD_STATE : CMD_STATES;
signal NEXT_CMD_STATE : CMD_STATES;
BEGIN
LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
'1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
'1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1';
nDREQ0 <= '0';
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
SD_CLK <= 'Z';
SD_CD_DATA3 <= 'Z';
SD_CDM_D1 <= 'Z';
----------------------------------------------------------------------------
-- IDE
----------------------------------------------------------------------------
CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
begin
if nRSTO = '0' then
CMD_STATE <= IDLE;
elsif rising_edge(MAIN_CLK) then
CMD_STATE <= NEXT_CMD_STATE; -- go to next
nIDE_RD <= NEXT_nIDE_RD; -- go to next
nIDE_WR <= NEXT_nIDE_WR; -- go to next
else
CMD_STATE <= CMD_STATE; -- halten
nIDE_RD <= nIDE_RD; -- halten
nIDE_WR <= nIDE_WR; -- halten
end if;
end process CMD_REG;
CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
begin
case CMD_STATE is
when IDLE =>
IDE_CF_TA <= '0';
if IDE_CF_CS = '1' then
NEXT_nIDE_RD <= not nFB_WR;
NEXT_nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T1;
else
NEXT_nIDE_RD <= '1';
NEXT_nIDE_WR <= '1';
NEXT_CMD_STATE <= IDLE;
end if;
when T1 =>
IDE_CF_TA <= '0';
NEXT_nIDE_RD <= not nFB_WR;
NEXT_nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T6;
when T6 =>
IF IDE_RDY = '1' then
IDE_CF_TA <= '1';
NEXT_nIDE_RD <= '1';
NEXT_nIDE_WR <= '1';
NEXT_CMD_STATE <= T7;
else
IDE_CF_TA <= '0';
NEXT_nIDE_RD <= not nFB_WR;
NEXT_nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T6;
end if;
when T7 =>
IDE_CF_TA <= '0';
NEXT_nIDE_RD <= '1';
NEXT_nIDE_WR <= '1';
NEXT_CMD_STATE <= IDLE;
end case;
end process CMD_DECODER;
IDE_RES <= not nnIDE_RES and nRSTO;
IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80
nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F
'0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F
nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F
'0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F
nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F
'0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F
nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F
'0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F
-----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772
-------------------------------------------------------------------------------------------------------------------------------------------
-- daten read fifo
RDF: dcfifo0
port map(
aclr => CLR_FIFO,
data => RDF_DIN,
rdclk => MAIN_CLK,
rdreq => RDF_RDE,
wrclk => FDC_CLK,
wrreq => RDF_WRE,
q => RDF_DOUT,
wrusedw => RDF_AZ
);
FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY
FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
-- daten write fifo
WRF: dcfifo1
port map(
aclr => CLR_FIFO,
data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
rdclk => FDC_CLK,
rdreq => WRF_RDE,
wrclk => MAIN_CLK,
wrreq => WRF_WRE,
q => WRF_DOUT,
rdusedw => WRF_AZ
);
CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
-- FIFO WRITE: GENAU 1 MAIN_CLK -------------------------------------------------------------------------
process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
begin
if nRSTO = '0' THEN
WRF_WRE <= '0';
elsif rising_edge(MAIN_CLK) then
IF FCF_APH = '1' and nFB_WR = '0' then
WRF_WRE <= '1';
else
WRF_WRE <= '0';
end if;
else
WRF_WRE <= WRF_WRE;
end if;
END PROCESS;
FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
begin
if nRSTO = '0' then
FCF_STATE <= FCF_IDLE;
DMA_ACTIV <= '0';
elsif rising_edge(FDC_CLK) then
FCF_STATE <= NEXT_FCF_STATE; -- go to next
DMA_ACTIV <= DMA_ACTIV_NEW;
else
FCF_STATE <= FCF_STATE; -- halten
DMA_ACTIV <= DMA_ACTIV;
end if;
end process FCF_REG;
FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
begin
if nRSTO = '0' then
FDC_OUT <= x"00";
elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
FDC_OUT <= CD_OUT_FDC; -- set
else
FDC_OUT <= FDC_OUT; -- halten
end if;
end process FDC_REG;
DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
begin
case FCF_STATE is
when FCF_IDLE =>
SCSI_CSn <= '1';
FDCS_In <= '1';
RDF_WRE <= '0';
WRF_RDE <= '0';
nSCSI_DACK <= '1';
if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then
DMA_ACTIV_NEW <= DMA_REQ;
NEXT_FCF_STATE <= FCF_T0;
else
DMA_ACTIV_NEW <= '0';
NEXT_FCF_STATE <= FCF_IDLE;
end if;
when FCF_T0 =>
SCSI_CSn <= '1';
FDCS_In <= '1';
RDF_WRE <= '0';
nSCSI_DACK <= '1';
DMA_ACTIV_NEW <= DMA_REQ;
WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO
if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike?
NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start
else
NEXT_FCF_STATE <= FCF_T1;
end if;
when FCF_T1 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T2;
when FCF_T2 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T3;
when FCF_T3 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T6;
when FCF_T6 =>
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO
NEXT_FCF_STATE <= FCF_T7;
when FCF_T7 =>
SCSI_CSn <= '1';
FDCS_In <= '1';
RDF_WRE <= '0';
WRF_RDE <= '0';
nSCSI_DACK <= '1';
DMA_ACTIV_NEW <= '0';
if FDC_CS = '1' and DMA_REQ = '0' then
NEXT_FCF_STATE <= FCF_T7;
else
NEXT_FCF_STATE <= FCF_IDLE;
end if;
end case;
end process FCF_DECODER;
I_FDC: WF1772IP_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
CSn => FDCS_In,
RWn => nFDC_WR,
A1 => CA2,
A0 => CA1,
DATA_IN => CD_IN_FDC,
DATA_OUT => CD_OUT_FDC,
-- DATA_EN => CD_EN_FDC,
RDn => nRD_DATA,
TR00n => TRACK00,
IPn => nINDEX,
WPRTn => nWP,
DDEn => '0', -- Fixed to MFM.
HDTYPE => HD_DD_OUT,
MO => MOT_ON,
WG => WR_GATE,
WD => WR_DATA,
STEP => STEP,
DIRC => STEP_DIR,
DRQ => DMA_DRQ_I,
INTRQ => FDINT
);
DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2
DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2
WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2
HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else
DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
--- WDC BSL REGISTER -------------------------------------------------------
process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
begin
if nRSTO = '0' THEN
WDC_BSL <= "00";
elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
IF FB_B0 = '1' THEN
WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
else
WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
end if;
end if;
END PROCESS;
--- DMA MODUS REGISTER -------------------------------------------------------
process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
begin
if nRSTO = '0' THEN
DMA_MODUS <= x"0000";
elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
IF FB_B0 = '1' THEN
DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
else
DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
end if;
IF FB_B1 = '1' THEN
DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
else
DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
end if;
else
DMA_MODUS <= DMA_MODUS;
end if;
END PROCESS;
-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
begin
if nRSTO = '0' or CLR_FIFO = '1' THEN
DMA_BYT_CNT <= x"00000000";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
DMA_BYT_CNT(31 downto 17) <= "000000000000000";
DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
DMA_BYT_CNT(8 downto 0) <= "000000000";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
DMA_BYT_CNT <= FB_AD;
else
DMA_BYT_CNT <= DMA_BYT_CNT;
end if;
END PROCESS;
--------------------------------------------------------------------
FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
DMA_STATUS(0) <= '1'; -- DMA OK
DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0';
DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else
'1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------
process(FDC_CLK, nRSTO, DMA_DRQ_REG)
begin
if nRSTO = '0' THEN
DMA_DRQ_REG <= "00";
elsif rising_edge(FDC_CLK) then
DMA_DRQ_REG(0) <= DMA_DRQQ;
DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
else
DMA_DRQ_REG <= DMA_DRQ_REG;
end if;
END PROCESS;
-- DMA ADRESSE ------------------------------------------------------
process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
begin
if nRSTO = '0' THEN
DMA_TOP <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
DMA_TOP <= FB_AD(31 downto 24);
else
DMA_TOP <= DMA_TOP;
end if;
END PROCESS;
process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
begin
if nRSTO = '0' THEN
DMA_HIGH <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
DMA_HIGH <= FB_AD(23 downto 16);
else
DMA_HIGH <= DMA_HIGH;
end if;
END PROCESS;
process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
begin
DMA_MID <= DMA_MID;
if nRSTO = '0' THEN
DMA_MID <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
if DMA_MID_CS = '1' then
DMA_MID <= FB_AD(23 downto 16);
elsif DMA_ADR_CS = '1' then
DMA_MID <= FB_AD(15 downto 8);
end if;
end if;
END PROCESS;
process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
begin
DMA_LOW <= DMA_LOW;
if nRSTO = '0' THEN
DMA_LOW <= x"00";
elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
if DMA_LOW_CS = '1'then
DMA_LOW <= FB_AD(23 downto 16);
elsif DMA_ADR_CS = '1' then
DMA_LOW <= FB_AD(7 downto 0);
end if;
end if;
END PROCESS;
--------------------------------------------------------------------------------------------
DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2
DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2
DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2
DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2
FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-- DIRECTZUGRIFF
DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG
DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- DMA RW TOGGLE ------------------------------------------
process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
begin
if nRSTO = '0' THEN
DMA_DIR_OLD <= '0';
elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then
DMA_DIR_OLD <= DMA_MODUS(8);
else
DMA_DIR_OLD <= DMA_DIR_OLD;
end if;
END PROCESS;
CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
-- SCSI ----------------------------------------------------------------------------------
I_SCSI: WF5380_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
ADR => CA2 & CA1 & CA0,
DATA_IN => CD_IN_FDC,
DATA_OUT => SCSI_DOUT,
--DATA_EN : out bit;
-- Bus and DMA controls:
CSn => '1', --SCSI_CSn, ABGESCHALTET
RDn => (not nFDC_WR) or (not SCSI_CS),
WRn => nFDC_WR or (not SCSI_CS),
EOPn => '1',
DACKn => nSCSI_DACK,
DRQ => SCSI_DRQ,
INT => SCSI_INT,
-- READY =>
-- SCSI bus:
DB_INn => SCSI_D,
DB_OUTn => DB_OUTn,
DB_EN => DB_EN,
DBP_INn => SCSI_PAR,
DBP_OUTn => DBP_OUTn,
DBP_EN => DBP_EN, -- wenn 1 dann output
RST_INn => nSCSI_RST,
RST_OUTn => RST_OUTn,
RST_EN => RST_EN,
BSY_INn => nSCSI_BUSY,
BSY_OUTn => BSY_OUTn,
BSY_EN => BSY_EN,
SEL_INn => nSCSI_SEL,
SEL_OUTn => SEL_OUTn,
SEL_EN => SEL_EN,
ACK_INn => '1',
ACK_OUTn => nSCSI_ACK,
-- ACK_EN => ACK_EN,
ATN_INn => '1',
ATN_OUTn => nSCSI_ATN,
-- ATN_EN => ATN_EN,
REQ_INn => nSCSI_DRQ,
-- REQ_OUTn => REQ_OUTn,
-- REQ_EN => REQ_EN,
IOn_IN => nSCSI_I_O,
-- IOn_OUT => IOn_OUT,
-- IO_EN => IO_EN,
CDn_IN => nSCSI_C_D,
-- CDn_OUT => CDn_OUT,
-- CD_EN => CD_EN,
MSG_INn => nSCSI_MSG
-- MSG_OUTn => MSG_OUTn,
-- MSG_EN => MSG_EN
);
-- SCSI ACSI ---------------------------------------------------------------
SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET
SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
ACSI_DIR <= '0';
ACSI_D <= "ZZZZZZZZ";
nACSI_CS <= '1';
ACSI_A1 <= CA1;
nACSI_RESET <= nRSTO;
nACSI_ACK <= '1';
----------------------------------------------------------------------------
-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
----------------------------------------------------------------------------
ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000
nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
----------------------------------------------------------------------------
-- ACIA KEYBOARD
----------------------------------------------------------------------------
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
CS2n => FB_ADR(2),
CS1 => '1',
CS0 => ACIA_CS_I,
E => ACIA_CS_I,
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_OUT => DATA_OUT_ACIA_I,
-- DATA_EN => DATA_EN_ACIA_I,
TXCLK => CLK500k,
RXCLK => CLK500k,
RXDATA => KEYB_RxD,
CTSn => '0',
DCDn => '0',
IRQn => IRQ_KEYBDn,
TXDATA => AMKB_TX
--RTSn => -- Not used.
);
ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8
KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------
process(CLK2M, AMKB_RX, AMKB_REG)
begin
if rising_edge(CLK2M) then
IF AMKB_RX = '0' THEN
IF AMKB_REG < 16 THEN
AMKB_REG <= "00000";
ELSE
AMKB_REG <= AMKB_REG - 1;
END IF;
ELSE
IF AMKB_REG > 15 THEN
AMKB_REG <= "11111";
ELSE
AMKB_REG <= AMKB_REG + 1;
END IF;
END IF;
ELSE
AMKB_REG <= AMKB_REG;
end if;
END PROCESS;
----------------------------------------------------------------------------
-- ACIA MIDI
----------------------------------------------------------------------------
I_ACIA_MIDI: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
CS2n => '0',
CS1 => FB_ADR(2),
CS0 => ACIA_CS_I,
E => ACIA_CS_I,
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_OUT => DATA_OUT_ACIA_II,
-- DATA_EN => DATA_EN_ACIA_II,
TXCLK => CLK500k,
RXCLK => CLK500k,
RXDATA => MIDI_IN,
CTSn => '0',
DCDn => '0',
IRQn => IRQ_MIDIn,
TXDATA => MIDI_OUT
--RTSn => -- Not used.
);
MIDI_TLR <= MIDI_OUT;
MIDI_OLR <= MIDI_OUT;
FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
----------------------------------------------------------------------------
-- MFP
----------------------------------------------------------------------------
I_MFP: WF68901IP_TOP_SOC
port map(
-- System control:
CLK => MAIN_CLK,
RESETn => nRSTO,
-- Asynchronous bus control:
DSn => not LDS,
CSn => not MFP_CS,
RWn => nFB_WR,
DTACKn => DTACK_OUT_MFPn,
-- Data and Adresses:
RS => FB_ADR(5 downto 1),
DATA_IN => FB_AD(23 downto 16),
DATA_OUT => DATA_OUT_MFP,
-- DATA_EN => DATA_EN_MFP,
GPIP_IN(7) => not DMA_DRQ_Q,
GPIP_IN(6) => not RI,
GPIP_IN(5) => DINTn,
GPIP_IN(4) => IRQ_ACIAn,
GPIP_IN(3) => DSP_INT,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY,
-- GPIP_OUT =>, -- Not used; all GPIPs are direction input.
-- GPIP_EN =>, -- Not used; all GPIPs are direction input.
-- Interrupt control:
IACKn => not MFP_INTACK,
IEIn => '0',
-- IEOn =>, -- Not used.
IRQn => nMFP_INT,
-- Timers and timer control:
XTAL1 => CLK2M4576,
TAI => '0',
TBI => nBLANK,
-- TAO =>,
-- TBO =>,
-- TCO =>,
TDO => TDO,
-- Serial I/O control:
RC => TDO,
TC => TDO,
SI => RxD,
SO => TxD
-- SO_EN => MFP_SO_EN
-- DMA control:
-- RRn =>,
-- TRn =>
);
MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40
MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000
LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
'0' when FDINT = '1' else
'0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1';
-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------
process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
begin
if nRSTO = '0' THEN
IRQ_ACIAn <= '1';
elsif rising_edge(MAIN_CLK) then
IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
else
IRQ_ACIAn <= IRQ_ACIAn;
end if;
END PROCESS;
----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
I_SOUND: WF2149IP_TOP_SOC
port map(
SYS_CLK => MAIN_CLK,
RESETn => nRSTO,
WAV_CLK => CLK2M,
SELn => '1',
BDIR => SNDIR_I,
BC2 => '1',
BC1 => SNDCS_I,
A9n => '0',
A8 => '1',
DA_IN => FB_AD(31 downto 24),
DA_OUT => DA_OUT_X,
IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => LP_STR,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
IO_A_OUT(1) => DSA_D,
IO_A_OUT(0) => nSDSEL,
-- IO_A_EN =>, -- Not required.
IO_B_IN => LP_D,
IO_B_OUT => LP_D_X,
-- IO_B_EN => IO_B_EN,
OUT_A => YM_QA,
OUT_B => YM_QB,
OUT_C => YM_QC
);
SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4
SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;
END FalconIO_SDCard_IDE_CF_architecture;

406
BaS_GNU/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd Normal file
View File

@@ -0,0 +1,406 @@
----------------------------------------------------------------------
---- ----
---- Atari Coldfire IP Core ----
---- ----
---- This file is part of the Atari Coldfire project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- ----
---- ----
---- ----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
-- 1.0 Initial Release, 20090925.
--
library ieee;
use ieee.std_logic_1164.all;
package FalconIO_SDCard_IDE_CF_PKG is
component WF25915IP_TOP_V1_SOC -- GLUE.
port (
-- Clock system:
GL_CLK : in std_logic; -- Originally 8MHz.
GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK.
-- Core address select:
GL_ROMSEL_FC_E0n : in std_logic;
EN_RAM_14MB : in std_logic;
-- Adress decoder outputs:
GL_ROM_6n : out std_logic; -- STE.
GL_ROM_5n : out std_logic; -- STE.
GL_ROM_4n : out std_logic; -- ST.
GL_ROM_3n : out std_logic; -- ST.
GL_ROM_2n : out std_logic;
GL_ROM_1n : out std_logic;
GL_ROM_0n : out std_logic;
GL_ACIACS : out std_logic;
GL_MFPCSn : out std_logic;
GL_SNDCSn : out std_logic;
GL_FCSn : out std_logic;
GL_STE_SNDCS : out std_logic; -- STE: Sound chip select.
GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control.
GL_STE_RTCCSn : out std_logic; --STE only.
GL_STE_RTC_WRn : out std_logic; --STE only.
GL_STE_RTC_RDn : out std_logic; --STE only.
-- 6800 peripheral control,
GL_VPAn : out std_logic;
GL_VMAn : in std_logic;
GL_DMA_SYNC : in std_logic;
GL_DEVn : out std_logic;
GL_RAMn : out std_logic;
GL_DMAn : out std_logic;
-- Interrupt system:
-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
GL_AVECn : out std_logic;
GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only.
GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only.
GL_MFPINTn : in std_logic; -- ST.
GL_STE_EINT3n : in std_logic; --STE only.
GL_STE_EINT5n : in std_logic; --STE only.
GL_STE_EINT7n : in std_logic; --STE only.
GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only.
GL_IACKn : out std_logic; -- ST.
GL_STE_IPL2n : out std_logic; --STE only.
GL_STE_IPL1n : out std_logic; --STE only.
GL_STE_IPL0n : out std_logic; --STE only.
-- Video timing:
GL_BLANKn : out std_logic;
GL_DE : out std_logic;
GL_MULTISYNC : in std_logic_vector(3 downto 2);
GL_VIDEO_HIMODE : out std_logic;
GL_HSYNC_INn : in std_logic;
GL_HSYNC_OUTn : out std_logic;
GL_VSYNC_INn : in std_logic;
GL_VSYNC_OUTn : out std_logic;
GL_SYNC_OUT_EN : out std_logic;
-- Bus arstd_logicration control:
GL_RDY_INn : in std_logic;
GL_RDY_OUTn : out std_logic;
GL_BRn : out std_logic;
GL_BGIn : in std_logic;
GL_BGOn : out std_logic;
GL_BGACK_INn : in std_logic;
GL_BGACK_OUTn : out std_logic;
-- Adress and data bus:
GL_ADDRESS : in std_logic_vector(23 downto 1);
-- ST: put the data bus to 1 downto 0.
-- STE: put the data out bus to 15 downto 0.
GL_DATA_IN : in std_logic_vector(7 downto 0);
GL_DATA_OUT : out std_logic_vector(15 downto 0);
GL_DATA_EN : out std_logic;
-- Asynchronous bus control:
GL_RWn_IN : in std_logic;
GL_RWn_OUT : out std_logic;
GL_AS_INn : in std_logic;
GL_AS_OUTn : out std_logic;
GL_UDS_INn : in std_logic;
GL_UDS_OUTn : out std_logic;
GL_LDS_INn : in std_logic;
GL_LDS_OUTn : out std_logic;
GL_DTACK_INn : in std_logic;
GL_DTACK_OUTn : out std_logic;
GL_CTRL_EN : out std_logic;
-- System control:
GL_RESETn : in std_logic;
GL_BERRn : out std_logic;
-- Processor function codes:
GL_FC : in std_logic_vector(2 downto 0);
-- STE enhancements:
GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD).
GL_STE_FCCLK : out std_logic; -- Floppy controller clock select.
GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte.
GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte.
GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte.
GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable.
GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte.
GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X.
GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y.
GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X.
GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y.
GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset.
GL_STE_PENn : in std_logic; -- Input of the light pen.
GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip.
GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor.
);
end component WF25915IP_TOP_V1_SOC;
component WF5380_TOP_SOC
port (
CLK : in std_logic;
RESETn : in std_logic;
ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
EOPn : in std_logic;
DACKn : in std_logic;
DRQ : out std_logic;
INT : out std_logic;
READY : out std_logic;
DB_INn : in std_logic_vector(7 downto 0);
DB_OUTn : out std_logic_vector(7 downto 0);
DB_EN : out std_logic;
DBP_INn : in std_logic;
DBP_OUTn : out std_logic;
DBP_EN : out std_logic;
RST_INn : in std_logic;
RST_OUTn : out std_logic;
RST_EN : out std_logic;
BSY_INn : in std_logic;
BSY_OUTn : out std_logic;
BSY_EN : out std_logic;
SEL_INn : in std_logic;
SEL_OUTn : out std_logic;
SEL_EN : out std_logic;
ACK_INn : in std_logic;
ACK_OUTn : out std_logic;
ACK_EN : out std_logic;
ATN_INn : in std_logic;
ATN_OUTn : out std_logic;
ATN_EN : out std_logic;
REQ_INn : in std_logic;
REQ_OUTn : out std_logic;
REQ_EN : out std_logic;
IOn_IN : in std_logic;
IOn_OUT : out std_logic;
IO_EN : out std_logic;
CDn_IN : in std_logic;
CDn_OUT : out std_logic;
CD_EN : out std_logic;
MSG_INn : in std_logic;
MSG_OUTn : out std_logic;
MSG_EN : out std_logic
);
end component WF5380_TOP_SOC;
component WF1772IP_TOP_SOC -- FDC.
port (
CLK : in std_logic; -- 16MHz clock!
RESETn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks.
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end component WF1772IP_TOP_SOC;
component WF68901IP_TOP_SOC -- MFP.
port ( -- System control:
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
-- Data and Adresses:
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_EN : out std_logic_vector(7 downto 0);
-- Interrupt control:
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Timers and timer control:
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
-- Serial I/O control:
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
-- DMA control:
RRn : out std_logic;
TRn : out std_logic
);
end component WF68901IP_TOP_SOC;
component WF2149IP_TOP_SOC -- Sound.
port(
SYS_CLK : in std_logic; -- Read the inforation in the header!
RESETn : in std_logic;
WAV_CLK : in std_logic; -- Read the inforation in the header!
SELn : in std_logic;
BDIR : in std_logic;
BC2, BC1 : in std_logic;
A9n, A8 : in std_logic;
DA_IN : in std_logic_vector(7 downto 0);
DA_OUT : out std_logic_vector(7 downto 0);
DA_EN : out std_logic;
IO_A_IN : in std_logic_vector(7 downto 0);
IO_A_OUT : out std_logic_vector(7 downto 0);
IO_A_EN : out std_logic;
IO_B_IN : in std_logic_vector(7 downto 0);
IO_B_OUT : out std_logic_vector(7 downto 0);
IO_B_EN : out std_logic;
OUT_A : out std_logic; -- Analog (PWM) outputs.
OUT_B : out std_logic;
OUT_C : out std_logic
);
end component WF2149IP_TOP_SOC;
component WF6850IP_TOP_SOC -- ACIA.
port (
CLK : in std_logic;
RESETn : in std_logic;
CS2n, CS1, CS0 : in std_logic;
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
TXCLK : in std_logic;
RXCLK : in std_logic;
RXDATA : in std_logic;
CTSn : in std_logic;
DCDn : in std_logic;
IRQn : out std_logic;
TXDATA : out std_logic;
RTSn : out std_logic
);
end component WF6850IP_TOP_SOC;
component WF_SD_CARD
port (
RESETn : in std_logic;
CLK : in std_logic;
ACSI_A1 : in std_logic;
ACSI_CSn : in std_logic;
ACSI_ACKn : in std_logic;
ACSI_INTn : out std_logic;
ACSI_DRQn : out std_logic;
ACSI_D_IN : in std_logic_vector(7 downto 0);
ACSI_D_OUT : out std_logic_vector(7 downto 0);
ACSI_D_EN : out std_logic;
MC_DO : in std_logic;
MC_PIO_DMAn : in std_logic;
MC_RWn : in std_logic;
MC_CLR_CMD : in std_logic;
MC_DONE : out std_logic;
MC_GOT_CMD : out std_logic;
MC_D_IN : in std_logic_vector(7 downto 0);
MC_D_OUT : out std_logic_vector(7 downto 0);
MC_D_EN : out std_logic
);
end component WF_SD_CARD;
component dcfifo0
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component dcfifo0;
component dcfifo1
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
end FalconIO_SDCard_IDE_CF_PKG;

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----------------------------------------------------------------------
---- ----
---- Atari Coldfire IP Core ----
---- ----
---- This file is part of the Atari Coldfire project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- ----
---- ----
---- ----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
-- 1.0 Initial Release, 20090925.
--
library ieee;
use ieee.std_logic_1164.all;
package FalconIO_SDCard_IDE_CF_PKG is
component WF25915IP_TOP_V1_SOC -- GLUE.
port (
-- Clock system:
GL_CLK : in std_logic; -- Originally 8MHz.
GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK.
-- Core address select:
GL_ROMSEL_FC_E0n : in std_logic;
EN_RAM_14MB : in std_logic;
-- Adress decoder outputs:
GL_ROM_6n : out std_logic; -- STE.
GL_ROM_5n : out std_logic; -- STE.
GL_ROM_4n : out std_logic; -- ST.
GL_ROM_3n : out std_logic; -- ST.
GL_ROM_2n : out std_logic;
GL_ROM_1n : out std_logic;
GL_ROM_0n : out std_logic;
GL_ACIACS : out std_logic;
GL_MFPCSn : out std_logic;
GL_SNDCSn : out std_logic;
GL_FCSn : out std_logic;
GL_STE_SNDCS : out std_logic; -- STE: Sound chip select.
GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control.
GL_STE_RTCCSn : out std_logic; --STE only.
GL_STE_RTC_WRn : out std_logic; --STE only.
GL_STE_RTC_RDn : out std_logic; --STE only.
-- 6800 peripheral control,
GL_VPAn : out std_logic;
GL_VMAn : in std_logic;
GL_DMA_SYNC : in std_logic;
GL_DEVn : out std_logic;
GL_RAMn : out std_logic;
GL_DMAn : out std_logic;
-- Interrupt system:
-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
GL_AVECn : out std_logic;
GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only.
GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only.
GL_MFPINTn : in std_logic; -- ST.
GL_STE_EINT3n : in std_logic; --STE only.
GL_STE_EINT5n : in std_logic; --STE only.
GL_STE_EINT7n : in std_logic; --STE only.
GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only.
GL_IACKn : out std_logic; -- ST.
GL_STE_IPL2n : out std_logic; --STE only.
GL_STE_IPL1n : out std_logic; --STE only.
GL_STE_IPL0n : out std_logic; --STE only.
-- Video timing:
GL_BLANKn : out std_logic;
GL_DE : out std_logic;
GL_MULTISYNC : in std_logic_vector(3 downto 2);
GL_VIDEO_HIMODE : out std_logic;
GL_HSYNC_INn : in std_logic;
GL_HSYNC_OUTn : out std_logic;
GL_VSYNC_INn : in std_logic;
GL_VSYNC_OUTn : out std_logic;
GL_SYNC_OUT_EN : out std_logic;
-- Bus arstd_logicration control:
GL_RDY_INn : in std_logic;
GL_RDY_OUTn : out std_logic;
GL_BRn : out std_logic;
GL_BGIn : in std_logic;
GL_BGOn : out std_logic;
GL_BGACK_INn : in std_logic;
GL_BGACK_OUTn : out std_logic;
-- Adress and data bus:
GL_ADDRESS : in std_logic_vector(23 downto 1);
-- ST: put the data bus to 1 downto 0.
-- STE: put the data out bus to 15 downto 0.
GL_DATA_IN : in std_logic_vector(7 downto 0);
GL_DATA_OUT : out std_logic_vector(15 downto 0);
GL_DATA_EN : out std_logic;
-- Asynchronous bus control:
GL_RWn_IN : in std_logic;
GL_RWn_OUT : out std_logic;
GL_AS_INn : in std_logic;
GL_AS_OUTn : out std_logic;
GL_UDS_INn : in std_logic;
GL_UDS_OUTn : out std_logic;
GL_LDS_INn : in std_logic;
GL_LDS_OUTn : out std_logic;
GL_DTACK_INn : in std_logic;
GL_DTACK_OUTn : out std_logic;
GL_CTRL_EN : out std_logic;
-- System control:
GL_RESETn : in std_logic;
GL_BERRn : out std_logic;
-- Processor function codes:
GL_FC : in std_logic_vector(2 downto 0);
-- STE enhancements:
GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD).
GL_STE_FCCLK : out std_logic; -- Floppy controller clock select.
GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte.
GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte.
GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte.
GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable.
GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte.
GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X.
GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y.
GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X.
GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y.
GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset.
GL_STE_PENn : in std_logic; -- Input of the light pen.
GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip.
GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor.
);
end component WF25915IP_TOP_V1_SOC;
component WF5380_TOP_SOC
port (
CLK : in std_logic;
RESETn : in std_logic;
ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
EOPn : in std_logic;
DACKn : in std_logic;
DRQ : out std_logic;
INT : out std_logic;
READY : out std_logic;
DB_INn : in std_logic_vector(7 downto 0);
DB_OUTn : out std_logic_vector(7 downto 0);
DB_EN : out std_logic;
DBP_INn : in std_logic;
DBP_OUTn : out std_logic;
DBP_EN : out std_logic;
RST_INn : in std_logic;
RST_OUTn : out std_logic;
RST_EN : out std_logic;
BSY_INn : in std_logic;
BSY_OUTn : out std_logic;
BSY_EN : out std_logic;
SEL_INn : in std_logic;
SEL_OUTn : out std_logic;
SEL_EN : out std_logic;
ACK_INn : in std_logic;
ACK_OUTn : out std_logic;
ACK_EN : out std_logic;
ATN_INn : in std_logic;
ATN_OUTn : out std_logic;
ATN_EN : out std_logic;
REQ_INn : in std_logic;
REQ_OUTn : out std_logic;
REQ_EN : out std_logic;
IOn_IN : in std_logic;
IOn_OUT : out std_logic;
IO_EN : out std_logic;
CDn_IN : in std_logic;
CDn_OUT : out std_logic;
CD_EN : out std_logic;
MSG_INn : in std_logic;
MSG_OUTn : out std_logic;
MSG_EN : out std_logic
);
end component WF5380_TOP_SOC;
component WF1772IP_TOP_SOC -- FDC.
port (
CLK : in std_logic; -- 16MHz clock!
RESETn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks.
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end component WF1772IP_TOP_SOC;
component WF68901IP_TOP_SOC -- MFP.
port ( -- System control:
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
-- Data and Adresses:
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_EN : out std_logic_vector(7 downto 0);
-- Interrupt control:
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Timers and timer control:
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
-- Serial I/O control:
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
-- DMA control:
RRn : out std_logic;
TRn : out std_logic
);
end component WF68901IP_TOP_SOC;
component WF2149IP_TOP_SOC -- Sound.
port(
SYS_CLK : in std_logic; -- Read the inforation in the header!
RESETn : in std_logic;
WAV_CLK : in std_logic; -- Read the inforation in the header!
SELn : in std_logic;
BDIR : in std_logic;
BC2, BC1 : in std_logic;
A9n, A8 : in std_logic;
DA_IN : in std_logic_vector(7 downto 0);
DA_OUT : out std_logic_vector(7 downto 0);
DA_EN : out std_logic;
IO_A_IN : in std_logic_vector(7 downto 0);
IO_A_OUT : out std_logic_vector(7 downto 0);
IO_A_EN : out std_logic;
IO_B_IN : in std_logic_vector(7 downto 0);
IO_B_OUT : out std_logic_vector(7 downto 0);
IO_B_EN : out std_logic;
OUT_A : out std_logic; -- Analog (PWM) outputs.
OUT_B : out std_logic;
OUT_C : out std_logic
);
end component WF2149IP_TOP_SOC;
component WF6850IP_TOP_SOC -- ACIA.
port (
CLK : in std_logic;
RESETn : in std_logic;
CS2n, CS1, CS0 : in std_logic;
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
TXCLK : in std_logic;
RXCLK : in std_logic;
RXDATA : in std_logic;
CTSn : in std_logic;
DCDn : in std_logic;
IRQn : out std_logic;
TXDATA : out std_logic;
RTSn : out std_logic
);
end component WF6850IP_TOP_SOC;
component WF_SD_CARD
port (
RESETn : in std_logic;
CLK : in std_logic;
ACSI_A1 : in std_logic;
ACSI_CSn : in std_logic;
ACSI_ACKn : in std_logic;
ACSI_INTn : out std_logic;
ACSI_DRQn : out std_logic;
ACSI_D_IN : in std_logic_vector(7 downto 0);
ACSI_D_OUT : out std_logic_vector(7 downto 0);
ACSI_D_EN : out std_logic;
MC_DO : in std_logic;
MC_PIO_DMAn : in std_logic;
MC_RWn : in std_logic;
MC_CLR_CMD : in std_logic;
MC_DONE : out std_logic;
MC_GOT_CMD : out std_logic;
MC_D_IN : in std_logic_vector(7 downto 0);
MC_D_OUT : out std_logic_vector(7 downto 0);
MC_D_EN : out std_logic
);
end component WF_SD_CARD;
component dcfifo0
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component dcfifo0;
component dcfifo1
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;
end FalconIO_SDCard_IDE_CF_PKG;

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