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reenabled all modules

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This commit is contained in:
Markus Fröschle
2014-12-24 16:11:12 +00:00
parent e7e4fa4e75
commit 517599bc33
4 changed files with 166 additions and 166 deletions
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2
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -692,8 +692,8 @@ set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME firebee_tb -section_id fi
set_location_assignment PIN_T8 -to FB_CS_n[1] set_location_assignment PIN_T8 -to FB_CS_n[1]
set_location_assignment PIN_T9 -to FB_CS_n[2] set_location_assignment PIN_T9 -to FB_CS_n[2]
set_location_assignment PIN_V6 -to FB_CS_n[3] set_location_assignment PIN_V6 -to FB_CS_n[3]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id firebee_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id firebee_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

8
vhdl/rtl/vhdl/DSP/DSP.vhd
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@@ -31,7 +31,7 @@ ENTITY DSP IS
CLK_33M : in std_logic; CLK_33M : in std_logic;
CLK_MAIN : in std_logic; CLK_MAIN : in std_logic;
fb_oe_n : in std_logic; fb_oe_n : in std_logic;
FB_WRn : in std_logic; fb_wr_n : in std_logic;
FB_CS1n : in std_logic; FB_CS1n : in std_logic;
FB_CS2n : in std_logic; FB_CS2n : in std_logic;
FB_SIZE0 : in std_logic; FB_SIZE0 : in std_logic;
@@ -67,14 +67,14 @@ BEGIN
SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n; SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n;
SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1'; SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1';
SRBLEn <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; SRBLEn <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
SRWEn <= '0' when FB_WRn = '0' and SRCSn = '0' and CLK_MAIN = '0' else '1'; SRWEn <= '0' when fb_wr_n = '0' and SRCSn = '0' and CLK_MAIN = '0' else '1';
SROEn <= '0' when fb_oe_n = '0' and SRCSn = '0' else '1'; SROEn <= '0' when fb_oe_n = '0' and SRCSn = '0' else '1';
DSP_INT <= '0'; DSP_INT <= '0';
DSP_TA <= '0'; DSP_TA <= '0';
IO_OUT(17 downto 0) <= FB_ADR(18 downto 1); IO_OUT(17 downto 0) <= FB_ADR(18 downto 1);
IO_EN <= '1'; IO_EN <= '1';
SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when FB_WRn = '0' and SRCSn = '0' else x"0000"; SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when fb_wr_n = '0' and SRCSn = '0' else x"0000";
SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0'; SRD_EN <= '1' when fb_wr_n = '0' and SRCSn = '0' else '0';
FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000"; FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000";
FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000"; FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000";
FB_AD_EN <= '1' when fb_oe_n = '0' and SRCSn = '0' else '0'; FB_AD_EN <= '1' when fb_oe_n = '0' and SRCSn = '0' else '0';

298
vhdl/rtl/vhdl/Firebee/Firebee.vhd
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@@ -1046,37 +1046,37 @@ BEGIN
CF_CSn => CF_CSn CF_CSn => CF_CSn
); );
-- I_DSP: DSP I_DSP: DSP
-- PORT MAP( PORT MAP(
-- clk_33m => clk_33m, clk_33m => clk_33m,
-- clk_main => clk_main, clk_main => clk_main,
-- fb_oe_n => fb_oe_n, fb_oe_n => fb_oe_n,
-- fb_wr_n => fb_wr_n, fb_wr_n => fb_wr_n,
-- FB_CS1n => fb_cs_n(1), FB_CS1n => fb_cs_n(1),
-- FB_CS2n => fb_cs_n(2), FB_CS2n => fb_cs_n(2),
-- fb_size0 => fb_size(0), fb_size0 => fb_size(0),
-- fb_size1 => fb_size(1), fb_size1 => fb_size(1),
-- fb_burst_n => fb_burst_n, fb_burstn => fb_burst_n,
-- fb_adr => fb_adr, fb_adr => fb_adr,
-- resetn => reset_n, resetn => reset_n,
-- FB_CS3n => fb_cs_n(3), FB_CS3n => fb_cs_n(3),
-- SRCSn => DSP_SRCSn, SRCSn => DSP_SRCSn,
-- SRBLEn => DSP_SRBLEn, SRBLEn => DSP_SRBLEn,
-- SRBHEn => DSP_SRBHEn, SRBHEn => DSP_SRBHEn,
-- SRWEn => DSP_SRWEn, SRWEn => DSP_SRWEn,
-- SROEn => DSP_SROEn, SROEn => DSP_SROEn,
-- dsp_int => dsp_int, dsp_int => dsp_int,
-- dsp_ta => dsp_ta, dsp_ta => dsp_ta,
-- fb_ad_IN => fb_ad, fb_ad_IN => fb_ad,
-- fb_ad_OUT => fb_ad_out_dsp, fb_ad_OUT => fb_ad_out_dsp,
-- fb_ad_EN => fb_ad_en_dsp, fb_ad_EN => fb_ad_en_dsp,
-- IO_IN => DSP_IO, IO_IN => DSP_IO,
-- IO_OUT => dsp_io_out, IO_OUT => dsp_io_out,
-- IO_EN => dsp_io_en, IO_EN => dsp_io_en,
-- SRD_IN => DSP_SRD, SRD_IN => DSP_SRD,
-- SRD_OUT => dsp_srd_out, SRD_OUT => dsp_srd_out,
-- SRD_EN => dsp_srd_en SRD_EN => dsp_srd_en
-- ); );
I_SOUND: WF2149IP_TOP_SOC I_SOUND: WF2149IP_TOP_SOC
PORT MAP( PORT MAP(
@@ -1163,32 +1163,32 @@ BEGIN
-- TRn => -- Not used. -- TRn => -- Not used.
); );
-- I_ACIA_MIDI: WF6850IP_TOP_SOC I_ACIA_MIDI: WF6850IP_TOP_SOC
-- PORT MAP( PORT MAP(
-- clk => clk_main, clk => clk_main,
-- resetn => reset_n, resetn => reset_n,
--
-- CS2n => '0', CS2n => '0',
-- cs1 => fb_adr(2), cs1 => fb_adr(2),
-- cs0 => acia_cs, cs0 => acia_cs,
-- E => acia_cs, E => acia_cs,
-- RWn => fb_wr_n, RWn => fb_wr_n,
-- rs => fb_adr(1), rs => fb_adr(1),
--
-- data_in => fb_ad(31 DOWNTO 24), data_in => fb_ad(31 DOWNTO 24),
-- data_out => data_out_acia_iI, data_out => data_out_acia_iI,
-- -- DATA_EN => -- Not used. -- DATA_EN => -- Not used.
--
-- txclk => clk_500k, txclk => clk_500k,
-- rxclk => clk_500k, rxclk => clk_500k,
-- rxdata => midi_in, rxdata => midi_in,
-- CTSn => '0', CTSn => '0',
-- DCDn => '0', DCDn => '0',
--
-- irq_n => irq_midi_n, irq_n => irq_midi_n,
-- txdata => midi_out txdata => midi_out
-- --RTSn => -- Not used. --RTSn => -- Not used.
-- ); );
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
PORT MAP( PORT MAP(
@@ -1218,98 +1218,98 @@ BEGIN
--RTSn => -- Not used. --RTSn => -- Not used.
); );
-- I_SCSI: WF5380_TOP_SOC I_SCSI: WF5380_TOP_SOC
-- PORT MAP( PORT MAP(
-- clk => clk_fdc, clk => clk_fdc,
-- resetn => reset_n, resetn => reset_n,
-- ADR => ca, ADR => ca,
-- data_in => data_in_fdc_scsi, data_in => data_in_fdc_scsi,
-- data_out => data_out_scsi, data_out => data_out_scsi,
-- --DATA_EN =>, --DATA_EN =>,
-- -- Bus and DMA controls: -- Bus and DMA controls:
-- CSn => scsi_csn, CSn => scsi_csn,
-- RDn => NOT fdc_wr_n OR NOT scsi_cs, RDn => NOT fdc_wr_n OR NOT scsi_cs,
-- WRn => fdc_wr_n OR NOT scsi_cs, WRn => fdc_wr_n OR NOT scsi_cs,
-- EOPn => '1', EOPn => '1',
-- DACKn => scsi_dack_n, DACKn => scsi_dack_n,
-- DRQ => scsi_drq, DRQ => scsi_drq,
-- INT => scsi_int, INT => scsi_int,
-- -- READY =>, -- READY =>,
-- -- SCSI bus: -- SCSI bus:
-- DB_INn => SCSI_D, DB_INn => SCSI_D,
-- DB_OUTn => scsi_d_out_n, DB_OUTn => scsi_d_out_n,
-- DB_EN => scsi_d_en, DB_EN => scsi_d_en,
-- DBP_INn => SCSI_PAR, DBP_INn => SCSI_PAR,
-- DBP_OUTn => scsi_dbp_out_n, DBP_OUTn => scsi_dbp_out_n,
-- DBP_EN => scsi_dbp_en, -- wenn 1 dann OUTput DBP_EN => scsi_dbp_en, -- wenn 1 dann OUTput
-- RST_INn => SCSI_RSTn, RST_INn => SCSI_RSTn,
-- RST_OUTn => scsi_rst_out_n, RST_OUTn => scsi_rst_out_n,
-- RST_EN => scsi_rst_en, RST_EN => scsi_rst_en,
-- BSY_INn => SCSI_BUSYn, BSY_INn => SCSI_BUSYn,
-- BSY_OUTn => scsi_bsy_out_n, BSY_OUTn => scsi_bsy_out_n,
-- BSY_EN => scsi_bsy_en, BSY_EN => scsi_bsy_en,
-- SEL_INn => SCSI_SELn, SEL_INn => SCSI_SELn,
-- SEL_OUTn => scsi_sel_out_n, SEL_OUTn => scsi_sel_out_n,
-- SEL_EN => scsi_sel_en, SEL_EN => scsi_sel_en,
-- ACK_INn => '1', ACK_INn => '1',
-- ACK_OUTn => SCSI_ACKn, ACK_OUTn => SCSI_ACKn,
-- -- ACK_EN => ACK_EN, -- ACK_EN => ACK_EN,
-- ATN_INn => '1', ATN_INn => '1',
-- ATN_OUTn => SCSI_ATNn, ATN_OUTn => SCSI_ATNn,
-- -- ATN_EN => ATN_EN, -- ATN_EN => ATN_EN,
-- REQ_INn => scsi_drqn, REQ_INn => scsi_drqn,
-- -- REQ_OUTn => REQ_OUTn, -- REQ_OUTn => REQ_OUTn,
-- -- REQ_EN => REQ_EN, -- REQ_EN => REQ_EN,
-- IOn_IN => SCSI_IOn, IOn_IN => SCSI_IOn,
-- -- IOn_OUT => IOn_OUT, -- IOn_OUT => IOn_OUT,
-- -- IO_EN => IO_EN, -- IO_EN => IO_EN,
-- CDn_IN => SCSI_CDn, CDn_IN => SCSI_CDn,
-- -- CDn_OUT => CDn_OUT, -- CDn_OUT => CDn_OUT,
-- -- CD_EN => CD_EN, -- CD_EN => CD_EN,
-- MSG_INn => SCSI_MSGn MSG_INn => SCSI_MSGn
-- -- MSG_OUTn => MSG_OUTn, -- MSG_OUTn => MSG_OUTn,
-- -- MSG_EN => MSG_EN -- MSG_EN => MSG_EN
-- ); );
--
-- I_FDC: WF1772IP_TOP_SOC
-- PORT MAP(
-- clk => clk_fdc,
-- resetn => reset_n,
-- CSn => fdc_cs_n,
-- RWn => fdc_wr_n,
-- A1 => ca(2),
-- A0 => ca(1),
-- data_in => data_in_fdc_scsi,
-- data_out => data_out_fdc,
-- -- DATA_EN => CD_EN_FDC,
-- RDn => FDD_RDn,
-- TR00n => FDD_TRACK00,
-- IPn => FDD_INDEXn,
-- WPRTn => FDD_WPn,
-- DDEn => '0', -- Fixed to MFM.
-- HDTYPE => hd_dd_out,
-- MO => FDD_MOT_ON,
-- WG => FDD_WR_GATE,
-- WD => FDD_WDn,
-- STEP => FDD_STEP,
-- DIRC => FDD_STEP_DIR,
-- DRQ => drq_fdc,
-- INTRQ => fd_int
-- );
-- I_RTC: RTC I_FDC: WF1772IP_TOP_SOC
-- PORT MAP( PORT MAP(
-- clk_main => clk_main, clk => clk_fdc,
-- fb_adr => fb_adr(19 DOWNTO 0), resetn => reset_n,
-- FB_CS1n => fb_cs_n(1), CSn => fdc_cs_n,
-- fb_size0 => fb_size(0), RWn => fdc_wr_n,
-- fb_size1 => fb_size(1), A1 => ca(2),
-- fb_wr_n => fb_wr_n, A0 => ca(1),
-- fb_oe_n => fb_oe_n, data_in => data_in_fdc_scsi,
-- fb_ad_IN => fb_ad(23 DOWNTO 16), data_out => data_out_fdc,
-- fb_ad_OUT => fb_ad_out_rtc, -- DATA_EN => CD_EN_FDC,
-- fb_ad_EN_23_16 => fb_ad_en_rtc, RDn => FDD_RDn,
-- pic_int => pic_int TR00n => FDD_TRACK00,
-- ); IPn => FDD_INDEXn,
WPRTn => FDD_WPn,
DDEn => '0', -- Fixed to MFM.
HDTYPE => hd_dd_out,
MO => FDD_MOT_ON,
WG => FDD_WR_GATE,
WD => FDD_WDn,
STEP => FDD_STEP,
DIRC => FDD_STEP_DIR,
DRQ => drq_fdc,
INTRQ => fd_int
);
I_RTC: RTC
PORT MAP(
clk_main => clk_main,
fb_adr => fb_adr(19 DOWNTO 0),
FB_CS1n => fb_cs_n(1),
fb_size0 => fb_size(0),
fb_size1 => fb_size(1),
fb_wr_n => fb_wr_n,
fb_oe_n => fb_oe_n,
fb_ad_IN => fb_ad(23 DOWNTO 16),
fb_ad_OUT => fb_ad_out_rtc,
fb_ad_EN_23_16 => fb_ad_en_rtc,
pic_int => pic_int
);
END ARCHITECTURE; END ARCHITECTURE;

20
vhdl/rtl/vhdl/RTC/rtc.vhd
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@@ -54,7 +54,7 @@ entity RTC is
FB_CS1n : in std_logic; FB_CS1n : in std_logic;
FB_SIZE0 : in std_logic; FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic; FB_SIZE1 : in std_logic;
FB_WRn : in std_logic; FB_WR_n : in std_logic;
fb_oe_n : in std_logic; fb_oe_n : in std_logic;
FB_AD_IN : in std_logic_vector(23 downto 16); FB_AD_IN : in std_logic_vector(23 downto 16);
FB_AD_OUT : out std_logic_vector(23 downto 16); FB_AD_OUT : out std_logic_vector(23 downto 16);
@@ -116,13 +116,13 @@ begin
variable ADRVAR : std_logic_vector(5 downto 0); variable ADRVAR : std_logic_vector(5 downto 0);
begin begin
wait until CLK_MAIN = '1' and CLK_MAIN' event; wait until CLK_MAIN = '1' and CLK_MAIN' event;
if UHR_AS = '1' and FB_WRn = '0' then if UHR_AS = '1' and fb_wr_n = '0' then
RTC_ADR <= FB_AD_IN(21 downto 16); RTC_ADR <= FB_AD_IN(21 downto 16);
end if; end if;
for i in 0 to 63 loop for i in 0 to 63 loop
ADRVAR := conv_std_logic_vector(i,6); ADRVAR := conv_std_logic_vector(i,6);
if RTC_ADR = ADRVAR and UHR_DS = '1' and FB_WRn = '0' then if RTC_ADR = ADRVAR and UHR_DS = '1' and fb_wr_n = '0' then
VALUES(i) <= FB_AD_IN(23 downto 16); VALUES(i) <= FB_AD_IN(23 downto 16);
end if; end if;
end loop; end loop;
@@ -160,7 +160,7 @@ begin
end if; end if;
-- Seconds: -- Seconds:
if INC_SEC = '1' and (RTC_ADR /= "000000" or UHR_DS = '0' or FB_WRn = '1') then if INC_SEC = '1' and (RTC_ADR /= "000000" or UHR_DS = '0' or fb_wr_n = '1') then
if VALUES(0) = x"3B" then -- 59. if VALUES(0) = x"3B" then -- 59.
VALUES(0) <= (others => '0'); VALUES(0) <= (others => '0');
else else
@@ -169,7 +169,7 @@ begin
end if; end if;
-- Minutes: -- Minutes:
if INC_MIN = '1' and (RTC_ADR /= "000010" or UHR_DS = '0' or FB_WRn = '1') then if INC_MIN = '1' and (RTC_ADR /= "000010" or UHR_DS = '0' or fb_wr_n = '1') then
if VALUES(2) = x"3B" then -- 59. if VALUES(2) = x"3B" then -- 59.
VALUES(2) <= (others => '0'); VALUES(2) <= (others => '0');
else else
@@ -178,7 +178,7 @@ begin
end if; end if;
-- Hours: -- Hours:
if INC_HOUR = '1' and (WINTERTIME = '0' or VALUES(12)(0) = '0') and (RTC_ADR /= "000100" or UHR_DS = '0' or FB_WRn = '1') then if INC_HOUR = '1' and (WINTERTIME = '0' or VALUES(12)(0) = '0') and (RTC_ADR /= "000100" or UHR_DS = '0' or fb_wr_n = '1') then
if VALUES(4) = x"17" then -- 23. if VALUES(4) = x"17" then -- 23.
VALUES(4) <= (others => '0'); VALUES(4) <= (others => '0');
elsif SUMMERTIME = '1' then elsif SUMMERTIME = '1' then
@@ -189,7 +189,7 @@ begin
end if; end if;
-- Day and day of the week: -- Day and day of the week:
if INC_DAY = '1' and (RTC_ADR /= "000110" or UHR_DS = '0' or FB_WRn = '1') then if INC_DAY = '1' and (RTC_ADR /= "000110" or UHR_DS = '0' or fb_wr_n = '1') then
if VALUES(6) = x"07" then if VALUES(6) = x"07" then
VALUES(6) <= x"01"; VALUES(6) <= x"01";
else else
@@ -197,7 +197,7 @@ begin
end if; end if;
end if; end if;
if INC_DAY = '1' and (RTC_ADR /= "000111" or UHR_DS = '0' or FB_WRn = '1') then if INC_DAY = '1' and (RTC_ADR /= "000111" or UHR_DS = '0' or fb_wr_n = '1') then
if VALUES(7) = DAYs_PER_MONTH then if VALUES(7) = DAYs_PER_MONTH then
VALUES(7) <= x"01"; VALUES(7) <= x"01";
else else
@@ -206,7 +206,7 @@ begin
end if; end if;
-- Month: -- Month:
if INC_MONAT = '1' and (RTC_ADR /= "001000" or UHR_DS = '0' or FB_WRn = '1') then if INC_MONAT = '1' and (RTC_ADR /= "001000" or UHR_DS = '0' or fb_wr_n = '1') then
if VALUES(8) = x"0C" then if VALUES(8) = x"0C" then
VALUES(8) <= x"01"; VALUES(8) <= x"01";
else else
@@ -215,7 +215,7 @@ begin
end if; end if;
-- Year: -- Year:
if INC_JAHR = '1' and (RTC_ADR /= "001001" or UHR_DS = '0' or FB_WRn = '1') then if INC_JAHR = '1' and (RTC_ADR /= "001001" or UHR_DS = '0' or fb_wr_n = '1') then
if VALUES(9) = x"63" then -- 99. if VALUES(9) = x"63" then -- 99.
VALUES(9) <= (others => '0'); VALUES(9) <= (others => '0');
else else