233 lines
10 KiB
VHDL
233 lines
10 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- This file is part of the 'Firebee' project. ----
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---- http://acp.atari.org ----
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---- ----
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---- Description: ----
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---- This design unit provides the RTC logic for the 'Firebee' ----
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---- computer. It is optimized for the use of an Altera Cyclone ----
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---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----
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---- tion of the Firebee configware originally provided by Fredi ----
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---- Ashwanden and Wolfgang Förster. This release is in compa- ----
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---- rision to the first edition completely written in VHDL. ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 2 of the License, or (at your option) any later ----
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---- version. ----
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---- ----
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---- This program is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU General Public ----
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---- License along with this program; if not, write to the Free ----
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---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
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---- Boston, MA 02110-1301, USA. ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K12B 20120801 WF
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-- Initial Release of the second edition.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity RTC is
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port(
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CLK_MAIN : in std_logic;
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FB_ADR : in std_logic_vector(19 downto 0);
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FB_CS1n : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_WR_n : in std_logic;
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fb_oe_n : in std_logic;
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FB_AD_IN : in std_logic_vector(23 downto 16);
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FB_AD_OUT : out std_logic_vector(23 downto 16);
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FB_AD_EN_23_16 : out std_logic;
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PIC_INT : in std_logic
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);
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end entity RTC;
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architecture BEHAVIOUR of RTC is
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type VALUES_TYPE is array(63 downto 0) of std_logic_vector(7 downto 0);
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signal VALUES : VALUES_TYPE;
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signal FB_B1 : std_logic;
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signal FB_B3 : std_logic;
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signal UHR_AS : std_logic;
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signal UHR_DS : std_logic;
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signal RTC_ADR : std_logic_vector(5 downto 0);
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signal EIGHTHs_OF_SECOND : std_logic_vector(2 downto 0);
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signal PIC_INT_SYNC : std_logic_vector(2 downto 0);
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signal INC_SEC : std_logic;
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signal INC_MIN : std_logic;
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signal INC_HOUR : std_logic;
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signal INC_DAY : std_logic;
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signal DAYs_PER_MONTH : std_logic_vector(7 downto 0);
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signal WINTERTIME : std_logic;
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signal SUMMERTIME : std_logic;
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signal INC_MONAT : std_logic;
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signal INC_JAHR : std_logic;
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signal UPDATE_ON : std_logic;
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begin
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-- Byte selectors:
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FB_B1 <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
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'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
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FB_B3 <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
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'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
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UHR_AS <= '1' when FB_B1 = '1' and FB_CS1n = '0' and FB_ADR(19 downto 1) = x"7C4B0" else '0'; -- $FFFF8961.
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UHR_DS <= '1' when FB_B3 = '1' and FB_CS1n = '0' and FB_ADR(19 downto 1) = x"7C4B1" else '0'; -- $FFFF8963.
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UPDATE_ON <= not VALUES(11)(7); -- UPDATE ON OFF
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INC_SEC <= '1' when EIGHTHs_OF_SECOND = 7 and PIC_INT_SYNC(2) = '1' and UPDATE_ON = '1' else '0';
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INC_MIN <= '1' when INC_SEC = '1' and VALUES(0) = x"3B" else '0'; -- 59.
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INC_HOUR <= '1' when INC_MIN = '1' and VALUES(2) = x"3B" else '0'; -- 59.
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INC_DAY <= '1' when INC_HOUR = '1' and VALUES(2) = x"17" else '0'; -- 23.
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INC_MONAT <= '1' when INC_DAY = '1' and VALUES(7) = DAYs_PER_MONTH else '0';
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INC_JAHR <= '1' when INC_MONAT = '1' and VALUES(8) = x"C" else '0'; -- 12.
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DAYs_PER_MONTH <= x"1F" when VALUES(8) = x"01" or VALUES(8) = x"03" or VALUES(8) = x"05" or VALUES(8) = x"07" or VALUES(8) = x"08" or VALUES(8) = x"0A" or VALUES(8) = x"0C" else
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x"1E" when VALUES(8) = x"04" or VALUES(8) = x"06" or VALUES(8) = x"09" or VALUES(8) = x"0B" else
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x"1D" when VALUES(8) = x"02" and VALUES(9)(1 downto 0) = x"00" else x"1C";
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P_1287 : process
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-- C1287: 0 = SEK 2 = MIN 4 = STD 6 = WOCHENTAG 7 = TAG 8 = MONAT 9 = JAHR
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variable ADRVAR : std_logic_vector(5 downto 0);
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begin
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wait until CLK_MAIN = '1' and CLK_MAIN' event;
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if UHR_AS = '1' and fb_wr_n = '0' then
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RTC_ADR <= FB_AD_IN(21 downto 16);
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end if;
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for i in 0 to 63 loop
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ADRVAR := conv_std_logic_vector(i,6);
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if RTC_ADR = ADRVAR and UHR_DS = '1' and fb_wr_n = '0' then
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VALUES(i) <= FB_AD_IN(23 downto 16);
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end if;
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end loop;
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PIC_INT_SYNC(0) <= PIC_INT;
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PIC_INT_SYNC(1) <= PIC_INT_SYNC(0);
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PIC_INT_SYNC(2) <= not PIC_INT_SYNC(1) and PIC_INT_SYNC(0);
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VALUES(10)(6) <= '0'; -- No UIP.
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VALUES(11)(2) <= '1'; -- Always binary.
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VALUES(11)(1) <= '1'; -- Always 24h format.
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VALUES(11)(0) <= '1'; -- Always correction of summertime.
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VALUES(13)(7) <= '1'; -- Always true.
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-- Summer- wintertime: bit 0 in the register D provides information wether there is summer- or wintertime.
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if VALUES(6)= x"01" and VALUES(4) = x"01" and VALUES(8) = x"04" and VALUES(7) > x"17" then -- Last Sunday in April.
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SUMMERTIME <= '1';
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else
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SUMMERTIME <= '0';
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end if;
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if VALUES(6)= x"01" and VALUES(4) = x"01" and VALUES(8) = x"0A" and VALUES(7) > x"18" then -- Last Sunday in October.
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WINTERTIME <= '1';
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else
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WINTERTIME <= '0';
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end if;
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if INC_HOUR = '1' and (SUMMERTIME or WINTERTIME) = '1' then
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VALUES(13)(0) <= SUMMERTIME;
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end if;
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-- Eighths of a second:
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if PIC_INT_SYNC(2) = '1' and UPDATE_ON = '1' then
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EIGHTHs_OF_SECOND <= EIGHTHs_OF_SECOND + '1';
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end if;
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-- Seconds:
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if INC_SEC = '1' and (RTC_ADR /= "000000" or UHR_DS = '0' or fb_wr_n = '1') then
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if VALUES(0) = x"3B" then -- 59.
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VALUES(0) <= (others => '0');
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else
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VALUES(0) <= VALUES(0) + '1';
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end if;
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end if;
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-- Minutes:
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if INC_MIN = '1' and (RTC_ADR /= "000010" or UHR_DS = '0' or fb_wr_n = '1') then
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if VALUES(2) = x"3B" then -- 59.
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VALUES(2) <= (others => '0');
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else
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VALUES(2) <= VALUES(2) + '1';
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end if;
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end if;
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-- Hours:
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if INC_HOUR = '1' and (WINTERTIME = '0' or VALUES(12)(0) = '0') and (RTC_ADR /= "000100" or UHR_DS = '0' or fb_wr_n = '1') then
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if VALUES(4) = x"17" then -- 23.
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VALUES(4) <= (others => '0');
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elsif SUMMERTIME = '1' then
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VALUES(4) <= VALUES(4) + "10";
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else
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VALUES(4) <= VALUES(4) + '1';
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end if;
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end if;
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-- Day and day of the week:
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if INC_DAY = '1' and (RTC_ADR /= "000110" or UHR_DS = '0' or fb_wr_n = '1') then
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if VALUES(6) = x"07" then
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VALUES(6) <= x"01";
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else
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VALUES(6) <= VALUES(6) + '1';
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end if;
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end if;
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if INC_DAY = '1' and (RTC_ADR /= "000111" or UHR_DS = '0' or fb_wr_n = '1') then
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if VALUES(7) = DAYs_PER_MONTH then
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VALUES(7) <= x"01";
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else
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VALUES(7) <= VALUES(7) + '1';
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end if;
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end if;
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-- Month:
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if INC_MONAT = '1' and (RTC_ADR /= "001000" or UHR_DS = '0' or fb_wr_n = '1') then
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if VALUES(8) = x"0C" then
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VALUES(8) <= x"01";
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else
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VALUES(8) <= VALUES(8) + '1';
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end if;
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end if;
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-- Year:
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if INC_JAHR = '1' and (RTC_ADR /= "001001" or UHR_DS = '0' or fb_wr_n = '1') then
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if VALUES(9) = x"63" then -- 99.
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VALUES(9) <= (others => '0');
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else
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VALUES(9) <= VALUES(9) + '1';
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end if;
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end if;
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end process P_1287;
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-- Data out multiplexers:
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FB_AD_EN_23_16 <= (UHR_DS or UHR_AS) and not fb_oe_n;
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FB_AD_OUT(23 downto 16) <= VALUES(conv_integer(RTC_ADR)) when UHR_DS = '1' else
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"00" & RTC_ADR when UHR_AS = '1' else x"00";
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end architecture BEHAVIOUR;
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