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removed all dependencies to obsolete ieee.std_logic_arith and ieee.std_logic_unsigned in favour of ieee.numeric_std. There are a few things that still need to be fixed because of that, however.

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This commit is contained in:
Markus Fröschle
2014-08-04 17:23:47 +00:00
parent d96e0b82bc
commit 4c2be14e28
42 changed files with 2695 additions and 2662 deletions
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4
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C40F484C6
set_global_assignment -name TOP_LEVEL_ENTITY firebee
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -406,7 +406,7 @@ set_global_assignment -name AUTO_RAM_RECOGNITION OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_location_assignment PIN_AB12 -to CLK_33M
set_location_assignment PIN_G2 -to CLK_MAIN
set_location_assignment PIN_G1 -to CLK_MAIN
set_location_assignment PIN_AB10 -to CLK_24M576
set_location_assignment PIN_J1 -to CLK_USB
set_location_assignment PIN_T4 -to CLK_25M

32
vhdl/backend/Altera/Firebee/firebee.sdc
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@@ -71,10 +71,10 @@ create_generated_clock -name {altpll4:I_PLL4|altpll:altpll_component|altpll4_alt
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}] 0.040
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}] 0.040
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}] 0.080
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}] 0.080
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}] 0.080
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}] 0.080
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
@@ -99,10 +99,10 @@ set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {al
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}] 0.040
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}] 0.040
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}] 0.080
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}] 0.080
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}] 0.080
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}] 0.080
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
@@ -127,10 +127,10 @@ set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {al
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}] 0.040
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}] 0.040
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}] 0.10
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}] 0.10
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}] 0.10
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}] 0.10
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070
@@ -151,10 +151,10 @@ set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {a
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}] 0.040
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}] 0.040
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}] 0.10
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}] 0.10
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}] 0.10
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}] 0.10
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070

2
vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd
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@@ -4,7 +4,7 @@
---- http://acp.atari.org ----
---- ----
---- Description: ----
---- This design unit provides the bit block transfer processor ----
---- This design unit provides the std_logic block transfer processor ----
---- (BLITTER) of the 'Firebee' computer. ----
---- It is optimized for the use of an Altera Cyclone ----
---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----

6
vhdl/rtl/vhdl/DMA/fbee_dma.vhd
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@@ -44,7 +44,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FBEE_DMA is
port(
@@ -392,8 +392,8 @@ begin
DMA_REQ <= '1' when ((DMA_DRQ_IN = '1' and DMA_MODE(7) = '1') or (SCSI_DRQ = '1' and DMA_MODE(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODE(6) = '0' and CLR_FIFO = '0' else '0';
DMA_DRQ_OUT <= '1' when DMA_DRQ_REG = "11" and DMA_MODE(6) = '0' else '0';
DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODE(8) = '0' and RDF_AZ > 15 and DMA_MODE(6) = '0' else
'1' when DMA_STATUS(1) = '1' and DMA_MODE(8) = '1' and WRF_AZ < 512 and DMA_MODE(6) = '0' else '0';
DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODE(8) = '0' and unsigned(RDF_AZ) > 15 and DMA_MODE(6) = '0' else
'1' when DMA_STATUS(1) = '1' and DMA_MODE(8) = '1' and unsigned(WRF_AZ) < 512 and DMA_MODE(6) = '0' else '0';
DMA_DRQ11_I <= '1' when DMA_DRQ_REG = "11" and DMA_MODE(6) = '0' else '0';
DMA_DRQ11 <= DMA_DRQ11_I;

36
vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
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@@ -92,7 +92,7 @@ use work.firebee_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity firebee is
port(
@@ -206,7 +206,7 @@ entity firebee is
ACSI_DRQn : in std_logic;
ACSI_INTn : in std_logic;
FDD_DCHGn : in bit;
FDD_DCHGn : in std_logic;
FDD_SDSELn : out std_logic;
FDD_HD_DD : in std_logic;
FDD_RDn : in std_logic;
@@ -233,7 +233,7 @@ entity firebee is
SD_CARD_DETECT : in std_logic;
SD_WP : in std_logic;
CF_WP : in bit;
CF_WP : in std_logic;
CF_CSn : out std_logic_vector(1 downto 0);
DSP_IO : inout std_logic_vector(17 downto 0);
@@ -304,10 +304,10 @@ component altpll_reconfig1
port(
busy : out std_logic;
clock : in std_logic;
counter_param : in std_logic_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
counter_type : in std_logic_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
data_in : in std_logic_VECTOR (8 DOWNTO 0) := (OTHERS => '0');
data_out : out std_logic_VECTOR (8 DOWNTO 0);
counter_param : in std_logic_VECTOR (2 downto 0) := (others => '0');
counter_type : in std_logic_VECTOR (3 downto 0) := (others => '0');
data_in : in std_logic_VECTOR (8 downto 0) := (others => '0');
data_out : out std_logic_VECTOR (8 downto 0);
pll_areset : out std_logic;
pll_areset_in : in std_logic := '0';
pll_configupdate : out std_logic;
@@ -395,8 +395,8 @@ component altpll_reconfig1
signal FB_AD_OUT_RTC : std_logic_vector(7 downto 0);
signal FB_AD_OUT_VIDEO : std_logic_vector(31 downto 0);
signal FB_ADR : std_logic_vector(31 downto 0);
signal FB_B0 : std_logic; -- UPPER Byte BEI 16 BIT BUS
signal FB_B1 : std_logic; -- LOWER Byte BEI 16 BIT BUS
signal FB_B0 : std_logic; -- UPPER Byte BEI 16 std_logic BUS
signal FB_B1 : std_logic; -- LOWER Byte BEI 16 std_logic BUS
signal FB_DDR : std_logic_vector(127 downto 0);
signal FB_LE : std_logic_vector(3 downto 0);
signal FB_VDOE : std_logic_vector(3 downto 0);
@@ -459,7 +459,7 @@ component altpll_reconfig1
signal SR_FIFO_WRE : std_logic;
signal SR_VDMP : std_logic_vector(7 downto 0);
signal TDO : std_logic;
signal TIMEBASE : std_logic_vector(17 downto 0);
signal TIMEBASE : unsigned (17 downto 0);
signal VD_EN : std_logic;
signal VD_EN_I : std_logic;
signal VD_OUT : std_logic_vector(31 downto 0);
@@ -558,7 +558,7 @@ begin
P_TIMEBASE: process
begin
wait until CLK_500K = '1' and CLK_500K' event;
TIMEBASE <= TIMEBASE + '1';
TIMEBASE <= TIMEBASE + 1;
end process P_TIMEBASE;
RESETn <= RSTO_MCFn and LOCKED;
@@ -1305,3 +1305,17 @@ begin
PIC_INT => PIC_INT
);
end architecture;
configuration NO_SCSI of firebee is
for Structure
for all:
WF5380_TOP_SOC use entity work.WF5380_TOP_SOC(LIGHT);
end for;
end for;
end configuration no_scsi;
configuration FULL of firebee is
for Structure
-- default configuration
end for;
end configuration FULL;

3
vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
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@@ -326,7 +326,7 @@ package firebee_pkg is
ROM4n : out std_logic;
ROM3n : out std_logic;
CF_WP : in bit;
CF_WP : in std_logic;
CF_CSn : out std_logic_vector(1 downto 0)
);
end component;
@@ -393,7 +393,6 @@ package firebee_pkg is
component WF2149IP_TOP_SOC
port(
SYS_CLK : in std_logic;
RESETn : in std_logic;

8
vhdl/rtl/vhdl/Interrupt/interrupt.vhd
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@@ -44,8 +44,8 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-- use ieee.std_logic_arith.all;
entity INTHANDLER is
port(
@@ -216,9 +216,9 @@ begin
if INT_ENA(i) = '1' and RESETn = '1' then
INT_LA(i) <= x"0";
elsif INT_L(i) = '1' and INT_LA(i) < x"7" then
INT_LA(i) <= INT_LA(i) + '1';
INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) + 1);
elsif INT_L(i) = '0' and INT_LA(i) > x"8" then
INT_LA(i) <= INT_LA(i) - '1';
INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) - 1);
elsif INT_L(i) = '1' and INT_LA(i) > x"6" then
INT_LA(i) <= x"F";
elsif INT_L(i) = '0' and INT_LA(i) > x"9" then

4
vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd
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@@ -44,7 +44,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity IDE_CF_SD_ROM is
port(
@@ -85,7 +85,7 @@ entity IDE_CF_SD_ROM is
ROM4n : out std_logic;
ROM3n : out std_logic;
CF_WP : in bit;
CF_WP : in std_logic;
CF_CSn : out std_logic_vector(1 downto 0)
);
end entity IDE_CF_SD_ROM;

54
vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
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@@ -44,7 +44,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity VIDEO_CTRL is
port(
@@ -262,7 +262,7 @@ begin
'1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '0' and FB_ADR(1) = '1' else -- Low word.
'1' when FB_ADR(1 downto 0) = "11" else '0'; -- Byte 3.
-- 16 bit selectors:
-- 16 std_logic selectors:
FB_16B(0) <= not FB_ADR(0);
FB_16B(1) <= '1'when FB_ADR(0) = '1' else
'1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- No byte.
@@ -706,7 +706,7 @@ begin
elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" then
HSY_LEN <= x"20";
elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' then
HSY_LEN <= x"10" + ('0' & VR_FRQ(7 downto 1)); -- HSYNC pulse length in pixels = frequency/500ns.
HSY_LEN <= std_logic_vector(unsigned'(x"10") + unsigned('0' & VR_FRQ(7 downto 1))); -- HSYNC pulse length in pixels = frequency/500ns.
else
HSY_LEN <= x"00";
end if;
@@ -728,9 +728,9 @@ begin
P_DOUBLE_LINE_2 : process
begin
wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < HDIS_END - '1' then
if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < std_logic_vector(unsigned(HDIS_END) - 1) then
INTER_ZEI_I <= '1'; -- Switch insertion line to "double". Line zero due to SYNC.
elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > HDIS_END - "10" then
elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > std_logic_vector(unsigned(HDIS_END) - 10) then
INTER_ZEI_I <= '1'; -- Switch insertion mode to "normal". Lines and line zero due to SYNC.
else
INTER_ZEI_I <= '0';
@@ -740,16 +740,16 @@ begin
end process P_DOUBLE_LINE_2;
-- The following multiplications change every time the video resolution is changed.
MUL1 <= VDL_HBE * MULF(5 downto 1);
MUL2 <= (VDL_HHT + '1' + VDL_HSS) * MULF(5 downto 1);
MUL3 <= (VDL_HHT + "10") * MULF(5 downto 1);
MUL1 <= std_logic_vector(unsigned(VDL_HBE) * unsigned(MULF(5 downto 1)));
MUL2 <= std_logic_vector(unsigned(VDL_HHT) + 1 + unsigned(VDL_HSS) * unsigned(MULF(5 downto 1)));
MUL3 <= std_logic_vector(unsigned(VDL_HHT) + 10 * unsigned(MULF(5 downto 1)));
BORDER_LEFT <= VDL_HBE when FBEE_VIDEO_ON = '1' else
x"015" when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
x"02A" when ATARI_SYNC = '1' else MUL1(16 downto 5);
HDIS_START <= VDL_HDB when FBEE_VIDEO_ON = '1' else BORDER_LEFT + '1';
HDIS_END <= VDL_HDE when FBEE_VIDEO_ON = '1' else BORDER_LEFT + HDIS_LEN;
BORDER_RIGHT <= VDL_HBB when FBEE_VIDEO_ON = '1' else HDIS_END + '1';
HDIS_START <= VDL_HDB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + 1);
HDIS_END <= VDL_HDE when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + unsigned(HDIS_LEN));
BORDER_RIGHT <= VDL_HBB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(HDIS_END) + 1);
HS_START <= VDL_HSS when FBEE_VIDEO_ON = '1' else
ATARI_HL(11 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
ATARI_HH(11 downto 0) when VDL_VMD(2) = '1' else MUL2(16 downto 5);
@@ -764,7 +764,7 @@ begin
"00110101111" when ATARI_SYNC = '1' and ST_VIDEO = '1' else -- 431.
"00111111111" when ATARI_SYNC = '1' else '0' & VDL_VDE(10 downto 1); -- 511.
BORDER_BOTTOM <= VDL_VBB when FBEE_VIDEO_ON = '1' else
VDIS_END + '1' when ATARI_SYNC = '1' else ('0' & VDL_VBB(10 downto 1)) + '1';
std_logic_vector(unsigned(VDIS_END) + 1) when ATARI_SYNC = '1' else ('0' & std_logic_vector(unsigned(VDL_VBB(10 downto 1)) + 1));
VS_START <= VDL_VSS when FBEE_VIDEO_ON = '1' else
ATARI_VL(10 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
ATARI_VH(10 downto 0) when ATARI_SYNC = '1' else '0' & VDL_VSS(10 downto 1);
@@ -772,7 +772,7 @@ begin
ATARI_VL(26 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
ATARI_VH(26 downto 16) when ATARI_SYNC = '1' else '0' & VDL_VFT(10 downto 1);
LAST <= '1' when VHCNT = H_TOTAL - "10" else '0';
LAST <= '1' when VHCNT = std_logic_vector(unsigned(H_TOTAL) - 10) else '0';
VIDEO_CLOCK_DOMAIN : process
begin
@@ -793,19 +793,19 @@ begin
end if;
if LAST = '0' then
VHCNT <= VHCNT + '1';
VHCNT <= std_logic_vector(unsigned(VHCNT) + 1);
else
VHCNT <= (others => '0');
end if;
if LAST = '1' and VVCNT = V_TOTAL - '1' then
if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 1) then
VVCNT <= (others => '0');
elsif LAST = '1' then
VVCNT <= VVCNT + '1';
VVCNT <= std_logic_vector(unsigned(VVCNT) + 1);
end if;
-- Display on/off:
if LAST = '1' and VVCNT > BORDER_TOP - '1' and VVCNT < BORDER_BOTTOM - '1' then
if LAST = '1' and VVCNT > std_logic_vector(unsigned(BORDER_TOP) - 1) and VVCNT < std_logic_vector(unsigned(BORDER_BOTTOM) - 1) then
DPO_ZL <= '1';
elsif LAST = '1' then
DPO_ZL <= '0';
@@ -817,7 +817,7 @@ begin
DPO_ON <= '0';
end if;
if VHCNT = BORDER_RIGHT - '1' then
if VHCNT = std_logic_vector(unsigned(BORDER_RIGHT) - 1) then
DPO_OFF <= '1';
else
DPO_OFF <= '0';
@@ -826,7 +826,7 @@ begin
DISP_ON <= (DISP_ON and not DPO_OFF) or (DPO_ON and DPO_ZL);
-- Data transfer on/off:
if VHCNT = HDIS_START - '1' then
if VHCNT = std_logic_vector(unsigned(HDIS_START) - 1) then
VDO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING.
else
VDO_ON <= '0';
@@ -838,7 +838,7 @@ begin
VDO_OFF <= '0';
end if;
if LAST = '1' and VVCNT >= VDIS_START - '1' and VVCNT < VDIS_END then
if LAST = '1' and VVCNT >= std_logic_vector(unsigned(VDIS_START) - 1) and VVCNT < VDIS_END then
VDO_ZL <= '1'; -- Take over at the end of the line.
elsif LAST = '1' then
VDO_ZL <= '0'; -- 1 ZEILE DAVOR ON OFF
@@ -848,19 +848,19 @@ begin
VDTRON <= (VDTRON and not VDO_OFF) or (VDO_ON and VDO_ZL);
-- Delay and SYNC
if VHCNT = HS_START - "11" then
if VHCNT = std_logic_vector(unsigned(HS_START) - 11) then
HSYNC_START <= '1';
else
HSYNC_START <= '0';
end if;
if HSYNC_START = '1' then
HSYNC_I <= HSY_LEN;
HSYNC_I <= std_logic_vector(unsigned(HSY_LEN));
elsif HSYNC_I > x"00" then
HSYNC_I <= HSYNC_I - '1';
HSYNC_I <= std_logic_vector(unsigned(HSYNC_I) - 1);
end if;
if LAST = '1' and VVCNT = VS_START - "11" then
if LAST = '1' and VVCNT = std_logic_vector(unsigned(VS_START) - 11) then
VSYNC_START <= '1'; -- start am ende der Zeile vor dem vsync
else
VSYNC_START <= '0';
@@ -869,7 +869,7 @@ begin
if LAST = '1' and VSYNC_START = '1' then -- Start at the end of the line before VSYNC.
VSYNC_I <= "011"; -- 3 lines vsync length.
elsif LAST = '1' and VSYNC_I > "000" then
VSYNC_I <= VSYNC_I - '1'; -- Count down.
VSYNC_I <= std_logic_vector(unsigned(VSYNC_I) - 1); -- Count down.
end if;
if FBEE_VCTR(15) = '1' and VDL_VCT(5) = '1' and VSYNC_I = "000" then
@@ -897,7 +897,7 @@ begin
RAND <= RAND(5 downto 0) & (DISP_ON and not VDTRON and FBEE_VCTR(25));
RAND_ON <= RAND(6);
if LAST = '1' and VVCNT = V_TOTAL - "10" then
if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 10) then
FIFO_CLR <= '1';
elsif LAST = '1' then
FIFO_CLR <= '0';
@@ -928,7 +928,7 @@ begin
end if;
if VDTRON = '1' and SYNC_PIX = '0' then
SUB_PIXEL_CNT <= SUB_PIXEL_CNT + '1';
SUB_PIXEL_CNT <= std_logic_vector(unsigned(SUB_PIXEL_CNT) + 1);
elsif VDTRON = '1' then
SUB_PIXEL_CNT <= (others => '0');
end if;

106
vhdl/rtl/vhdl/WF5380/wf5380_control.vhd
View File

@@ -14,7 +14,7 @@
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- All rights reserved. No portion of this sourcecode may be ----
---- reproduced or transmitted in any form by any means, whether ----
---- by electronic, mechanical, photocopying, recording or ----
@@ -30,57 +30,57 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF5380_CONTROL is
port (
-- System controls:
CLK : in bit;
RESETn : in bit; -- System reset.
CLK : in std_logic;
RESETn : in std_logic; -- System reset.
-- System controls:
BSY_INn : in bit; -- SCSI BSY_INn bit.
BSY_OUTn : out bit; -- SCSI BSY_INn bit.
DATA_EN : out bit; -- Enable the SCSI data lines.
SEL_INn : in bit; -- SCSI SEL_INn bit.
ARB_EN : in bit; -- Arbitration enable.
BSY_DISn : in bit; -- BSY monitoring enable.
RSTn : in bit; -- SCSI reset.
BSY_INn : in std_logic; -- SCSI BSY_INn std_logic.
BSY_OUTn : out std_logic; -- SCSI BSY_INn std_logic.
DATA_EN : out std_logic; -- Enable the SCSI data lines.
SEL_INn : in std_logic; -- SCSI SEL_INn std_logic.
ARB_EN : in std_logic; -- Arstd_logicration enable.
BSY_DISn : in std_logic; -- BSY monitoring enable.
RSTn : in std_logic; -- SCSI reset.
ARB : out bit; -- Arbitration flag.
AIP : out bit; -- Arbitration in progress flag.
LA : out bit; -- Lost arbitration flag.
ARB : out std_logic; -- Arstd_logicration flag.
AIP : out std_logic; -- Arstd_logicration in progress flag.
LA : out std_logic; -- Lost arstd_logicration flag.
ACK_INn : in bit;
ACK_OUTn : out bit;
REQ_INn : in bit;
REQ_OUTn : out bit;
ACK_INn : in std_logic;
ACK_OUTn : out std_logic;
REQ_INn : in std_logic;
REQ_OUTn : out std_logic;
DACKn : in bit; -- Data acknowledge.
READY : out bit;
DRQ : out bit; -- Data request.
DACKn : in std_logic; -- Data acknowledge.
READY : out std_logic;
DRQ : out std_logic; -- Data request.
TARG : in bit; -- Target mode indicator.
BLK : in bit; -- Block mode indicator.
PINT_EN : in bit; -- Parity interrupt enable.
SPER : in bit; -- Parity error.
SER_ID : in bit; -- SER matches ODR bits.
RPI : in bit; -- Reset interrupts.
DMA_EN : in bit; -- DMA mode enable.
SDS : in bit; -- Start DMA send, write only.
SDT : in bit; -- Start DMA target receive, write only.
SDI : in bit; -- Start DMA initiator receive, write only.
EOP_EN : in bit; -- EOP interrupt enable.
EOPn : in bit; -- End of process indicator.
PHSM : in bit; -- Phase match flag.
TARG : in std_logic; -- Target mode indicator.
BLK : in std_logic; -- Block mode indicator.
PINT_EN : in std_logic; -- Parity interrupt enable.
SPER : in std_logic; -- Parity error.
SER_ID : in std_logic; -- SER matches ODR std_logics.
RPI : in std_logic; -- Reset interrupts.
DMA_EN : in std_logic; -- DMA mode enable.
SDS : in std_logic; -- Start DMA send, write only.
SDT : in std_logic; -- Start DMA target receive, write only.
SDI : in std_logic; -- Start DMA initiator receive, write only.
EOP_EN : in std_logic; -- EOP interrupt enable.
EOPn : in std_logic; -- End of process indicator.
PHSM : in std_logic; -- Phase match flag.
INT : out bit; -- Interrupt.
IDR_WR : out bit; -- Write input data register during DMA.
ODR_WR : out bit; -- Write output data register, during DMA.
CHK_PAR : out bit; -- Check Parity during DMA operation.
BSY_ERR : out bit; -- Busy monitoring error.
DMA_SND : out bit; -- Indicates direction of target DMA.
DMA_ACTIVE : out bit -- DMA is active.
INT : out std_logic; -- Interrupt.
IDR_WR : out std_logic; -- Write input data register during DMA.
ODR_WR : out std_logic; -- Write output data register, during DMA.
CHK_PAR : out std_logic; -- Check Parity during DMA operation.
BSY_ERR : out std_logic; -- Busy monitoring error.
DMA_SND : out std_logic; -- Indicates direction of target DMA.
DMA_ACTIVE : out std_logic -- DMA is active.
);
end entity WF5380_CONTROL;
@@ -91,11 +91,11 @@ signal CTRL_STATE : CTRL_STATES;
signal NEXT_CTRL_STATE : CTRL_STATES;
signal DMA_STATE : DMA_STATES;
signal NEXT_DMA_STATE : DMA_STATES;
signal BUS_FREE : bit;
signal BUS_FREE : std_logic;
signal DELAY_800ns : boolean;
signal DELAY_2200ns : boolean;
signal DMA_ACTIVE_I : bit;
signal EOP_In : bit;
signal DMA_ACTIVE_I : std_logic;
signal EOP_In : std_logic;
begin
IN_BUFFER: process
-- This buffer shall prevent some signals against
@@ -399,14 +399,14 @@ begin
-- A bus free is valid if the BSY_INn signal is
-- at least 437.5ns inactive ans SEL_INn is inactive.
-- The delay are 7 clock cycles of 16MHz.
variable TMP : std_logic_vector(2 downto 0);
variable TMP : unsigned (2 downto 0);
begin
if RESETn = '0' then
BUS_FREE <= '0';
TMP := "000";
elsif CLK = '1' and CLK' event then
if BSY_INn = '1' and TMP < x"111" then
TMP := TMP + '1';
TMP := TMP + 1;
elsif BSY_INn = '0' then
TMP := "000";
end if;
@@ -424,7 +424,7 @@ begin
DELAY_800: process(RESETn, CLK)
-- This is the delay of 812.5ns.
-- It is derived from 13 16MHz clock cycles.
variable TMP : std_logic_vector(3 downto 0);
variable TMP : unsigned (3 downto 0);
begin
if RESETn = '0' then
DELAY_800ns <= false;
@@ -433,7 +433,7 @@ begin
if CTRL_STATE /= WAIT_800ns then
TMP := x"0";
elsif TMP <= x"D" then
TMP := TMP + '1';
TMP := TMP + 1;
end if;
--
if TMP = x"D" then
@@ -505,7 +505,7 @@ begin
P_LA: process(RESETn, CLK)
-- This flip flop controls the LA
-- (lost arbitration) flag.
-- (lost arstd_logicration) flag.
begin
if RESETn = '0' then
LA <= '0';
@@ -549,7 +549,7 @@ begin
-- least 437.5ns inactive. The delay are 7 clock cycles
-- of 16MHz. This logic also provides the respective
-- error flags for the BSR.
variable TMP : std_logic_vector(2 downto 0);
variable TMP : unsigned (2 downto 0);
begin
if RESETn = '0' then
INT <= '0';
@@ -596,7 +596,7 @@ begin
end if;
--
if BSY_INn = '1' and TMP < x"111" then
TMP := TMP + '1'; -- Bus settle delay.
TMP := TMP + 1; -- Bus settle delay.
elsif BSY_INn = '0' then
TMP := "000";
end if;
@@ -612,3 +612,7 @@ begin
end if;
end process INTERRUPTS;
end BEHAVIOUR;
architecture LIGHT of WF5380_CONTROL is
begin
end LIGHT;

157
vhdl/rtl/vhdl/WF5380/wf5380_pkg.vhd
View File

@@ -16,7 +16,7 @@
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- All rights reserved. No portion of this sourcecode may be ----
---- reproduced or transmitted in any form by any means, whether ----
---- by electronic, mechanical, photocopying, recording or ----
@@ -31,92 +31,93 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package WF5380_PKG is
component WF5380_REGISTERS
port (
CLK : in bit;
RESETn : in bit;
ADR : in bit_vector(2 downto 0);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
CSn : in bit;
RDn : in bit;
WRn : in bit;
RSTn : in bit;
RST : out bit;
ARB_EN : out bit;
DMA_ACTIVE : in bit;
DMA_EN : out bit;
BSY_DISn : out bit;
EOP_EN : out bit;
PINT_EN : out bit;
SPER : out bit;
TARG : out bit;
BLK : out bit;
DMA_DIS : in bit;
IDR_WR : in bit;
ODR_WR : in bit;
CHK_PAR : in bit;
AIP : in bit;
ARB : in bit;
LA : in bit;
CSD : in bit_vector(7 downto 0);
CSB : in bit_vector(7 downto 0);
BSR : in bit_vector(7 downto 0);
ODR_OUT : out bit_vector(7 downto 0);
ICR_OUT : out bit_vector(7 downto 0);
TCR_OUT : out bit_vector(3 downto 0);
SER_OUT : out bit_vector(7 downto 0);
SDS : out bit;
SDT : out bit;
SDI : out bit;
RPI : out bit
CLK : in std_logic;
RESETn : in std_logic;
ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
RSTn : in std_logic;
RST : out std_logic;
ARB_EN : out std_logic;
DMA_ACTIVE : in std_logic;
DMA_EN : out std_logic;
BSY_DISn : out std_logic;
EOP_EN : out std_logic;
PINT_EN : out std_logic;
SPER : out std_logic;
TARG : out std_logic;
BLK : out std_logic;
DMA_DIS : in std_logic;
IDR_WR : in std_logic;
ODR_WR : in std_logic;
CHK_PAR : in std_logic;
AIP : in std_logic;
ARB : in std_logic;
LA : in std_logic;
CSD : in std_logic_vector(7 downto 0);
CSB : in std_logic_vector(7 downto 0);
BSR : in std_logic_vector(7 downto 0);
ODR_OUT : out std_logic_vector(7 downto 0);
ICR_OUT : out std_logic_vector(7 downto 0);
TCR_OUT : out std_logic_vector(3 downto 0);
SER_OUT : out std_logic_vector(7 downto 0);
SDS : out std_logic;
SDT : out std_logic;
SDI : out std_logic;
RPI : out std_logic
);
end component;
component WF5380_CONTROL
port (
CLK : in bit;
RESETn : in bit;
BSY_INn : in bit;
BSY_OUTn : out bit;
DATA_EN : out bit;
SEL_INn : in bit;
ARB_EN : in bit;
BSY_DISn : in bit;
RSTn : in bit;
ARB : out bit;
AIP : out bit;
LA : out bit;
ACK_INn : in bit;
ACK_OUTn : out bit;
REQ_INn : in bit;
REQ_OUTn : out bit;
DACKn : in bit;
READY : out bit;
DRQ : out bit;
TARG : in bit;
BLK : in bit;
PINT_EN : in bit;
SPER : in bit;
SER_ID : in bit;
RPI : in bit;
DMA_EN : in bit;
SDS : in bit;
SDT : in bit;
SDI : in bit;
EOP_EN : in bit;
EOPn : in bit;
PHSM : in bit;
INT : out bit;
IDR_WR : out bit;
ODR_WR : out bit;
CHK_PAR : out bit;
BSY_ERR : out bit;
DMA_SND : out bit;
DMA_ACTIVE : out bit
CLK : in std_logic;
RESETn : in std_logic;
BSY_INn : in std_logic;
BSY_OUTn : out std_logic;
DATA_EN : out std_logic;
SEL_INn : in std_logic;
ARB_EN : in std_logic;
BSY_DISn : in std_logic;
RSTn : in std_logic;
ARB : out std_logic;
AIP : out std_logic;
LA : out std_logic;
ACK_INn : in std_logic;
ACK_OUTn : out std_logic;
REQ_INn : in std_logic;
REQ_OUTn : out std_logic;
DACKn : in std_logic;
READY : out std_logic;
DRQ : out std_logic;
TARG : in std_logic;
BLK : in std_logic;
PINT_EN : in std_logic;
SPER : in std_logic;
SER_ID : in std_logic;
RPI : in std_logic;
DMA_EN : in std_logic;
SDS : in std_logic;
SDT : in std_logic;
SDI : in std_logic;
EOP_EN : in std_logic;
EOPn : in std_logic;
PHSM : in std_logic;
INT : out std_logic;
IDR_WR : out std_logic;
ODR_WR : out std_logic;
CHK_PAR : out std_logic;
BSY_ERR : out std_logic;
DMA_SND : out std_logic;
DMA_ACTIVE : out std_logic
);
end component;
end WF5380_PKG;

100
vhdl/rtl/vhdl/WF5380/wf5380_registers.vhd
View File

@@ -32,7 +32,7 @@
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- All rights reserved. No portion of this sourcecode may be ----
---- reproduced or transmitted in any form by any means, whether ----
---- by electronic, mechanical, photocopying, recording or ----
@@ -48,68 +48,68 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF5380_REGISTERS is
port (
-- System controls:
CLK : in bit;
RESETn : in bit; -- System reset.
CLK : in std_logic;
RESETn : in std_logic; -- System reset.
-- Address and data:
ADR : in bit_vector(2 downto 0);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
-- Bus and DMA controls:
CSn : in bit;
RDn : in bit;
WRn : in bit;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
-- Core controls:
RSTn : in bit; -- SCSI reset.
RST : out bit; -- Programmed SCSI reset.
ARB_EN : out bit; -- Arbitration enable.
DMA_ACTIVE : in bit; -- DMA is running.
DMA_EN : out bit; -- DMA mode enable.
BSY_DISn : out bit; -- BSY monitoring enable.
EOP_EN : out bit; -- EOP interrupt enable.
PINT_EN : out bit; -- Parity interrupt enable.
SPER : out bit; -- Parity error.
TARG : out bit; -- Target mode.
BLK : out bit; -- Block DMA mode.
DMA_DIS : in bit; -- Reset the DMA_EN by this signal.
IDR_WR : in bit; -- Write input data register during DMA.
ODR_WR : in bit; -- Write output data register, during DMA.
CHK_PAR : in bit; -- Check Parity during DMA operation.
AIP : in bit; -- Arbitration in progress.
ARB : in bit; -- Arbitration.
LA : in bit; -- Lost arbitration.
RSTn : in std_logic; -- SCSI reset.
RST : out std_logic; -- Programmed SCSI reset.
ARB_EN : out std_logic; -- Arstd_logicration enable.
DMA_ACTIVE : in std_logic; -- DMA is running.
DMA_EN : out std_logic; -- DMA mode enable.
BSY_DISn : out std_logic; -- BSY monitoring enable.
EOP_EN : out std_logic; -- EOP interrupt enable.
PINT_EN : out std_logic; -- Parity interrupt enable.
SPER : out std_logic; -- Parity error.
TARG : out std_logic; -- Target mode.
BLK : out std_logic; -- Block DMA mode.
DMA_DIS : in std_logic; -- Reset the DMA_EN by this signal.
IDR_WR : in std_logic; -- Write input data register during DMA.
ODR_WR : in std_logic; -- Write output data register, during DMA.
CHK_PAR : in std_logic; -- Check Parity during DMA operation.
AIP : in std_logic; -- Arstd_logicration in progress.
ARB : in std_logic; -- Arstd_logicration.
LA : in std_logic; -- Lost arstd_logicration.
CSD : in bit_vector(7 downto 0); -- SCSI data.
CSB : in bit_vector(7 downto 0); -- Current SCSI bus status.
BSR : in bit_vector(7 downto 0); -- Bus and status.
CSD : in std_logic_vector(7 downto 0); -- SCSI data.
CSB : in std_logic_vector(7 downto 0); -- Current SCSI bus status.
BSR : in std_logic_vector(7 downto 0); -- Bus and status.
ODR_OUT : out bit_vector(7 downto 0); -- This is the ODR register.
ICR_OUT : out bit_vector(7 downto 0); -- This is the ICR register.
TCR_OUT : out bit_vector(3 downto 0); -- This is the TCR register.
SER_OUT : out bit_vector(7 downto 0); -- This is the SER register.
ODR_OUT : out std_logic_vector(7 downto 0); -- This is the ODR register.
ICR_OUT : out std_logic_vector(7 downto 0); -- This is the ICR register.
TCR_OUT : out std_logic_vector(3 downto 0); -- This is the TCR register.
SER_OUT : out std_logic_vector(7 downto 0); -- This is the SER register.
SDS : out bit; -- Start DMA send, write only.
SDT : out bit; -- Start DMA target receive, write only.
SDI : out bit; -- Start DMA initiator receive, write only.
RPI : out bit
SDS : out std_logic; -- Start DMA send, write only.
SDT : out std_logic; -- Start DMA target receive, write only.
SDI : out std_logic; -- Start DMA initiator receive, write only.
RPI : out std_logic
);
end entity WF5380_REGISTERS;
architecture BEHAVIOUR of WF5380_REGISTERS is
signal ICR : bit_vector(7 downto 0); -- Initiator command register, read/write.
signal IDR : bit_vector(7 downto 0); -- Input data register.
signal MR2 : bit_vector(7 downto 0); -- Mode register 2, read/write.
signal ODR : bit_vector(7 downto 0); -- Output data register, write only.
signal SER : bit_vector(7 downto 0); -- Select enable register, write only.
signal TCR : bit_vector(3 downto 0); -- Target command register, read/write.
signal ICR : std_logic_vector(7 downto 0); -- Initiator command register, read/write.
signal IDR : std_logic_vector(7 downto 0); -- Input data register.
signal MR2 : std_logic_vector(7 downto 0); -- Mode register 2, read/write.
signal ODR : std_logic_vector(7 downto 0); -- Output data register, write only.
signal SER : std_logic_vector(7 downto 0); -- Select enable register, write only.
signal TCR : std_logic_vector(3 downto 0); -- Target command register, read/write.
begin
REGISTERS: process(RESETn, CLK)
-- This process reflects all registers in the 5380.
@@ -178,7 +178,7 @@ begin
PARITY: process(RESETn, CLK)
-- This is the parity generating logic with it's related
-- error generation.
variable PAR_VAR : bit;
variable PAR_VAR : std_logic;
variable LOCK : boolean;
begin
if RESETn = '0' then
@@ -235,7 +235,7 @@ begin
RST <= ICR(7);
-- Readback, unused bit positions are read back zero.
-- Readback, unused std_logic positions are read back zero.
DATA_OUT <= CSD when ADR = "000" and CSn = '0' and RDn = '0' else -- Current SCSI data.
ICR(7) & AIP & LA & ICR(4 downto 0) when ADR = "001" and CSn = '0' and RDn = '0' else
MR2 when ADR = "010" and CSn = '0' and RDn = '0' else
@@ -246,3 +246,7 @@ begin
RPI <= '1' when ADR = "111" and CSn = '0' and RDn = '0' else '0'; -- Reset parity/interrupts.
end BEHAVIOUR;
architecture LIGHT of WF5380_REGISTERS is
begin
end LIGHT;

184
vhdl/rtl/vhdl/WF5380/wf5380_soc_top.vhd
View File

@@ -21,7 +21,7 @@
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- All rights reserved. No portion of this sourcecode may be ----
---- reproduced or transmitted in any form by any means, whether ----
---- by electronic, mechanical, photocopying, recording or ----
@@ -45,104 +45,104 @@ use ieee.std_logic_unsigned.all;
entity WF5380_TOP_SOC is
port (
-- System controls:
CLK : in bit; -- Use a 16MHz Clock.
RESETn : in bit;
CLK : in std_logic; -- Use a 16MHz Clock.
RESETn : in std_logic;
-- Address and data:
ADR : in bit_vector(2 downto 0);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
-- Bus and DMA controls:
CSn : in bit;
RDn : in bit;
WRn : in bit;
EOPn : in bit;
DACKn : in bit;
DRQ : out bit;
INT : out bit;
READY : out bit;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
EOPn : in std_logic;
DACKn : in std_logic;
DRQ : out std_logic;
INT : out std_logic;
READY : out std_logic;
-- SCSI bus:
DB_INn : in bit_vector(7 downto 0);
DB_OUTn : out bit_vector(7 downto 0);
DB_EN : out bit;
DBP_INn : in bit;
DBP_OUTn : out bit;
DBP_EN : out bit;
RST_INn : in bit;
RST_OUTn : out bit;
RST_EN : out bit;
BSY_INn : in bit;
BSY_OUTn : out bit;
BSY_EN : out bit;
SEL_INn : in bit;
SEL_OUTn : out bit;
SEL_EN : out bit;
ACK_INn : in bit;
ACK_OUTn : out bit;
ACK_EN : out bit;
ATN_INn : in bit;
ATN_OUTn : out bit;
ATN_EN : out bit;
REQ_INn : in bit;
REQ_OUTn : out bit;
REQ_EN : out bit;
IOn_IN : in bit;
IOn_OUT : out bit;
IO_EN : out bit;
CDn_IN : in bit;
CDn_OUT : out bit;
CD_EN : out bit;
MSG_INn : in bit;
MSG_OUTn : out bit;
MSG_EN : out bit
DB_INn : in std_logic_vector(7 downto 0);
DB_OUTn : out std_logic_vector(7 downto 0);
DB_EN : out std_logic;
DBP_INn : in std_logic;
DBP_OUTn : out std_logic;
DBP_EN : out std_logic;
RST_INn : in std_logic;
RST_OUTn : out std_logic;
RST_EN : out std_logic;
BSY_INn : in std_logic;
BSY_OUTn : out std_logic;
BSY_EN : out std_logic;
SEL_INn : in std_logic;
SEL_OUTn : out std_logic;
SEL_EN : out std_logic;
ACK_INn : in std_logic;
ACK_OUTn : out std_logic;
ACK_EN : out std_logic;
ATN_INn : in std_logic;
ATN_OUTn : out std_logic;
ATN_EN : out std_logic;
REQ_INn : in std_logic;
REQ_OUTn : out std_logic;
REQ_EN : out std_logic;
IOn_IN : in std_logic;
IOn_OUT : out std_logic;
IO_EN : out std_logic;
CDn_IN : in std_logic;
CDn_OUT : out std_logic;
CD_EN : out std_logic;
MSG_INn : in std_logic;
MSG_OUTn : out std_logic;
MSG_EN : out std_logic
);
end entity WF5380_TOP_SOC;
architecture STRUCTURE of WF5380_TOP_SOC is
signal ACK_OUT_CTRLn : bit;
signal AIP : bit;
signal ARB : bit;
signal ARB_EN : bit;
signal BLK : bit;
signal BSR : bit_vector(7 downto 0);
signal BSY_DISn : bit;
signal BSY_ERR : bit;
signal BSY_OUT_CTRLn : bit;
signal CHK_PAR : bit;
signal CSD : bit_vector(7 downto 0);
signal CSB : bit_vector(7 downto 0);
signal DATA_EN_CTRL : bit;
signal DB_EN_I : bit;
signal DMA_ACTIVE : bit;
signal DMA_EN : bit;
signal DMA_DIS : bit;
signal DMA_SND : bit;
signal DRQ_I : bit;
signal EDMA : bit;
signal EOP_EN : bit;
signal ICR : bit_vector(7 downto 0);
signal IDR_WR : bit;
signal INT_I : bit;
signal LA : bit;
signal ODR : bit_vector(7 downto 0);
signal ODR_WR : bit;
signal PCHK : bit;
signal PHSM : bit;
signal PINT_EN : bit;
signal REQ_OUT_CTRLn : bit;
signal RPI : bit;
signal RST : bit;
signal SDI : bit;
signal SDS : bit;
signal SDT : bit;
signal SER : bit_vector(7 downto 0);
signal SER_ID : bit;
signal SPER : bit;
signal TARG : bit;
signal TCR : bit_vector(3 downto 0);
signal ACK_OUT_CTRLn : std_logic;
signal AIP : std_logic;
signal ARB : std_logic;
signal ARB_EN : std_logic;
signal BLK : std_logic;
signal BSR : std_logic_vector(7 downto 0);
signal BSY_DISn : std_logic;
signal BSY_ERR : std_logic;
signal BSY_OUT_CTRLn : std_logic;
signal CHK_PAR : std_logic;
signal CSD : std_logic_vector(7 downto 0);
signal CSB : std_logic_vector(7 downto 0);
signal DATA_EN_CTRL : std_logic;
signal DB_EN_I : std_logic;
signal DMA_ACTIVE : std_logic;
signal DMA_EN : std_logic;
signal DMA_DIS : std_logic;
signal DMA_SND : std_logic;
signal DRQ_I : std_logic;
signal EDMA : std_logic;
signal EOP_EN : std_logic;
signal ICR : std_logic_vector(7 downto 0);
signal IDR_WR : std_logic;
signal INT_I : std_logic;
signal LA : std_logic;
signal ODR : std_logic_vector(7 downto 0);
signal ODR_WR : std_logic;
signal PCHK : std_logic;
signal PHSM : std_logic;
signal PINT_EN : std_logic;
signal REQ_OUT_CTRLn : std_logic;
signal RPI : std_logic;
signal RST : std_logic;
signal SDI : std_logic;
signal SDS : std_logic;
signal SDT : std_logic;
signal SER : std_logic_vector(7 downto 0);
signal SER_ID : std_logic;
signal SPER : std_logic;
signal TARG : std_logic;
signal TCR : std_logic_vector(3 downto 0);
begin
EDMA <= '1' when EOPn = '0' and DACKn = '0' and RDn = '0' else
'1' when EOPn = '0' and DACKn = '0' and WRn = '0' else '0';
@@ -188,7 +188,7 @@ begin
RST_EN <= '1' when RST = '1' else '0'; -- Open drain control.
-- Data enables:
DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arbitration.
DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arstd_logicration.
'1' when ICR(0) = '1' and TARG = '1' and DMA_SND = '1' else -- Target 'Send' mode.
'1' when ICR(0) = '1' and TARG = '0' and IOn_IN = '0' and PHSM = '1' else
'1' when ICR(6) = '1' else '0'; -- Test mode enable.
@@ -281,3 +281,7 @@ begin
DMA_ACTIVE => DMA_ACTIVE
);
end STRUCTURE;
architecture LIGHT of WF5380_TOP_SOC is
begin
end LIGHT;

226
vhdl/rtl/vhdl/WF5380/wf5380_top.vhd
View File

@@ -16,7 +16,7 @@
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- Copyright <20> 2009-2010 Wolfgang Foerster Inventronik GmbH. ----
---- All rights reserved. No portion of this sourcecode may be ----
---- reproduced or transmitted in any form by any means, whether ----
---- by electronic, mechanical, photocopying, recording or ----
@@ -35,27 +35,27 @@ use work.wf5380_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF5380_TOP is
port (
-- System controls:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Address and data:
ADR : in std_logic_vector(2 downto 0);
DATA : inout std_logic_vector(7 downto 0);
-- Bus and DMA controls:
CSn : in bit;
RDn : in bit;
WRn : in bit;
EOPn : in bit;
DACKn : in bit;
DRQ : out bit;
INT : out bit;
READY : out bit;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
EOPn : in std_logic;
DACKn : in std_logic;
DRQ : out std_logic;
INT : out std_logic;
READY : out std_logic;
-- SCSI bus:
DBn : inout std_logic_vector(7 downto 0);
@@ -76,113 +76,113 @@ architecture STRUCTURE of WF5380_TOP is
component WF5380_TOP_SOC
port (
-- System controls:
CLK : in bit;
RESETn : in bit;
ADR : in bit_vector(2 downto 0);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
CSn : in bit;
RDn : in bit;
WRn : in bit;
EOPn : in bit;
DACKn : in bit;
DRQ : out bit;
INT : out bit;
READY : out bit;
DB_INn : in bit_vector(7 downto 0);
DB_OUTn : out bit_vector(7 downto 0);
DB_EN : out bit;
DBP_INn : in bit;
DBP_OUTn : out bit;
DBP_EN : out bit;
RST_INn : in bit;
RST_OUTn : out bit;
RST_EN : out bit;
BSY_INn : in bit;
BSY_OUTn : out bit;
BSY_EN : out bit;
SEL_INn : in bit;
SEL_OUTn : out bit;
SEL_EN : out bit;
ACK_INn : in bit;
ACK_OUTn : out bit;
ACK_EN : out bit;
ATN_INn : in bit;
ATN_OUTn : out bit;
ATN_EN : out bit;
REQ_INn : in bit;
REQ_OUTn : out bit;
REQ_EN : out bit;
IOn_IN : in bit;
IOn_OUT : out bit;
IO_EN : out bit;
CDn_IN : in bit;
CDn_OUT : out bit;
CD_EN : out bit;
MSG_INn : in bit;
MSG_OUTn : out bit;
MSG_EN : out bit
CLK : in std_logic;
RESETn : in std_logic;
ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
EOPn : in std_logic;
DACKn : in std_logic;
DRQ : out std_logic;
INT : out std_logic;
READY : out std_logic;
DB_INn : in std_logic_vector(7 downto 0);
DB_OUTn : out std_logic_vector(7 downto 0);
DB_EN : out std_logic;
DBP_INn : in std_logic;
DBP_OUTn : out std_logic;
DBP_EN : out std_logic;
RST_INn : in std_logic;
RST_OUTn : out std_logic;
RST_EN : out std_logic;
BSY_INn : in std_logic;
BSY_OUTn : out std_logic;
BSY_EN : out std_logic;
SEL_INn : in std_logic;
SEL_OUTn : out std_logic;
SEL_EN : out std_logic;
ACK_INn : in std_logic;
ACK_OUTn : out std_logic;
ACK_EN : out std_logic;
ATN_INn : in std_logic;
ATN_OUTn : out std_logic;
ATN_EN : out std_logic;
REQ_INn : in std_logic;
REQ_OUTn : out std_logic;
REQ_EN : out std_logic;
IOn_IN : in std_logic;
IOn_OUT : out std_logic;
IO_EN : out std_logic;
CDn_IN : in std_logic;
CDn_OUT : out std_logic;
CD_EN : out std_logic;
MSG_INn : in std_logic;
MSG_OUTn : out std_logic;
MSG_EN : out std_logic
);
end component;
--
signal ADR_IN : bit_vector(2 downto 0);
signal DATA_IN : bit_vector(7 downto 0);
signal DATA_OUT : bit_vector(7 downto 0);
signal DATA_EN : bit;
signal DB_INn : bit_vector(7 downto 0);
signal DB_OUTn : bit_vector(7 downto 0);
signal DB_EN : bit;
signal DBP_INn : bit;
signal DBP_OUTn : bit;
signal DBP_EN : bit;
signal RST_INn : bit;
signal RST_OUTn : bit;
signal RST_EN : bit;
signal BSY_INn : bit;
signal BSY_OUTn : bit;
signal BSY_EN : bit;
signal SEL_INn : bit;
signal SEL_OUTn : bit;
signal SEL_EN : bit;
signal ACK_INn : bit;
signal ACK_OUTn : bit;
signal ACK_EN : bit;
signal ATN_INn : bit;
signal ATN_OUTn : bit;
signal ATN_EN : bit;
signal REQ_INn : bit;
signal REQ_OUTn : bit;
signal REQ_EN : bit;
signal IOn_IN : bit;
signal IOn_OUT : bit;
signal IO_EN : bit;
signal CDn_IN : bit;
signal CDn_OUT : bit;
signal CD_EN : bit;
signal MSG_INn : bit;
signal MSG_OUTn : bit;
signal MSG_EN : bit;
signal ADR_IN : std_logic_vector(2 downto 0);
signal DATA_IN : std_logic_vector(7 downto 0);
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_EN : std_logic;
signal DB_INn : std_logic_vector(7 downto 0);
signal DB_OUTn : std_logic_vector(7 downto 0);
signal DB_EN : std_logic;
signal DBP_INn : std_logic;
signal DBP_OUTn : std_logic;
signal DBP_EN : std_logic;
signal RST_INn : std_logic;
signal RST_OUTn : std_logic;
signal RST_EN : std_logic;
signal BSY_INn : std_logic;
signal BSY_OUTn : std_logic;
signal BSY_EN : std_logic;
signal SEL_INn : std_logic;
signal SEL_OUTn : std_logic;
signal SEL_EN : std_logic;
signal ACK_INn : std_logic;
signal ACK_OUTn : std_logic;
signal ACK_EN : std_logic;
signal ATN_INn : std_logic;
signal ATN_OUTn : std_logic;
signal ATN_EN : std_logic;
signal REQ_INn : std_logic;
signal REQ_OUTn : std_logic;
signal REQ_EN : std_logic;
signal IOn_IN : std_logic;
signal IOn_OUT : std_logic;
signal IO_EN : std_logic;
signal CDn_IN : std_logic;
signal CDn_OUT : std_logic;
signal CD_EN : std_logic;
signal MSG_INn : std_logic;
signal MSG_OUTn : std_logic;
signal MSG_EN : std_logic;
begin
ADR_IN <= To_BitVector(ADR);
ADR_IN <= ADR;
DATA_IN <= To_BitVector(DATA);
DATA <= To_StdLogicVector(DATA_OUT) when DATA_EN = '1' else (others => 'Z');
DATA_IN <= DATA;
DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
DB_INn <= To_BitVector(DBn);
DBn <= To_StdLogicVector(DB_OUTn) when DB_EN = '1' else (others => 'Z');
DB_INn <= DBn;
DBn <= DB_OUTn when DB_EN = '1' else (others => 'Z');
DBP_INn <= To_Bit(DBPn);
DBP_INn <= DBPn;
RST_INn <= To_Bit(RSTn);
BSY_INn <= To_Bit(BSYn);
SEL_INn <= To_Bit(SELn);
ACK_INn <= To_Bit(ACKn);
ATN_INn <= To_Bit(ATNn);
REQ_INn <= To_Bit(REQn);
IOn_IN <= To_Bit(IOn);
CDn_IN <= To_Bit(CDn);
MSG_INn <= To_Bit(MSGn);
RST_INn <= RSTn;
BSY_INn <= BSYn;
SEL_INn <= SELn;
ACK_INn <= ACKn;
ATN_INn <= ATNn;
REQ_INn <= REQn;
IOn_IN <= IOn;
CDn_IN <= CDn;
MSG_INn <= MSGn;
DBPn <= '1' when DBP_OUTn = '1' and DBP_EN = '1' else
'0' when DBP_OUTn = '0' and DBP_EN = '1' else 'Z';
@@ -256,3 +256,7 @@ begin
MSG_EN => MSG_EN
);
end STRUCTURE;
architecture LIGHT of WF5380_TOP is
begin
end LIGHT;

48
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_am_detector.vhd
View File

@@ -22,9 +22,9 @@
---- 2. every second pulse is a data. ----
---- 3. a logic 1 is represented by two consecutive pulses (clock and data). ----
---- 4. a logic 0 is represented by one clock pulse and no data pulse. ----
---- 5. Hence there are a maximum of two pulses per data bit. ----
---- 6. one clock and one data pulse come together in one bit cell. ----
---- 7. the duration of a bit cell in FM is 4 microseconds. ----
---- 5. Hence there are a maximum of two pulses per data std_logic. ----
---- 6. one clock and one data pulse come together in one std_logic cell. ----
---- 7. the duration of a std_logic cell in FM is 4 microseconds. ----
---- 8. an ID address mark is represented as data FE with clock C7. ----
---- 9. a DATA address mark is represented as data FB with clock C7. ----
---- Examples: ----
@@ -52,11 +52,11 @@
---- 4. a logic 0 is represented by a clock pulse and no data pulse if ----
---- following a 0. ----
---- 5. a logic 0 is represented by no pulse if following a 1. ----
---- 6. Hence there are a maximum of one pulse per data bit. ----
---- 7. one clock and one data pulse form together one bit cell. ----
---- 8. the duration of a bit cell in MFM is 2 microseconds. ----
---- 6. Hence there are a maximum of one pulse per data std_logic. ----
---- 7. one clock and one data pulse form together one std_logic cell. ----
---- 8. the duration of a std_logic cell in MFM is 2 microseconds. ----
---- 9. an address mark sync is represented as data A1 with missing clock ----
---- pulse between bit 4 and 5. ----
---- pulse between std_logic 4 and 5. ----
---- Examples: ----
---- Binary data FE 1 1 1 1 1 1 1 0 is represented in MFM as follows: ----
---- 0101010101010100 this is the ID address mark. ----
@@ -66,11 +66,11 @@
---- 0101010101001010 this is the deleted DATA address mark. ----
---- the A1 data 1 0 1 0 0 0 0 1 is represented as follows: ----
---- 0100010010101001 ----
---- with the missing clock pulse between bits 4 and 5 there results: ----
---- with the missing clock pulse between std_logics 4 and 5 there results: ----
---- results: 0100010010001001 this is the address mark sync. ----
---- ----
---- Both MFM and FM are during read and write shifted with most significant ----
---- bit (MSB) first. During the FM address marks are written without a ----
---- std_logic (MSB) first. During the FM address marks are written without a ----
---- SYNC pulse the MFM coded data requires a synchronisation (A1 with ----
---- missing clock pulse because at the beginning of the data stream it is ----
---- not defined wether a clock pulse or a data pulse appears first. In FM ----
@@ -122,34 +122,34 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_AM_DETECTOR is
port(
-- System control
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Controls:
DDEn : in bit;
DDEn : in std_logic;
-- Serial data and clock:
DATA : in bit;
DATA_STRB : in bit;
DATA : in std_logic;
DATA_STRB : in std_logic;
-- Address mark detector:
ID_AM : out bit; -- ID address mark strobe.
DATA_AM : out bit; -- Data address mark strobe.
DDATA_AM : out bit -- Deleted data address mark strobe.
ID_AM : out std_logic; -- ID address mark strobe.
DATA_AM : out std_logic; -- Data address mark strobe.
DDATA_AM : out std_logic -- Deleted data address mark strobe.
);
end WF1772IP_AM_DETECTOR;
architecture BEHAVIOR of WF1772IP_AM_DETECTOR is
signal SHIFT : bit_vector(15 downto 0);
signal SHIFT : std_logic_vector(15 downto 0);
signal SYNC : boolean;
signal ID_AM_I : bit;
signal DATA_AM_I : bit;
signal DDATA_AM_I : bit;
signal ID_AM_I : std_logic;
signal DATA_AM_I : std_logic;
signal DDATA_AM_I : std_logic;
begin
SHIFTREG: process(RESETn, CLK)
begin
@@ -176,7 +176,7 @@ begin
-- SYNC goes low again. This mechanism is used to detect the correct address
-- marks in the MFM data stream during the type III read track command.
-- This is an improvement over the original WD1772 chip.
variable TMP : std_logic_vector(4 downto 0);
variable TMP : unsigned (4 downto 0);
begin
if RESETn = '0' then
TMP := "00000";
@@ -184,7 +184,7 @@ begin
if SHIFT = "0100010010001001" and DDEn = '0' then
TMP := "10001"; -- Load sync time counter.
elsif DATA_STRB = '1' and TMP > "00000" then
TMP := TMP - '1';
TMP := TMP - 1;
end if;
end if;
case TMP is

160
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_control.vhd
View File

@@ -71,85 +71,85 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_CONTROL is
port(
-- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Chip control signals:
A1, A0 : in bit;
RWn : in bit;
CSn : in bit;
DDEn : in bit;
A1, A0 : in std_logic;
RWn : in std_logic;
CSn : in std_logic;
DDEn : in std_logic;
-- Registers:
DR : in bit_vector(7 downto 0); -- Data register.
DR : in std_logic_vector(7 downto 0); -- Data register.
CMD : in std_logic_vector(7 downto 0); -- Command register.
DSR : in std_logic_vector(7 downto 0); -- Shift register.
TR : in std_logic_vector(7 downto 0); -- Track register.
SR : in std_logic_vector(7 downto 0); -- Sector register.
-- Status flags:
MO : buffer bit; -- Motor on status flag.
WR_PR : out bit; -- Write protect status flag.
SPINUP_RECTYPE : out bit; -- Spin up / record type status flag.
SEEK_RNF : out bit; -- Seek error / record not found status flag.
CRC_ERRFLAG : out bit; -- CRC status flag.
LOST_DATA_TR00 : out bit; -- Status flag indicates lost data or track 00 position.
DRQ : out bit; -- Data request.
DRQ_IPn : out bit; -- Data request status flag.
BUSY : buffer bit; -- BUSY status flag.
MO : buffer std_logic; -- Motor on status flag.
WR_PR : out std_logic; -- Write protect status flag.
SPINUP_RECTYPE : out std_logic; -- Spin up / record type status flag.
SEEK_RNF : out std_logic; -- Seek error / record not found status flag.
CRC_ERRFLAG : out std_logic; -- CRC status flag.
LOST_DATA_TR00 : out std_logic; -- Status flag indicates lost data or track 00 position.
DRQ : out std_logic; -- Data request.
DRQ_IPn : out std_logic; -- Data request status flag.
BUSY : buffer std_logic; -- BUSY status flag.
-- Address mark detector controls:
AM_2_DISK : out bit; -- Enables / disables the address mark detector.
ID_AM : in bit; -- Address mark of the ID field
DATA_AM : in bit; -- Address mark of the data field
DDATA_AM : in bit; -- Address mark of a deleted data field
AM_2_DISK : out std_logic; -- Enables / disables the address mark detector.
ID_AM : in std_logic; -- Address mark of the ID field
DATA_AM : in std_logic; -- Address mark of the data field
DDATA_AM : in std_logic; -- Address mark of a deleted data field
-- CRC unit controls:
CRC_ERR : in bit; -- CRC decoder's error.
CRC_PRES : out bit; -- Preset CRC during write operations.
CRC_ERR : in std_logic; -- CRC decoder's error.
CRC_PRES : out std_logic; -- Preset CRC during write operations.
-- Track register controls:
TR_PRES : out bit; -- Set x"FF".
TR_CLR : out bit; -- Clear.
TR_INC : out bit; -- Increment.
TR_DEC : out bit; -- Decrement.
TR_PRES : out std_logic; -- Set x"FF".
TR_CLR : out std_logic; -- Clear.
TR_INC : out std_logic; -- Increment.
TR_DEC : out std_logic; -- Decrement.
-- Sector register control:
SR_LOAD : out bit; -- Load.
SR_INC : out bit; -- Increment.
SR_LOAD : out std_logic; -- Load.
SR_INC : out std_logic; -- Increment.
-- The TRACK_NR is required during the type III command
-- 'Read Address'. TRACK_NR is the content of the TRACKMEM.
TRACK_NR : out std_logic_vector(7 downto 0);
-- DATA register control:
DR_CLR : out bit; -- Clear.
DR_LOAD : out bit; -- LOAD.
DR_CLR : out std_logic; -- Clear.
DR_LOAD : out std_logic; -- LOAD.
-- Shift register control:
SHFT_LOAD_ND : out bit; -- Load normal data.
SHFT_LOAD_SD : out bit; -- Load special data.
SHFT_LOAD_ND : out std_logic; -- Load normal data.
SHFT_LOAD_SD : out std_logic; -- Load special data.
-- Transceiver controls:
CRC_2_DISK : out bit; -- Cause the Transceiver to write out CRC data.
DSR_2_DISK : out bit; -- Cause the Transceiver to write normal data.
FF_2_DISK : out bit; -- Cause the Transceiver to write x"FF" bytes.
PRECOMP_EN : out bit; -- Enables the write precompensation.
CRC_2_DISK : out std_logic; -- Cause the Transceiver to write out CRC data.
DSR_2_DISK : out std_logic; -- Cause the Transceiver to write normal data.
FF_2_DISK : out std_logic; -- Cause the Transceiver to write x"FF" bytes.
PRECOMP_EN : out std_logic; -- Enables the write precompensation.
-- Miscellaneous Controls:
DATA_STRB : in bit; -- Data strobe (read and write operation)
WPRTn : in bit; -- Write protect flag
IPn : in bit; -- Index pulse flag
TRACK00n : in bit; -- Track zero flag
DISK_RWn : out bit; -- This signal reflects the data direction.
DIRC : out bit; -- Step direction control.
STEP : out bit; -- Step pulse.
WG : out bit; -- Write gate control.
INTRQ : out bit -- Interrupt request flag.
DATA_STRB : in std_logic; -- Data strobe (read and write operation)
WPRTn : in std_logic; -- Write protect flag
IPn : in std_logic; -- Index pulse flag
TRACK00n : in std_logic; -- Track zero flag
DISK_RWn : out std_logic; -- This signal reflects the data direction.
DIRC : out std_logic; -- Step direction control.
STEP : out std_logic; -- Step pulse.
WG : out std_logic; -- Write gate control.
INTRQ : out std_logic -- Interrupt request flag.
);
end WF1772IP_CONTROL;
@@ -176,17 +176,17 @@ architecture BEHAVIOR of WF1772IP_CONTROL is
signal CMD_WR : boolean;
signal STAT_RD : boolean;
signal DELAY : boolean;
signal DRQ_I : bit;
signal DRQ_I : std_logic;
signal INDEX_CNT : boolean;
signal DIR : bit;
signal INDEX_MARK : bit;
signal DIR : std_logic;
signal INDEX_MARK : std_logic;
signal STEP_TRAP : boolean;
signal TYPE_IV_BREAK : boolean;
signal BYTE_RDY : boolean;
signal SECT_LEN : std_logic_vector(10 downto 0);
signal SECT_LEN : unsigned (10 downto 0);
signal TRACKMEM : std_logic_vector(7 downto 0);
signal T3_TRADR : boolean;
signal T3_DATATYPE : bit_vector(7 downto 0);
signal T3_DATATYPE : std_logic_vector(7 downto 0);
begin
-- The Forced interrupt stops any command at the end of an internal micro instruction.
-- Forced interrupt waits until ALU operations in progress are complete (CRC calculations,
@@ -720,7 +720,7 @@ begin
-- In T1_STEP_PULSE the delay is according to the CMD(1 downto 0) as follows:
-- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms.
-- In T1_VERIFY_DELAY there is a delay of 30ms.
variable DELCNT : std_logic_vector(19 downto 0);
variable DELCNT : unsigned (19 downto 0);
begin
if RESETn = '0' then
DELCNT := (others => '0');
@@ -734,21 +734,21 @@ begin
case CMD_STATE is
-- Time delays work on CLK edges.
when DELAY_15MS | T1_CHECK_DIR | T1_STEP_DELAY | T1_VERIFY_DELAY =>
DELCNT := DELCNT + '1';
DELCNT := DELCNT + 1;
-- Bit count delays work on data strobes.
-- Read from disk operation:
when T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | T2_SCAN_TRACK | T2_SCAN_SECT |
T2_SCAN_LEN | T2_VERIFY_CRC_1 | T2_VERIFY_AM | T2_FIRSTBYTE |
T2_NEXTBYTE | T2_VERIFY_CRC_2 | T3_SHIFT | T3_SHIFT_ADR | T3_VERIFY_CRC =>
if DATA_STRB = '1' then
DELCNT := DELCNT + '1';
DELCNT := DELCNT + 1;
end if;
-- Write to disk operation:
when T2_DELAY_B2 | T2_DELAY_B8 | T2_WR_LEADIN |
T2_WR_AM | T2_DELAY_B1 |T2_DELAY_B11 | T2_WR_BYTE | T2_DATALOST |
T2_WR_CRC | T2_WR_FF | T3_DELAY_B3 | T3_WR_DATA | T3_DATALOST =>
if DATA_STRB = '1' then
DELCNT := DELCNT + '1';
DELCNT := DELCNT + 1;
end if;
when others =>
DELCNT := (others => '0'); -- Clear the delay counter if not used.
@@ -786,7 +786,7 @@ begin
when T1_SCAN_TRACK | T2_SCAN_TRACK | T2_SCAN_LEN | T2_FIRSTBYTE | T2_NEXTBYTE |
T2_WR_BYTE | T2_DATALOST | T2_WR_FF | T3_DATALOST | T3_SHIFT_ADR =>
case DELCNT is
when x"00008" => DELAY <= true; -- The delay in this case is 8 bit times.
when x"00008" => DELAY <= true; -- The delay in this case is 8 std_logic times.
when others => DELAY <= false;
end case;
when T1_SCAN_CRC =>
@@ -795,9 +795,9 @@ begin
when others => DELAY <= false;
end case;
when T2_WR_AM =>
if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark bits (FM mode).
if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark std_logics (FM mode).
DELAY <= true;
elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark bits (MFM mode).
elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark std_logics (MFM mode).
DELAY <= true;
else
DELAY <= false;
@@ -811,9 +811,9 @@ begin
DELAY <= false;
end if;
when T2_WR_LEADIN =>
if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero bits in FM mode.
if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero std_logics in FM mode.
DELAY <= true;
elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero bits in MFM mode.
elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero std_logics in MFM mode.
DELAY <= true;
else
DELAY <= false;
@@ -853,16 +853,16 @@ begin
when others => DELAY <= false;
end case;
when T3_WR_DATA =>
if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC bits.
if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC std_logics.
DELAY <= true;
elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data bits.
elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data std_logics.
DELAY <= true;
else
DELAY <= false;
end if;
when T3_SHIFT =>
case DELCNT is
when x"00001" => DELAY <= true; -- Scan just one data bit.
when x"00001" => DELAY <= true; -- Scan just one data std_logic.
when others => DELAY <= false;
end case;
when others =>
@@ -876,8 +876,8 @@ begin
-- It is achieved by counting the index pulses of the disk. This encounters problems,
-- if the disk is not inserted. For this reason there is additionally to the index counter
-- a timeout which is active if there are no index pulses.
variable CNT : std_logic_vector(3 downto 0);
variable TIMEOUT : std_logic_vector(27 downto 0);
variable CNT : unsigned (3 downto 0);
variable TIMEOUT : unsigned (27 downto 0);
variable LOCK : boolean;
begin
if RESETn = '0' then
@@ -890,14 +890,14 @@ begin
when SPINUP | T1_SPINDOWN | T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC |
T2_INIT | T2_SCAN_TRACK | T2_SCAN_SECT |T2_SCAN_LEN | T2_VERIFY_CRC_1 | T3_RD_ADR | T3_VERIFY_AM =>
if IPn = '0' and LOCK = false then -- Count the index pulses.
CNT := CNT + '1';
CNT := CNT + 1;
LOCK := true;
elsif IPn = '1' then
LOCK := false;
end if;
--
if TIMEOUT < x"17FFFFF" then -- Timeout of about 1.5s.
TIMEOUT := TIMEOUT + '1';
TIMEOUT := TIMEOUT + 1;
end if;
when others =>
CNT := x"0";
@@ -959,7 +959,7 @@ begin
-- This process counts the bytes read in the type III read address
-- command during the command states T3_SHIFT_ADR, T3_LOAD_DATA2,
-- T3_SET_DRQ_2 and T3_CHECK_RD.
variable CNT : std_logic_vector(2 downto 0);
variable CNT : unsigned (2 downto 0);
begin
if RESETn = '0' then
CNT := "000";
@@ -968,7 +968,7 @@ begin
when T3_VERIFY_AM =>
CNT := "000"; -- Clear the counter right befor the count operation.
when T3_SET_DRQ_2 =>
CNT := CNT + '1'; -- Increment after each read cycle.
CNT := CNT + 1; -- Increment after each read cycle.
when others =>
null;
end case;
@@ -981,17 +981,17 @@ begin
BYTEASMBLY: process(RESETn, CLK)
-- This process controls the condition in the CMD_STATE T3_CHECK_DR.
-- Therefore the bits shifted into the DSR in command state T3_SHIFT are counted.
-- Therefore the std_logics shifted into the DSR in command state T3_SHIFT are counted.
-- The count condition is entering the command state T3_CHECK_INDEX_3. The clear
-- condition is either the command state IDLE or the command state T3_CHECK_DR.
variable CNT : std_logic_vector(3 downto 0);
variable CNT : unsigned (3 downto 0);
begin
if RESETn = '0' then
CNT := x"0";
elsif CLK = '1' and CLK' event then
case CMD_STATE is
when IDLE => CNT := x"0";
when T3_CHECK_INDEX_3 => CNT := CNT + '1';
when T3_CHECK_INDEX_3 => CNT := CNT + 1;
when T3_CHECK_DR => CNT := (others => '0');
when others => null;
end case;
@@ -1037,7 +1037,7 @@ begin
when others =>
null;
end case;
-- The data request bit is also cleared by reading or writing the
-- The data request std_logic is also cleared by reading or writing the
-- data register (direct memory access operation).
if (DATA_RD = true or DATA_WR = true) then
DRQ_I <= '0';
@@ -1144,7 +1144,7 @@ begin
end process P_INTRQ;
P_LOST_DATA_TR00: process(RESETn, CLK)
-- Logic for the status bit number 2:
-- Logic for the status std_logic number 2:
-- The TRACK00 flag is used to detect wether a floppy disk drive
-- is connected or not.
begin
@@ -1174,7 +1174,7 @@ begin
end process P_LOST_DATA_TR00;
MOTORSWITCH: process(RESETn, CLK)
variable INDEXCNT : std_logic_vector(3 downto 0);
variable INDEXCNT : unsigned (3 downto 0);
variable LOCK : boolean;
begin
if RESETn = '0' then
@@ -1186,7 +1186,7 @@ begin
INDEXCNT := x"9"; -- Initialise the index counter.
LOCK := false;
elsif LOCK = false and IPn = '0' and INDEXCNT > x"0" then
INDEXCNT := INDEXCNT - '1'; -- Count the index pulses in the IDLE state.
INDEXCNT := INDEXCNT - 1; -- Count the index pulses in the IDLE state.
LOCK := true;
elsif IPn = '1' then
LOCK := false;
@@ -1255,7 +1255,7 @@ begin
-- If after 255 stepping pulses no TRACK00n was not detected, the
-- RESTORE command is terminated and the interrupt request and the
-- seek error are set.
variable STEP_CNT : std_logic_vector(7 downto 0);
variable STEP_CNT : unsigned (7 downto 0);
begin
if RESETn = '0' then
STEP_CNT := (others => '0');
@@ -1265,7 +1265,7 @@ begin
elsif CMD(7 downto 4) /= "0000" then -- No RESTORE command.
STEP_CNT := x"00";
elsif CMD_STATE = T1_STEP and STEP_CNT < x"FF" then
STEP_CNT := STEP_CNT + '1';
STEP_CNT := STEP_CNT + 1;
end if;
end if;
--
@@ -1278,7 +1278,7 @@ begin
STEPPULSE: process(RESETn, CLK)
-- The step pulse duration is in the original WD1772 4us in MFM mode and 8 us.
-- in FM mode This process is responsible to provide the correct pulse lengths.
variable CNT : std_logic_vector(7 downto 0);
variable CNT : unsigned (7 downto 0);
begin
if RESETn = '0' then
CNT := (others => '0');
@@ -1339,7 +1339,7 @@ begin
when others => SECT_LEN <= "10000000000"; -- Dummy for U, X, Z, W, H, L, -.
end case;
when T2_LOAD_DATA | T2_LOAD_SHFT =>
SECT_LEN <= SECT_LEN - '1';
SECT_LEN <= SECT_LEN - 1;
when others =>
null;
end case;

28
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
View File

@@ -84,33 +84,33 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_CRC_LOGIC is
port(
-- System control
CLK : in bit;
RESETn : in bit;
DISK_RWn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
DISK_RWn : in std_logic;
-- Preset controls:
DDEn : in bit;
ID_AM : in bit;
DDEn : in std_logic;
ID_AM : in std_logic;
DATA_AM : in Bit;
DDATA_AM : in Bit;
-- CRC unit:
SD : in bit; -- Serial data input.
CRC_STRB : in bit; -- Data strobe.
CRC_2_DISK : in bit; -- Forces the unit to flush the CRC remainder.
CRC_PRES : in bit; -- Presets the CRC unit during write to disk.
CRC_SDOUT : out bit; -- Serial data output.
CRC_ERR : out bit -- Indicates CRC error.
SD : in std_logic; -- Serial data input.
CRC_STRB : in std_logic; -- Data strobe.
CRC_2_DISK : in std_logic; -- Forces the unit to flush the CRC remainder.
CRC_PRES : in std_logic; -- Presets the CRC unit during write to disk.
CRC_SDOUT : out std_logic; -- Serial data output.
CRC_ERR : out std_logic -- Indicates CRC error.
);
end WF1772IP_CRC_LOGIC;
architecture BEHAVIOR of WF1772IP_CRC_LOGIC is
signal CRC_SHIFT : bit_vector(15 downto 0);
signal CRC_SHIFT : std_logic_vector(15 downto 0);
begin
P_CRC: process
-- The shift register is initialised with appropriate values in HD or DD mode.
@@ -148,7 +148,7 @@ begin
-- In this mode the CRC is encoded. In read from disk mode, the encoding works as CRC
-- verification. In this operating condition the ID or the data field is compared
-- against the CRC checksum. if there are no errors, the shift register's value is
-- x"0000" after the last bit of the checksum is shifted in. In write to disk mode the
-- x"0000" after the last std_logic of the checksum is shifted in. In write to disk mode the
-- CRC linear feedback shift register (lfsr) works to generate the CRC remainder of the
-- ID or data field.
CRC_SHIFT <= CRC_SHIFT(14 downto 12) & (CRC_SHIFT(15) xor CRC_SHIFT(11) xor SD) &

80
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
View File

@@ -80,7 +80,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_DIGITAL_PLL is
generic(
@@ -94,37 +94,37 @@ entity WF1772IP_DIGITAL_PLL is
-- may not drop below zero.
TOP : integer range 0 to 255 := 152; -- +18.0%
BOTTOM : integer range 0 to 255 := 104; -- -18.0%
PHASE_CORR : integer range 0 to 128 := 75
PHASE_CORR : unsigned (7 downto 0) := to_unsigned(75, 8)
);
port(
-- System control
CLK : in bit; -- 16MHz clock.
RESETn : in bit;
CLK : in std_logic; -- 16MHz clock.
RESETn : in std_logic;
-- Controls
DDEn : in bit; -- Double density enable.
HDTYPE : in bit; -- This control is '1' when HD disks are inserted.
DISK_RWn : in bit; -- Read write control.
DDEn : in std_logic; -- Double density enable.
HDTYPE : in std_logic; -- This control is '1' when HD disks are inserted.
DISK_RWn : in std_logic; -- Read write control.
-- Data and clock lines
RDn : in bit; -- Read signal from the disk.
PLL_D : out bit; -- Synchronous read signal.
PLL_DSTRB : out bit -- Read strobe.
RDn : in std_logic; -- Read signal from the disk.
PLL_D : out std_logic; -- Synchronous read signal.
PLL_DSTRB : out std_logic -- Read strobe.
);
end WF1772IP_DIGITAL_PLL;
architecture BEHAVIOR of WF1772IP_DIGITAL_PLL is
signal RD_In : bit;
signal UP, DOWN : bit;
signal PHASE_DECREASE : bit;
signal PHASE_INCREASE : bit;
signal HI_STOP, LOW_STOP : bit;
signal PER_CNT : std_logic_vector(7 downto 0);
signal ADDER_IN : std_logic_vector(7 downto 0);
signal ADDER_MSBs : bit_vector(2 downto 0);
signal RD_PULSE : bit;
signal ROLL_OVER : bit;
signal HISTORY_REG : bit_vector(1 downto 0);
signal RD_In : std_logic;
signal UP, DOWN : std_logic;
signal PHASE_DECREASE : std_logic;
signal PHASE_INCREASE : std_logic;
signal HI_STOP, LOW_STOP : std_logic;
signal PER_CNT : unsigned (7 downto 0);
signal ADDER_IN : unsigned (7 downto 0);
signal ADDER_MSBs : std_logic_vector(2 downto 0);
signal RD_PULSE : std_logic;
signal ROLL_OVER : std_logic;
signal HISTORY_REG : std_logic_vector(1 downto 0);
signal ERROR_HISTORY : integer range 0 to 2;
begin
INPORT: process
@@ -172,9 +172,9 @@ begin
PER_CNT <= "10000000"; -- Initial value is 128.
elsif CLK = '1' and CLK' event then
if UP = '1' then
PER_CNT <= PER_CNT + '1';
PER_CNT <= PER_CNT + 1;
elsif DOWN = '1' then
PER_CNT <= PER_CNT - '1';
PER_CNT <= PER_CNT - 1;
end if;
end if;
end process PERIOD_CNT;
@@ -186,9 +186,9 @@ begin
-- of the PLL in read from disk mode. It should be a good solution concer-
-- ning alternative read write cycles.
"10000000" when DISK_RWn = '0' else -- Nominal value for write to disk.
PER_CNT + PHASE_CORR when PHASE_INCREASE = '1' else -- Phase lags.
PER_CNT - PHASE_CORR when PHASE_DECREASE = '1' else -- Phase leeds.
PER_CNT; -- No phase correction;
(PER_CNT + PHASE_CORR) when PHASE_INCREASE = '1' else -- Phase lags.
(PER_CNT - PHASE_CORR) when PHASE_DECREASE = '1' else -- Phase leeds.
(PER_CNT); -- No phase correction;
ADDER: process(RESETn, CLK, DDEn, HDTYPE)
-- Clock adjustment: The clock cycle is 62.5ns for the 16MHz system clock.
@@ -200,7 +200,8 @@ begin
-- The adder rolls over every 2us for DDEn = 0 and HDTYPE = 0.
-- The adder rolls over every 1us for DDEn = 0 and HDTYPE = 1.
-- The given times are the half of a data period time in MFM or FM.
variable ADDER_DATA : std_logic_vector(12 downto 0);
variable ADDER_DATA : unsigned (12 downto 0);
variable cat : std_logic_vector(1 downto 0) := "00";
begin
if RESETn = '0' then
ADDER_DATA := (others => '0');
@@ -208,15 +209,16 @@ begin
ADDER_DATA := ADDER_DATA + ADDER_IN;
end if;
--
case DDEn & HDTYPE is
cat := DDEn & HDTYPE;
case cat is
when "01" => -- MFM mode using HD disks, results in 1us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(10 downto 8));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(10 downto 8));
when "00" => -- MFM mode using DD disks, results in 2us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(11 downto 9));
when "11" => -- FM mode using HD disks, results in 2us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(11 downto 9));
when "10" => -- FM mode using DD disks, results in 4us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(12 downto 10));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(12 downto 10));
end case;
end process ADDER;
@@ -285,7 +287,7 @@ begin
FREQUENCY_DECODER: process(RESETn, CLK, HI_STOP, LOW_STOP)
-- The frequency decoder controls the period of the data inspection window respective to the
-- ERROR_HISTORY for the 11 bit adder is as follows:
-- ERROR_HISTORY for the 11 std_logic adder is as follows:
-- ERROR_HISTORY = 0:
-- -> no correction necessary <-
-- ERROR_HISTORY = 1:
@@ -294,9 +296,9 @@ begin
-- ERROR_HISTORY = 2:
-- MSBs input: 7 6 5 4 3 2 1 0
-- Correction output: -4 -3 -2 -1 +1 +2 +3 +4
-- The most significant bit of the FREQ_AMOUNT controls incrementation or decrementation
-- The most significant std_logic of the FREQ_AMOUNT controls incrementation or decrementation
-- of the adder (0 is up).
variable FREQ_AMOUNT: std_logic_vector(3 downto 0);
variable FREQ_AMOUNT: unsigned (3 downto 0);
begin
if RESETn = '0' then
FREQ_AMOUNT := "0000";
@@ -329,7 +331,7 @@ begin
FREQ_AMOUNT := "0000";
end case;
elsif FREQ_AMOUNT(2 downto 0) > "000" then
FREQ_AMOUNT := FREQ_AMOUNT - '1'; -- Modify the frequency amount register.
FREQ_AMOUNT := FREQ_AMOUNT - 1; -- Modify the frequency amount register.
end if;
end if;
--
@@ -348,13 +350,13 @@ begin
end process FREQUENCY_DECODER;
PHASE_DECODER: process(RESETn, CLK)
-- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant bit
-- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant std_logic
-- of PHASE_AMOUNT indicates with a '0', that the next rollover should appear earlier. In case of a
-- phase lag, the next rollover should come later (indicated by a '1' of the most significant bit of
-- phase lag, the next rollover should come later (indicated by a '1' of the most significant std_logic of
-- PHASE_AMOUNT).
-- This implementation gives the freedom to adjust the phase amount individually for every mode
-- depending on DDEn and HDTYPE.
variable PHASE_AMOUNT: std_logic_vector(5 downto 0);
variable PHASE_AMOUNT: unsigned (5 downto 0);
begin
if RESETn = '0' then
PHASE_AMOUNT := "000000";

250
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_pkg.vhd
View File

@@ -64,169 +64,169 @@ package WF1772IP_PKG is
-- component declarations:
component WF1772IP_AM_DETECTOR
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
DATA : in bit;
DATA_STRB : in bit;
ID_AM : out bit;
DATA_AM : out bit;
DDATA_AM : out bit
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
DATA : in std_logic;
DATA_STRB : in std_logic;
ID_AM : out std_logic;
DATA_AM : out std_logic;
DDATA_AM : out std_logic
);
end component;
component WF1772IP_CONTROL
port(
CLK : in bit;
RESETn : in bit;
A1, A0 : in bit;
RWn : in bit;
CSn : in bit;
DDEn : in bit;
DR : in bit_vector(7 downto 0);
CLK : in std_logic;
RESETn : in std_logic;
A1, A0 : in std_logic;
RWn : in std_logic;
CSn : in std_logic;
DDEn : in std_logic;
DR : in std_logic_vector(7 downto 0);
CMD : in std_logic_vector(7 downto 0);
DSR : in std_logic_vector(7 downto 0);
TR : in std_logic_vector(7 downto 0);
SR : in std_logic_vector(7 downto 0);
MO : out bit;
WR_PR : out bit;
SPINUP_RECTYPE : out bit;
SEEK_RNF : out bit;
CRC_ERRFLAG : out bit;
LOST_DATA_TR00 : out bit;
DRQ : out bit;
DRQ_IPn : out bit;
BUSY : out bit;
AM_2_DISK : out bit;
ID_AM : in bit;
DATA_AM : in bit;
DDATA_AM : in bit;
CRC_ERR : in bit;
CRC_PRES : out bit;
TR_PRES : out bit;
TR_CLR : out bit;
TR_INC : out bit;
TR_DEC : out bit;
SR_LOAD : out bit;
SR_INC : out bit;
MO : out std_logic;
WR_PR : out std_logic;
SPINUP_RECTYPE : out std_logic;
SEEK_RNF : out std_logic;
CRC_ERRFLAG : out std_logic;
LOST_DATA_TR00 : out std_logic;
DRQ : out std_logic;
DRQ_IPn : out std_logic;
BUSY : out std_logic;
AM_2_DISK : out std_logic;
ID_AM : in std_logic;
DATA_AM : in std_logic;
DDATA_AM : in std_logic;
CRC_ERR : in std_logic;
CRC_PRES : out std_logic;
TR_PRES : out std_logic;
TR_CLR : out std_logic;
TR_INC : out std_logic;
TR_DEC : out std_logic;
SR_LOAD : out std_logic;
SR_INC : out std_logic;
TRACK_NR : out std_logic_vector(7 downto 0);
DR_CLR : out bit;
DR_LOAD : out bit;
SHFT_LOAD_SD : out bit;
SHFT_LOAD_ND : out bit;
CRC_2_DISK : out bit;
DSR_2_DISK : out bit;
FF_2_DISK : out bit;
PRECOMP_EN : out bit;
DATA_STRB : in bit;
DISK_RWn : out bit;
WPRTn : in bit;
TRACK00n : in bit;
IPn : in bit;
DIRC : out bit;
STEP : out bit;
WG : out bit;
INTRQ : out bit
DR_CLR : out std_logic;
DR_LOAD : out std_logic;
SHFT_LOAD_SD : out std_logic;
SHFT_LOAD_ND : out std_logic;
CRC_2_DISK : out std_logic;
DSR_2_DISK : out std_logic;
FF_2_DISK : out std_logic;
PRECOMP_EN : out std_logic;
DATA_STRB : in std_logic;
DISK_RWn : out std_logic;
WPRTn : in std_logic;
TRACK00n : in std_logic;
IPn : in std_logic;
DIRC : out std_logic;
STEP : out std_logic;
WG : out std_logic;
INTRQ : out std_logic
);
end component;
component WF1772IP_CRC_LOGIC
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
DISK_RWn : in bit;
ID_AM : in bit;
DATA_AM : in bit;
DDATA_AM : in bit;
SD : in bit;
CRC_STRB : in bit;
CRC_2_DISK : in bit;
CRC_PRES : in bit;
CRC_SDOUT : out bit;
CRC_ERR : out bit
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
DISK_RWn : in std_logic;
ID_AM : in std_logic;
DATA_AM : in std_logic;
DDATA_AM : in std_logic;
SD : in std_logic;
CRC_STRB : in std_logic;
CRC_2_DISK : in std_logic;
CRC_PRES : in std_logic;
CRC_SDOUT : out std_logic;
CRC_ERR : out std_logic
);
end component;
component WF1772IP_DIGITAL_PLL
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
HDTYPE : in bit;
DISK_RWn : in bit;
RDn : in bit;
PLL_D : out bit;
PLL_DSTRB : out bit
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic;
DISK_RWn : in std_logic;
RDn : in std_logic;
PLL_D : out std_logic;
PLL_DSTRB : out std_logic
);
end component;
component WF1772IP_REGISTERS
port(
CLK : in bit;
RESETn : in bit;
CSn : in bit;
ADR : in bit_vector(1 downto 0);
RWn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
CSn : in std_logic;
ADR : in std_logic_vector(1 downto 0);
RWn : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (7 downto 0);
DATA_EN : out bit;
DATA_EN : out std_logic;
CMD : out std_logic_vector(7 downto 0);
SR : out std_logic_vector(7 downto 0);
TR : out std_logic_vector(7 downto 0);
DSR : out std_logic_vector(7 downto 0);
DR : out bit_vector(7 downto 0);
SD_R : in bit;
DATA_STRB : in bit;
DR_CLR : in bit;
DR_LOAD : in bit;
TR_PRES : in bit;
TR_CLR : in bit;
TR_INC : in bit;
TR_DEC : in bit;
DR : out std_logic_vector(7 downto 0);
SD_R : in std_logic;
DATA_STRB : in std_logic;
DR_CLR : in std_logic;
DR_LOAD : in std_logic;
TR_PRES : in std_logic;
TR_CLR : in std_logic;
TR_INC : in std_logic;
TR_DEC : in std_logic;
TRACK_NR : in std_logic_vector(7 downto 0);
SR_LOAD : in bit;
SR_INC : in bit;
SHFT_LOAD_SD : in bit;
SHFT_LOAD_ND : in bit;
MOTOR_ON : in bit;
WRITE_PROTECT : in bit;
SPINUP_RECTYPE : in bit;
SEEK_RNF : in bit;
CRC_ERRFLAG : in bit;
LOST_DATA_TR00 : in bit;
DRQ : in bit;
DRQ_IPn : in bit;
BUSY : in bit;
DDEn : in bit
SR_LOAD : in std_logic;
SR_INC : in std_logic;
SHFT_LOAD_SD : in std_logic;
SHFT_LOAD_ND : in std_logic;
MOTOR_ON : in std_logic;
WRITE_PROTECT : in std_logic;
SPINUP_RECTYPE : in std_logic;
SEEK_RNF : in std_logic;
CRC_ERRFLAG : in std_logic;
LOST_DATA_TR00 : in std_logic;
DRQ : in std_logic;
DRQ_IPn : in std_logic;
BUSY : in std_logic;
DDEn : in std_logic
);
end component;
component WF1772IP_TRANSCEIVER
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
HDTYPE : in bit;
ID_AM : in bit;
DATA_AM : in bit;
DDATA_AM : in bit;
SHFT_LOAD_SD : in bit;
DR : in bit_vector(7 downto 0);
PRECOMP_EN : in bit;
AM_TYPE : in bit;
AM_2_DISK : in bit;
CRC_2_DISK : in bit;
DSR_2_DISK : in bit;
FF_2_DISK : in bit;
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic;
ID_AM : in std_logic;
DATA_AM : in std_logic;
DDATA_AM : in std_logic;
SHFT_LOAD_SD : in std_logic;
DR : in std_logic_vector(7 downto 0);
PRECOMP_EN : in std_logic;
AM_TYPE : in std_logic;
AM_2_DISK : in std_logic;
CRC_2_DISK : in std_logic;
DSR_2_DISK : in std_logic;
FF_2_DISK : in std_logic;
SR_SDOUT : in std_logic;
CRC_SDOUT : in bit;
WRn : out bit;
PLL_DSTRB : in bit;
PLL_D : in bit;
WDATA : out bit;
DATA_STRB : out bit;
SD_R : out bit
CRC_SDOUT : in std_logic;
WRn : out std_logic;
PLL_DSTRB : in std_logic;
PLL_D : in std_logic;
WDATA : out std_logic;
DATA_STRB : out std_logic;
SD_R : out std_logic
);
end component;
end WF1772IP_PKG;

76
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_registers.vhd
View File

@@ -59,65 +59,65 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_REGISTERS is
port(
-- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Bus interface:
CSn : in bit;
ADR : in bit_vector(1 downto 0);
RWn : in bit;
CSn : in std_logic;
ADR : in std_logic_vector(1 downto 0);
RWn : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (7 downto 0);
DATA_EN : out bit;
DATA_EN : out std_logic;
-- FDC data:
CMD : out std_logic_vector(7 downto 0); -- Command register.
SR : out std_logic_vector(7 downto 0); -- Sector register.
TR : out std_logic_vector(7 downto 0); -- Track register.
DSR : out std_logic_vector(7 downto 0); -- Data shift register.
DR : out bit_vector(7 downto 0); -- Data register.
DR : out std_logic_vector(7 downto 0); -- Data register.
-- Serial data and clock strobes (in and out):
DATA_STRB : in bit; -- Strobe for the incoming data.
SD_R : in bit; -- Serial data input.
DATA_STRB : in std_logic; -- Strobe for the incoming data.
SD_R : in std_logic; -- Serial data input.
-- DATA register control:
DR_CLR : in bit; -- Clear.
DR_LOAD : in bit; -- LOAD.
DR_CLR : in std_logic; -- Clear.
DR_LOAD : in std_logic; -- LOAD.
-- Track register controls:
TR_PRES : in bit; -- Set x"FF".
TR_CLR : in bit; -- Clear.
TR_INC : in bit; -- Increment.
TR_DEC : in bit; -- Decrement.
TR_PRES : in std_logic; -- Set x"FF".
TR_CLR : in std_logic; -- Clear.
TR_INC : in std_logic; -- Increment.
TR_DEC : in std_logic; -- Decrement.
-- Sector register control:
TRACK_NR : in std_logic_vector(7 downto 0);
SR_LOAD : in bit; -- Load.
SR_INC : in bit; -- Increment.
SR_LOAD : in std_logic; -- Load.
SR_INC : in std_logic; -- Increment.
-- Shift register control:
SHFT_LOAD_SD : in bit;
SHFT_LOAD_ND : in bit;
SHFT_LOAD_SD : in std_logic;
SHFT_LOAD_ND : in std_logic;
-- Status register stuff
MOTOR_ON : in bit;
WRITE_PROTECT : in bit;
SPINUP_RECTYPE : in bit; -- Disk is on speed / data mark status.
SEEK_RNF : in bit; -- Seek error / record not found status flag.
CRC_ERRFLAG : in bit; -- CRC status flag.
LOST_DATA_TR00 : in bit;
DRQ : in bit;
DRQ_IPn : in bit;
BUSY : in bit;
MOTOR_ON : in std_logic;
WRITE_PROTECT : in std_logic;
SPINUP_RECTYPE : in std_logic; -- Disk is on speed / data mark status.
SEEK_RNF : in std_logic; -- Seek error / record not found status flag.
CRC_ERRFLAG : in std_logic; -- CRC status flag.
LOST_DATA_TR00 : in std_logic;
DRQ : in std_logic;
DRQ_IPn : in std_logic;
BUSY : in std_logic;
-- Others:
DDEn : in bit
DDEn : in std_logic
);
end WF1772IP_REGISTERS;
@@ -131,7 +131,7 @@ signal DATA_REG : std_logic_vector(7 downto 0);
signal COMMAND_REG : std_logic_vector(7 downto 0);
signal SECTOR_REG : std_logic_vector(7 downto 0);
signal TRACK_REG : std_logic_vector(7 downto 0);
signal STATUS_REG : bit_vector(7 downto 0);
signal STATUS_REG : std_logic_vector(7 downto 0);
signal SD_R_I : std_logic;
begin
-- Type conversion To_Std_Logic:
@@ -176,7 +176,7 @@ begin
end if;
end process DATAREG;
-- Data register buffered for further data processing.
DR <= To_BitVector(DATA_REG);
DR <= (DATA_REG);
SECTORREG: process(RESETn, CLK)
begin
@@ -190,7 +190,7 @@ begin
-- 'Read Address'.
SECTOR_REG <= TRACK_NR;
elsif SR_INC = '1' then
SECTOR_REG <= SECTOR_REG + '1';
SECTOR_REG <= std_logic_vector(unsigned(SECTOR_REG) + 1);
end if;
end if;
end process SECTORREG;
@@ -208,9 +208,9 @@ begin
elsif TR_CLR = '1' then
TRACK_REG <= (others => '0'); -- Reset the track register.
elsif TR_INC = '1' then
TRACK_REG <= TRACK_REG + '1'; -- Increment register contents.
TRACK_REG <= std_logic_vector(unsigned(TRACK_REG) + 1); -- Increment register contents.
elsif TR_DEC = '1' then
TRACK_REG <= TRACK_REG - '1'; -- Decrement register contents.
TRACK_REG <= std_logic_vector(unsigned(TRACK_REG) - 1); -- Decrement register contents.
end if;
end if;
end process TRACKREG;
@@ -253,12 +253,12 @@ begin
-- The register data after writing to the track register is valid at least
-- after 32us in FM mode and after 16us in MFM mode.
-- Read from status register. This register is read only:
-- Be aware, that the status register data bits 7 to 1 after writing
-- Be aware, that the status register data std_logics 7 to 1 after writing
-- the command regsiter are valid at least after 64us in FM mode or 32us in MFM mode and
-- the bit 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode.
-- the std_logic 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode.
DATA_OUT <= TRACK_REG when CSn = '0' and ADR = "01" and RWn = '1' else
SECTOR_REG when CSn = '0' and ADR = "10" and RWn = '1' else
DATA_REG when CSn = '0' and ADR = "11" and RWn = '1' else
To_StdLogicVector(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0');
(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0');
DATA_EN <= '1' when CSn = '0' and RWn = '1' else '0';
end architecture BEHAVIOR;

78
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_top.vhd
View File

@@ -69,60 +69,60 @@ use work.WF1772IP_PKG.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_TOP is
port (
CLK : in bit; -- 16MHz clock!
MRn : in bit;
CSn : in bit;
RWn : in bit;
A1, A0 : in bit;
CLK : in std_logic; -- 16MHz clock!
MRn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA : inout std_logic_vector(7 downto 0);
RDn : in bit;
TR00n : in bit;
IPn : in bit;
WPRTn : in bit;
DDEn : in bit;
HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks.
MO : out bit;
WG : out bit;
WD : out bit;
STEP : out bit;
DIRC : out bit;
DRQ : out bit;
INTRQ : out bit
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks.
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end entity WF1772IP_TOP;
architecture STRUCTURE of WF1772IP_TOP is
component WF1772IP_TOP_SOC
port (
CLK : in bit;
RESETn : in bit;
CSn : in bit;
RWn : in bit;
A1, A0 : in bit;
CLK : in std_logic;
RESETn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
RDn : in bit;
TR00n : in bit;
IPn : in bit;
WPRTn : in bit;
DDEn : in bit;
HDTYPE : in bit;
MO : out bit;
WG : out bit;
WD : out bit;
STEP : out bit;
DIRC : out bit;
DRQ : out bit;
INTRQ : out bit
DATA_EN : out std_logic;
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic;
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end component;
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_EN : bit;
signal DATA_EN : std_logic;
begin
DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');

124
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_top_soc.vhd
View File

@@ -73,82 +73,82 @@ use work.WF1772IP_PKG.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_TOP_SOC is
port (
CLK : in bit; -- 16MHz clock!
RESETn : in bit;
CSn : in bit;
RWn : in bit;
A1, A0 : in bit;
CLK : in std_logic; -- 16MHz clock!
RESETn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
RDn : in bit;
TR00n : in bit;
IPn : in bit;
WPRTn : in bit;
DDEn : in bit;
HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks.
MO : out bit;
WG : out bit;
WD : out bit;
STEP : out bit;
DIRC : out bit;
DRQ : out bit;
INTRQ : out bit
DATA_EN : out std_logic;
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks.
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end entity WF1772IP_TOP_SOC;
architecture STRUCTURE of WF1772IP_TOP_SOC is
signal DATA_OUT_REG : std_logic_vector(7 downto 0);
signal DATA_EN_REG : bit;
signal DATA_EN_REG : std_logic;
signal CMD_I : std_logic_vector(7 downto 0);
signal DR_I : bit_vector(7 downto 0);
signal DR_I : std_logic_vector(7 downto 0);
signal DSR_I : std_logic_vector(7 downto 0);
signal TR_I : std_logic_vector(7 downto 0);
signal SR_I : std_logic_vector(7 downto 0);
signal ID_AM_I : bit;
signal DATA_AM_I : bit;
signal DDATA_AM_I : bit;
signal AM_TYPE_I : bit;
signal AM_2_DISK_I : bit;
signal DATA_STRB_I : bit;
signal BUSY_I : bit;
signal DRQ_I : bit;
signal DRQ_IPn_I : bit;
signal LD_TR00_I : bit;
signal SP_RT_I : bit;
signal SEEK_RNF_I : bit;
signal WR_PR_I : bit;
signal MO_I : bit;
signal PLL_DSTRB_I : bit;
signal PLL_D_I : bit;
signal CRC_SD_I : bit;
signal CRC_ERR_I : bit;
signal CRC_PRES_I : bit;
signal CRC_ERRFLAG_I : bit;
signal SD_R_I : bit;
signal CRC_SDOUT_I : bit;
signal SHFT_LOAD_SD_I : bit;
signal SHFT_LOAD_ND_I : bit;
signal WR_In : bit;
signal TR_PRES_I : bit;
signal TR_CLR_I : bit;
signal TR_INC_I : bit;
signal TR_DEC_I : bit;
signal SR_LOAD_I : bit;
signal SR_INC_I : bit;
signal DR_CLR_I : bit;
signal DR_LOAD_I : bit;
signal ID_AM_I : std_logic;
signal DATA_AM_I : std_logic;
signal DDATA_AM_I : std_logic;
signal AM_TYPE_I : std_logic;
signal AM_2_DISK_I : std_logic;
signal DATA_STRB_I : std_logic;
signal BUSY_I : std_logic;
signal DRQ_I : std_logic;
signal DRQ_IPn_I : std_logic;
signal LD_TR00_I : std_logic;
signal SP_RT_I : std_logic;
signal SEEK_RNF_I : std_logic;
signal WR_PR_I : std_logic;
signal MO_I : std_logic;
signal PLL_DSTRB_I : std_logic;
signal PLL_D_I : std_logic;
signal CRC_SD_I : std_logic;
signal CRC_ERR_I : std_logic;
signal CRC_PRES_I : std_logic;
signal CRC_ERRFLAG_I : std_logic;
signal SD_R_I : std_logic;
signal CRC_SDOUT_I : std_logic;
signal SHFT_LOAD_SD_I : std_logic;
signal SHFT_LOAD_ND_I : std_logic;
signal WR_In : std_logic;
signal TR_PRES_I : std_logic;
signal TR_CLR_I : std_logic;
signal TR_INC_I : std_logic;
signal TR_DEC_I : std_logic;
signal SR_LOAD_I : std_logic;
signal SR_INC_I : std_logic;
signal DR_CLR_I : std_logic;
signal DR_LOAD_I : std_logic;
signal TRACK_NR_I : std_logic_vector(7 downto 0);
signal CRC_2_DISK_I : bit;
signal DSR_2_DISK_I : bit;
signal FF_2_DISK_I : bit;
signal PRECOMP_EN_I : bit;
signal DISK_RWn_I : bit;
signal WDATA_I : bit;
signal CRC_2_DISK_I : std_logic;
signal DSR_2_DISK_I : std_logic;
signal FF_2_DISK_I : std_logic;
signal PRECOMP_EN_I : std_logic;
signal DISK_RWn_I : std_logic;
signal WDATA_I : std_logic;
begin
-- Three state data bus:
DATA_OUT <= DATA_OUT_REG when DATA_EN_REG = '1' else (others => '0');
@@ -160,7 +160,7 @@ begin
DRQ <= DRQ_I;
-- Write deleted data address mark in MFM mode in 'Write Sector' command in
-- case of asserted command bit 0.
-- case of asserted command std_logic 0.
AM_TYPE_I <= '0' when CMD_I(7 downto 5) = "101" and CMD_I(0) = '1' else '1';
-- The CRC unit is used during read from disk and write to disk.

90
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd
View File

@@ -65,44 +65,44 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_TRANSCEIVER is
port(
-- System control
CLK : in bit; -- must be 16MHz
RESETn : in bit;
CLK : in std_logic; -- must be 16MHz
RESETn : in std_logic;
-- Data and Control:
HDTYPE : in bit; -- Floppy type HD or DD.
DDEn : in bit; -- Double density select (FM or MFM).
ID_AM : in bit; -- ID addressmark strobe.
HDTYPE : in std_logic; -- Floppy type HD or DD.
DDEn : in std_logic; -- Double density select (FM or MFM).
ID_AM : in std_logic; -- ID addressmark strobe.
DATA_AM : in Bit; -- Data addressmark strobe.
DDATA_AM : in Bit; -- Deleted data addressmark strobe.
SHFT_LOAD_SD : in bit; -- Indication for shift register load time.
DR : in bit_vector(7 downto 0); -- Content of the data register.
SHFT_LOAD_SD : in std_logic; -- Indication for shift register load time.
DR : in std_logic_vector(7 downto 0); -- Content of the data register.
-- Data strobes:
PLL_DSTRB : in bit; -- Clock strobe for RD serial data input.
DATA_STRB : buffer bit;
PLL_DSTRB : in std_logic; -- Clock strobe for RD serial data input.
DATA_STRB : buffer std_logic;
-- Data strobe and data for the CRC during write operation:
WDATA : buffer bit;
WDATA : buffer std_logic;
-- Encoder (logic to disk):
PRECOMP_EN : in bit; -- control signal for MFM write precompensation.
AM_TYPE : in bit; -- Write deleted address mark in MFM mode when 0.
AM_2_DISK : in bit;
DSR_2_DISK : in bit;
FF_2_DISK : in bit;
CRC_2_DISK : in bit;
PRECOMP_EN : in std_logic; -- control signal for MFM write precompensation.
AM_TYPE : in std_logic; -- Write deleted address mark in MFM mode when 0.
AM_2_DISK : in std_logic;
DSR_2_DISK : in std_logic;
FF_2_DISK : in std_logic;
CRC_2_DISK : in std_logic;
SR_SDOUT : in std_logic; -- encoder's data input from the shift register (serial).
CRC_SDOUT : in bit; -- encoder's data input from the CRC unit (serial).
WRn : out bit; -- write output for the MFM drive containing clock and data.
CRC_SDOUT : in std_logic; -- encoder's data input from the CRC unit (serial).
WRn : out std_logic; -- write output for the MFM drive containing clock and data.
-- Decoder (disk to logic):
PLL_D : in bit; -- Serial data input.
SD_R : out bit -- Serial (decoded) data output.
PLL_D : in std_logic; -- Serial data input.
SD_R : out std_logic -- Serial (decoded) data output.
);
end WF1772IP_TRANSCEIVER;
@@ -117,17 +117,17 @@ signal PRECOMP : PRECOMP_VALUES;
signal DEC_STATE : DEC_STATES;
signal NEXT_DEC_STATE : DEC_STATES;
signal FM_In : bit;
signal FM_In : std_logic;
signal CLKMASK : bit; -- Control for suppression of FM clock transitions.
signal CLKMASK : std_logic; -- Control for suppression of FM clock transitions.
signal MFM_10_STRB : bit;
signal MFM_01_STRB : bit;
signal MFM_10_STRB : std_logic;
signal MFM_01_STRB : std_logic;
signal WR_CNT : std_logic_vector(3 downto 0);
signal MFM_In : bit;
signal MFM_In : std_logic;
signal AM_SHFT : bit_vector(31 downto 0);
signal AM_SHFT : std_logic_vector(31 downto 0);
begin
-- ####################### encoder stuff ###########################
@@ -157,7 +157,7 @@ begin
-- Input multiplexer:
WDATA <= AM_SHFT(31) when AM_2_DISK = '1' else -- Address mark data data.
To_Bit(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data.
(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data.
CRC_SDOUT when CRC_2_DISK = '1' else -- CRC data.
'1' when FF_2_DISK = '1' else '0'; -- Write zeros is default.
@@ -168,10 +168,10 @@ begin
CLK_MASK: process(CLK)
-- This part of software controls the suppression of the clock pulses
-- during transmission of several FM special characters. During writing
-- 'normal' data to the disk, only 8 mask bits of the shift register are
-- used. During writing MFM sync and address mark bits, the register is
-- used with 32 mask bits.
variable MASK_SHFT : bit_vector(23 downto 0);
-- 'normal' data to the disk, only 8 mask std_logics of the shift register are
-- used. During writing MFM sync and address mark std_logics, the register is
-- used with 32 mask std_logics.
variable MASK_SHFT : std_logic_vector(23 downto 0);
variable LOCK : boolean;
begin
if CLK = '1' and CLK' event then
@@ -189,8 +189,8 @@ begin
end case;
elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode.
case DR is
when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between bits 4 and 5.
when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between bits 3 and 4.
when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between std_logics 4 and 5.
when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between std_logics 3 and 4.
when others => MASK_SHFT := x"FFFFFF"; -- Normal data.
end case;
elsif AM_2_DISK = '1' and DDEn = '1' and LOCK = false then -- FM mode.
@@ -212,14 +212,14 @@ begin
FM_ENCODER: process (RESETn, DATA_STRB, CLK)
-- For DD type floppies the data rate is 125kBps. Therefore there are 128 16-MHz clocks cycles
-- per FM bit.
-- per FM std_logic.
-- For HD type floppies the data rate is 250kBps. Therefore there are 64 16-MHz clocks cycles
-- per FM bit.
-- per FM std_logic.
-- The FM write pulse width is 1.375us for DD and 0.750us HD type floppies.
-- This process provides the FM encoded signal. The first pulse is in any case the clock
-- pulse and the second pulse is due to data. The FM encoding is very simple and therefore
-- self explaining.
variable CNT : std_logic_vector(7 downto 0);
variable CNT : unsigned (7 downto 0);
begin
if RESETn = '0' then
FM_In <= '1';
@@ -230,7 +230,7 @@ begin
if DATA_STRB = '1' then
CNT := x"00";
else
CNT := CNT + '1';
CNT := CNT + 1;
end if;
-- The flux reversal pulses are centered between the DATA_STRB pulses.
-- In detail: the clock pulse appears in the middle of the first half
@@ -318,7 +318,7 @@ begin
-- WRITEPATTERN(2) is the previous WDATA.
-- WRITEPATTERN(1) is the current WDATA to be sent.
-- WRITEPATTERN(0) is the next WDATA to be sent.
variable WRITEPATTERN : bit_vector(3 downto 0);
variable WRITEPATTERN : std_logic_vector(3 downto 0);
begin
if RESETn = '0' then
PRECOMP <= NOMINAL;
@@ -343,14 +343,14 @@ begin
MFM_STROBES: process (RESETn, DATA_STRB, CLK)
-- For the MFM frequency is 250 kBps for DD type floppies, there are 64
-- 16 MHz clock cycles per MFM bit and for HD type floppies, which have
-- 500 kBps there are 32 16MHz clock pulses for one MFM bit.
-- 16 MHz clock cycles per MFM std_logic and for HD type floppies, which have
-- 500 kBps there are 32 16MHz clock pulses for one MFM std_logic.
-- The MFM state machine (Moore) switches on the DATA_STRB.
-- During one cycle there are the two further strobes MFM_10_STRB and
-- MFM_01_STRB which control the MFM output in the process MFM_WR_OUT.
-- The strobes are centered in the middle of the first half and in the
-- middle of the second half of the DATA_STRB cycle.
variable CNT : std_logic_vector(5 downto 0);
variable CNT : unsigned (5 downto 0);
begin
if RESETn = '0' then
CNT := "000000";
@@ -358,7 +358,7 @@ begin
if DATA_STRB = '1' then
CNT := (others => '0');
else
CNT := CNT + '1';
CNT := CNT + 1;
end if;
if HDTYPE = '1' then
case CNT is
@@ -397,7 +397,7 @@ begin
-- WD177x floppy disc controller.
MFM_WR_TIMING: process(RESETn, CLK)
variable CLKMASK_MFM : bit;
variable CLKMASK_MFM : std_logic;
begin
if RESETn = '0' then
WR_CNT <= x"F";
@@ -413,7 +413,7 @@ begin
elsif MFM_STATE = B_01 and MFM_01_STRB = '1' then
WR_CNT <= x"0";
elsif WR_CNT < x"F" then
WR_CNT <= WR_CNT + '1';
WR_CNT <= std_logic_vector(unsigned(WR_CNT) + 1);
end if;
end if;
end process MFM_WR_TIMING;

46
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_gpio.vhd
View File

@@ -56,42 +56,42 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_GPIO is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Timer controls:
AER_4 : out bit;
AER_3 : out bit;
AER_4 : out std_logic;
AER_3 : out std_logic;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_OUT_EN : buffer bit_vector(7 downto 0);
GP_INT : out bit_vector(7 downto 0)
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_OUT_EN : buffer std_logic_vector(7 downto 0);
GP_INT : out std_logic_vector(7 downto 0)
);
end entity WF68901IP_GPIO;
architecture BEHAVIOR of WF68901IP_GPIO is
signal GPDR : bit_vector(7 downto 0);
signal DDR : bit_vector(7 downto 0);
signal AER : bit_vector(7 downto 0);
signal GPDR_I : bit_vector(7 downto 0);
signal GPDR : std_logic_vector(7 downto 0);
signal DDR : std_logic_vector(7 downto 0);
signal AER : std_logic_vector(7 downto 0);
signal GPDR_I : std_logic_vector(7 downto 0);
begin
-- These two bits control the timers A and B pulse width operation and the
-- These two std_logics control the timers A and B pulse width operation and the
-- timers A and B event count operation.
AER_4 <= AER(4);
AER_3 <= AER(3);
@@ -120,7 +120,7 @@ begin
end if;
end process GPIO_REGISTERS;
GPIP_OUT <= GPDR; -- Port outputs.
GPIP_OUT_EN <= DDR; -- The DDR is capable to control bitwise the GPIP.
GPIP_OUT_EN <= DDR; -- The DDR is capable to control std_logicwise the GPIP.
DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS <= "00010" else '0';
DATA_OUT <= DDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00010" else
AER when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00001" else
@@ -128,7 +128,7 @@ begin
P_GPDR: process(GPIP_IN, GPIP_OUT_EN, GPDR)
-- Read back control: Read the port pins, if the data direction is configured as input.
-- Read the respective GPDR register bit, if the data direction is configured as output.
-- Read the respective GPDR register std_logic, if the data direction is configured as output.
begin
for i in 7 downto 0 loop
if GPIP_OUT_EN(i) = '1' then -- Port is configured output.

104
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd
View File

@@ -58,48 +58,48 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_INTERRUPTS is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Interrupt control:
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Interrupt sources:
GP_INT : in bit_vector(7 downto 0);
GP_INT : in std_logic_vector(7 downto 0);
AER_4 : in bit;
AER_3 : in bit;
TAI : in bit;
TBI : in bit;
TA_PWM : in bit;
TB_PWM : in bit;
TIMER_A_INT : in bit;
TIMER_B_INT : in bit;
TIMER_C_INT : in bit;
TIMER_D_INT : in bit;
AER_4 : in std_logic;
AER_3 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
TA_PWM : in std_logic;
TB_PWM : in std_logic;
TIMER_A_INT : in std_logic;
TIMER_B_INT : in std_logic;
TIMER_C_INT : in std_logic;
TIMER_D_INT : in std_logic;
RCV_ERR : in bit;
TRM_ERR : in bit;
RCV_BUF_F : in bit;
TRM_BUF_E : in bit
RCV_ERR : in std_logic;
TRM_ERR : in std_logic;
RCV_BUF_F : in std_logic;
TRM_BUF_E : in std_logic
);
end entity WF68901IP_INTERRUPTS;
@@ -108,27 +108,27 @@ architecture BEHAVIOR of WF68901IP_INTERRUPTS is
type INT_STATES is (SCAN, REQUEST, VECTOR_OUT);
signal INT_STATE : INT_STATES;
-- The registers:
signal IERA : bit_vector(7 downto 0);
signal IERB : bit_vector(7 downto 0);
signal IPRA : bit_vector(7 downto 0);
signal IPRB : bit_vector(7 downto 0);
signal ISRA : bit_vector(7 downto 0);
signal ISRB : bit_vector(7 downto 0);
signal IMRA : bit_vector(7 downto 0);
signal IMRB : bit_vector(7 downto 0);
signal VR : bit_vector(7 downto 3);
signal IERA : std_logic_vector(7 downto 0);
signal IERB : std_logic_vector(7 downto 0);
signal IPRA : std_logic_vector(7 downto 0);
signal IPRB : std_logic_vector(7 downto 0);
signal ISRA : std_logic_vector(7 downto 0);
signal ISRB : std_logic_vector(7 downto 0);
signal IMRA : std_logic_vector(7 downto 0);
signal IMRB : std_logic_vector(7 downto 0);
signal VR : std_logic_vector(7 downto 3);
-- Interconnect:
signal VECT_NUMBER : bit_vector(7 downto 0);
signal INT_SRC : bit_vector(15 downto 0);
signal INT_SRC_EDGE : bit_vector(15 downto 0);
signal INT_ENA : bit_vector(15 downto 0);
signal INT_MASK : bit_vector(15 downto 0);
signal INT_PENDING : bit_vector(15 downto 0);
signal INT_SERVICE : bit_vector(15 downto 0);
signal INT_PASS : bit_vector(15 downto 0);
signal INT_OUT : bit_vector(15 downto 0);
signal GP_INT_4 : bit;
signal GP_INT_3 : bit;
signal VECT_NUMBER : std_logic_vector(7 downto 0);
signal INT_SRC : std_logic_vector(15 downto 0);
signal INT_SRC_EDGE : std_logic_vector(15 downto 0);
signal INT_ENA : std_logic_vector(15 downto 0);
signal INT_MASK : std_logic_vector(15 downto 0);
signal INT_PENDING : std_logic_vector(15 downto 0);
signal INT_SERVICE : std_logic_vector(15 downto 0);
signal INT_PASS : std_logic_vector(15 downto 0);
signal INT_OUT : std_logic_vector(15 downto 0);
signal GP_INT_4 : std_logic;
signal GP_INT_3 : std_logic;
begin
-- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin.
-- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated
@@ -162,7 +162,7 @@ begin
EDGE_ENA: process(RESETn, CLK)
-- These are the 16 edge detectors of the 16 interrupt input sources. This
-- process also provides the disabling or enabling via the IERA and IERB registers.
variable LOCK : bit_vector(15 downto 0);
variable LOCK : std_logic_vector(15 downto 0);
begin
if RESETn = '0' then
INT_SRC_EDGE <= x"0000";
@@ -234,7 +234,7 @@ begin
end if;
-- Pending register:
-- set and clear bit logic.
-- set and clear std_logic logic.
for i in 15 downto 8 loop
if INT_SRC_EDGE(i) = '1' then
IPRA(i-8) <= '1';
@@ -255,7 +255,7 @@ begin
end loop;
-- In-Service register:
-- Set bit logic, VR(3) is the service register enable.
-- Set std_logic logic, VR(3) is the service register enable.
for i in 15 downto 8 loop
if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
ISRA(i-8) <= '1';

334
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd
View File

@@ -60,203 +60,203 @@ use ieee.std_logic_1164.all;
package WF68901IP_PKG is
component WF68901IP_USART_TOP
port ( CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RC : in bit;
TC : in bit;
SI : in bit;
SO : out bit;
SO_EN : out bit;
RX_ERR_INT : out bit;
RX_BUFF_INT : out bit;
TX_ERR_INT : out bit;
TX_BUFF_INT : out bit;
RRn : out bit;
TRn : out bit
port ( CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
RX_ERR_INT : out std_logic;
RX_BUFF_INT : out std_logic;
TX_ERR_INT : out std_logic;
TX_BUFF_INT : out std_logic;
RRn : out std_logic;
TRn : out std_logic
);
end component;
component WF68901IP_USART_CTRL
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RX_SAMPLE : in bit;
RX_DATA : in bit_vector(7 downto 0);
TX_DATA : out bit_vector(7 downto 0);
SCR_OUT : out bit_vector(7 downto 0);
BF : in bit;
BE : in bit;
FE : in bit;
OE : in bit;
UE : in bit;
PE : in bit;
M_CIP : in bit;
FS_B : in bit;
TX_END : in bit;
CL : out bit_vector(1 downto 0);
ST : out bit_vector(1 downto 0);
FS_CLR : out bit;
RSR_READ : out bit;
TSR_READ : out bit;
UDR_READ : out bit;
UDR_WRITE : out bit;
LOOPBACK : out bit;
SDOUT_EN : out bit;
SD_LEVEL : out bit;
CLK_MODE : out bit;
RE : out bit;
TE : out bit;
P_ENA : out bit;
P_EOn : out bit;
SS : out bit;
BR : out bit
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
RX_SAMPLE : in std_logic;
RX_DATA : in std_logic_vector(7 downto 0);
TX_DATA : out std_logic_vector(7 downto 0);
SCR_OUT : out std_logic_vector(7 downto 0);
BF : in std_logic;
BE : in std_logic;
FE : in std_logic;
OE : in std_logic;
UE : in std_logic;
PE : in std_logic;
M_CIP : in std_logic;
FS_B : in std_logic;
TX_END : in std_logic;
CL : out std_logic_vector(1 downto 0);
ST : out std_logic_vector(1 downto 0);
FS_CLR : out std_logic;
RSR_READ : out std_logic;
TSR_READ : out std_logic;
UDR_READ : out std_logic;
UDR_WRITE : out std_logic;
LOOPBACK : out std_logic;
SDOUT_EN : out std_logic;
SD_LEVEL : out std_logic;
CLK_MODE : out std_logic;
RE : out std_logic;
TE : out std_logic;
P_ENA : out std_logic;
P_EOn : out std_logic;
SS : out std_logic;
BR : out std_logic
);
end component;
component WF68901IP_USART_TX
port (
CLK : in bit;
RESETn : in bit;
SCR : in bit_vector(7 downto 0);
TX_DATA : in bit_vector(7 downto 0);
SDATA_OUT : out bit;
TXCLK : in bit;
CL : in bit_vector(1 downto 0);
ST : in bit_vector(1 downto 0);
TE : in bit;
BR : in bit;
P_ENA : in bit;
P_EOn : in bit;
UDR_WRITE : in bit;
TSR_READ : in bit;
CLK_MODE : in bit;
TX_END : out bit;
UE : out bit;
BE : out bit
CLK : in std_logic;
RESETn : in std_logic;
SCR : in std_logic_vector(7 downto 0);
TX_DATA : in std_logic_vector(7 downto 0);
SDATA_OUT : out std_logic;
TXCLK : in std_logic;
CL : in std_logic_vector(1 downto 0);
ST : in std_logic_vector(1 downto 0);
TE : in std_logic;
BR : in std_logic;
P_ENA : in std_logic;
P_EOn : in std_logic;
UDR_WRITE : in std_logic;
TSR_READ : in std_logic;
CLK_MODE : in std_logic;
TX_END : out std_logic;
UE : out std_logic;
BE : out std_logic
);
end component;
component WF68901IP_USART_RX
port (
CLK : in bit;
RESETn : in bit;
SCR : in bit_vector(7 downto 0);
RX_SAMPLE : out bit;
RX_DATA : out bit_vector(7 downto 0);
RXCLK : in bit;
SDATA_IN : in bit;
CL : in bit_vector(1 downto 0);
ST : in bit_vector(1 downto 0);
P_ENA : in bit;
P_EOn : in bit;
CLK_MODE : in bit;
RE : in bit;
FS_CLR : in bit;
SS : in bit;
RSR_READ : in bit;
UDR_READ : in bit;
M_CIP : out bit;
FS_B : out bit;
BF : out bit;
OE : out bit;
PE : out bit;
FE : out bit
CLK : in std_logic;
RESETn : in std_logic;
SCR : in std_logic_vector(7 downto 0);
RX_SAMPLE : out std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RXCLK : in std_logic;
SDATA_IN : in std_logic;
CL : in std_logic_vector(1 downto 0);
ST : in std_logic_vector(1 downto 0);
P_ENA : in std_logic;
P_EOn : in std_logic;
CLK_MODE : in std_logic;
RE : in std_logic;
FS_CLR : in std_logic;
SS : in std_logic;
RSR_READ : in std_logic;
UDR_READ : in std_logic;
M_CIP : out std_logic;
FS_B : out std_logic;
BF : out std_logic;
OE : out std_logic;
PE : out std_logic;
FE : out std_logic
);
end component;
component WF68901IP_INTERRUPTS
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
GP_INT : in bit_vector(7 downto 0);
AER_4 : in bit;
AER_3 : in bit;
TAI : in bit;
TBI : in bit;
TA_PWM : in bit;
TB_PWM : in bit;
TIMER_A_INT : in bit;
TIMER_B_INT : in bit;
TIMER_C_INT : in bit;
TIMER_D_INT : in bit;
RCV_ERR : in bit;
TRM_ERR : in bit;
RCV_BUF_F : in bit;
TRM_BUF_E : in bit
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
GP_INT : in std_logic_vector(7 downto 0);
AER_4 : in std_logic;
AER_3 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
TA_PWM : in std_logic;
TB_PWM : in std_logic;
TIMER_A_INT : in std_logic;
TIMER_B_INT : in std_logic;
TIMER_C_INT : in std_logic;
TIMER_D_INT : in std_logic;
RCV_ERR : in std_logic;
TRM_ERR : in std_logic;
RCV_BUF_F : in std_logic;
TRM_BUF_E : in std_logic
);
end component;
component WF68901IP_GPIO
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
AER_4 : out bit;
AER_3 : out bit;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_OUT_EN : out bit_vector(7 downto 0);
GP_INT : out bit_vector(7 downto 0)
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
AER_4 : out std_logic;
AER_3 : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_OUT_EN : out std_logic_vector(7 downto 0);
GP_INT : out std_logic_vector(7 downto 0)
);
end component;
component WF68901IP_TIMERS
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
XTAL1 : in bit;
TAI : in bit;
TBI : in bit;
AER_4 : in bit;
AER_3 : in bit;
TA_PWM : out bit;
TB_PWM : out bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
TIMER_A_INT : out bit;
TIMER_B_INT : out bit;
TIMER_C_INT : out bit;
TIMER_D_INT : out bit
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
XTAL1 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
AER_4 : in std_logic;
AER_3 : in std_logic;
TA_PWM : out std_logic;
TB_PWM : out std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
TIMER_A_INT : out std_logic;
TIMER_B_INT : out std_logic;
TIMER_C_INT : out std_logic;
TIMER_D_INT : out std_logic
);
end component;

168
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_timers.vhd
View File

@@ -65,71 +65,71 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_TIMERS is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Timers and timer control:
XTAL1 : in bit; -- Use an oszillator instead of a quartz.
TAI : in bit;
TBI : in bit;
AER_4 : in bit;
AER_3 : in bit;
TA_PWM : out bit; -- Indicates, that timer A is in PWM mode (used in Interrupt logic).
TB_PWM : out bit; -- Indicates, that timer B is in PWM mode (used in Interrupt logic).
TAO : buffer bit;
TBO : buffer bit;
TCO : buffer bit;
TDO : buffer bit;
TIMER_A_INT : out bit;
TIMER_B_INT : out bit;
TIMER_C_INT : out bit;
TIMER_D_INT : out bit
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
AER_4 : in std_logic;
AER_3 : in std_logic;
TA_PWM : out std_logic; -- Indicates, that timer A is in PWM mode (used in Interrupt logic).
TB_PWM : out std_logic; -- Indicates, that timer B is in PWM mode (used in Interrupt logic).
TAO : buffer std_logic;
TBO : buffer std_logic;
TCO : buffer std_logic;
TDO : buffer std_logic;
TIMER_A_INT : out std_logic;
TIMER_B_INT : out std_logic;
TIMER_C_INT : out std_logic;
TIMER_D_INT : out std_logic
);
end entity WF68901IP_TIMERS;
architecture BEHAVIOR of WF68901IP_TIMERS is
signal XTAL1_S : bit;
signal XTAL_STRB : bit;
signal TACR : bit_vector(4 downto 0); -- Timer A control register.
signal TBCR : bit_vector(4 downto 0); -- Timer B control register.
signal TCDCR : bit_vector(5 downto 0); -- Timer C and D control register.
signal TADR : bit_vector(7 downto 0); -- Timer A data register.
signal TBDR : bit_vector(7 downto 0); -- Timer B data register.
signal TCDR : bit_vector(7 downto 0); -- Timer C data register.
signal TDDR : bit_vector(7 downto 0); -- Timer D data register.
signal TIMER_A : std_logic_vector(7 downto 0); -- Timer A count register.
signal TIMER_B : std_logic_vector(7 downto 0); -- Timer B count register.
signal TIMER_C : std_logic_vector(7 downto 0); -- Timer C count register.
signal TIMER_D : std_logic_vector(7 downto 0); -- Timer D count register.
signal TIMER_R_A : bit_vector(7 downto 0); -- Timer A readback register.
signal TIMER_R_B : bit_vector(7 downto 0); -- Timer B readback register.
signal TIMER_R_C : bit_vector(7 downto 0); -- Timer C readback register.
signal TIMER_R_D : bit_vector(7 downto 0); -- Timer D readback register.
signal A_CNTSTRB : bit;
signal B_CNTSTRB : bit;
signal C_CNTSTRB : bit;
signal D_CNTSTRB : bit;
signal TAI_I : bit;
signal TBI_I : bit;
signal TAI_STRB : bit; -- Strobe for the event counter mode.
signal TBI_STRB : bit; -- Strobe for the event counter mode.
signal TAO_I : bit; -- Timer A output signal.
signal TBO_I : bit; -- Timer A output signal.
signal XTAL1_S : std_logic;
signal XTAL_STRB : std_logic;
signal TACR : std_logic_vector(4 downto 0); -- Timer A control register.
signal TBCR : std_logic_vector(4 downto 0); -- Timer B control register.
signal TCDCR : std_logic_vector(5 downto 0); -- Timer C and D control register.
signal TADR : std_logic_vector(7 downto 0); -- Timer A data register.
signal TBDR : std_logic_vector(7 downto 0); -- Timer B data register.
signal TCDR : std_logic_vector(7 downto 0); -- Timer C data register.
signal TDDR : std_logic_vector(7 downto 0); -- Timer D data register.
signal TIMER_A : unsigned (7 downto 0); -- Timer A count register.
signal TIMER_B : unsigned (7 downto 0); -- Timer B count register.
signal TIMER_C : unsigned (7 downto 0); -- Timer C count register.
signal TIMER_D : unsigned (7 downto 0); -- Timer D count register.
signal TIMER_R_A : std_logic_vector (7 downto 0); -- Timer A readback register.
signal TIMER_R_B : std_logic_vector (7 downto 0); -- Timer B readback register.
signal TIMER_R_C : std_logic_vector (7 downto 0); -- Timer C readback register.
signal TIMER_R_D : std_logic_vector (7 downto 0); -- Timer D readback register.
signal A_CNTSTRB : std_logic;
signal B_CNTSTRB : std_logic;
signal C_CNTSTRB : std_logic;
signal D_CNTSTRB : std_logic;
signal TAI_I : std_logic;
signal TBI_I : std_logic;
signal TAI_STRB : std_logic; -- Strobe for the event counter mode.
signal TBI_STRB : std_logic; -- Strobe for the event counter mode.
signal TAO_I : std_logic; -- Timer A output signal.
signal TBO_I : std_logic; -- Timer A output signal.
begin
SYNC: process
-- This process provides a 'clean' XTAL1.
@@ -208,16 +208,16 @@ begin
elsif DSn = '0' and RWn = '1' and RS = "10010" then
READ_D := true;
elsif DSn = '1' and READ_A = true then
TIMER_R_A <= To_BitVector(TIMER_A);
TIMER_R_A <= std_logic_vector(TIMER_A);
READ_A := false;
elsif DSn = '1' and READ_B = true then
TIMER_R_B <= To_BitVector(TIMER_B);
TIMER_R_B <= std_logic_vector(TIMER_B);
READ_B := false;
elsif DSn = '1' and READ_C = true then
TIMER_R_C <= To_BitVector(TIMER_C);
TIMER_R_C <= std_logic_vector(TIMER_C);
READ_C := false;
elsif DSn = '1' and READ_D = true then
TIMER_R_D <= To_BitVector(TIMER_D);
TIMER_R_D <= std_logic_vector(TIMER_D);
READ_D := false;
end if;
end if;
@@ -290,12 +290,12 @@ begin
PRESCALE_A: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
A_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TACR(2 downto 0) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -313,12 +313,12 @@ begin
PRESCALE_B: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
B_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TBCR(2 downto 0) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -336,12 +336,12 @@ begin
PRESCALE_C: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
C_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TCDCR(5 downto 3) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -359,12 +359,12 @@ begin
PRESCALE_D: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
D_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TCDCR(2 downto 0) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -391,32 +391,32 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "01111" and TACR(3 downto 0) = x"0" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_A <= To_StdLogicVector(DATA_IN);
TIMER_A <= unsigned(DATA_IN);
else
case TACR(3 downto 0) is
when x"0" => -- Timer is off.
TAO_I <= '0';
when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
if A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
TIMER_A <= TIMER_A - '1';
TIMER_A <= TIMER_A - 1;
elsif A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
TIMER_A <= To_StdLogicVector(TADR);
TIMER_A <= unsigned(TADR);
TAO_I <= not TAO_I; -- Toggle the timer A output pin.
TIMER_A_INT <= '1';
end if;
when x"8" => -- Event count operation.
if TAI_STRB = '1' and TIMER_A /= x"01" then -- Count.
TIMER_A <= TIMER_A - '1';
TIMER_A <= unsigned(TIMER_A) - 1;
elsif TAI_STRB = '1' and TIMER_A = x"01" then -- Reload.
TIMER_A <= To_StdLogicVector(TADR);
TIMER_A <= unsigned(TADR);
TAO_I <= not TAO_I; -- Toggle the timer A output pin.
TIMER_A_INT <= '1';
end if;
when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
if TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
TIMER_A <= TIMER_A - '1';
TIMER_A <= unsigned(TIMER_A) - 1;
elsif TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
TIMER_A <= To_StdLogicVector(TADR);
TIMER_A <= unsigned(TADR);
TAO_I <= not TAO_I; -- Toggle the timer A output pin.
TIMER_A_INT <= '1';
end if;
@@ -436,32 +436,32 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10000" and TBCR(3 downto 0) = x"0" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_B <= To_StdLogicVector(DATA_IN);
TIMER_B <= unsigned(DATA_IN);
else
case TBCR(3 downto 0) is
when x"0" => -- Timer is off.
TBO_I <= '0';
when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
if B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
TIMER_B <= TIMER_B - '1';
TIMER_B <= TIMER_B - 1;
elsif B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
TIMER_B <= To_StdLogicVector(TBDR);
TIMER_B <= unsigned(TBDR);
TBO_I <= not TBO_I; -- Toggle the timer B output pin.
TIMER_B_INT <= '1';
end if;
when x"8" => -- Event count operation.
if TBI_STRB = '1' and TIMER_B /= x"01" then -- Count.
TIMER_B <= TIMER_B - '1';
TIMER_B <= TIMER_B - 1;
elsif TBI_STRB = '1' and TIMER_B = x"01" then -- Reload.
TIMER_B <= To_StdLogicVector(TBDR);
TIMER_B <= unsigned(TBDR);
TBO_I <= not TBO_I; -- Toggle the timer B output pin.
TIMER_B_INT <= '1';
end if;
when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
if TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
TIMER_B <= TIMER_B - '1';
TIMER_B <= TIMER_B - 1;
elsif TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
TIMER_B <= To_StdLogicVector(TBDR);
TIMER_B <= unsigned(TBDR);
TBO_I <= not TBO_I; -- Toggle the timer B output pin.
TIMER_B_INT <= '1';
end if;
@@ -481,16 +481,16 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10001" and TCDCR(5 downto 3) = "000" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_C <= To_StdLogicVector(DATA_IN);
TIMER_C <= unsigned(DATA_IN);
else
case TCDCR(5 downto 3) is
when "000" => -- Timer is off.
TCO <= '0';
when others => -- Delay counter mode.
if C_CNTSTRB = '1' and TIMER_C /= x"01" then -- Count.
TIMER_C <= TIMER_C - '1';
TIMER_C <= TIMER_C - 1;
elsif C_CNTSTRB = '1' and TIMER_C = x"01" then -- Reload.
TIMER_C <= To_StdLogicVector(TCDR);
TIMER_C <= unsigned(TCDR);
TCO <= not TCO; -- Toggle the timer C output pin.
TIMER_C_INT <= '1';
end if;
@@ -510,16 +510,16 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10010" and TCDCR(2 downto 0) = "000" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_D <= To_StdLogicVector(DATA_IN);
TIMER_D <= unsigned(DATA_IN);
else
case TCDCR(2 downto 0) is
when "000" => -- Timer is off.
TDO <= '0';
when others => -- Delay counter mode.
if D_CNTSTRB = '1' and TIMER_D /= x"01" then -- Count.
TIMER_D <= TIMER_D - '1';
TIMER_D <= TIMER_D - 1;
elsif D_CNTSTRB = '1' and TIMER_D = x"01" then -- Reload.
TIMER_D <= To_StdLogicVector(TDDR);
TIMER_D <= unsigned(TDDR);
TDO <= not TDO; -- Toggle the timer D output pin.
TIMER_D_INT <= '1';
end if;

120
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd
View File

@@ -62,103 +62,103 @@ use work.wf68901ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_TOP is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
RS : in std_logic_vector(5 downto 1);
DATA : inout std_logic_vector(7 downto 0);
GPIP : inout std_logic_vector(7 downto 0);
-- Interrupt control:
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Timers and timer control:
XTAL1 : in bit; -- Use an oszillator instead of a quartz.
TAI : in bit;
TBI : in bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
-- Serial I/O control:
RC : in bit;
TC : in bit;
SI : in bit;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
-- DMA control:
RRn : out bit;
TRn : out bit
RRn : out std_logic;
TRn : out std_logic
);
end entity WF68901IP_TOP;
architecture STRUCTURE of WF68901IP_TOP is
component WF68901IP_TOP_SOC
port(CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
DTACKn : out bit;
RS : in bit_vector(5 downto 1);
port(CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_EN : out bit_vector(7 downto 0);
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
XTAL1 : in bit;
TAI : in bit;
TBI : in bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
RC : in bit;
TC : in bit;
SI : in bit;
SO : out bit;
SO_EN : out bit;
RRn : out bit;
TRn : out bit
DATA_EN : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_EN : out std_logic_vector(7 downto 0);
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
XTAL1 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
RRn : out std_logic;
TRn : out std_logic
);
end component;
--
signal DTACK_In : bit;
signal IRQ_In : bit;
signal DTACK_In : std_logic;
signal IRQ_In : std_logic;
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_EN : bit;
signal GPIP_IN : bit_vector(7 downto 0);
signal GPIP_OUT : bit_vector(7 downto 0);
signal GPIP_EN : bit_vector(7 downto 0);
signal SO_I : bit;
signal SO_EN : bit;
signal DATA_EN : std_logic;
signal GPIP_IN : std_logic_vector(7 downto 0);
signal GPIP_OUT : std_logic_vector(7 downto 0);
signal GPIP_EN : std_logic_vector(7 downto 0);
signal SO_I : std_logic;
signal SO_EN : std_logic;
begin
DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain.
IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
GPIP_IN <= To_BitVector(GPIP);
GPIP_IN <= GPIP;
P_GPIP_OUT: process(GPIP_OUT, GPIP_EN)
begin

130
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd
View File

@@ -67,88 +67,88 @@ use work.wf68901ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_TOP_SOC is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DTACKn : out bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_EN : out bit_vector(7 downto 0);
DATA_EN : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_EN : out std_logic_vector(7 downto 0);
-- Interrupt control:
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Timers and timer control:
XTAL1 : in bit; -- Use an oszillator instead of a quartz.
TAI : in bit;
TBI : in bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
-- Serial I/O control:
RC : in bit;
TC : in bit;
SI : in bit;
SO : out bit;
SO_EN : out bit;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
-- DMA control:
RRn : out bit;
TRn : out bit
RRn : out std_logic;
TRn : out std_logic
);
end entity WF68901IP_TOP_SOC;
architecture STRUCTURE of WF68901IP_TOP_SOC is
signal DATA_IN_I : bit_vector(7 downto 0);
signal DTACK_In : bit;
signal DATA_IN_I : std_logic_vector(7 downto 0);
signal DTACK_In : std_logic;
signal DTACK_LOCK : boolean;
signal DTACK_OUTn : bit;
signal RX_ERR_INT_I : bit;
signal TX_ERR_INT_I : bit;
signal RX_BUFF_INT_I : bit;
signal TX_BUFF_INT_I : bit;
signal DATA_OUT_USART_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_USART_I : bit;
signal DATA_OUT_INT_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_INT_I : bit;
signal DATA_OUT_GPIO_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_GPIO_I : bit;
signal DATA_OUT_TIMERS_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_TIMERS_I : bit;
signal SO_I : bit;
signal SO_EN_I : bit;
signal GPIP_IN_I : bit_vector(7 downto 0);
signal GPIP_OUT_I : bit_vector(7 downto 0);
signal GPIP_EN_I : bit_vector(7 downto 0);
signal GP_INT_I : bit_vector(7 downto 0);
signal TIMER_A_INT_I : bit;
signal TIMER_B_INT_I : bit;
signal TIMER_C_INT_I : bit;
signal TIMER_D_INT_I : bit;
signal IRQ_In : bit;
signal AER_4_I : bit;
signal AER_3_I : bit;
signal TA_PWM_I : bit;
signal TB_PWM_I : bit;
signal DTACK_OUTn : std_logic;
signal RX_ERR_INT_I : std_logic;
signal TX_ERR_INT_I : std_logic;
signal RX_BUFF_INT_I : std_logic;
signal TX_BUFF_INT_I : std_logic;
signal DATA_OUT_USART_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_USART_I : std_logic;
signal DATA_OUT_INT_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_INT_I : std_logic;
signal DATA_OUT_GPIO_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_GPIO_I : std_logic;
signal DATA_OUT_TIMERS_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_TIMERS_I : std_logic;
signal SO_I : std_logic;
signal SO_EN_I : std_logic;
signal GPIP_IN_I : std_logic_vector(7 downto 0);
signal GPIP_OUT_I : std_logic_vector(7 downto 0);
signal GPIP_EN_I : std_logic_vector(7 downto 0);
signal GP_INT_I : std_logic_vector(7 downto 0);
signal TIMER_A_INT_I : std_logic;
signal TIMER_B_INT_I : std_logic;
signal TIMER_C_INT_I : std_logic;
signal TIMER_D_INT_I : std_logic;
signal IRQ_In : std_logic;
signal AER_4_I : std_logic;
signal AER_3_I : std_logic;
signal TA_PWM_I : std_logic;
signal TB_PWM_I : std_logic;
begin
-- Interrupt request (open drain):
IRQn <= IRQ_In;
@@ -162,13 +162,13 @@ begin
GPIP_OUT <= GPIP_OUT_I;
GPIP_EN <= GPIP_EN_I;
DATA_IN_I <= To_BitVector(DATA_IN);
DATA_IN_I <= DATA_IN;
DATA_EN <= DATA_OUT_EN_USART_I or DATA_OUT_EN_INT_I or DATA_OUT_EN_GPIO_I or DATA_OUT_EN_TIMERS_I;
-- Output data multiplexer:
DATA_OUT <= To_StdLogicVector(DATA_OUT_USART_I) when DATA_OUT_EN_USART_I = '1' else
To_StdLogicVector(DATA_OUT_INT_I) when DATA_OUT_EN_INT_I = '1' else
To_StdLogicVector(DATA_OUT_GPIO_I) when DATA_OUT_EN_GPIO_I = '1' else
To_StdLogicVector(DATA_OUT_TIMERS_I) when DATA_OUT_EN_TIMERS_I = '1' else (others => '1');
DATA_OUT <= DATA_OUT_USART_I when DATA_OUT_EN_USART_I = '1' else
DATA_OUT_INT_I when DATA_OUT_EN_INT_I = '1' else
DATA_OUT_GPIO_I when DATA_OUT_EN_GPIO_I = '1' else
DATA_OUT_TIMERS_I when DATA_OUT_EN_TIMERS_I = '1' else (others => '1');
-- Data acknowledge handshake is provided by the following statement and the consecutive two
-- processes. For more information refer to the M68000 family reference manual.

90
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
View File

@@ -56,67 +56,67 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_CTRL is
port (
-- System Control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- USART data register
RX_SAMPLE : in bit;
RX_DATA : in bit_vector(7 downto 0);
TX_DATA : out bit_vector(7 downto 0);
SCR_OUT : out bit_vector(7 downto 0);
RX_SAMPLE : in std_logic;
RX_DATA : in std_logic_vector(7 downto 0);
TX_DATA : out std_logic_vector(7 downto 0);
SCR_OUT : out std_logic_vector(7 downto 0);
-- USART control inputs:
BF : in bit;
BE : in bit;
FE : in bit;
OE : in bit;
UE : in bit;
PE : in bit;
M_CIP : in bit;
FS_B : in bit;
TX_END : in bit;
BF : in std_logic;
BE : in std_logic;
FE : in std_logic;
OE : in std_logic;
UE : in std_logic;
PE : in std_logic;
M_CIP : in std_logic;
FS_B : in std_logic;
TX_END : in std_logic;
-- USART control outputs:
CL : out bit_vector(1 downto 0);
ST : out bit_vector(1 downto 0);
FS_CLR : out bit;
UDR_WRITE : out bit;
UDR_READ : out bit;
RSR_READ : out bit;
TSR_READ : out bit;
LOOPBACK : out bit;
SDOUT_EN : out bit;
SD_LEVEL : out bit;
CLK_MODE : out bit;
RE : out bit;
TE : out bit;
P_ENA : out bit;
P_EOn : out bit;
SS : out bit;
BR : out bit
CL : out std_logic_vector(1 downto 0);
ST : out std_logic_vector(1 downto 0);
FS_CLR : out std_logic;
UDR_WRITE : out std_logic;
UDR_READ : out std_logic;
RSR_READ : out std_logic;
TSR_READ : out std_logic;
LOOPBACK : out std_logic;
SDOUT_EN : out std_logic;
SD_LEVEL : out std_logic;
CLK_MODE : out std_logic;
RE : out std_logic;
TE : out std_logic;
P_ENA : out std_logic;
P_EOn : out std_logic;
SS : out std_logic;
BR : out std_logic
);
end entity WF68901IP_USART_CTRL;
architecture BEHAVIOR of WF68901IP_USART_CTRL is
signal SCR : bit_vector(7 downto 0); -- Synchronous data register.
signal UCR : bit_vector(7 downto 1); -- USART control register.
signal RSR : bit_vector(7 downto 0); -- Receiver status register.
signal TSR : bit_vector(7 downto 0); -- Transmitter status register.
signal UDR : bit_vector(7 downto 0); -- USART data register.
signal SCR : std_logic_vector(7 downto 0); -- Synchronous data register.
signal UCR : std_logic_vector(7 downto 1); -- USART control register.
signal RSR : std_logic_vector(7 downto 0); -- Receiver status register.
signal TSR : std_logic_vector(7 downto 0); -- Transmitter status register.
signal UDR : std_logic_vector(7 downto 0); -- USART data register.
begin
USART_REGISTERS: process(RESETn, CLK)
begin

156
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
View File

@@ -58,52 +58,52 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_RX is
port (
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
SCR : in bit_vector(7 downto 0); -- Synchronous character.
RX_SAMPLE : buffer bit; -- Flag indicating valid shift register data.
RX_DATA : out bit_vector(7 downto 0); -- Received data.
SCR : in std_logic_vector(7 downto 0); -- Synchronous character.
RX_SAMPLE : buffer std_logic; -- Flag indicating valid shift register data.
RX_DATA : out std_logic_vector(7 downto 0); -- Received data.
RXCLK : in bit; -- Receiver clock.
SDATA_IN : in bit; -- Serial data input.
RXCLK : in std_logic; -- Receiver clock.
SDATA_IN : in std_logic; -- Serial data input.
CL : in bit_vector(1 downto 0); -- Character length.
ST : in bit_vector(1 downto 0); -- Start and stop bit configuration.
P_ENA : in bit; -- Parity enable.
P_EOn : in bit; -- Even or odd parity.
CLK_MODE : in bit; -- Clock mode configuration bit.
RE : in bit; -- Receiver enable.
FS_CLR : in bit; -- Clear the Found/Search flag for resynchronisation purpose.
SS : in bit; -- Synchronous strip enable.
UDR_READ : in bit; -- Flag indicating reading the data register.
RSR_READ : in bit; -- Flag indicating reading the receiver status register.
CL : in std_logic_vector(1 downto 0); -- Character length.
ST : in std_logic_vector(1 downto 0); -- Start and stop std_logic configuration.
P_ENA : in std_logic; -- Parity enable.
P_EOn : in std_logic; -- Even or odd parity.
CLK_MODE : in std_logic; -- Clock mode configuration std_logic.
RE : in std_logic; -- Receiver enable.
FS_CLR : in std_logic; -- Clear the Found/Search flag for resynchronisation purpose.
SS : in std_logic; -- Synchronous strip enable.
UDR_READ : in std_logic; -- Flag indicating reading the data register.
RSR_READ : in std_logic; -- Flag indicating reading the receiver status register.
M_CIP : out bit; -- Match/Character in progress.
FS_B : buffer bit; -- Find/Search or Break detect flag.
BF : out bit; -- Buffer full.
OE : out bit; -- Overrun error.
PE : out bit; -- Parity error.
FE : out bit -- Framing error.
M_CIP : out std_logic; -- Match/Character in progress.
FS_B : buffer std_logic; -- Find/Search or Break detect flag.
BF : out std_logic; -- Buffer full.
OE : out std_logic; -- Overrun error.
PE : out std_logic; -- Parity error.
FE : out std_logic -- Framing error.
);
end entity WF68901IP_USART_RX;
architecture BEHAVIOR of WF68901IP_USART_RX is
type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
signal SDATA_DIV16 : bit;
signal SDATA_IN_I : bit;
signal SDATA_EDGE : bit;
signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal CLK_2_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
signal SDATA_DIV16 : std_logic;
signal SDATA_IN_I : std_logic;
signal SDATA_EDGE : std_logic;
signal SHIFT_REG : std_logic_vector(7 downto 0);
signal CLK_STRB : std_logic;
signal CLK_2_STRB : std_logic;
signal BITCNT : unsigned (2 downto 0);
signal BREAK : boolean;
signal RDRF : bit;
signal RDRF : std_logic;
signal STARTBIT : boolean;
begin
BF <= RDRF; -- Buffer full = Receiver Data Register Full.
@@ -113,21 +113,21 @@ begin
'1' when RCV_STATE = SYNC and ST = "00" and SS = '1' and SHIFT_REG /= SCR else '0';
-- Data multiplexer for the received data:
RX_DATA <= "000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 databits.
"00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 databits.
'0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 databits.
SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 databits.
RX_DATA <= "000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 datastd_logics.
"00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 datastd_logics.
'0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 datastd_logics.
SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 datastd_logics.
P_SAMPLE: process
-- This process provides the 'valid transition logic' of the originally MC68901. For further
-- details see the 'M68000 FAMILY REFERENCE MANUAL'.
variable LOW_FLT : std_logic_vector(1 downto 0);
variable HI_FLT : std_logic_vector(1 downto 0);
variable LOW_FLT : unsigned (1 downto 0);
variable HI_FLT : unsigned (1 downto 0);
variable CLK_LOCK : boolean;
variable EDGE_LOCK : boolean;
variable TIMER : std_logic_vector(2 downto 0);
variable TIMER : unsigned (2 downto 0);
variable TIMER_LOCK : boolean;
variable NEW_SDATA : bit;
variable NEW_SDATA : std_logic;
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' or RE = '0' then
@@ -141,18 +141,18 @@ begin
NEW_SDATA := '1';
-- Positive or negative edge detector for the incoming data.
-- Any transition must be valid for at least three receiver clock
-- cycles. The TIMER locking inhibits detecting four receiver
-- cycles. The TIMER locking inhistd_logics detecting four receiver
-- clock cycles after a valid transition.
elsif RXCLK = '1' and SDATA_IN = '0' and CLK_LOCK = false and LOW_FLT > "00" then
CLK_LOCK := true;
EDGE_LOCK := false;
HI_FLT := "00";
LOW_FLT := LOW_FLT - '1';
LOW_FLT := LOW_FLT - 1;
elsif RXCLK = '1' and SDATA_IN = '1' and CLK_LOCK = false and HI_FLT < "11" then
CLK_LOCK := true;
EDGE_LOCK := false;
LOW_FLT := "11";
HI_FLT := HI_FLT + '1';
HI_FLT := HI_FLT + 1;
elsif RXCLK = '1' and EDGE_LOCK = false and LOW_FLT = "00" then
EDGE_LOCK := true;
SDATA_EDGE <= '1'; -- Falling edge detected.
@@ -183,26 +183,26 @@ begin
elsif RXCLK = '1' and TIMER = "011" and TIMER_LOCK = false then
TIMER_LOCK := true;
SDATA_DIV16 <= NEW_SDATA; -- Scan the new data.
TIMER := TIMER + '1'; -- Timing is active.
TIMER := TIMER + 1; -- Timing is active.
elsif RXCLK = '1' and TIMER < "111" and TIMER_LOCK = false then
TIMER_LOCK := true;
TIMER := TIMER + '1'; -- Timing is active.
TIMER := TIMER + 1; -- Timing is active.
elsif RXCLK = '0' then
TIMER_LOCK := false;
end if;
end process P_SAMPLE;
P_START_BIT: process(CLK)
-- This is the valid start bit logic of the original MC68901 multi function
-- This is the valid start std_logic logic of the original MC68901 multi function
-- port's USART receiver.
variable TMP : std_logic_vector(2 downto 0);
variable TMP : unsigned (2 downto 0);
variable LOCK : boolean;
begin
if CLK = '1' and CLK' event then
if RESETn = '0' then
TMP := "000";
LOCK := true;
elsif RE = '0' or RCV_STATE /= IDLE then -- Start bit logic disabled.
elsif RE = '0' or RCV_STATE /= IDLE then -- Start std_logic logic disabled.
TMP := "000";
LOCK := true;
elsif SDATA_EDGE = '1' then
@@ -210,7 +210,7 @@ begin
LOCK := false; -- Start counting.
elsif RXCLK = '1' and SDATA_IN = '0' and TMP < "111" and LOCK = false then
LOCK := true;
TMP := TMP + '1'; -- Count 8 low bits to declare start condition valid.
TMP := TMP + 1; -- Count 8 low std_logics to declare start condition valid.
elsif RXCLK = '0' then
LOCK := false;
end if;
@@ -228,7 +228,7 @@ begin
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(4 downto 0);
variable CLK_DIVCNT : unsigned (4 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CLK_MODE = '0' then -- Divider off.
@@ -241,7 +241,7 @@ begin
else
CLK_STRB <= '0';
end if;
CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
CLK_2_STRB <= '0'; -- No 1 1/2 stop std_logics in no div by 16 mode.
elsif SDATA_EDGE = '1' then
CLK_DIVCNT := "01100"; -- Div by 16 mode.
CLK_STRB <= '0'; -- Default.
@@ -250,11 +250,11 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
CLK_STRB <= '0'; -- Default.
CLK_2_STRB <= '0'; -- Default.
if CLK_DIVCNT > "00000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_DIVCNT := CLK_DIVCNT - 1;
CLK_LOCK := true;
if CLK_DIVCNT = "01000" then
-- This strobe is asserted at half of the clock cycle.
-- It is used for the stop bit timing.
-- It is used for the stop std_logic timing.
CLK_2_STRB <= '1';
end if;
elsif CLK_DIVCNT = "00000" then
@@ -309,7 +309,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end process P_M_CIP;
BREAK_DETECT: process(RESETn, CLK)
-- A break condition occurs, if there is no STOP1 bit and the
-- A break condition occurs, if there is no STOP1 std_logic and the
-- shift register contains zero data.
begin
if RESETn = '0' then
@@ -319,7 +319,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
BREAK <= false;
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG = x"00" then
BREAK <= true; -- Break detected (empty shift register and no stop bit).
BREAK <= true; -- Break detected (empty shift register and no stop std_logic).
elsif RCV_STATE = STOP1 and SDATA_IN_I = '1' then
BREAK <= false; -- UPDATE.
elsif RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
@@ -332,7 +332,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
P_FS_B: process(RESETn, CLK)
-- In the synchronous mode, this process provides the flag detecting the synchronous
-- character. In the asynchronous mode, the flag indicates a break condition.
variable FS_B_I : bit;
variable FS_B_I : std_logic;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
@@ -378,9 +378,9 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' and ST /= "00" then -- Asynchronous mode.
BITCNT <= BITCNT + '1';
BITCNT <= BITCNT + 1;
elsif RCV_STATE = SAMPLE and CLK_STRB = '1' and ST = "00" and FS_B = '1' then -- Synchronous mode.
BITCNT <= BITCNT + '1'; -- Count, if matched data found (FS_B = '1').
BITCNT <= BITCNT + 1; -- Count, if matched data found (FS_B = '1').
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
@@ -403,7 +403,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end process BUFFER_FULL;
OVERRUN: process(RESETn, CLK)
variable OE_I : bit;
variable OE_I : std_logic;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
@@ -438,8 +438,8 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end process OVERRUN;
PARITY_TEST: process(RESETn, CLK)
variable PAR_TMP : bit;
variable P_ERR : bit;
variable PAR_TMP : std_logic;
variable P_ERR : std_logic;
begin
if RESETn = '0' then
PE <= '0';
@@ -472,8 +472,8 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
FRAME_ERR: process(RESETn, CLK)
-- This module detects a framing error
-- during stop bit 1 and stop bit 2.
variable FE_I: bit;
-- during stop std_logic 1 and stop std_logic 2.
variable FE_I: std_logic;
begin
if RESETn = '0' then
FE_I := '0';
@@ -518,15 +518,15 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
if ST = "00" then
RCV_NEXT_STATE <= SAMPLE; -- Synchronous mode.
elsif SDATA_IN_I = '0' and CLK_MODE = '0' then
RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
RCV_NEXT_STATE <= SAMPLE; -- Startstd_logic detected in div by 1 mode.
elsif STARTBIT = true and CLK_MODE = '1' then
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
RCV_NEXT_STATE <= WAIT_START; -- Startstd_logic detected in div by 16 mode.
else
RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
RCV_NEXT_STATE <= IDLE; -- No startstd_logic; sleep well :-)
end if;
when WAIT_START =>
-- This state delays the sample process by one CLK_STRB pulse
-- to eliminate the start bit.
-- to eliminate the start std_logic.
if CLK_STRB = '1' then
RCV_NEXT_STATE <= SAMPLE;
else
@@ -535,14 +535,14 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
when SAMPLE =>
if CLK_STRB = '1' then
if CL = "11" and BITCNT < "100" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data std_logics.
elsif CL = "10" and BITCNT < "101" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data std_logics.
elsif CL = "01" and BITCNT < "110" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data std_logics.
elsif CL = "00" and BITCNT < "111" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop bits).
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data std_logics.
elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop std_logics).
RCV_NEXT_STATE <= IDLE; -- No parity check enabled.
elsif P_ENA = '0' then
RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
@@ -554,7 +554,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end if;
when PARITY =>
if CLK_STRB = '1' then
if ST = "00" then -- Synchronous mode (no stop bits).
if ST = "00" then -- Synchronous mode (no stop std_logics).
RCV_NEXT_STATE <= IDLE;
else
RCV_NEXT_STATE <= STOP1;
@@ -564,21 +564,21 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end if;
when STOP1 =>
if CLK_STRB = '1' then
if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop bit after non zero data.
if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop std_logic after non zero data.
RCV_NEXT_STATE <= SYNC; -- Framing error detected.
elsif ST = "11" or ST = "10" then
RCV_NEXT_STATE <= STOP2; -- More than one stop bits selected.
RCV_NEXT_STATE <= STOP2; -- More than one stop std_logics selected.
else
RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
RCV_NEXT_STATE <= SYNC; -- One stop std_logic selected.
end if;
else
RCV_NEXT_STATE <= STOP1;
end if;
when STOP2 =>
if CLK_2_STRB = '1' and ST = "10" then
RCV_NEXT_STATE <= SYNC; -- One and a half stop bits selected.
RCV_NEXT_STATE <= SYNC; -- One and a half stop std_logics selected.
elsif CLK_STRB = '1' then
RCV_NEXT_STATE <= SYNC; -- Two stop bits selected.
RCV_NEXT_STATE <= SYNC; -- Two stop std_logics selected.
else
RCV_NEXT_STATE <= STOP2;
end if;

106
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_top.vhd
View File

@@ -58,76 +58,76 @@ use work.wf68901ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_TOP is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Serial I/O control:
RC : in bit; -- Receiver clock.
TC : in bit; -- Transmitter clock.
SI : in bit; -- Serial input.
SO : out bit; -- Serial output.
SO_EN : out bit; -- Serial output enable.
RC : in std_logic; -- Receiver clock.
TC : in std_logic; -- Transmitter clock.
SI : in std_logic; -- Serial input.
SO : out std_logic; -- Serial output.
SO_EN : out std_logic; -- Serial output enable.
-- Interrupt channels:
RX_ERR_INT : out bit; -- Receiver errors.
RX_BUFF_INT : out bit; -- Receiver buffer full.
TX_ERR_INT : out bit; -- Transmitter errors.
TX_BUFF_INT : out bit; -- Transmitter buffer empty.
RX_ERR_INT : out std_logic; -- Receiver errors.
RX_BUFF_INT : out std_logic; -- Receiver buffer full.
TX_ERR_INT : out std_logic; -- Transmitter errors.
TX_BUFF_INT : out std_logic; -- Transmitter buffer empty.
-- DMA control:
RRn : out bit;
TRn : out bit
RRn : out std_logic;
TRn : out std_logic
);
end entity WF68901IP_USART_TOP;
architecture STRUCTURE of WF68901IP_USART_TOP is
signal BF_I : bit;
signal BE_I : bit;
signal FE_I : bit;
signal OE_I : bit;
signal UE_I : bit;
signal PE_I : bit;
signal LOOPBACK_I : bit;
signal SD_LEVEL_I : bit;
signal SDATA_IN_I : bit;
signal SDATA_OUT_I : bit;
signal RXCLK_I : bit;
signal CLK_MODE_I : bit;
signal SCR_I : bit_vector(7 downto 0);
signal RX_SAMPLE_I : bit;
signal RX_DATA_I : bit_vector(7 downto 0);
signal TX_DATA_I : bit_vector(7 downto 0);
signal CL_I : bit_vector(1 downto 0);
signal ST_I : bit_vector(1 downto 0);
signal P_ENA_I : bit;
signal P_EOn_I : bit;
signal RE_I : bit;
signal TE_I : bit;
signal FS_CLR_I : bit;
signal SS_I : bit;
signal M_CIP_I : bit;
signal FS_B_I : bit;
signal BR_I : bit;
signal UDR_READ_I : bit;
signal UDR_WRITE_I : bit;
signal RSR_READ_I : bit;
signal TSR_READ_I : bit;
signal TX_END_I : bit;
signal BF_I : std_logic;
signal BE_I : std_logic;
signal FE_I : std_logic;
signal OE_I : std_logic;
signal UE_I : std_logic;
signal PE_I : std_logic;
signal LOOPBACK_I : std_logic;
signal SD_LEVEL_I : std_logic;
signal SDATA_IN_I : std_logic;
signal SDATA_OUT_I : std_logic;
signal RXCLK_I : std_logic;
signal CLK_MODE_I : std_logic;
signal SCR_I : std_logic_vector(7 downto 0);
signal RX_SAMPLE_I : std_logic;
signal RX_DATA_I : std_logic_vector(7 downto 0);
signal TX_DATA_I : std_logic_vector(7 downto 0);
signal CL_I : std_logic_vector(1 downto 0);
signal ST_I : std_logic_vector(1 downto 0);
signal P_ENA_I : std_logic;
signal P_EOn_I : std_logic;
signal RE_I : std_logic;
signal TE_I : std_logic;
signal FS_CLR_I : std_logic;
signal SS_I : std_logic;
signal M_CIP_I : std_logic;
signal FS_B_I : std_logic;
signal BR_I : std_logic;
signal UDR_READ_I : std_logic;
signal UDR_WRITE_I : std_logic;
signal RSR_READ_I : std_logic;
signal TSR_READ_I : std_logic;
signal TX_END_I : std_logic;
begin
SO <= SDATA_OUT_I when TE_I = '1' else SD_LEVEL_I;
-- Loopback mode:

98
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
View File

@@ -57,45 +57,45 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_TX is
port (
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
SCR : in bit_vector(7 downto 0); -- Synchronous character.
TX_DATA : in bit_vector(7 downto 0); -- Normal data.
SCR : in std_logic_vector(7 downto 0); -- Synchronous character.
TX_DATA : in std_logic_vector(7 downto 0); -- Normal data.
SDATA_OUT : out bit; -- Serial data output.
TXCLK : in bit; -- Transmitter clock.
SDATA_OUT : out std_logic; -- Serial data output.
TXCLK : in std_logic; -- Transmitter clock.
CL : in bit_vector(1 downto 0); -- Character length.
ST : in bit_vector(1 downto 0); -- Start and stop bit configuration.
TE : in bit; -- Transmitter enable.
BR : in bit; -- BREAK character send enable (all '0' without stop bit).
P_ENA : in bit; -- Parity enable.
P_EOn : in bit; -- Even or odd parity.
UDR_WRITE : in bit; -- Flag indicating writing the data register.
TSR_READ : in bit; -- Flag indicating reading the transmitter status register.
CLK_MODE : in bit; -- Transmitter clock mode.
CL : in std_logic_vector(1 downto 0); -- Character length.
ST : in std_logic_vector(1 downto 0); -- Start and stop std_logic configuration.
TE : in std_logic; -- Transmitter enable.
BR : in std_logic; -- BREAK character send enable (all '0' without stop std_logic).
P_ENA : in std_logic; -- Parity enable.
P_EOn : in std_logic; -- Even or odd parity.
UDR_WRITE : in std_logic; -- Flag indicating writing the data register.
TSR_READ : in std_logic; -- Flag indicating reading the transmitter status register.
CLK_MODE : in std_logic; -- Transmitter clock mode.
TX_END : out bit; -- End of transmission flag.
UE : out bit; -- Underrun Flag.
BE : out bit -- Buffer empty flag.
TX_END : out std_logic; -- End of transmission flag.
UE : out std_logic; -- Underrun Flag.
BE : out std_logic -- Buffer empty flag.
);
end entity WF68901IP_USART_TX;
architecture BEHAVIOR of WF68901IP_USART_TX is
type TR_STATES is (IDLE, CHECK_BREAK, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
signal TR_STATE, TR_NEXT_STATE : TR_STATES;
signal CLK_STRB : bit;
signal CLK_2_STRB : bit;
signal SHIFT_REG : bit_vector(7 downto 0);
signal BITCNT : std_logic_vector(2 downto 0);
signal PARITY_I : bit;
signal TDRE : bit;
signal BREAK : bit;
signal CLK_STRB : std_logic;
signal CLK_2_STRB : std_logic;
signal SHIFT_REG : std_logic_vector(7 downto 0);
signal BITCNT : unsigned (2 downto 0);
signal PARITY_I : std_logic;
signal TDRE : std_logic;
signal BREAK : std_logic;
begin
BE <= TDRE; -- Buffer empty flag.
@@ -140,7 +140,7 @@ begin
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(4 downto 0);
variable CLK_DIVCNT : unsigned (4 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CLK_MODE = '0' then -- Divider off.
@@ -153,7 +153,7 @@ begin
else
CLK_STRB <= '0';
end if;
CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
CLK_2_STRB <= '0'; -- No 1 1/2 stop std_logics in no div by 16 mode.
elsif TR_STATE = IDLE then
CLK_DIVCNT := "10000"; -- Div by 16 mode.
CLK_STRB <= '0';
@@ -162,11 +162,11 @@ begin
CLK_2_STRB <= '0'; -- Default.
-- Works on negative TXCLK edge:
if CLK_DIVCNT > "00000" and TXCLK = '0' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_DIVCNT := CLK_DIVCNT - 1;
CLK_LOCK := true;
if CLK_DIVCNT = "01000" then
-- This strobe is asserted at half of the clock cycle.
-- It is used for the stop bit timing.
-- It is used for the stop std_logic timing.
CLK_2_STRB <= '1';
end if;
elsif CLK_DIVCNT = "00000" then
@@ -197,10 +197,10 @@ begin
elsif TR_STATE = LOAD_SHFT then
-- Load 'normal' data if there is no break condition:
case CL is
when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 databits.
when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 databits.
when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 databits.
when "00" => SHIFT_REG <= TX_DATA; -- 8 databits.
when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 datastd_logics.
when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 datastd_logics.
when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 datastd_logics.
when "00" => SHIFT_REG <= TX_DATA; -- 8 datastd_logics.
end case;
elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
@@ -209,11 +209,11 @@ begin
end process SHIFTREG;
P_BITCNT: process
-- Counter for the data bits transmitted.
-- Counter for the data std_logics transmitted.
begin
wait until CLK = '1' and CLK' event;
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
BITCNT <= BITCNT + 1;
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
end if;
@@ -274,7 +274,7 @@ begin
end process P_TX_END;
PARITY_GEN: process
variable PAR_TMP : bit;
variable PAR_TMP : std_logic;
begin
wait until CLK = '1' and CLK' event;
if TR_STATE = START then -- Calculate the parity during the start phase.
@@ -325,7 +325,7 @@ begin
end if;
when LOAD_SHFT =>
TR_NEXT_STATE <= START;
when START => -- Send the start bit.
when START => -- Send the start std_logic.
if CLK_STRB = '1' then
TR_NEXT_STATE <= SHIFTOUT;
else
@@ -334,15 +334,15 @@ begin
when SHIFTOUT =>
if CLK_STRB = '1' then
if BITCNT < "100" and CL = "11" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data std_logics.
elsif BITCNT < "101" and CL = "10" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data std_logics.
elsif BITCNT < "110" and CL = "01" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data std_logics.
elsif BITCNT < "111" and CL = "00" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data std_logics.
elsif P_ENA = '0' and BREAK = '1' then
TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop bits.
TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop std_logics.
elsif P_ENA = '0' and ST = "00" then
TR_NEXT_STATE <= IDLE; -- Synchronous mode, no parity check enabled.
elsif P_ENA = '0' then
@@ -355,9 +355,9 @@ begin
end if;
when PARITY =>
if CLK_STRB = '1' then
if ST = "00" then -- Synchronous mode (no stop bits).
if ST = "00" then -- Synchronous mode (no stop std_logics).
TR_NEXT_STATE <= IDLE;
elsif BREAK = '1' then -- No stop bits during break condition.
elsif BREAK = '1' then -- No stop std_logics during break condition.
TR_NEXT_STATE <= IDLE;
else
TR_NEXT_STATE <= STOP1;
@@ -367,17 +367,17 @@ begin
end if;
when STOP1 =>
if CLK_STRB = '1' and (ST = "11" or ST = "10") then
TR_NEXT_STATE <= STOP2; -- More than one stop bits selected.
TR_NEXT_STATE <= STOP2; -- More than one stop std_logics selected.
elsif CLK_STRB = '1' then
TR_NEXT_STATE <= IDLE; -- One stop bits selected.
TR_NEXT_STATE <= IDLE; -- One stop std_logics selected.
else
TR_NEXT_STATE <= STOP1;
end if;
when STOP2 =>
if CLK_2_STRB = '1' and ST = "10" then
TR_NEXT_STATE <= IDLE; -- One and a half stop bits selected.
TR_NEXT_STATE <= IDLE; -- One and a half stop std_logics selected.
elsif CLK_STRB = '1' then
TR_NEXT_STATE <= IDLE; -- Two stop bits detected.
TR_NEXT_STATE <= IDLE; -- Two stop std_logics detected.
else
TR_NEXT_STATE <= STOP2;
end if;

18
vhdl/rtl/vhdl/WF_SND2149_IP/wf2149ip_pkg.vhd
View File

@@ -63,22 +63,22 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
component WF2149IP_WAVE
port(
RESETn : in bit;
SYS_CLK : in bit;
RESETn : in std_logic;
SYS_CLK : in std_logic;
WAV_STRB : in bit;
WAV_STRB : in std_logic;
ADR : in bit_vector(3 downto 0);
ADR : in std_logic_vector(3 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
DATA_EN : out std_logic;
BUSCYCLE : in BUSCYCLES;
CTRL_REG : in bit_vector(5 downto 0);
CTRL_REG : in std_logic_vector(5 downto 0);
OUT_A : out bit;
OUT_B : out bit;
OUT_C : out bit
OUT_A : out std_logic;
OUT_B : out std_logic;
OUT_C : out std_logic
);
end component;
end WF2149IP_PKG;

76
vhdl/rtl/vhdl/WF_SND2149_IP/wf2149ip_top.vhd
View File

@@ -81,66 +81,66 @@ use work.wf2149ip_pkg.all;
entity WF2149IP_TOP is
port(
SYS_CLK : in bit; -- Read the inforation in the header!
RESETn : in bit;
SYS_CLK : in std_logic; -- Read the inforation in the header!
RESETn : in std_logic;
WAV_CLK : in bit; -- Read the inforation in the header!
SELn : in bit;
WAV_CLK : in std_logic; -- Read the inforation in the header!
SELn : in std_logic;
BDIR : in bit;
BC2, BC1 : in bit;
BDIR : in std_logic;
BC2, BC1 : in std_logic;
A9n, A8 : in bit;
A9n, A8 : in std_logic;
DA : inout std_logic_vector(7 downto 0);
IO_A : inout std_logic_vector(7 downto 0);
IO_B : inout std_logic_vector(7 downto 0);
OUT_A : out bit; -- Analog (PWM) outputs.
OUT_B : out bit;
OUT_C : out bit
OUT_A : out std_logic; -- Analog (PWM) outputs.
OUT_B : out std_logic;
OUT_C : out std_logic
);
end WF2149IP_TOP;
architecture STRUCTURE of WF2149IP_TOP is
component WF2149IP_TOP_SOC
port(
SYS_CLK : in bit;
RESETn : in bit;
WAV_CLK : in bit;
SELn : in bit;
BDIR : in bit;
BC2, BC1 : in bit;
A9n, A8 : in bit;
SYS_CLK : in std_logic;
RESETn : in std_logic;
WAV_CLK : in std_logic;
SELn : in std_logic;
BDIR : in std_logic;
BC2, BC1 : in std_logic;
A9n, A8 : in std_logic;
DA_IN : in std_logic_vector(7 downto 0);
DA_OUT : out std_logic_vector(7 downto 0);
DA_EN : out bit;
IO_A_IN : in bit_vector(7 downto 0);
IO_A_OUT : out bit_vector(7 downto 0);
IO_A_EN : out bit;
IO_B_IN : in bit_vector(7 downto 0);
IO_B_OUT : out bit_vector(7 downto 0);
IO_B_EN : out bit;
OUT_A : out bit;
OUT_B : out bit;
OUT_C : out bit
DA_EN : out std_logic;
IO_A_IN : in std_logic_vector(7 downto 0);
IO_A_OUT : out std_logic_vector(7 downto 0);
IO_A_EN : out std_logic;
IO_B_IN : in std_logic_vector(7 downto 0);
IO_B_OUT : out std_logic_vector(7 downto 0);
IO_B_EN : out std_logic;
OUT_A : out std_logic;
OUT_B : out std_logic;
OUT_C : out std_logic
);
end component;
--
signal DA_OUT : std_logic_vector(7 downto 0);
signal DA_EN : bit;
signal IO_A_IN : bit_vector(7 downto 0);
signal IO_A_OUT : bit_vector(7 downto 0);
signal IO_A_EN : bit;
signal IO_B_IN : bit_vector(7 downto 0);
signal IO_B_OUT : bit_vector(7 downto 0);
signal IO_B_EN : bit;
signal DA_EN : std_logic;
signal IO_A_IN : std_logic_vector(7 downto 0);
signal IO_A_OUT : std_logic_vector(7 downto 0);
signal IO_A_EN : std_logic;
signal IO_B_IN : std_logic_vector(7 downto 0);
signal IO_B_OUT : std_logic_vector(7 downto 0);
signal IO_B_EN : std_logic;
begin
IO_A_IN <= To_BitVector(IO_A);
IO_B_IN <= To_BitVector(IO_B);
IO_A_IN <= (IO_A);
IO_B_IN <= (IO_B);
IO_A <= To_StdLogicVector(IO_A_OUT) when IO_A_EN = '1' else (others => 'Z');
IO_B <= To_StdLogicVector(IO_B_OUT) when IO_B_EN = '1' else (others => 'Z');
IO_A <= (IO_A_OUT) when IO_A_EN = '1' else (others => 'Z');
IO_B <= (IO_B_OUT) when IO_B_EN = '1' else (others => 'Z');
DA <= DA_OUT when DA_EN = '1' else (others => 'Z');

65
vhdl/rtl/vhdl/WF_SND2149_IP/wf2149ip_top_soc.vhd
View File

@@ -78,51 +78,52 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wf2149ip_pkg.all;
entity WF2149IP_TOP_SOC is
port(
SYS_CLK : in bit; -- Read the inforation in the header!
RESETn : in bit;
SYS_CLK : in std_logic; -- Read the inforation in the header!
RESETn : in std_logic;
WAV_CLK : in bit; -- Read the inforation in the header!
SELn : in bit;
WAV_CLK : in std_logic; -- Read the inforation in the header!
SELn : in std_logic;
BDIR : in bit;
BC2, BC1 : in bit;
BDIR : in std_logic;
BC2, BC1 : in std_logic;
A9n, A8 : in bit;
A9n, A8 : in std_logic;
DA_IN : in std_logic_vector(7 downto 0);
DA_OUT : out std_logic_vector(7 downto 0);
DA_EN : out bit;
DA_EN : out std_logic;
IO_A_IN : in bit_vector(7 downto 0);
IO_A_OUT : out bit_vector(7 downto 0);
IO_A_EN : out bit;
IO_B_IN : in bit_vector(7 downto 0);
IO_B_OUT : out bit_vector(7 downto 0);
IO_B_EN : out bit;
IO_A_IN : in std_logic_vector(7 downto 0);
IO_A_OUT : out std_logic_vector(7 downto 0);
IO_A_EN : out std_logic;
IO_B_IN : in std_logic_vector(7 downto 0);
IO_B_OUT : out std_logic_vector(7 downto 0);
IO_B_EN : out std_logic;
OUT_A : out bit; -- Analog (PWM) outputs.
OUT_B : out bit;
OUT_C : out bit
OUT_A : out std_logic; -- Analog (PWM) outputs.
OUT_B : out std_logic;
OUT_C : out std_logic
);
end WF2149IP_TOP_SOC;
architecture STRUCTURE of WF2149IP_TOP_SOC is
signal BUSCYCLE : BUSCYCLES;
signal DATA_OUT_I : std_logic_vector(7 downto 0);
signal DATA_EN_I : bit;
signal WAV_STRB : bit;
signal ADR_I : bit_vector(3 downto 0);
signal CTRL_REG : bit_vector(7 downto 0);
signal PORT_A : bit_vector(7 downto 0);
signal PORT_B : bit_vector(7 downto 0);
signal DATA_EN_I : std_logic;
signal WAV_STRB : std_logic;
signal ADR_I : std_logic_vector(3 downto 0);
signal CTRL_REG : std_logic_vector(7 downto 0);
signal PORT_A : std_logic_vector(7 downto 0);
signal PORT_B : std_logic_vector(7 downto 0);
begin
P_WAVSTRB: process(RESETn, SYS_CLK)
variable LOCK : boolean;
variable TMP : bit;
variable TMP : std_logic;
begin
if RESETn = '0' then
LOCK := false;
@@ -144,7 +145,7 @@ begin
end if;
end process P_WAVSTRB;
with BDIR & BC2 & BC1 select
with std_logic_vector(unsigned'(BDIR & BC2 & BC1)) select
BUSCYCLE <= INACTIVE when "000" | "010" | "101",
ADDRESS when "001" | "100" | "111",
R_READ when "011",
@@ -159,7 +160,7 @@ begin
ADR_I <= (others => '0');
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
ADR_I <= To_BitVector(DA_IN(3 downto 0));
ADR_I <= (DA_IN(3 downto 0));
end if;
end if;
end process ADDRESSLATCH;
@@ -171,7 +172,7 @@ begin
CTRL_REG <= x"00";
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = R_WRITE and ADR_I = x"7" then
CTRL_REG <= To_BitVector(DA_IN);
CTRL_REG <= (DA_IN);
end if;
end if;
end process P_CTRL_REG;
@@ -183,9 +184,9 @@ begin
PORT_B <= x"00";
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = R_WRITE and ADR_I = x"E" then
PORT_A <= To_BitVector(DA_IN);
PORT_A <= (DA_IN);
elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
PORT_B <= To_BitVector(DA_IN);
PORT_B <= (DA_IN);
end if;
end if;
end process DIG_PORTS;
@@ -222,8 +223,8 @@ begin
'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
DA_OUT <= DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
end STRUCTURE;

110
vhdl/rtl/vhdl/WF_SND2149_IP/wf2149ip_wave.vhd
View File

@@ -60,32 +60,32 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.wf2149ip_pkg.all;
entity WF2149IP_WAVE is
port(
RESETn : in bit;
SYS_CLK : in bit;
RESETn : in std_logic;
SYS_CLK : in std_logic;
WAV_STRB : in bit;
WAV_STRB : in std_logic;
ADR : in bit_vector(3 downto 0);
ADR : in std_logic_vector(3 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
DATA_EN : out std_logic;
BUSCYCLE : in BUSCYCLES;
CTRL_REG : in bit_vector(5 downto 0);
CTRL_REG : in std_logic_vector(5 downto 0);
OUT_A : out bit;
OUT_B : out bit;
OUT_C : out bit
OUT_A : out std_logic;
OUT_B : out std_logic;
OUT_C : out std_logic
);
end entity WF2149IP_WAVE;
architecture BEHAVIOR of WF2149IP_WAVE is
signal FREQUENCY_A : std_logic_vector(11 downto 0);
signal FREQUENCY_A : unsigned (11 downto 0);
signal FREQUENCY_B : std_logic_vector(11 downto 0);
signal FREQUENCY_C : std_logic_vector(11 downto 0);
signal NOISE_FREQ : std_logic_vector(4 downto 0);
@@ -95,14 +95,14 @@ signal LEVEL_C : std_logic_vector(4 downto 0);
signal ENV_FREQ : std_logic_vector(15 downto 0);
signal ENV_SHAPE : std_logic_vector(3 downto 0);
signal ENV_RESET : boolean;
signal ENV_STRB : bit;
signal OSC_A_OUT : bit;
signal OSC_B_OUT : bit;
signal OSC_C_OUT : bit;
signal NOISE_OUT : bit;
signal AUDIO_A : bit;
signal AUDIO_B : bit;
signal AUDIO_C : bit;
signal ENV_STRB : std_logic;
signal OSC_A_OUT : std_logic;
signal OSC_B_OUT : std_logic;
signal OSC_C_OUT : std_logic;
signal NOISE_OUT : std_logic;
signal AUDIO_A : std_logic;
signal AUDIO_B : std_logic;
signal AUDIO_C : std_logic;
signal VOL_ENV : std_logic_vector(4 downto 0);
signal AMPLITUDE_A : std_logic_vector(4 downto 0);
signal AMPLITUDE_B : std_logic_vector(4 downto 0);
@@ -130,8 +130,8 @@ begin
ENV_RESET <= false; -- Initialize signal.
if BUSCYCLE = R_WRITE then
case ADR is
when x"0" => FREQUENCY_A(7 downto 0) <= DATA_IN;
when x"1" => FREQUENCY_A(11 downto 8) <= DATA_IN(3 downto 0);
when x"0" => FREQUENCY_A(7 downto 0) <= unsigned(DATA_IN);
when x"1" => FREQUENCY_A(11 downto 8) <= unsigned(DATA_IN(3 downto 0));
when x"2" => FREQUENCY_B(7 downto 0) <= DATA_IN;
when x"3" => FREQUENCY_B(11 downto 8) <= DATA_IN(3 downto 0);
when x"4" => FREQUENCY_C(7 downto 0) <= DATA_IN;
@@ -151,8 +151,8 @@ begin
end process REGISTERS;
-- Read back the configuration registers:
DATA_OUT <= FREQUENCY_A(7 downto 0) when BUSCYCLE = R_READ and ADR = x"0" else
"0000" & FREQUENCY_A(11 downto 8) when BUSCYCLE = R_READ and ADR = x"1" else
DATA_OUT <= std_logic_vector(FREQUENCY_A(7 downto 0)) when BUSCYCLE = R_READ and ADR = x"0" else
"0000" & std_logic_vector(FREQUENCY_A(11 downto 8)) when BUSCYCLE = R_READ and ADR = x"1" else
FREQUENCY_B(7 downto 0) when BUSCYCLE = R_READ and ADR = x"2" else
"0000" & FREQUENCY_B(11 downto 8) when BUSCYCLE = R_READ and ADR = x"3" else
FREQUENCY_C(7 downto 0) when BUSCYCLE = R_READ and ADR = x"4" else
@@ -168,10 +168,10 @@ begin
'1' when BUSCYCLE = R_READ and ADR >= x"8" and ADR <= x"D" else '0';
MUSICGENERATOR: process(RESETn, SYS_CLK)
variable CLK_DIV : std_logic_vector(2 downto 0);
variable CNT_CH_A : std_logic_vector(11 downto 0);
variable CNT_CH_B : std_logic_vector(11 downto 0);
variable CNT_CH_C : std_logic_vector(11 downto 0);
variable CLK_DIV : unsigned (2 downto 0);
variable CNT_CH_A : unsigned (11 downto 0);
variable CNT_CH_B : unsigned (11 downto 0);
variable CNT_CH_C : unsigned (11 downto 0);
begin
if RESETn = '0' then
CLK_DIV := "000";
@@ -186,37 +186,37 @@ begin
-- Divider by 8 for the oscillators brings in connection
-- with the toggle flip flops CH_x_OUT the required divider
-- ratio of 16.
CLK_DIV := CLK_DIV + '1';
CLK_DIV := CLK_DIV + 1;
if CLK_DIV = "000" then
if FREQUENCY_A = x"000" then
CNT_CH_A := (others => '0');
OSC_A_OUT <= '0';
elsif CNT_CH_A = x"000" then
CNT_CH_A := FREQUENCY_A - '1' ;
CNT_CH_A := FREQUENCY_A - 1 ;
OSC_A_OUT <= not OSC_A_OUT;
else
CNT_CH_A := CNT_CH_A - '1';
CNT_CH_A := CNT_CH_A - 1;
end if;
if FREQUENCY_B = x"000" then
CNT_CH_B := (others => '0');
OSC_B_OUT <= '0';
elsif CNT_CH_B = x"000" then
CNT_CH_B := FREQUENCY_B - '1' ;
CNT_CH_B := unsigned(FREQUENCY_B) - 1 ;
OSC_B_OUT <= not OSC_B_OUT;
else
CNT_CH_B := CNT_CH_B - '1';
CNT_CH_B := CNT_CH_B - 1;
end if;
if FREQUENCY_C = x"000" then
CNT_CH_C := (others => '0');
OSC_C_OUT <= '0';
elsif CNT_CH_C = x"000" then
CNT_CH_C := FREQUENCY_C - '1' ;
CNT_CH_C := unsigned(FREQUENCY_C) - 1 ;
OSC_C_OUT <= not OSC_C_OUT;
else
CNT_CH_C := CNT_CH_C - '1';
CNT_CH_C := CNT_CH_C - 1;
end if;
end if;
end if;
@@ -228,8 +228,8 @@ begin
-- (ESE Artists' factory) approach for a 2149 equivalent. But the implementation
-- is done in another way.
-- LFSR (linear feedback shift register polynomial: f(x) = x^17 + x^14 + 1.
variable CLK_DIV : std_logic_vector(3 downto 0);
variable CNT_NOISE : std_logic_vector(4 downto 0);
variable CLK_DIV : unsigned (3 downto 0);
variable CNT_NOISE : unsigned (4 downto 0);
variable N_SHFT : std_logic_vector(16 downto 0);
begin
wait until SYS_CLK = '1' and SYS_CLK' event;
@@ -239,43 +239,43 @@ begin
NOISE_OUT <= '1';
elsif WAV_STRB = '1' then
-- Divider by 16 for the noise generator.
CLK_DIV := CLK_DIV + '1';
CLK_DIV := CLK_DIV + 1;
if CLK_DIV = x"0" then
-- Noise frequency counter.
if NOISE_FREQ = "00000" then
CNT_NOISE := (others => '0');
elsif CNT_NOISE = "00000" then
CNT_NOISE := NOISE_FREQ - '1' ;
CNT_NOISE := unsigned(NOISE_FREQ) - 1 ;
N_SHFT := N_SHFT(15 downto 14) & not(N_SHFT(16) xor N_SHFT(13)) &
N_SHFT(12 downto 0) & not N_SHFT(16);
else
CNT_NOISE := CNT_NOISE - '1';
CNT_NOISE := CNT_NOISE - 1;
end if;
end if;
end if;
NOISE_OUT <= To_Bit(N_SHFT(16));
NOISE_OUT <= N_SHFT(16);
end process NOISEGENERATOR;
ENVELOPE_PERIOD: process(RESETn, SYS_CLK)
-- The envelope period is controlled by the Envelope Frequency and the divider ratio which is
-- 256/32 = 8. For further information see the original data sheet.
variable ENV_CLK : std_logic_vector(18 downto 0);
variable ENVELOPE_CLK : std_logic_vector(18 downto 0);
variable LOCK : boolean;
begin
if RESETn = '0' then
ENV_STRB <= '0';
ENV_CLK := (others => '0');
ENVELOPE_CLK := (others => '0');
LOCK := false;
elsif SYS_CLK = '1' and SYS_CLK' event then
if WAV_STRB = '1' and LOCK = false then
LOCK := true;
if ENV_FREQ = x"0000" then
ENV_STRB <= '0';
elsif ENV_CLK = x"0000" & "000" then
ENV_CLK := (ENV_FREQ & "111") - '1' ;
elsif ENVELOPE_CLK = x"0000" & "000" then
ENVELOPE_CLK := std_logic_vector(((unsigned(ENV_FREQ) & unsigned'("111"))) - 1);
ENV_STRB <= '1';
else
ENV_CLK := ENV_CLK - '1';
ENVELOPE_CLK := std_logic_vector(unsigned(ENVELOPE_CLK) - 1);
ENV_STRB <= '0';
end if;
elsif WAV_STRB = '0' then
@@ -312,7 +312,7 @@ begin
-- 1 1 1 1 /|___
--
variable ENV_STOP : boolean;
variable ENV_UP_DNn : bit;
variable ENV_UP_DNn : std_logic;
begin
if RESETn = '0' then
VOL_ENV <= (others => '0');
@@ -333,22 +333,22 @@ begin
case ENV_SHAPE is
when "1001" | "0011" | "0010" | "0001" | "0000" =>
if VOL_ENV > "00000" then
VOL_ENV <= VOL_ENV - '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) - 1);
end if;
when "1111" | "0111" | "0110" | "0101" | "0100" =>
if VOL_ENV < "11111" and ENV_STOP = false then
VOL_ENV <= VOL_ENV + '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) + 1);
else
VOL_ENV <= "00000";
ENV_STOP := true;
end if;
when "1000" =>
VOL_ENV <= VOL_ENV - '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) - 1);
when "1110" | "1010" =>
if ENV_UP_DNn = '0' then
VOL_ENV <= VOL_ENV - '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) - 1);
else
VOL_ENV <= VOL_ENV + '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) + 1);
end if;
--
if VOL_ENV = "00001" then
@@ -358,16 +358,16 @@ begin
end if;
when "1011" =>
if VOL_ENV > "00000" and ENV_STOP = false then
VOL_ENV <= VOL_ENV - '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) - 1);
else
VOL_ENV <= "11111";
ENV_STOP := true;
end if;
when "1100" =>
VOL_ENV <= VOL_ENV + '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) + 1);
when "1101" =>
if VOL_ENV < "11111" then
VOL_ENV <= VOL_ENV + '1';
VOL_ENV <= std_logic_vector(unsigned(VOL_ENV) + 1);
end if;
when others => null; -- Covers U, X, Z, W, H, L, -.
end case;
@@ -508,7 +508,7 @@ begin
-- a PWM frequency of 16MHz).
begin
wait until SYS_CLK = '1' and SYS_CLK' event;
PWM_RAMP <= PWM_RAMP + '1';
PWM_RAMP <= std_logic_vector(unsigned(PWM_RAMP) + 1);
end process DA_CONVERSION;
OUT_A <= '0' when VOLUME_A = x"00" else '1' when PWM_RAMP < VOLUME_A else '0';
OUT_B <= '0' when VOLUME_B = x"00" else '1' when PWM_RAMP < VOLUME_B else '0';

56
vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
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@@ -63,48 +63,48 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF6850IP_CTRL_STATUS is
port (
CLK : in std_logic;
RESETn : in bit;
RESETn : in std_logic;
CS : in bit_vector(2 downto 0); -- Active if "011".
E : in bit;
RWn : in bit;
RS : in bit;
CS : in std_logic_vector(2 downto 0); -- Active if "011".
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
-- Status register stuff:
RDRF : in bit; -- Receive data register full.
TDRE : in bit; -- Transmit data register empty.
DCDn : in bit; -- Data carrier detect.
CTSn : in bit; -- Clear to send.
FE : in bit; -- Framing error.
OVR : in bit; -- Overrun error.
PE : in bit; -- Parity error.
RDRF : in std_logic; -- Receive data register full.
TDRE : in std_logic; -- Transmit data register empty.
DCDn : in std_logic; -- Data carrier detect.
CTSn : in std_logic; -- Clear to send.
FE : in std_logic; -- Framing error.
OVR : in std_logic; -- Overrun error.
PE : in std_logic; -- Parity error.
-- Control register stuff:
MCLR : buffer bit; -- Master clear (high active).
RTSn : out bit; -- Request to send.
CDS : out bit_vector(1 downto 0); -- Clock control.
WS : out bit_vector(2 downto 0); -- Word select.
TC : out bit_vector(1 downto 0); -- Transmit control.
IRQn : buffer bit -- Interrupt request.
MCLR : buffer std_logic; -- Master clear (high active).
RTSn : out std_logic; -- Request to send.
CDS : out std_logic_vector(1 downto 0); -- Clock control.
WS : out std_logic_vector(2 downto 0); -- Word select.
TC : out std_logic_vector(1 downto 0); -- Transmit control.
IRQn : buffer std_logic -- Interrupt request.
);
end entity WF6850IP_CTRL_STATUS;
architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
signal CTRL_REG : bit_vector(7 downto 0);
signal STATUS_REG : bit_vector(7 downto 0);
signal RIE : bit;
signal CTS_In : bit;
signal DCD_In : bit;
signal DCD_FLAGn : bit;
signal CTRL_REG : std_logic_vector(7 downto 0);
signal STATUS_REG : std_logic_vector(7 downto 0);
signal RIE : std_logic;
signal CTS_In : std_logic;
signal DCD_In : std_logic;
signal DCD_FLAGn : std_logic;
begin
CTS_In <= CTSn;
DCD_In <= DCDn; -- immer 0

86
vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_receive.vhd
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@@ -58,44 +58,44 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF6850IP_RECEIVE is
port (
CLK : in bit;
RESETn : in bit;
MCLR : in bit;
CLK : in std_logic;
RESETn : in std_logic;
MCLR : in std_logic;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
WS : in bit_vector(2 downto 0);
CDS : in bit_vector(1 downto 0);
WS : in std_logic_vector(2 downto 0);
CDS : in std_logic_vector(1 downto 0);
RXCLK : in bit;
RXDATA : in bit;
RXCLK : in std_logic;
RXDATA : in std_logic;
RDRF : buffer bit;
OVR : out bit;
PE : out bit;
FE : out bit
RDRF : buffer std_logic;
OVR : out std_logic;
PE : out std_logic;
FE : out std_logic
);
end entity WF6850IP_RECEIVE;
architecture BEHAVIOR of WF6850IP_RECEIVE is
type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
signal RXDATA_I : bit;
signal RXDATA_S : bit;
signal DATA_REG : bit_vector(7 downto 0);
signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
signal RXDATA_I : std_logic;
signal RXDATA_S : std_logic;
signal DATA_REG : std_logic_vector(7 downto 0);
signal SHIFT_REG : std_logic_vector(7 downto 0);
signal CLK_STRB : std_logic;
signal BITCNT : unsigned (2 downto 0);
begin
P_SAMPLE: process
-- This filter provides a synchronisation to the system
@@ -121,7 +121,7 @@ begin
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
variable CLK_DIVCNT : unsigned (6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- Divider off.
@@ -144,7 +144,7 @@ begin
CLK_STRB <= '0';
else
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_DIVCNT := CLK_DIVCNT - 1;
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
@@ -181,11 +181,11 @@ begin
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
DATA_REG <= x"00";
elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 std_logic data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 std_logic data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
@@ -212,7 +212,7 @@ begin
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
BITCNT <= BITCNT + 1;
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
@@ -220,8 +220,8 @@ begin
FRAME_ERR: process(RESETn, CLK)
-- This module detects a framing error
-- during stop bit 1 and stop bit 2.
variable FE_I: bit;
-- during stop std_logic 1 and stop std_logic 2.
variable FE_I: std_logic;
begin
if RESETn = '0' then
FE_I := '0';
@@ -246,7 +246,7 @@ begin
end process FRAME_ERR;
OVERRUN: process(RESETn, CLK)
variable OVR_I : bit;
variable OVR_I : std_logic;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
@@ -280,8 +280,8 @@ begin
end process OVERRUN;
PARITY_TEST: process(RESETn, CLK)
variable PAR_TMP : bit;
variable PE_I : bit;
variable PAR_TMP : std_logic;
variable PE_I : std_logic;
begin
if RESETn = '0' then
PE <= '0';
@@ -309,7 +309,7 @@ begin
end if;
-- Transmit the parity flag together with the data
-- In other words: no parity to the status register
-- when RDRF inhibits the data transfer to the
-- when RDRF inhistd_logics the data transfer to the
-- receiver data register.
if RCV_STATE = SYNC and RDRF = '0' then
PE <= PE_I;
@@ -353,13 +353,13 @@ begin
case RCV_STATE is
when IDLE =>
if RXDATA_S = '0' and CDS = "00" then
RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
RCV_NEXT_STATE <= SAMPLE; -- Startstd_logic detected in div by 1 mode.
elsif RXDATA_S = '0' and CDS = "01" then
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
RCV_NEXT_STATE <= WAIT_START; -- Startstd_logic detected in div by 16 mode.
elsif RXDATA_S = '0' and CDS = "10" then
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
RCV_NEXT_STATE <= WAIT_START; -- Startstd_logic detected in div by 64 mode.
else
RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
RCV_NEXT_STATE <= IDLE; -- No startstd_logic; sleep well :-)
end if;
when WAIT_START =>
if CLK_STRB = '1' then
@@ -374,9 +374,9 @@ begin
when SAMPLE =>
if CLK_STRB = '1' then
if BITCNT < "110" and WS(2) = '0' then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data std_logics.
elsif BITCNT < "111" and WS(2) = '1' then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data std_logics.
elsif WS = "100" or WS = "101" then
RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
else
@@ -396,9 +396,9 @@ begin
if RXDATA_S = '0' then
RCV_NEXT_STATE <= SYNC; -- Framing error detected.
elsif WS = "000" or WS = "001" or WS = "100" then
RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
RCV_NEXT_STATE <= STOP2; -- Two stop std_logics selected.
else
RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
RCV_NEXT_STATE <= SYNC; -- One stop std_logic selected.
end if;
else
RCV_NEXT_STATE <= STOP1;

62
vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd
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@@ -56,57 +56,57 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF6850IP_TOP is
port (
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
CS2n, CS1, CS0 : in bit;
E : in bit;
RWn : in bit;
RS : in bit;
CS2n, CS1, CS0 : in std_logic;
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA : inout std_logic_vector(7 downto 0);
TXCLK : in bit;
RXCLK : in bit;
RXDATA : in bit;
CTSn : in bit;
DCDn : in bit;
TXCLK : in std_logic;
RXCLK : in std_logic;
RXDATA : in std_logic;
CTSn : in std_logic;
DCDn : in std_logic;
IRQn : out std_logic;
TXDATA : out bit;
RTSn : out bit
TXDATA : out std_logic;
RTSn : out std_logic
);
end entity WF6850IP_TOP;
architecture STRUCTURE of WF6850IP_TOP is
component WF6850IP_TOP_SOC
port (
CLK : in bit;
RESETn : in bit;
CS2n, CS1, CS0 : in bit;
E : in bit;
RWn : in bit;
RS : in bit;
CLK : in std_logic;
RESETn : in std_logic;
CS2n, CS1, CS0 : in std_logic;
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
TXCLK : in bit;
RXCLK : in bit;
RXDATA : in bit;
CTSn : in bit;
DCDn : in bit;
IRQn : out bit;
TXDATA : out bit;
RTSn : out bit
DATA_EN : out std_logic;
TXCLK : in std_logic;
RXCLK : in std_logic;
RXDATA : in std_logic;
CTSn : in std_logic;
DCDn : in std_logic;
IRQn : out std_logic;
TXDATA : out std_logic;
RTSn : out std_logic
);
end component;
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_EN : bit;
signal IRQ_In : bit;
signal DATA_EN : std_logic;
signal IRQ_In : std_logic;
begin
DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.

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vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd
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@@ -61,124 +61,124 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF6850IP_TOP_SOC is
port (
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
CS2n, CS1, CS0 : in bit;
E : in bit;
RWn : in bit;
RS : in bit;
CS2n, CS1, CS0 : in std_logic;
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
DATA_EN : out std_logic;
TXCLK : in bit;
RXCLK : in bit;
RXDATA : in bit;
CTSn : in bit;
DCDn : in bit;
TXCLK : in std_logic;
RXCLK : in std_logic;
RXDATA : in std_logic;
CTSn : in std_logic;
DCDn : in std_logic;
IRQn : out bit;
TXDATA : out bit;
RTSn : out bit
IRQn : out std_logic;
TXDATA : out std_logic;
RTSn : out std_logic
);
end entity WF6850IP_TOP_SOC;
architecture STRUCTURE of WF6850IP_TOP_SOC is
component WF6850IP_CTRL_STATUS
port (
CLK : in bit;
RESETn : in bit;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
RDRF : in bit;
TDRE : in bit;
DCDn : in bit;
CTSn : in bit;
FE : in bit;
OVR : in bit;
PE : in bit;
MCLR : out bit;
RTSn : out bit;
CDS : out bit_vector(1 downto 0);
WS : out bit_vector(2 downto 0);
TC : out bit_vector(1 downto 0);
IRQn : out bit
CLK : in std_logic;
RESETn : in std_logic;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
RDRF : in std_logic;
TDRE : in std_logic;
DCDn : in std_logic;
CTSn : in std_logic;
FE : in std_logic;
OVR : in std_logic;
PE : in std_logic;
MCLR : out std_logic;
RTSn : out std_logic;
CDS : out std_logic_vector(1 downto 0);
WS : out std_logic_vector(2 downto 0);
TC : out std_logic_vector(1 downto 0);
IRQn : out std_logic
);
end component;
component WF6850IP_RECEIVE
port (
CLK : in bit;
RESETn : in bit;
MCLR : in bit;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
WS : in bit_vector(2 downto 0);
CDS : in bit_vector(1 downto 0);
RXCLK : in bit;
RXDATA : in bit;
RDRF : out bit;
OVR : out bit;
PE : out bit;
FE : out bit
CLK : in std_logic;
RESETn : in std_logic;
MCLR : in std_logic;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
WS : in std_logic_vector(2 downto 0);
CDS : in std_logic_vector(1 downto 0);
RXCLK : in std_logic;
RXDATA : in std_logic;
RDRF : out std_logic;
OVR : out std_logic;
PE : out std_logic;
FE : out std_logic
);
end component;
component WF6850IP_TRANSMIT
port (
CLK : in bit;
RESETn : in bit;
MCLR : in bit;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
DATA_IN : in bit_vector(7 downto 0);
CTSn : in bit;
TC : in bit_vector(1 downto 0);
WS : in bit_vector(2 downto 0);
CDS : in bit_vector(1 downto 0);
TXCLK : in bit;
TDRE : out bit;
TXDATA : out bit
CLK : in std_logic;
RESETn : in std_logic;
MCLR : in std_logic;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
CTSn : in std_logic;
TC : in std_logic_vector(1 downto 0);
WS : in std_logic_vector(2 downto 0);
CDS : in std_logic_vector(1 downto 0);
TXCLK : in std_logic;
TDRE : out std_logic;
TXDATA : out std_logic
);
end component;
signal DATA_IN_I : bit_vector(7 downto 0);
signal DATA_RX : bit_vector(7 downto 0);
signal DATA_RX_EN : bit;
signal DATA_CTRL : bit_vector(7 downto 0);
signal DATA_CTRL_EN : bit;
signal RDRF_I : bit;
signal TDRE_I : bit;
signal FE_I : bit;
signal OVR_I : bit;
signal PE_I : bit;
signal MCLR_I : bit;
signal CDS_I : bit_vector(1 downto 0);
signal WS_I : bit_vector(2 downto 0);
signal TC_I : bit_vector(1 downto 0);
signal IRQ_In : bit;
signal DATA_IN_I : std_logic_vector(7 downto 0);
signal DATA_RX : std_logic_vector(7 downto 0);
signal DATA_RX_EN : std_logic;
signal DATA_CTRL : std_logic_vector(7 downto 0);
signal DATA_CTRL_EN : std_logic;
signal RDRF_I : std_logic;
signal TDRE_I : std_logic;
signal FE_I : std_logic;
signal OVR_I : std_logic;
signal PE_I : std_logic;
signal MCLR_I : std_logic;
signal CDS_I : std_logic_vector(1 downto 0);
signal WS_I : std_logic_vector(2 downto 0);
signal TC_I : std_logic_vector(1 downto 0);
signal IRQ_In : std_logic;
begin
DATA_IN_I <= To_BitVector(DATA_IN);
DATA_IN_I <= (DATA_IN);
DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else
To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
DATA_OUT <= (DATA_RX) when DATA_RX_EN = '1' else
(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
IRQn <= '0' when IRQ_In = '0' else '1';

68
vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_transmit.vhd
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@@ -59,42 +59,42 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF6850IP_TRANSMIT is
port (
CLK : in std_logic;
RESETn : in bit;
MCLR : in bit;
RESETn : in std_logic;
MCLR : in std_logic;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in bit_vector(7 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
CTSn : in bit;
CTSn : in std_logic;
TC : in bit_vector(1 downto 0);
WS : in bit_vector(2 downto 0);
CDS : in bit_vector(1 downto 0);
TC : in std_logic_vector(1 downto 0);
WS : in std_logic_vector(2 downto 0);
CDS : in std_logic_vector(1 downto 0);
TXCLK : in bit;
TXCLK : in std_logic;
TDRE : buffer bit;
TXDATA : out bit
TDRE : buffer std_logic;
TXDATA : out std_logic
);
end entity WF6850IP_TRANSMIT;
architecture BEHAVIOR of WF6850IP_TRANSMIT is
type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
signal TR_STATE, TR_NEXT_STATE : TR_STATES;
signal CLK_STRB : bit;
signal DATA_REG : bit_vector(7 downto 0);
signal SHIFT_REG : bit_vector(7 downto 0);
signal BITCNT : std_logic_vector(2 downto 0);
signal PARITY_I : bit;
signal CLK_STRB : std_logic;
signal DATA_REG : std_logic_vector(7 downto 0);
signal SHIFT_REG : std_logic_vector(7 downto 0);
signal BITCNT : unsigned(2 downto 0);
signal PARITY_I : std_logic;
begin
-- The default condition in this statement is to ensure
-- to cover all possibilities for example if there is a
@@ -111,7 +111,7 @@ begin
CLKDIV: process(CLK)
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
variable CLK_DIVCNT : unsigned (6 downto 0);
begin
if rising_edge(CLK) then
if CDS = "00" then -- divider off
@@ -135,7 +135,7 @@ begin
else
-- Works on negative TXCLK edge:
if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_DIVCNT := CLK_DIVCNT - 1;
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
@@ -173,9 +173,9 @@ begin
if MCLR = '1' then
DATA_REG <= x"00";
elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode.
DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 std_logic data mode.
elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
DATA_REG <= DATA_IN; -- 8 bit data mode.
DATA_REG <= DATA_IN; -- 8 std_logic data mode.
end if;
end if;
end process DATAREG;
@@ -191,7 +191,7 @@ begin
-- If during LOAD_SHIFT the transmitter data register
-- is empty (TDRE = '1') the shift register will not
-- be loaded. When additionally TC = "11", the break
-- character (zero data and no stop bits) is sent.
-- character (zero data and no stop std_logics) is sent.
SHIFT_REG <= DATA_REG;
elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
@@ -200,11 +200,11 @@ begin
end process SHIFTREG;
P_BITCNT: process(CLK)
-- Counter for the data bits transmitted.
-- Counter for the data std_logics transmitted.
begin
if rising_edge(CLK) then
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
BITCNT <= BITCNT + 1;
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
end if;
@@ -232,7 +232,7 @@ begin
end process P_TDRE;
PARITY_GEN: process(CLK)
variable PAR_TMP : bit;
variable PAR_TMP : std_logic;
begin
if rising_edge(CLK) then
if TR_STATE = START then -- Calculate the parity during the start phase.
@@ -291,12 +291,12 @@ begin
when SHIFTOUT =>
if CLK_STRB = '1' then
if BITCNT < "110" and WS(2) = '0' then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data std_logics.
elsif BITCNT < "111" and WS(2) = '1' then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data std_logics.
elsif WS = "100" or WS = "101" then
if TDRE = '1' and TC = "11" then
-- Break condition, do not send a stop bit.
-- Break condition, do not send a stop std_logic.
TR_NEXT_STATE <= IDLE;
else
TR_NEXT_STATE <= STOP1; -- No parity check enabled.
@@ -310,7 +310,7 @@ begin
when PARITY =>
if CLK_STRB = '1' then
if TDRE = '1' and TC = "11" then
-- Break condition, do not send a stop bit.
-- Break condition, do not send a stop std_logic.
TR_NEXT_STATE <= IDLE;
else
TR_NEXT_STATE <= STOP1; -- No parity check enabled.
@@ -320,9 +320,9 @@ begin
end if;
when STOP1 =>
if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then
TR_NEXT_STATE <= STOP2; -- Two stop bits selected.
TR_NEXT_STATE <= STOP2; -- Two stop std_logics selected.
elsif CLK_STRB = '1' then
TR_NEXT_STATE <= IDLE; -- One stop bits selected.
TR_NEXT_STATE <= IDLE; -- One stop std_logics selected.
else
TR_NEXT_STATE <= STOP1;
end if;