307 lines
16 KiB
VHDL
307 lines
16 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- This file is part of the 'Firebee' project. ----
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---- http://acp.atari.org ----
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---- ----
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---- Description: ----
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---- This design unit provides the interruptlogic of the 'Firebee'----
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---- computer. It is optimized for the use of an Altera Cyclone ----
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---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----
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---- tion of the Firebee configware originally provided by Fredi ----
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---- Ashwanden and Wolfgang Förster. This release is in compa- ----
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---- rision to the first edition completely written in VHDL. ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 2 of the License, or (at your option) any later ----
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---- version. ----
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---- ----
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---- This program is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU General Public ----
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---- License along with this program; if not, write to the Free ----
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---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
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---- Boston, MA 02110-1301, USA. ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K12B 20120801 WF
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-- Initial Release of the second edition.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- use ieee.std_logic_arith.all;
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entity INTHANDLER is
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port(
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CLK_MAIN : in std_logic;
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RESETn : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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FB_CSn : in std_logic_vector(2 downto 1);
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_WRn : in std_logic;
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FB_OEn : in std_logic;
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FB_AD_IN : in std_logic_vector(31 downto 0);
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FB_AD_OUT : out std_logic_vector(31 downto 0);
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FB_AD_EN_31_24 : out std_logic;
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FB_AD_EN_23_16 : out std_logic;
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FB_AD_EN_15_8 : out std_logic;
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FB_AD_EN_7_0 : out std_logic;
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PIC_INT : in std_logic;
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E0_INT : in std_logic;
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DVI_INT : in std_logic;
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PCI_INTAn : in std_logic;
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PCI_INTBn : in std_logic;
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PCI_INTCn : in std_logic;
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PCI_INTDn : in std_logic;
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MFP_INTn : in std_logic;
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DSP_INT : in std_logic;
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VSYNC : in std_logic;
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HSYNC : in std_logic;
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DRQ_DMA : in std_logic;
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IRQn : out std_logic_vector(7 downto 2);
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INT_HANDLER_TA : out std_logic;
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FBEE_CONF : out std_logic_vector(31 downto 0);
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TIN0 : out std_logic
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);
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end entity INTHANDLER;
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architecture BEHAVIOUR of INTHANDLER is
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type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0);
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signal INT_LA : INT_LA_TYPE;
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signal FB_B : std_logic_vector(3 downto 0);
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signal INT_CTR : std_logic_vector(31 downto 0);
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signal INT_CTR_CS : std_logic;
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signal INT_LATCH : std_logic_vector(31 downto 0);
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signal INT_LATCH_CS : std_logic;
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signal INT_CLEAR : std_logic_vector(31 downto 0);
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signal INT_CLEAR_CS : std_logic;
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signal INT_IN : std_logic_vector(31 downto 0);
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signal INT_ENA : std_logic_vector(31 downto 0);
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signal INT_ENA_CS : std_logic;
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signal INT_L : std_logic_vector(9 downto 0);
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signal FBEE_CONF_REG : std_logic_vector(31 downto 0);
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signal FBEE_CONF_CS : std_logic;
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signal PSEUDO_BUS_ERROR : std_logic;
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begin
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-- Byte selectors:
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FB_B(0) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "00" else -- HH Byte.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
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'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
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FB_B(1) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
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'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
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FB_B(2) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "10" else -- LH Byte.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
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'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
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FB_B(3) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte.
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'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
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'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
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INT_CTR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000000" else '0'; -- $10000/4;
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INT_ENA_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000001" else '0'; -- $10004/4;
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INT_CLEAR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000010" else '0'; -- $10008/4;
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INT_LATCH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000011" else '0'; -- $1000C/4;
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P_INT_CTRL : process
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-- Interrupt control register:
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--BIT0 = INT5, Bit1 = INT7.
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-- Interrupt enabe register:
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-- BIT31 = INT7, Bit30 = INT6, Bit29 = INT5, Bit28 = INT4, Bit27 = INT3, Bit26 = INT2
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-- The interrupt clear register is write only; 1 = interrupt clear.
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begin
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wait until CLK_MAIN = '1' and CLK_MAIN' event;
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if INT_CTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
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INT_CTR(31 downto 24) <= FB_AD_IN(31 downto 24);
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elsif INT_CTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
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INT_CTR(23 downto 16) <= FB_AD_IN(23 downto 16);
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elsif INT_CTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
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INT_CTR(15 downto 8) <= FB_AD_IN(15 downto 8);
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elsif INT_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
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INT_CTR(7 downto 0) <= FB_AD_IN(7 downto 0);
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end if;
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--
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if RESETn = '0' then
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INT_ENA <= (others => '0');
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elsif INT_ENA_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
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INT_ENA(31 downto 24) <= FB_AD_IN(31 downto 24);
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elsif INT_ENA_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
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INT_ENA(23 downto 16) <= FB_AD_IN(23 downto 16);
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elsif INT_ENA_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
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INT_ENA(15 downto 8) <= FB_AD_IN(15 downto 8);
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elsif INT_ENA_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
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INT_ENA(7 downto 0) <= FB_AD_IN(7 downto 0);
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end if;
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--
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if INT_CLEAR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
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INT_CLEAR(31 downto 24) <= FB_AD_IN(31 downto 24);
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elsif INT_CLEAR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
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INT_CLEAR(23 downto 16) <= FB_AD_IN(23 downto 16);
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elsif INT_CLEAR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
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INT_CLEAR(15 downto 8) <= FB_AD_IN(15 downto 8);
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elsif INT_CLEAR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
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INT_CLEAR(7 downto 0) <= FB_AD_IN(7 downto 0);
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end if;
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end process P_INT_CTRL;
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-- Interrupt latch register: read only.
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IRQn(2) <= '0' when HSYNC = '1' and INT_ENA(26) = '1' else '1';
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IRQn(3) <= '0' when INT_CTR(0) = '1' and INT_ENA(27) = '1' else '1';
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IRQn(4) <= '0' when VSYNC = '1' and INT_ENA(28) = '1' else '1';
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IRQn(5) <= '0' when INT_LATCH /= x"00000000" and INT_ENA(29) = '1' else '1';
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IRQn(6) <= '0' when MFP_INTn = '0' and INT_ENA(30) = '1' else '1';
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IRQn(7) <= '0' when PSEUDO_BUS_ERROR = '1' and INT_ENA(31) = '1' else '1';
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PSEUDO_BUS_ERROR <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F8C8" else -- SCC
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F8E0" else -- VME
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-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F920" else -- PADDLE
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-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F921" else -- PADDLE
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-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F922" else -- PADDLE
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA9" else -- MFP2
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFAA" else -- MFP2
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 8) = x"F87" else -- TT SCSI
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC2" else -- ST UHR
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'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC3" else '0'; -- ST UHR
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-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F890" else -- DMA SOUND
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-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F891" else -- DMA SOUND
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-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND
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-- IF video ADR changes:
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TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2.
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P_INT_LATCH : process
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begin
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wait until CLK_MAIN = '1' and CLK_MAIN' event;
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if RESETn = '0' then
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INT_L <= (others => '0');
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else
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INT_L(0) <= PIC_INT and INT_ENA(0);
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INT_L(1) <= E0_INT and INT_ENA(1);
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INT_L(2) <= DVI_INT and INT_ENA(2);
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INT_L(3) <= not PCI_INTAn and INT_ENA(3);
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INT_L(4) <= not PCI_INTBn and INT_ENA(4);
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INT_L(5) <= not PCI_INTCn and INT_ENA(5);
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INT_L(6) <= not PCI_INTDn and INT_ENA(6);
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INT_L(7) <= DSP_INT and INT_ENA(7);
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INT_L(8) <= VSYNC and INT_ENA(8);
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INT_L(9) <= HSYNC and INT_ENA(9);
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end if;
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for i in 0 to 9 loop
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if INT_ENA(i) = '1' and RESETn = '1' then
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INT_LA(i) <= x"0";
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elsif INT_L(i) = '1' and INT_LA(i) < x"7" then
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INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) + 1);
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elsif INT_L(i) = '0' and INT_LA(i) > x"8" then
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INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) - 1);
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elsif INT_L(i) = '1' and INT_LA(i) > x"6" then
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INT_LA(i) <= x"F";
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elsif INT_L(i) = '0' and INT_LA(i) > x"9" then
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INT_LA(i) <= x"0";
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end if;
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end loop;
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for i in 0 to 31 loop
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if INT_CLEAR(i) = '0' and RESETn = '1' then
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INT_LATCH(i) <= '0';
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end if;
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end loop;
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for i in 0 to 9 loop
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if INT_LA(i)(3) = '1' then
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INT_LATCH(i) <= '1';
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end if;
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end loop;
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end process P_INT_LATCH;
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-- INT_IN:
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INT_IN(0) <= PIC_INT;
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INT_IN(1) <= E0_INT;
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INT_IN(2) <= DVI_INT;
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INT_IN(3) <= not PCI_INTAn;
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INT_IN(4) <= not PCI_INTBn;
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INT_IN(5) <= not PCI_INTCn;
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INT_IN(6) <= not PCI_INTDn;
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INT_IN(7) <= DSP_INT;
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INT_IN(8) <= VSYNC;
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INT_IN(9) <= HSYNC;
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INT_IN(25 downto 10) <= x"0000";
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INT_IN(26) <= HSYNC;
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INT_IN(27) <= INT_CTR(0);
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INT_IN(28) <= VSYNC;
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INT_IN(29) <= '1' when INT_LATCH /= x"00000000";
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INT_IN(30) <= not MFP_INTn;
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INT_IN(31) <= DRQ_DMA;
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FBEE_CONF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000001000000000000000000" else '0'; -- $40000/4.
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P_FBEE_CONFIG : process
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-- Firebee configuration register: BIT 31 -> 0 = CF 1 = IDE
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begin
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wait until CLK_MAIN = '1' and CLK_MAIN' event;
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if FBEE_CONF_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
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FBEE_CONF_REG(31 downto 24) <= FB_AD_IN(31 downto 24);
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elsif FBEE_CONF_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
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FBEE_CONF_REG(23 downto 16) <= FB_AD_IN(23 downto 16);
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elsif FBEE_CONF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
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FBEE_CONF_REG(15 downto 8) <= FB_AD_IN(15 downto 8);
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elsif FBEE_CONF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
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FBEE_CONF_REG(7 downto 0) <= FB_AD_IN(7 downto 0);
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end if;
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FBEE_CONF <= FBEE_CONF_REG;
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end process P_FBEE_CONFIG;
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-- Data out multiplexers:
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FB_AD_EN_31_24 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
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FB_AD_EN_23_16 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
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FB_AD_EN_15_8 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
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FB_AD_EN_7_0 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
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FB_AD_OUT(31 downto 24) <= INT_CTR(31 downto 24) when INT_CTR_CS = '1' else
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INT_ENA(31 downto 24) when INT_ENA_CS = '1' else
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INT_LATCH(31 downto 24) when INT_LATCH_CS = '1' else
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INT_IN(31 downto 24) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(31 downto 24);
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FB_AD_OUT(23 downto 16) <= INT_CTR(23 downto 16) when INT_CTR_CS = '1' else
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INT_ENA(23 downto 16) when INT_ENA_CS = '1' else
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INT_LATCH(23 downto 16) when INT_LATCH_CS = '1' else
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INT_IN(23 downto 16) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(23 downto 16);
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FB_AD_OUT(15 downto 8) <= INT_CTR(15 downto 8) when INT_CTR_CS = '1' else
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INT_ENA(15 downto 8) when INT_ENA_CS = '1' else
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INT_LATCH(15 downto 8) when INT_LATCH_CS = '1' else
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INT_CLEAR(15 downto 8) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(15 downto 8);
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FB_AD_OUT(7 downto 0) <= INT_CTR(7 downto 0) when INT_CTR_CS = '1' else
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INT_ENA(7 downto 0) when INT_ENA_CS = '1' else
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INT_LATCH(7 downto 0) when INT_LATCH_CS = '1' else
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INT_CLEAR(7 downto 0) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(7 downto 0);
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INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS;
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end architecture BEHAVIOUR;
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