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integrated printf routines. Only tested yet for "before copy"-case (which is more difficult than afterwards).

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This commit is contained in:
Markus Fröschle
2012-10-25 18:12:16 +00:00
parent 410323d676
commit 481331dbf5
7 changed files with 188 additions and 175 deletions
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4
BaS_GNU/BaS_GNU/Makefile
View File

@@ -20,7 +20,7 @@ CPP=$(TCPREFIX)cpp
OBJCOPY=$(TCPREFIX)objcopy
INCLUDE=-Iinclude
CFLAGS=-mcpu=5474 -Wall -Wno-multichar -Os -fomit-frame-pointer -fno-strict-aliasing
CFLAGS=-mcpu=5474 -Wall -Wno-multichar -Os -fomit-frame-pointer -fno-strict-aliasing -fno-builtin
SRCDIR=sources
OBJDIR=objs
@@ -39,7 +39,7 @@ RAM_EXEC=ram.s19
CSRCS= \
$(SRCDIR)/sysinit.c \
$(SRCDIR)/init_fpga.c \
$(SRCDIR)/printf.c \
$(SRCDIR)/bas_printf.c \
$(SRCDIR)/BaS.c \
$(SRCDIR)/cache.c \
$(SRCDIR)/sd_card.c

6
BaS_GNU/BaS_GNU/bas.lk.in
View File

@@ -76,9 +76,9 @@ SECTIONS {
objs/BaS.o(.text)
/* put other routines into the same segment (RAM) as BaS.o */
objs/sd_card_asm.o(.text)
_printf_before_copy = . - (ADDR(.bas) - LOADADDR(.bas));
_printf_after_copy = ABSOLUTE(.);
objs/printf.o(.text)
_xprintf_before_copy = _xprintf - (_BaS - LOADADDR(.bas));
_xprintf_after_copy = _xprintf;
objs/bas_printf.o(.text)
objs/printf_helper.o(.text)
objs/sd_card.o(.text)
objs/mmu.o(.text)

8
BaS_GNU/BaS_GNU/include/printf.h → BaS_GNU/BaS_GNU/include/bas_printf.h
View File

@@ -1,9 +1,11 @@
#ifndef _PRINTF_H_
#define _PRINTF_H_
#ifndef _BAS_PRINTF_H_
#define _BAS_PRINTF_H_
#include <stdarg.h>
typedef uint32_t size_t;
extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
extern void xvprintf(const char *fmt, va_list va);
extern void xprintf(const char *fmt, ...);
extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
#endif /* _PRINTF_H_ */
#endif /* _BAS_PRINTF_H_ */

24
BaS_GNU/BaS_GNU/mcf5474.bdm
View File

@@ -11,41 +11,55 @@ reset
# set VBR
write-ctrl 0x0801 0x00000000
sleep 10
# Turn on MBAR at 0xFF00_0000
write-ctrl 0x0C0F 0xFF000000
sleep 10
# Turn on MMUBAR at 0xFF04_0000
#write-ctrl 0x0008 0xFF000001
#write 0xFF000008 0x00000000 4
# Turn on RAMBAR0 at address FF10_0000
write-ctrl 0x0C04 0xFF100007
sleep 10
# Turn on RAMBAR1 at address FF10_1000
write-ctrl 0x0C05 0xFF101001
sleep 10
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
write 0xFF000500 0xE0000000 4
write 0xFF000508 0x00001180 4 # 16-bit port
write 0xFF000504 0x007F0001 4
sleep 10
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
sleep 10
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
sleep 10
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
sleep 10
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
sleep 10
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
sleep 10
write 0xFF000108 0x73622830 4 # SDCFG1
sleep 10
write 0xFF00010C 0x46770000 4 # SDCFG2
sleep 10
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
sleep 10
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
sleep 10
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
sleep 10
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
sleep 10
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
sleep 10
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
sleep 10
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
sleep 10
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
load -v ram.s19.elf

36
BaS_GNU/BaS_GNU/mcf5474.gdb
View File

@@ -19,30 +19,30 @@ end
define setup-dram
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
set *((long *) 0xFF000500) = 0xE0000000 # flash address
set *((long *) 0xFF000508) = 0x00041180 # 16 bit 4ws aa
set *((long *) 0xFF000504) = 0x007F0001 # 8MB on
set *((long *) 0xFF000500) = 0xE0000000
set *((long *) 0xFF000508) = 0x00041180
set *((long *) 0xFF000504) = 0x007F0001
# set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
set *((long *) 0xFF000004) = 0x000002AA # SDRAMDS configuration
set *((long *) 0xFF000020) = 0x0000001A # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
set *((long *) 0xFF000024) = 0x0800001A # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
set *((long *) 0xFF000028) = 0x1000001A # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
set *((long *) 0xFF00002C) = 0x1800001A # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
set *((long *) 0xFF000108) = 0x73622830 # SDCFG1
set *((long *) 0xFF00010C) = 0x46770000 # SDCFG2
set *((long *) 0xFF000004) = 0x000002AA
set *((long *) 0xFF000020) = 0x0000001A
set *((long *) 0xFF000024) = 0x0800001A
set *((long *) 0xFF000028) = 0x1000001A
set *((long *) 0xFF00002C) = 0x1800001A
set *((long *) 0xFF000108) = 0x73622830
set *((long *) 0xFF00010C) = 0x46770000
set *((long *) 0xFF000104) = 0xE10D0002 # SDCR + IPALL
set *((long *) 0xFF000100) = 0x40010000 # SDMR (write to LEMR)
set *((long *) 0xFF000100) = 0x048D0000 # SDMR (write to LMR)
set *((long *) 0xFF000104) = 0xE10D0002 # SDCR + IPALL
set *((long *) 0xFF000104) = 0xE10D0004 # SDCR + IREF (first refresh)
set *((long *) 0xFF000104) = 0xE10D0004 # SDCR + IREF (first refresh)
set *((long *) 0xFF000100) = 0x008D0000 # SDMR (write to LMR)
set *((long *) 0xFF000104) = 0x710D0F00 # SDCR (lock SDMR and enable refresh)
set *((long *) 0xFF000104) = 0xE10D0002
set *((long *) 0xFF000100) = 0x40010000
set *((long *) 0xFF000100) = 0x048D0000
set *((long *) 0xFF000104) = 0xE10D0002
set *((long *) 0xFF000104) = 0xE10D0004
set *((long *) 0xFF000104) = 0xE10D0004
set *((long *) 0xFF000100) = 0x008D0000
set *((long *) 0xFF000104) = 0x710D0F00
end
#

5
BaS_GNU/BaS_GNU/sources/printf.c → BaS_GNU/BaS_GNU/sources/bas_printf.c
View File

@@ -33,10 +33,7 @@
*/
#include "MCF5475.h"
#include <stdarg.h>
#include <string.h>
#include <bas_printf.h>
/*
* Lexical definitions.
*

280
BaS_GNU/BaS_GNU/sources/sysinit.c
View File

@@ -11,6 +11,10 @@
#include "startcf.h"
#include "cache.h"
#include "sysinit.h"
#include "bas_printf.h"
extern void xprintf_before_copy(const char *fmt, ...);
#define xprintf xprintf_before_copy
#define UNUSED(x) (void)(x) /* Unused variable */
@@ -72,12 +76,10 @@ void wait_1us(void)
*/
void init_slt(void)
{
xprintf("slice timers initialization: ");
MCF_SLT0_STCNT = 0xffffffff;
MCF_SLT0_SCR = 0x05000000;
uart_out_word('SLT ');
uart_out_word('OK. ');
uart_out_word(0x0a0d);
xprintf("finished\r\n");
}
/*
@@ -151,10 +153,7 @@ void init_serial(void)
MCF_PSC3_PSCCR = 0x05;
MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/
uart_out_word('SERI');
uart_out_word('AL O');
uart_out_word('K. ');
uart_out_word(0x0a0d);
xprintf("serial interfaces initialization: finished\r\n");
}
/********************************************************************/
@@ -162,7 +161,7 @@ void init_serial(void)
/********************************************************************/
void init_ddram(void)
{
uart_out_word('DDRA');
xprintf("SDRAM controller initialization: ");
/*
* Check to see if the SDRAM has already been initialized
@@ -195,9 +194,7 @@ void init_ddram(void)
// MCF_SDRAMC_SDCR = 0x710F0F00; // SDCR (lock SDMR and enable refresh)
MCF_SDRAMC_SDCR = 0x710D0F00; // SDCR (lock SDMR and enable refresh)
}
uart_out_word('M OK');
uart_out_word('. ');
uart_out_word(0x0a0d);
xprintf("finished\r\n");
}
/*
@@ -205,7 +202,7 @@ void init_ddram(void)
*/
void init_fbcs()
{
uart_out_word('FBCS');
xprintf("FlexBus chip select registers initialization: ");
/* Flash */
MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS
@@ -238,8 +235,7 @@ void init_fbcs()
MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF
| MCF_FBCS_CSMR_V);
uart_out_word(' OK.');
uart_out_word(0x0a0d);
xprintf("finished\r\n");
}
@@ -254,7 +250,7 @@ static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
void init_pll(void)
{
uart_out_word('PLL ');
xprintf("FPGA PLL initialization: ");
wait_pll();
* (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */
@@ -296,8 +292,7 @@ void init_pll(void)
* (volatile uint8_t *) 0xf0000800 = 0; /* set */
uart_out_word('SET.');
uart_out_word(0x0a0d);
xprintf("finished\r\n");
}
@@ -346,7 +341,7 @@ void init_video_ddr(void) {
* INIT PCI
*/
void init_PCI(void) {
uart_out_word('PCI ');
xprintf("PCI BUS controller initialization: ");
MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI
+ MCF_PCIARB_PACR_EXTMPRI(0x1F)
@@ -377,8 +372,7 @@ void init_PCI(void) {
/* reset PCI devices */
MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
uart_out_word('OK. ');
uart_out_word(0x0d0a);
xprintf("finished\r\n");
}
@@ -387,7 +381,7 @@ void init_PCI(void) {
*/
void test_upd720101(void)
{
uart_out_word('NEC ');
xprintf("UDP720101 USB controller initialization: ");
/* select UPD720101 AD17 */
MCF_PCI_PCICAR = MCF_PCI_PCICAR_E +
@@ -412,8 +406,7 @@ void test_upd720101(void)
MCF_PCI_PCICAR_FUNCNUM(0) +
MCF_PCI_PCICAR_DWORD(57);
}
uart_out_word('OK. ');
uart_out_word(0x0d0a);
xprintf("finished\r\n");
}
/*
@@ -422,153 +415,163 @@ void test_upd720101(void)
void dvi_on(void) {
uint8_t RBYT;
uint8_t DBYT; /* only used for a dummy read */
int tries;
int num_tries = 0;
uart_out_word('DVI ');
xprintf("DVI digital video output initialization: ");
MCF_I2C_I2FDR = 0x3c; // 100kHz standard
tries = 0;
loop_i2c:
if (tries++ > 10)
goto next;
MCF_I2C_I2ICR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2CR = 0xA;
RBYT = MCF_I2C_I2DR;
MCF_I2C_I2SR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2ICR = 0x01;
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7a; // ADRESSE TFP410
do {
MCF_I2C_I2ICR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2CR = 0xA;
RBYT = MCF_I2C_I2DR;
MCF_I2C_I2SR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2ICR = 0x01;
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7a; // ADRESSE TFP410
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue;
MCF_I2C_I2DR = 0x00; // SUB ADRESS 0
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig
MCF_I2C_I2DR = 0x00; // SUB ADRESS 0
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
MCF_I2C_I2SR &= 0xfd; // clear bit
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
goto loop_i2c; // ack erhalten? -> nein
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
; // warten auf fertig
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2SR &= 0xfd; // clear bit
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x08; // txak=1
RBYT = MCF_I2C_I2DR;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue;
DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
if (RBYT != 0x4c)
goto loop_i2c;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
MCF_I2C_I2CR = 0x0; // stop
MCF_I2C_I2SR = 0x0; // clear sr
MCF_I2C_I2SR &= 0xfd;
while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)); // wait auf bus free
MCF_I2C_I2CR |= 0x08; // txak=1
RBYT = MCF_I2C_I2DR;
MCF_I2C_I2CR = 0xb0; // on tx master
MCF_I2C_I2DR = 0x7A;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable
DBYT = MCF_I2C_I2DR; // dummy read
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
if (RBYT != 0x4c)
continue;
MCF_I2C_I2SR &= 0xfd;;
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2SR = 0x0; // clear sr
MCF_I2C_I2CR = 0x0; // stop
MCF_I2C_I2SR = 0x0; // clear sr
while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)); // wait auf bus free
while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB))
; // wait auf bus free
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7A;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig
MCF_I2C_I2CR = 0xb0; // on tx master
MCF_I2C_I2DR = 0x7A;
MCF_I2C_I2SR &= 0xfd; // clear bit
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
; // warten auf fertig
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2SR &= 0xfd; // clear bit
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
MCF_I2C_I2SR &= 0xfd; // clear bit
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x08; // txak=1
MCF_I2C_I2SR &= 0xfd;
;
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2SR = 0x0; // clear sr
wait_50us();
RBYT = MCF_I2C_I2DR;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF));
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB))
; // wait auf bus free
DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7A;
if (RBYT != 0xbf)
goto loop_i2c;
goto dvi_ok;
next:
uart_out_word('NOT ');
dvi_ok:
uart_out_word('OK. ');
uart_out_word(0x0a0d);
MCF_I2C_I2CR = 0x0; // i2c off
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
; // warten auf fertig
UNUSED(DBYT); // Avoid warning
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue;
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue;
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x08; // txak=1
wait_50us();
RBYT = MCF_I2C_I2DR;
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
} while (RBYT != 0xbf || num_tries++ < 10);
if (num_tries >= 10) {
xprintf("FAILED!\r\n");
} else {
xprintf("finished\r\n");
}
UNUSED(DBYT);
// Avoid warning
}
@@ -714,9 +717,6 @@ void initialize_hardware(void) {
init_gpio();
init_serial();
uart_out_word(0x0d0a);
uart_out_word('----');
init_slt();
init_fbcs();
init_ddram();