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DDR2 simulation compiles in ModelSim

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This commit is contained in:
Markus Fröschle
2014-12-22 05:57:17 +00:00
parent 1aab3c25d2
commit 3e769ceeb4
17 changed files with 1087 additions and 1073 deletions
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4
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd
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@@ -80,7 +80,7 @@ entity WF68901IP_INTERRUPTS is
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
irq_n : out std_logic;
-- Interrupt sources:
GP_INT : in std_logic_vector(7 downto 0);
@@ -157,7 +157,7 @@ begin
IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1';
-- Interrupt request:
IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1';
irq_n <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1';
EDGE_ENA: process(RESETn, CLK)
-- These are the 16 edge detectors of the 16 interrupt input sources. This

2
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd
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@@ -192,7 +192,7 @@ component WF68901IP_INTERRUPTS
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
irq_n : out std_logic;
GP_INT : in std_logic_vector(7 downto 0);
AER_4 : in std_logic;
AER_3 : in std_logic;

8
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd
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@@ -84,7 +84,7 @@ entity WF68901IP_TOP is
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
irq_n : out std_logic;
-- Timers and timer control:
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
@@ -125,7 +125,7 @@ component WF68901IP_TOP_SOC
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
irq_n : out std_logic;
XTAL1 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
@@ -154,7 +154,7 @@ signal SO_I : std_logic;
signal SO_EN : std_logic;
begin
DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain.
IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
irq_n <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
@@ -194,7 +194,7 @@ begin
IACKn => IACKn,
IEIn => IEIn,
IEOn => IEOn,
IRQn => IRQ_In,
irq_n => IRQ_In,
XTAL1 => XTAL1,
TAI => TAI,
TBI => TBI,

6
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd
View File

@@ -93,7 +93,7 @@ entity WF68901IP_TOP_SOC is
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
irq_n : out std_logic;
-- Timers and timer control:
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
@@ -151,7 +151,7 @@ signal TA_PWM_I : std_logic;
signal TB_PWM_I : std_logic;
begin
-- Interrupt request (open drain):
IRQn <= IRQ_In;
irq_n <= IRQ_In;
-- Serial data output:
SO <= SO_I;
@@ -242,7 +242,7 @@ begin
IACKn => IACKn,
IEIn => IEIn,
IEOn => IEOn,
IRQn => IRQ_In,
irq_n => IRQ_In,
GP_INT => GP_INT_I,
AER_4 => AER_4_I,
AER_3 => AER_3_I,