diff --git a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd index 80e2c6b..ebfc3b3 100644 --- a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd +++ b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd @@ -1,100 +1,100 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This design unit provides the std_logic block transfer processor ---- ----- (BLITTER) of the 'Firebee' computer. ---- ----- It is optimized for the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- ----- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2012 Wolfgang Förster ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K12B 20120801 WF --- Initial Release of the second edition. - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity FBEE_BLITTER is - port( - RESETn : in std_logic; - CLK_MAIN : in std_logic; - CLK_DDR0 : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - FB_ALE : in std_logic; - FB_SIZE1 : in std_logic; - FB_SIZE0 : in std_logic; - FB_CSn : in std_logic_vector(3 downto 1); - FB_OEn : in std_logic; - FB_WRn : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_EN : out std_logic; - BLITTER_ON : in std_logic; - BLITTER_DIN : in std_logic_vector(127 downto 0); - BLITTER_DACK_SR : in std_logic; - BLITTER_RUN : out std_logic; - BLITTER_DOUT : out std_logic_vector(127 downto 0); - BLITTER_ADR : out std_logic_vector(31 downto 0); - BLITTER_SIG : out std_logic; - BLITTER_WR : out std_logic; - BLITTER_TA : out std_logic - ); -end entity FBEE_BLITTER; - -architecture BEHAVIOUR of FBEE_BLITTER is - signal BLITTER_DACK : std_logic_vector(4 downto 0); - signal BLITTER_DIN_I : std_logic_vector(127 downto 0); -begin - P_BLITTER_DACK: process - begin - wait until CLK_DDR0 = '1' and CLK_DDR0' event; - BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 downto 1); - if BLITTER_DACK(0) = '1' then - BLITTER_DIN_I <= BLITTER_DIN; - end if; - end process P_BLITTER_DACK; - - - BLITTER_RUN <= '0'; - BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; - DATA_OUT <= x"FEDCBA98"; - BLITTER_ADR <= x"76543210"; - BLITTER_SIG <= '0'; - BLITTER_WR <= '0'; - BLITTER_TA <= '0'; - DATA_EN <= '0'; -END BEHAVIOUR; +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- +---- ---- +---- Description: ---- +---- This design unit provides the std_logic block transfer processor ---- +---- (BLITTER) of the 'Firebee' computer. ---- +---- It is optimized for the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- +---- tion of the Firebee configware originally provided by Fredi ---- +---- Ashwanden and Wolfgang Förster. This release is in compa- ---- +---- rision to the first edition completely written in VHDL. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2012 Wolfgang Förster ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K12B 20120801 WF +-- Initial Release of the second edition. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity FBEE_BLITTER is + port( + RESETn : in std_logic; + CLK_MAIN : in std_logic; + CLK_DDR0 : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + FB_ALE : in std_logic; + FB_SIZE1 : in std_logic; + FB_SIZE0 : in std_logic; + fb_cs_n : in std_logic_vector(3 downto 1); + fb_oe_n : in std_logic; + FB_WRn : in std_logic; + DATA_IN : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_EN : out std_logic; + BLITTER_ON : in std_logic; + BLITTER_DIN : in std_logic_vector(127 downto 0); + BLITTER_DACK_SR : in std_logic; + BLITTER_RUN : out std_logic; + BLITTER_DOUT : out std_logic_vector(127 downto 0); + BLITTER_ADR : out std_logic_vector(31 downto 0); + BLITTER_SIG : out std_logic; + BLITTER_WR : out std_logic; + BLITTER_TA : out std_logic + ); +end entity FBEE_BLITTER; + +architecture BEHAVIOUR of FBEE_BLITTER is + signal BLITTER_DACK : std_logic_vector(4 downto 0); + signal BLITTER_DIN_I : std_logic_vector(127 downto 0); +begin + P_BLITTER_DACK: process + begin + wait until CLK_DDR0 = '1' and CLK_DDR0' event; + BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 downto 1); + if BLITTER_DACK(0) = '1' then + BLITTER_DIN_I <= BLITTER_DIN; + end if; + end process P_BLITTER_DACK; + + + BLITTER_RUN <= '0'; + BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + DATA_OUT <= x"FEDCBA98"; + BLITTER_ADR <= x"76543210"; + BLITTER_SIG <= '0'; + BLITTER_WR <= '0'; + BLITTER_TA <= '0'; + DATA_EN <= '0'; +END BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd index aa8228a..e0d5a09 100644 --- a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd +++ b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd @@ -55,8 +55,8 @@ ENTITY FBEE_DMA IS FB_ADR : IN STD_LOGIC_VECTOR(26 DOWNTO 0); FB_ALE : IN STD_LOGIC; FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - FB_CSn : IN STD_LOGIC_VECTOR(2 DOWNTO 1); - FB_OEn : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; FB_WRn : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -201,59 +201,59 @@ BEGIN FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYTE = '0' ELSE '0'; FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYTE = '0' ELSE '0'; - FB_AD_OUT(31 DOWNTO 24) <= dma_top WHEN dma_top_cs = '1' AND FB_OEn = '0' ELSE - x"00" WHEN dma_data_cs = '1' AND FB_OEn = '0' ELSE - dma_top WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE - dma_bytecnt(31 DOWNTO 24) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE - dma_mode(15 DOWNTO 8) WHEN dma_direct_cs = '1' AND FB_OEn = '0' ELSE - x"00" WHEN dma_mode_cs = '1' AND FB_OEn = '0' ELSE - dma_drq11_i & dma_drq_reg & IDE_INT & FD_INT & SCSI_INT & RDF_AZ(9 DOWNTO 8) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE - RDF_DOUT(7 DOWNTO 0) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; + FB_AD_OUT(31 DOWNTO 24) <= dma_top WHEN dma_top_cs = '1' AND fb_oe_n = '0' ELSE + x"00" WHEN dma_data_cs = '1' AND fb_oe_n = '0' ELSE + dma_top WHEN dma_adr_cs = '1' AND fb_oe_n = '0' ELSE + dma_bytecnt(31 DOWNTO 24) WHEN dma_bytecnt_cs = '1' AND fb_oe_n = '0' ELSE + dma_mode(15 DOWNTO 8) WHEN dma_direct_cs = '1' AND fb_oe_n = '0' ELSE + x"00" WHEN dma_mode_cs = '1' AND fb_oe_n = '0' ELSE + dma_drq11_i & dma_drq_reg & IDE_INT & FD_INT & SCSI_INT & RDF_AZ(9 DOWNTO 8) WHEN dma_az_cs = '1' AND fb_oe_n = '0' ELSE + RDF_DOUT(7 DOWNTO 0) WHEN fcf_cs = '1' AND fb_oe_n = '0' ELSE x"00"; - FB_AD_OUT(23 DOWNTO 16) <= "00000" & dma_status WHEN dma_mode_cs = '1' AND FB_OEn = '0' ELSE - FDC_OUT WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "00" AND FB_OEn = '0' ELSE - DATA_IN_SCSI WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "01" AND FB_OEn = '0' ELSE - dma_bytecnt(16 DOWNTO 9) WHEN dma_data_cs = '1' AND dma_mode(4) = '1' AND FB_OEn = '0' ELSE - "0000" & (NOT dma_status(1)) & "0" & WDC_BSL(1) & FLOPPY_HD_DD WHEN WDC_BSL_CS = '1' AND FB_OEn = '0' ELSE - RDF_AZ(7 DOWNTO 0) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE - SNDMACTL WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"0" AND FB_OEn = '0' ELSE - SNDBASHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"1" AND FB_OEn = '0' ELSE - SNDBASMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"2" AND FB_OEn = '0' ELSE - SNDBASLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"3" AND FB_OEn = '0' ELSE - SNDADRHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"4" AND FB_OEn = '0' ELSE - SNDADRMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"5" AND FB_OEn = '0' ELSE - SNDADRLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"6" AND FB_OEn = '0' ELSE - SNDENDHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"7" AND FB_OEn = '0' ELSE - SNDENDMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"8" AND FB_OEn = '0' ELSE - SNDENDLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"9" AND FB_OEn = '0' ELSE - SNDMODE WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"10" AND FB_OEn = '0' ELSE - dma_high WHEN dma_high_cs = '1' AND FB_OEn = '0' ELSE - dma_mid WHEN dma_mid_cs = '1' AND FB_OEn = '0' ELSE - dma_low WHEN dma_low_cs = '1' AND FB_OEn = '0' ELSE - dma_mode(7 DOWNTO 0) WHEN dma_direct_cs = '1' AND FB_OEn = '0' ELSE - dma_high WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE - dma_bytecnt(23 DOWNTO 16) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE - RDF_DOUT(15 DOWNTO 8) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; + FB_AD_OUT(23 DOWNTO 16) <= "00000" & dma_status WHEN dma_mode_cs = '1' AND fb_oe_n = '0' ELSE + FDC_OUT WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "00" AND fb_oe_n = '0' ELSE + DATA_IN_SCSI WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "01" AND fb_oe_n = '0' ELSE + dma_bytecnt(16 DOWNTO 9) WHEN dma_data_cs = '1' AND dma_mode(4) = '1' AND fb_oe_n = '0' ELSE + "0000" & (NOT dma_status(1)) & "0" & WDC_BSL(1) & FLOPPY_HD_DD WHEN WDC_BSL_CS = '1' AND fb_oe_n = '0' ELSE + RDF_AZ(7 DOWNTO 0) WHEN dma_az_cs = '1' AND fb_oe_n = '0' ELSE + SNDMACTL WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"0" AND fb_oe_n = '0' ELSE + SNDBASHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"1" AND fb_oe_n = '0' ELSE + SNDBASMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"2" AND fb_oe_n = '0' ELSE + SNDBASLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"3" AND fb_oe_n = '0' ELSE + SNDADRHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"4" AND fb_oe_n = '0' ELSE + SNDADRMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"5" AND fb_oe_n = '0' ELSE + SNDADRLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"6" AND fb_oe_n = '0' ELSE + SNDENDHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"7" AND fb_oe_n = '0' ELSE + SNDENDMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"8" AND fb_oe_n = '0' ELSE + SNDENDLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"9" AND fb_oe_n = '0' ELSE + SNDMODE WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"10" AND fb_oe_n = '0' ELSE + dma_high WHEN dma_high_cs = '1' AND fb_oe_n = '0' ELSE + dma_mid WHEN dma_mid_cs = '1' AND fb_oe_n = '0' ELSE + dma_low WHEN dma_low_cs = '1' AND fb_oe_n = '0' ELSE + dma_mode(7 DOWNTO 0) WHEN dma_direct_cs = '1' AND fb_oe_n = '0' ELSE + dma_high WHEN dma_adr_cs = '1' AND fb_oe_n = '0' ELSE + dma_bytecnt(23 DOWNTO 16) WHEN dma_bytecnt_cs = '1' AND fb_oe_n = '0' ELSE + RDF_DOUT(15 DOWNTO 8) WHEN fcf_cs = '1' AND fb_oe_n = '0' ELSE x"00"; - FB_AD_OUT(15 DOWNTO 8) <= "0" & dma_status & "00" & WRF_AZ(9 DOWNTO 8) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE - dma_mid WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE - dma_bytecnt(15 DOWNTO 8) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE - RDF_DOUT(23 DOWNTO 16) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; + FB_AD_OUT(15 DOWNTO 8) <= "0" & dma_status & "00" & WRF_AZ(9 DOWNTO 8) WHEN dma_az_cs = '1' AND fb_oe_n = '0' ELSE + dma_mid WHEN dma_adr_cs = '1' AND fb_oe_n = '0' ELSE + dma_bytecnt(15 DOWNTO 8) WHEN dma_bytecnt_cs = '1' AND fb_oe_n = '0' ELSE + RDF_DOUT(23 DOWNTO 16) WHEN fcf_cs = '1' AND fb_oe_n = '0' ELSE x"00"; - FB_AD_OUT(7 DOWNTO 0) <= WRF_AZ(7 DOWNTO 0) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE - dma_low WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE - dma_bytecnt(7 DOWNTO 0) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE - RDF_DOUT(31 DOWNTO 24) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; + FB_AD_OUT(7 DOWNTO 0) <= WRF_AZ(7 DOWNTO 0) WHEN dma_az_cs = '1' AND fb_oe_n = '0' ELSE + dma_low WHEN dma_adr_cs = '1' AND fb_oe_n = '0' ELSE + dma_bytecnt(7 DOWNTO 0) WHEN dma_bytecnt_cs = '1' AND fb_oe_n = '0' ELSE + RDF_DOUT(31 DOWNTO 24) WHEN fcf_cs = '1' AND fb_oe_n = '0' ELSE x"00"; FB_AD_EN_31_24 <= (dma_top_cs OR dma_data_cs OR dma_adr_cs OR dma_bytecnt_cs OR dma_direct_cs OR - dma_mode_cs OR dma_az_cs OR fcf_cs) AND NOT FB_OEn; + dma_mode_cs OR dma_az_cs OR fcf_cs) AND NOT fb_oe_n; FB_AD_EN_23_16 <= (dma_mode_cs OR dma_data_cs OR WDC_BSL_CS OR dma_az_cs OR DMA_SND_CS OR dma_high_cs OR - dma_mid_cs OR dma_low_cs OR dma_direct_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT FB_OEn; + dma_mid_cs OR dma_low_cs OR dma_direct_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT fb_oe_n; - FB_AD_EN_15_8 <= (dma_az_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT FB_OEn; + FB_AD_EN_15_8 <= (dma_az_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT fb_oe_n; - FB_AD_EN_7_0 <= (dma_az_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT FB_OEn; + FB_AD_EN_7_0 <= (dma_az_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT fb_oe_n; INBUFFER: PROCESS(CLK_MAIN) BEGIN @@ -275,22 +275,22 @@ BEGIN SCSI_CS <= SCSI_CS_I; - dma_mode_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C303" ELSE '0'; -- F8606/2 - dma_data_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C302" ELSE '0'; -- F8604/2 + dma_mode_cs <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C303" ELSE '0'; -- F8606/2 + dma_data_cs <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C302" ELSE '0'; -- F8604/2 FDC_CS <= '1' WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "00" AND FB_B1 = '1' ELSE '0'; SCSI_CS_I <= '1' WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "01" AND FB_B1 = '1' ELSE '0'; - dma_az_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"002010C" ELSE '0'; -- F002'010C LONG - dma_top_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2 - dma_high_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2 - dma_mid_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 - dma_low_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 - dma_direct_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20100" ELSE '0'; -- F002'0100 WORD - dma_adr_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20104" ELSE '0'; -- F002'0104 LONG - dma_bytecnt_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20108" ELSE '0'; -- F002'0108 LONG - DMA_SND_CS <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(20 DOWNTO 6) = 15x"3E24" ELSE '0'; -- F8900-F893F - fcf_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY + dma_az_cs <= '1' WHEN fb_cs_n(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"002010C" ELSE '0'; -- F002'010C LONG + dma_top_cs <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2 + dma_high_cs <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2 + dma_mid_cs <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 + dma_low_cs <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 + dma_direct_cs <= '1' WHEN fb_cs_n(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20100" ELSE '0'; -- F002'0100 WORD + dma_adr_cs <= '1' WHEN fb_cs_n(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20104" ELSE '0'; -- F002'0104 LONG + dma_bytecnt_cs <= '1' WHEN fb_cs_n(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20108" ELSE '0'; -- F002'0108 LONG + DMA_SND_CS <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(20 DOWNTO 6) = 15x"3E24" ELSE '0'; -- F8900-F893F + fcf_cs <= '1' WHEN fb_cs_n(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY DMA_CS <= fcf_cs OR dma_mode_cs OR DMA_SND_CS OR dma_adr_cs OR dma_direct_cs OR dma_bytecnt_cs; - WDC_BSL_CS <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C307" ELSE '0'; -- F860E/2 + WDC_BSL_CS <= '1' WHEN fb_cs_n(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C307" ELSE '0'; -- F860E/2 fcf_aph <= '1' WHEN FB_ALE = '1' AND FB_AD_IN(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY diff --git a/vhdl/rtl/vhdl/DSP/DSP.vhd b/vhdl/rtl/vhdl/DSP/DSP.vhd index 49aebad..8db50d5 100644 --- a/vhdl/rtl/vhdl/DSP/DSP.vhd +++ b/vhdl/rtl/vhdl/DSP/DSP.vhd @@ -1,81 +1,81 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:57 2009 - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - - --- Entity Declaration - -ENTITY DSP IS - port( - CLK_33M : in std_logic; - CLK_MAIN : in std_logic; - FB_OEn : in std_logic; - FB_WRn : in std_logic; - FB_CS1n : in std_logic; - FB_CS2n : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; - FB_BURSTn : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - RESETn : in std_logic; - FB_CS3n : in std_logic; - SRCSn : buffer std_logic; - SRBLEn : out std_logic; - SRBHEn : out std_logic; - SRWEn : out std_logic; - SROEn : out std_logic; - DSP_INT : out std_logic; - DSP_TA : out std_logic; - FB_AD_IN : in std_logic_vector(31 downto 0); - FB_AD_OUT : out std_logic_vector(31 downto 0); - FB_AD_EN : out std_logic; - IO_IN : in std_logic_vector(17 downto 0); - IO_OUT : out std_logic_vector(17 downto 0); - IO_EN : out std_logic; - SRD_IN : in std_logic_vector(15 downto 0); - SRD_OUT : out std_logic_vector(15 downto 0); - SRD_EN : out std_logic - ); -END DSP; - - --- Architecture Body - -ARCHITECTURE DSP_architecture OF DSP IS -BEGIN - SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n; - SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1'; - SRBLEn <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; - SRWEn <= '0' when FB_WRn = '0' and SRCSn = '0' and CLK_MAIN = '0' else '1'; - SROEn <= '0' when FB_OEn = '0' and SRCSn = '0' else '1'; - DSP_INT <= '0'; - DSP_TA <= '0'; - IO_OUT(17 downto 0) <= FB_ADR(18 downto 1); - IO_EN <= '1'; - SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when FB_WRn = '0' and SRCSn = '0' else x"0000"; - SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0'; - FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000"; - FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000"; - FB_AD_EN <= '1' when FB_OEn = '0' and SRCSn = '0' else '0'; -END DSP_architecture; +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:57 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY DSP IS + port( + CLK_33M : in std_logic; + CLK_MAIN : in std_logic; + fb_oe_n : in std_logic; + FB_WRn : in std_logic; + FB_CS1n : in std_logic; + FB_CS2n : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + FB_BURSTn : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + RESETn : in std_logic; + FB_CS3n : in std_logic; + SRCSn : buffer std_logic; + SRBLEn : out std_logic; + SRBHEn : out std_logic; + SRWEn : out std_logic; + SROEn : out std_logic; + DSP_INT : out std_logic; + DSP_TA : out std_logic; + FB_AD_IN : in std_logic_vector(31 downto 0); + FB_AD_OUT : out std_logic_vector(31 downto 0); + FB_AD_EN : out std_logic; + IO_IN : in std_logic_vector(17 downto 0); + IO_OUT : out std_logic_vector(17 downto 0); + IO_EN : out std_logic; + SRD_IN : in std_logic_vector(15 downto 0); + SRD_OUT : out std_logic_vector(15 downto 0); + SRD_EN : out std_logic + ); +END DSP; + + +-- Architecture Body + +ARCHITECTURE DSP_architecture OF DSP IS +BEGIN + SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n; + SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1'; + SRBLEn <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; + SRWEn <= '0' when FB_WRn = '0' and SRCSn = '0' and CLK_MAIN = '0' else '1'; + SROEn <= '0' when fb_oe_n = '0' and SRCSn = '0' else '1'; + DSP_INT <= '0'; + DSP_TA <= '0'; + IO_OUT(17 downto 0) <= FB_ADR(18 downto 1); + IO_EN <= '1'; + SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when FB_WRn = '0' and SRCSn = '0' else x"0000"; + SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0'; + FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000"; + FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when fb_oe_n = '0' and SRCSn = '0' else x"0000"; + FB_AD_EN <= '1' when fb_oe_n = '0' and SRCSn = '0' else '0'; +END DSP_architecture; diff --git a/vhdl/rtl/vhdl/Firebee/Firebee.vhd b/vhdl/rtl/vhdl/Firebee/Firebee.vhd index e9b5425..4bb2d7e 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee.vhd @@ -96,30 +96,30 @@ LIBRARY IEEE; ENTITY firebee IS PORT( - RSTO_MCFn : IN STD_LOGIC; -- reset SIGNAL from Coldfire - CLK_33M : IN STD_LOGIC; -- 33 MHz clock + rsto_mcf_n : IN STD_LOGIC; -- reset SIGNAL from Coldfire + clk_33m : IN STD_LOGIC; -- 33 MHz clock clk_main : IN STD_LOGIC; -- 33 MHz clock - CLK_24M576 : OUT STD_LOGIC; -- - CLK_25M : OUT STD_LOGIC; - clk_ddr_OUT : OUT STD_LOGIC; - clk_ddr_OUTn : OUT STD_LOGIC; + clk_24m576 : OUT STD_LOGIC; -- + clk_25m : OUT STD_LOGIC; + clk_ddr_out : OUT STD_LOGIC; + clk_ddr_out_n : OUT STD_LOGIC; clk_usb : OUT STD_LOGIC; fb_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); fb_ale : IN STD_LOGIC; - FB_BURSTn : IN STD_LOGIC; - FB_CSn : IN STD_LOGIC_VECTOR (3 DOWNTO 1); + fb_burst_n : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR (3 DOWNTO 1); fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - FB_OEn : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; - FB_TAn : OUT STD_LOGIC; + fb_ta_n : OUT STD_LOGIC; - DACK1n : IN STD_LOGIC; - DREQ1n : OUT STD_LOGIC; + dack1_n : IN STD_LOGIC; + dreq1_n : OUT STD_LOGIC; - MASTERn : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. - TOUT0n : IN STD_LOGIC; -- Not used so far. + master_n : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. + tout0_n : IN STD_LOGIC; -- Not used so far. led_fpga_ok : OUT STD_LOGIC; reserved_1 : OUT STD_LOGIC; @@ -132,10 +132,10 @@ ENTITY firebee IS vcs_n : OUT STD_LOGIC; clk_pixel : OUT STD_LOGIC; - SYNCn : OUT STD_LOGIC; - VSYNC : OUT STD_LOGIC; - HSYNC : OUT STD_LOGIC; - BLANKn : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + vsync : OUT STD_LOGIC; + hsync : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; vr : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); vg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); @@ -146,43 +146,43 @@ ENTITY firebee IS vd : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); vd_qs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - PD_vgAn : OUT STD_LOGIC; + pd_vga_n : OUT STD_LOGIC; vcke : OUT STD_LOGIC; pic_int : IN STD_LOGIC; e0_int : IN STD_LOGIC; dvi_int : IN STD_LOGIC; - PCI_INTAn : IN STD_LOGIC; - PCI_INTBn : IN STD_LOGIC; - PCI_INTCn : IN STD_LOGIC; - PCI_INTDn : IN STD_LOGIC; + pci_inta_n : IN STD_LOGIC; + pci_intb_n : IN STD_LOGIC; + pci_intc_n : IN STD_LOGIC; + pci_intd_n : IN STD_LOGIC; - IRQn : OUT STD_LOGIC_VECTOR (7 DOWNTO 2); + irq_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 2); tin0 : OUT STD_LOGIC; - YM_QA : OUT STD_LOGIC; - YM_QB : OUT STD_LOGIC; - YM_QC : OUT STD_LOGIC; + ym_qa : OUT STD_LOGIC; + ym_qb : OUT STD_LOGIC; + ym_qc : OUT STD_LOGIC; - LP_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); - LP_DIR : OUT STD_LOGIC; + lp_d : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); + lp_dir : OUT STD_LOGIC; - DSA_D : OUT STD_LOGIC; - LP_STR : OUT STD_LOGIC; - DTR : OUT STD_LOGIC; - RTS : OUT STD_LOGIC; - CTS : IN STD_LOGIC; - RI : IN STD_LOGIC; - DCD : IN STD_LOGIC; - LP_BUSY : IN STD_LOGIC; - RxD : IN STD_LOGIC; - TxD : OUT STD_LOGIC; - MIDI_IN : IN STD_LOGIC; - MIDI_OLR : OUT STD_LOGIC; - MIDI_TLR : OUT STD_LOGIC; - PIC_AMKB_RX : IN STD_LOGIC; - AMKB_RX : IN STD_LOGIC; - AMKB_TX : OUT STD_LOGIC; - DACK0n : IN STD_LOGIC; -- Not used. + dsa_d : OUT STD_LOGIC; + lp_str : OUT STD_LOGIC; + dtr : OUT STD_LOGIC; + rts : OUT STD_LOGIC; + cts : IN STD_LOGIC; + ri : IN STD_LOGIC; + dcd : IN STD_LOGIC; + lp_busy : IN STD_LOGIC; + rxd : IN STD_LOGIC; + txd : OUT STD_LOGIC; + midi_in : IN STD_LOGIC; + midi_olr : OUT STD_LOGIC; + midi_tlr : OUT STD_LOGIC; + pic_amkb_rx : IN STD_LOGIC; + amkb_rx : IN STD_LOGIC; + amkb_tx : OUT STD_LOGIC; + dack0_n : IN STD_LOGIC; -- Not used. scsi_drqn : IN STD_LOGIC; SCSI_MSGn : IN STD_LOGIC; @@ -256,7 +256,7 @@ END ENTITY firebee; ARCHITECTURE Structure of firebee is COMPONENT altpll1 PORT( - INclk0 : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; @@ -289,7 +289,7 @@ ARCHITECTURE Structure of firebee is PORT( areset : IN STD_LOGIC := '0'; configupdate : IN STD_LOGIC := '0'; - INclk0 : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; scanclk : IN STD_LOGIC := '1'; scanclkena : IN STD_LOGIC := '0'; scandata : IN STD_LOGIC := '0'; @@ -447,7 +447,7 @@ ARCHITECTURE Structure of firebee is SIGNAL scsi_rst_en : STD_LOGIC; SIGNAL scsi_rst_out_n : STD_LOGIC; SIGNAL scsi_sel_en : STD_LOGIC; - SIGNAL SCSI_SEL_OUTn : STD_LOGIC; + SIGNAL scsi_sel_out_n : STD_LOGIC; SIGNAL sd_cd_d3_en : STD_LOGIC; SIGNAL sd_cd_d3_out : STD_LOGIC; SIGNAL sd_cmd_d1_en : STD_LOGIC; @@ -492,7 +492,7 @@ BEGIN PORT MAP( inclk0 => clk_main, c0 => clk_2m4576, -- 2.4576 MHz - c1 => CLK_24M576, -- 24.576 MHz + c1 => clk_24m576, -- 24.576 MHz c2 => clk_48m, -- 48 MHz locked => locked ); @@ -552,11 +552,11 @@ BEGIN pll_areset => pll_areset ); - CLK_25M <= clk_25m_i; + clk_25m <= clk_25m_i; clk_usb <= clk_48m; - clk_ddr_OUT <= clk_ddr(0); - clk_ddr_OUTn <= NOT clk_ddr(0); + clk_ddr_out <= clk_ddr(0); + clk_ddr_out_n <= NOT clk_ddr(0); clk_pixel <= clk_pixel_i; @@ -566,23 +566,23 @@ BEGIN timebase <= timebase + 1; END PROCESS p_timebase; - reset_n <= RSTO_MCFn and locked; + reset_n <= rsto_mcf_n and locked; ide_res <= NOT ide_res_i and reset_n; - DREQ1n <= DACK1n; + dreq1_n <= dack1_n; led_fpga_ok <= timebase(17); -- won't work: doesn't seem to be connected falcon_io_ta <= acia_cs OR sndcs OR NOT dtack_out_mfp_n OR paddle_cs OR ide_cf_ta OR dma_cs; - FB_TAn <= '0' WHEN (blitter_ta OR video_ddr_ta OR video_mod_ta OR falcon_io_ta OR dsp_ta OR int_handler_ta) = '1' ELSE 'Z'; + fb_ta_n <= '0' WHEN (blitter_ta OR video_ddr_ta OR video_mod_ta OR falcon_io_ta OR dsp_ta OR int_handler_ta) = '1' ELSE 'Z'; - acia_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 3) & "000" = x"FFFC00" ELSE '0'; -- FFFC00 - FFFC07 - mfp_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 6) & "000000" = x"FFFA00" ELSE '0'; -- FFFA00/40 - paddle_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 6) & "000000"= x"FF9200" ELSE '0'; -- FF9200-FF923F - sndcs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 2) & "00" = x"FF8800" ELSE '0'; -- FF8800-FF8803 + acia_cs <= '1' WHEN fb_cs_n(1) = '0' and fb_adr(23 DOWNTO 3) & "000" = x"FFFC00" ELSE '0'; -- FFFC00 - FFFC07 + mfp_cs <= '1' WHEN fb_cs_n(1) = '0' and fb_adr(23 DOWNTO 6) & "000000" = x"FFFA00" ELSE '0'; -- FFFA00/40 + paddle_cs <= '1' WHEN fb_cs_n(1) = '0' and fb_adr(23 DOWNTO 6) & "000000"= x"FF9200" ELSE '0'; -- FF9200-FF923F + sndcs <= '1' WHEN fb_cs_n(1) = '0' and fb_adr(23 DOWNTO 2) & "00" = x"FF8800" ELSE '0'; -- FF8800-FF8803 sndcs_i <= '1' WHEN sndcs = '1' and fb_adr (1) = '0' ELSE '0'; sndir_i <= '1' WHEN sndcs = '1' and fb_wr_n = '0' ELSE '0'; - LP_D <= lp_d_x WHEN lp_dir_x = '0' ELSE (OTHERS => 'Z'); - LP_DIR <= lp_dir_x; + lp_d <= lp_d_x WHEN lp_dir_x = '0' ELSE (OTHERS => 'Z'); + lp_dir <= lp_dir_x; ACSI_D <= acsi_d_out WHEN acsi_d_en = '1' ELSE (OTHERS => 'Z'); @@ -591,9 +591,9 @@ BEGIN SCSI_PAR <= scsi_dbp_out_n WHEN scsi_dbp_en = '1' ELSE 'Z'; SCSI_RSTn <= scsi_rst_out_n WHEN scsi_rst_en = '1' ELSE 'Z'; SCSI_BUSYn <= scsi_bsy_out_n WHEN scsi_bsy_en = '1' ELSE 'Z'; - SCSI_SELn <= SCSI_SEL_OUTn WHEN scsi_sel_en = '1' ELSE 'Z'; + SCSI_SELn <= scsi_sel_out_n WHEN scsi_sel_en = '1' ELSE 'Z'; - keyb_rxd <= '0' WHEN AMKB_RX = '0' OR PIC_AMKB_RX = '0' ELSE '1'; -- get keyboard data either from PIC (PS/2) OR from Atari keyboard + keyb_rxd <= '0' WHEN amkb_rx = '0' OR pic_amkb_rx = '0' ELSE '1'; -- get keyboard data either from PIC (PS/2) OR from Atari keyboard SD_D3 <= sd_cd_d3_out WHEN sd_cd_d3_en = '1' ELSE 'Z'; SD_CMD_D1 <= sd_cmd_d1_out WHEN sd_cmd_d1_en = '1' ELSE 'Z'; @@ -604,13 +604,13 @@ BEGIN hd_dd_out <= FDD_HD_DD WHEN fbee_conf(29) = '0' ELSE wdc_bsl0; lds <= '1' WHEN mfp_cs = '1' OR mfp_intack = '1' ELSE '0'; acia_irq_n <= irq_keybd_n and irq_midi_n; - mfp_intack <= '1' WHEN FB_CSn(2) = '0' and fb_adr(19 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 + mfp_intack <= '1' WHEN fb_cs_n(2) = '0' and fb_adr(19 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 dint_n <= '0' WHEN ide_int = '1' and fbee_conf(28) = '1' ELSE '0' WHEN fd_int = '1' ELSE '0' WHEN scsi_int = '1' and fbee_conf(28) = '1' ELSE '1'; - MIDI_TLR <= midi_out; - MIDI_OLR <= midi_out; + midi_tlr <= midi_out; + midi_olr <= midi_out; byte <= '1' WHEN fb_size(1) = '0' and fb_size(0) = '1' ELSE '0'; fb_b0 <= '1' WHEN fb_adr(0) = '0' OR byte = '0' ELSE '0'; @@ -626,18 +626,18 @@ BEGIN fb_ad_out_dma(31 DOWNTO 24) WHEN fb_ad_en_31_24_dma = '1' ELSE vdr(31 DOWNTO 24) WHEN fb_vdoe = x"1" ELSE data_out_ddr_ctrl(31 DOWNTO 24) WHEN data_en_h_ddr_ctrl = '1' ELSE - da_out_x WHEN sndcs_i = '1' and FB_OEn = '0' ELSE - x"00" WHEN mfp_intack = '1' and FB_OEn = '0' ELSE - data_out_acia_i WHEN acia_cs = '1' and fb_adr(2) = '0' and FB_OEn = '0' ELSE - data_out_acia_iI WHEN acia_cs = '1' and fb_adr(2) = '1' and FB_OEn = '0' ELSE - x"BF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"0" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"1" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"8" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"9" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"A" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"B" and FB_OEn = '0' ELSE - x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and FB_OEn = '0' ELSE - x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and FB_OEn = '0' ELSE (OTHERS => 'Z'); + da_out_x WHEN sndcs_i = '1' and fb_oe_n = '0' ELSE + x"00" WHEN mfp_intack = '1' and fb_oe_n = '0' ELSE + data_out_acia_i WHEN acia_cs = '1' and fb_adr(2) = '0' and fb_oe_n = '0' ELSE + data_out_acia_iI WHEN acia_cs = '1' and fb_adr(2) = '1' and fb_oe_n = '0' ELSE + x"BF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"0" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"1" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"8" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"9" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"A" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"B" and fb_oe_n = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and fb_oe_n = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and fb_oe_n = '0' ELSE (OTHERS => 'Z'); fb_ad(23 DOWNTO 16) <= data_out_blitter(23 DOWNTO 16) WHEN data_en_blitter = '1' ELSE vdp_q1(23 DOWNTO 16) WHEN fb_vdoe = x"2" ELSE @@ -649,17 +649,17 @@ BEGIN fb_ad_out_dma(23 DOWNTO 16) WHEN fb_ad_en_23_16_dma = '1' ELSE vdr(23 DOWNTO 16) WHEN fb_vdoe = x"1" ELSE data_out_ddr_ctrl(23 DOWNTO 16) WHEN data_en_l_ddr_ctrl = '1' ELSE - data_out_mfp WHEN mfp_cs = '1' and FB_OEn = '0' ELSE - x"00" WHEN mfp_intack = '1' and FB_OEn = '0' ELSE + data_out_mfp WHEN mfp_cs = '1' and fb_oe_n = '0' ELSE + x"00" WHEN mfp_intack = '1' and fb_oe_n = '0' ELSE fb_ad_out_rtc WHEN fb_ad_en_rtc = '1' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"0" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"1" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"8" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"9" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"A" and FB_OEn = '0' ELSE - x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"B" and FB_OEn = '0' ELSE - x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and FB_OEn = '0' ELSE - x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and FB_OEn = '0' ELSE (OTHERS => 'Z'); + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"0" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"1" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"8" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"9" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"A" and fb_oe_n = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"B" and fb_oe_n = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and fb_oe_n = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and fb_oe_n = '0' ELSE (OTHERS => 'Z'); fb_ad(15 DOWNTO 8) <= data_out_blitter(15 DOWNTO 8) WHEN data_en_blitter = '1' ELSE vdp_q1(15 DOWNTO 8) WHEN fb_vdoe = x"2" ELSE @@ -670,7 +670,7 @@ BEGIN fb_ad_out_ih(15 DOWNTO 8) WHEN fb_ad_en_15_8_ih = '1' ELSE fb_ad_out_dma(15 DOWNTO 8) WHEN fb_ad_en_15_8_dma = '1' ELSE vdr(15 DOWNTO 8) WHEN fb_vdoe = x"1" ELSE - "000000" & data_out_mfp(7 DOWNTO 6) WHEN mfp_intack = '1' and FB_OEn = '0' ELSE (OTHERS => 'Z'); + "000000" & data_out_mfp(7 DOWNTO 6) WHEN mfp_intack = '1' and fb_oe_n = '0' ELSE (OTHERS => 'Z'); fb_ad(7 DOWNTO 0) <= data_out_blitter(7 DOWNTO 0) WHEN data_en_blitter = '1' ELSE vdp_q1(7 DOWNTO 0) WHEN fb_vdoe = x"2" ELSE @@ -681,7 +681,7 @@ BEGIN fb_ad_out_ih(7 DOWNTO 0) WHEN fb_ad_en_7_0_ih = '1' ELSE fb_ad_out_dma(7 DOWNTO 0) WHEN fb_ad_en_7_0_dma = '1' ELSE vdr(7 DOWNTO 0) WHEN fb_vdoe = x"1" ELSE - data_out_mfp(5 DOWNTO 0) & "00" WHEN mfp_intack = '1' and FB_OEn = '0' ELSE (OTHERS => 'Z'); + data_out_mfp(5 DOWNTO 0) & "00" WHEN mfp_intack = '1' and fb_oe_n = '0' ELSE (OTHERS => 'Z'); synchronization : PROCESS BEGIN @@ -716,9 +716,9 @@ BEGIN video_out : PROCESS BEGIN WAIT UNTIL RISING_EDGE(clk_pixel_i); - VSYNC <= vsync_i; - HSYNC <= hsync_i; - BLANKn <= blank_i_n; + vsync <= vsync_i; + hsync <= hsync_i; + blank_n <= blank_i_n; END PROCESS video_out; p_ddr_wr: PROCESS @@ -795,8 +795,8 @@ BEGIN clk_main => clk_main, ddr_sync_66m => ddr_sync_66m, fb_adr => fb_adr, - fb_cs1_n => FB_CSn(1), - fb_oe_n => FB_OEn, + fb_cs1_n => fb_cs_n(1), + fb_oe_n => fb_oe_n, fb_size0 => fb_size(0), fb_size1 => fb_size(1), fb_ale => fb_ale, @@ -808,7 +808,7 @@ BEGIN ba => ba, va => va, fb_le => fb_le, - CLK_33M => CLK_33M, + clk_33m => clk_33m, vras_n => vras_n, vcas_n => vcas_n, vwe_n => vwe_n, @@ -842,8 +842,8 @@ BEGIN -- fb_ale => fb_ale, -- fb_size1 => fb_size(1), -- fb_size0 => fb_size(0), --- FB_CSn => FB_CSn, --- FB_OEn => FB_OEn, +-- fb_cs_n => fb_cs_n, +-- fb_oe_n => fb_oe_n, -- fb_wr_n => fb_wr_n, -- DATA_IN => fb_ad, -- DATA_OUT => data_out_blitter, @@ -862,8 +862,8 @@ BEGIN I_VIDEOSYSTEM: VIDEO_SYSTEM PORT MAP( clk_main => clk_main, - CLK_33M => CLK_33M, - CLK_25M => clk_25m_i, + clk_33m => clk_33m, + clk_25m => clk_25m_i, clk_video => clk_video, clk_ddr3 => clk_ddr(3), clk_ddr2 => clk_ddr(2), @@ -879,8 +879,8 @@ BEGIN fb_ad_en_31_16 => fb_ad_en_31_16_video, fb_ad_en_15_0 => fb_ad_en_15_0_video, fb_ale => fb_ale, - FB_CSn => FB_CSn, - FB_OEn => FB_OEn, + fb_cs_n => fb_cs_n, + fb_oe_n => fb_oe_n, fb_wr_n => FB_WR_n, fb_size1 => fb_size(1), fb_size0 => fb_size(0), @@ -894,12 +894,12 @@ BEGIN RED => vr, GREEN => vg, BLUE => vb, - VSYNC => vsync_i, - HSYNC => hsync_i, - SYNCn => SYNCn, - BLANKn => blank_i_n, + vsync => vsync_i, + hsync => hsync_i, + sync_n => sync_n, + blank_n => blank_i_n, - PD_vgAn => PD_vgAn, + pd_vga_n => pd_vga_n, video_mod_ta => video_mod_ta, vd_vz => vd_vz, @@ -919,8 +919,8 @@ BEGIN -- clk_main => clk_main, -- resetn => reset_n, -- fb_adr => fb_adr, --- FB_CSn => FB_CSn(2 DOWNTO 1), --- FB_OEn => FB_OEn, +-- fb_cs_n => fb_cs_n(2 DOWNTO 1), +-- fb_oe_n => fb_oe_n, -- fb_size0 => fb_size(0), -- fb_size1 => fb_size(1), -- fb_wr_n => fb_wr_n, @@ -933,16 +933,16 @@ BEGIN -- pic_int => pic_int, -- e0_int => e0_int, -- dvi_int => dvi_int, --- PCI_INTAn => PCI_INTAn, --- PCI_INTBn => PCI_INTBn, --- PCI_INTCn => PCI_INTCn, --- PCI_INTDn => PCI_INTDn, +-- pci_inta_n => pci_inta_n, +-- pci_intb_n => pci_intb_n, +-- pci_intc_n => pci_intc_n, +-- pci_intd_n => pci_intd_n, -- mfp_intn => mfp_int_n, -- dsp_int => dsp_int, --- VSYNC => vsync_i, --- HSYNC => hsync_i, +-- vsync => vsync_i, +-- hsync => hsync_i, -- drq_dma => drq_dma, --- IRQn => IRQn, +-- irq_n => irq_n, -- int_handler_ta => int_handler_ta, -- fbee_conf => fbee_conf, -- tin0 => tin0 @@ -957,8 +957,8 @@ BEGIN -- fb_adr => fb_adr(26 DOWNTO 0), -- fb_ale => fb_ale, -- fb_size => fb_size, --- FB_CSn => FB_CSn(2 DOWNTO 1), --- FB_OEn => FB_OEn, +-- fb_cs_n => fb_cs_n(2 DOWNTO 1), +-- fb_oe_n => fb_oe_n, -- fb_wr_n => fb_wr_n, -- fb_ad_IN => fb_ad, -- fb_ad_OUT => fb_ad_out_dma, @@ -1007,7 +1007,7 @@ BEGIN -- clk_main => clk_main, -- -- fb_adr => fb_adr(19 DOWNTO 5), --- FB_CS1n => FB_CSn(1), +-- FB_CS1n => fb_cs_n(1), -- fb_wr_n => fb_wr_n, -- fb_b0 => fb_b0, -- fb_b1 => fb_b1, @@ -1046,18 +1046,18 @@ BEGIN -- I_DSP: DSP -- PORT MAP( --- CLK_33M => CLK_33M, +-- clk_33m => clk_33m, -- clk_main => clk_main, --- FB_OEn => FB_OEn, +-- fb_oe_n => fb_oe_n, -- fb_wr_n => fb_wr_n, --- FB_CS1n => FB_CSn(1), --- FB_CS2n => FB_CSn(2), +-- FB_CS1n => fb_cs_n(1), +-- FB_CS2n => fb_cs_n(2), -- fb_size0 => fb_size(0), -- fb_size1 => fb_size(1), --- FB_BURSTn => FB_BURSTn, +-- fb_burst_n => fb_burst_n, -- fb_adr => fb_adr, -- resetn => reset_n, --- FB_CS3n => FB_CSn(3), +-- FB_CS3n => fb_cs_n(3), -- SRCSn => DSP_SRCSn, -- SRBLEn => DSP_SRBLEn, -- SRBHEn => DSP_SRBHEn, @@ -1096,20 +1096,20 @@ BEGIN -- IO_A_IN => x"00", -- All port pINs are dedicated OUTputs. -- IO_A_OUT(7) => ide_res_i, -- IO_A_OUT(6) => lp_dir_x, --- IO_A_OUT(5) => LP_STR, --- IO_A_OUT(4) => DTR, --- IO_A_OUT(3) => RTS, +-- IO_A_OUT(5) => lp_str, +-- IO_A_OUT(4) => dtr, +-- IO_A_OUT(3) => rts, -- IO_A_OUT(2) => reserved_1, --- IO_A_OUT(1) => DSA_D, +-- IO_A_OUT(1) => dsa_d, -- IO_A_OUT(0) => FDD_SDSELn, --- -- IO_A_EN => TOUT0n, -- Not required. --- IO_B_IN => LP_D, +-- -- IO_A_EN => tout0_n, -- Not required. +-- IO_B_IN => lp_d, -- IO_B_OUT => lp_d_x, -- -- IO_B_EN => -- Not used. -- --- OUT_A => YM_QA, --- OUT_B => YM_QB, --- OUT_C => YM_QC +-- OUT_A => ym_qa, +-- OUT_B => ym_qb, +-- OUT_C => ym_qc -- ); I_MFP: WF68901IP_TOP_SOC @@ -1128,20 +1128,20 @@ BEGIN DATA_OUT => data_out_mfp, -- DATA_EN => DATA_EN_MFP, -- Not used. GPIP_IN(7) => NOT drq11_dma, - GPIP_IN(6) => NOT RI, + GPIP_IN(6) => NOT ri, GPIP_IN(5) => dint_n, GPIP_IN(4) => acia_irq_n, GPIP_IN(3) => dsp_int, - GPIP_IN(2) => NOT CTS, - GPIP_IN(1) => NOT DCD, - GPIP_IN(0) => LP_BUSY, + GPIP_IN(2) => NOT cts, + GPIP_IN(1) => NOT dcd, + GPIP_IN(0) => lp_busy, -- GPIP_OUT =>, -- Not used; all GPIPs are direction INput. -- GPIP_EN =>, -- Not used; all GPIPs are direction INput. -- Interrupt control: IACKn => NOT mfp_intack, IEIn => '0', -- IEOn =>, -- Not used. - IRQn => mfp_int_n, + irq_n => mfp_int_n, -- Timers and timer control: XTAL1 => clk_2m4576, TAI => '0', @@ -1153,8 +1153,8 @@ BEGIN -- Serial I/O control: RC => tdo, TC => tdo, - SI => RxD, - SO => TxD + SI => rxd, + SO => txd -- SO_EN => -- Not used. -- DMA control: -- RRn => -- Not used. @@ -1179,11 +1179,11 @@ BEGIN -- -- TXCLK => clk_500k, -- RXCLK => clk_500k, --- RXDATA => MIDI_IN, +-- RXDATA => midi_in, -- CTSn => '0', -- DCDn => '0', -- --- IRQn => irq_midi_n, +-- irq_n => irq_midi_n, -- TXDATA => midi_out -- --RTSn => -- Not used. -- ); @@ -1211,8 +1211,8 @@ BEGIN CTSn => '0', DCDn => '0', - IRQn => irq_keybd_n, - TXDATA => AMKB_TX + irq_n => irq_keybd_n, + TXDATA => amkb_tx --RTSn => -- Not used. ); @@ -1247,7 +1247,7 @@ BEGIN -- BSY_OUTn => scsi_bsy_out_n, -- BSY_EN => scsi_bsy_en, -- SEL_INn => SCSI_SELn, --- SEL_OUTn => SCSI_SEL_OUTn, +-- SEL_OUTn => scsi_sel_out_n, -- SEL_EN => scsi_sel_en, -- ACK_INn => '1', -- ACK_OUTn => SCSI_ACKn, @@ -1299,11 +1299,11 @@ BEGIN -- PORT MAP( -- clk_main => clk_main, -- fb_adr => fb_adr(19 DOWNTO 0), --- FB_CS1n => FB_CSn(1), +-- FB_CS1n => fb_cs_n(1), -- fb_size0 => fb_size(0), -- fb_size1 => fb_size(1), -- fb_wr_n => fb_wr_n, --- FB_OEn => FB_OEn, +-- fb_oe_n => fb_oe_n, -- fb_ad_IN => fb_ad(23 DOWNTO 16), -- fb_ad_OUT => fb_ad_out_rtc, -- fb_ad_EN_23_16 => fb_ad_en_rtc, diff --git a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd index 20e8951..59f048d 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd @@ -65,11 +65,11 @@ PACKAGE firebee_pkg IS FB_AD_EN_31_16 : OUT STD_LOGIC; -- Hi word. FB_AD_EN_15_0 : OUT STD_LOGIC; -- Low word. FB_ALE : IN STD_LOGIC; - FB_CSn : IN STD_LOGIC_VECTOR(3 DOWNTO 1); - FB_OEn : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; + fb_size0 : IN STD_LOGIC; VDP_IN : IN STD_LOGIC_VECTOR(63 DOWNTO 0); @@ -82,10 +82,10 @@ PACKAGE firebee_pkg IS BLUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VSYNC : OUT STD_LOGIC; HSYNC : OUT STD_LOGIC; - SYNCn : OUT STD_LOGIC; - BLANKn : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; - PD_VGAn : OUT STD_LOGIC; + pd_vga_n : OUT STD_LOGIC; VIDEO_MOD_TA : OUT STD_LOGIC; VD_VZ : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); @@ -106,9 +106,9 @@ PACKAGE firebee_pkg IS COMPONENT VIDEO_CTRL PORT( CLK_MAIN : IN STD_LOGIC; - FB_CSn : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); fb_wr_n : IN STD_LOGIC; - FB_OEn : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLK33M : IN STD_LOGIC; @@ -128,9 +128,9 @@ PACKAGE firebee_pkg IS CLUT_MUX_ADR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); HSYNC : OUT STD_LOGIC; VSYNC : OUT STD_LOGIC; - BLANKn : OUT STD_LOGIC; - SYNCn : OUT STD_LOGIC; - PD_VGAn : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + pd_vga_n : OUT STD_LOGIC; FIFO_RDE : OUT STD_LOGIC; COLOR2 : OUT STD_LOGIC; COLOR4 : OUT STD_LOGIC; @@ -162,8 +162,8 @@ PACKAGE firebee_pkg IS FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fb_cs1_n : IN STD_LOGIC; FB_OE_n : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; + fb_size0 : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; FB_ALE : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; FIFO_CLR : IN STD_LOGIC; @@ -204,11 +204,11 @@ PACKAGE firebee_pkg IS CLK_MAIN : IN STD_LOGIC; RESETn : IN STD_LOGIC; FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_CSn : IN STD_LOGIC_VECTOR(2 DOWNTO 1); - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_size0 : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; - FB_OEn : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_EN_31_24 : OUT STD_LOGIC; @@ -218,16 +218,16 @@ PACKAGE firebee_pkg IS PIC_INT : IN STD_LOGIC; E0_INT : IN STD_LOGIC; DVI_INT : IN STD_LOGIC; - PCI_INTAn : IN STD_LOGIC; - PCI_INTBn : IN STD_LOGIC; - PCI_INTCn : IN STD_LOGIC; - PCI_INTDn : IN STD_LOGIC; - MFP_INTn : IN STD_LOGIC; + pci_inta_n : IN STD_LOGIC; + pci_intb_n : IN STD_LOGIC; + pci_intc_n : IN STD_LOGIC; + pci_intd_n : IN STD_LOGIC; + mfp_int_n : IN STD_LOGIC; DSP_INT : IN STD_LOGIC; VSYNC : IN STD_LOGIC; HSYNC : IN STD_LOGIC; DRQ_DMA : IN STD_LOGIC; - IRQn : OUT STD_LOGIC_VECTOR(7 DOWNTO 2); + irq_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 2); INT_HANDLER_TA : OUT STD_LOGIC; FBEE_CONF : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TIN0 : OUT STD_LOGIC @@ -243,8 +243,8 @@ PACKAGE firebee_pkg IS FB_ADR : IN STD_LOGIC_VECTOR(26 DOWNTO 0); FB_ALE : IN STD_LOGIC; FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - FB_CSn : IN STD_LOGIC_VECTOR(2 DOWNTO 1); - FB_OEn : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -339,10 +339,10 @@ PACKAGE firebee_pkg IS CLK_DDR0 : IN STD_LOGIC; FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_ALE : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_CSn : IN STD_LOGIC_VECTOR(3 DOWNTO 1); - FB_OEn : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; + fb_size0 : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -363,12 +363,12 @@ PACKAGE firebee_pkg IS PORT( CLK_33M : IN STD_LOGIC; CLK_MAIN : IN STD_LOGIC; - FB_OEn : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; FB_CS1n : IN STD_LOGIC; FB_CS2n : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; + fb_size0 : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; FB_BURSTn : IN STD_LOGIC; FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); RESETn : IN STD_LOGIC; @@ -439,7 +439,7 @@ PACKAGE firebee_pkg IS IACKn : IN STD_LOGIC; IEIn : IN STD_LOGIC; IEOn : OUT STD_LOGIC; - IRQn : OUT STD_LOGIC; + irq_n : OUT STD_LOGIC; XTAL1 : IN STD_LOGIC; TAI : IN STD_LOGIC; TBI : IN STD_LOGIC; @@ -477,7 +477,7 @@ PACKAGE firebee_pkg IS CTSn : IN STD_LOGIC; DCDn : IN STD_LOGIC; - IRQn : OUT STD_LOGIC; + irq_n : OUT STD_LOGIC; TXDATA : OUT STD_LOGIC; RTSn : OUT STD_LOGIC ); @@ -566,10 +566,10 @@ PACKAGE firebee_pkg IS CLK_MAIN : IN STD_LOGIC; FB_ADR : IN STD_LOGIC_VECTOR(19 DOWNTO 0); FB_CS1n : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; + fb_size0 : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; - FB_OEn : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(23 DOWNTO 16); FB_AD_OUT : OUT STD_LOGIC_VECTOR(23 DOWNTO 16); FB_AD_EN_23_16 : OUT STD_LOGIC; diff --git a/vhdl/rtl/vhdl/Interrupt/interrupt.vhd b/vhdl/rtl/vhdl/Interrupt/interrupt.vhd index ed504a7..417c9aa 100644 --- a/vhdl/rtl/vhdl/Interrupt/interrupt.vhd +++ b/vhdl/rtl/vhdl/Interrupt/interrupt.vhd @@ -1,306 +1,306 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This design unit provides the interruptlogic of the 'Firebee'---- ----- computer. It is optimized for the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- ----- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K12B 20120801 WF --- Initial Release of the second edition. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; --- use ieee.std_logic_arith.all; - -entity INTHANDLER is - port( - CLK_MAIN : in std_logic; - RESETn : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - FB_CSn : in std_logic_vector(2 downto 1); - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; - FB_WRn : in std_logic; - FB_OEn : in std_logic; - FB_AD_IN : in std_logic_vector(31 downto 0); - FB_AD_OUT : out std_logic_vector(31 downto 0); - FB_AD_EN_31_24 : out std_logic; - FB_AD_EN_23_16 : out std_logic; - FB_AD_EN_15_8 : out std_logic; - FB_AD_EN_7_0 : out std_logic; - PIC_INT : in std_logic; - E0_INT : in std_logic; - DVI_INT : in std_logic; - PCI_INTAn : in std_logic; - PCI_INTBn : in std_logic; - PCI_INTCn : in std_logic; - PCI_INTDn : in std_logic; - MFP_INTn : in std_logic; - DSP_INT : in std_logic; - VSYNC : in std_logic; - HSYNC : in std_logic; - DRQ_DMA : in std_logic; - IRQn : out std_logic_vector(7 downto 2); - INT_HANDLER_TA : out std_logic; - FBEE_CONF : out std_logic_vector(31 downto 0); - TIN0 : out std_logic - ); -end entity INTHANDLER; - -architecture BEHAVIOUR of INTHANDLER is - type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0); - signal INT_LA : INT_LA_TYPE; - signal FB_B : std_logic_vector(3 downto 0); - signal INT_CTR : std_logic_vector(31 downto 0); - signal INT_CTR_CS : std_logic; - signal INT_LATCH : std_logic_vector(31 downto 0); - signal INT_LATCH_CS : std_logic; - signal INT_CLEAR : std_logic_vector(31 downto 0); - signal INT_CLEAR_CS : std_logic; - signal INT_IN : std_logic_vector(31 downto 0); - signal INT_ENA : std_logic_vector(31 downto 0); - signal INT_ENA_CS : std_logic; - signal INT_L : std_logic_vector(9 downto 0); - signal FBEE_CONF_REG : std_logic_vector(31 downto 0); - signal FBEE_CONF_CS : std_logic; - signal PSEUDO_BUS_ERROR : std_logic; -begin - -- Byte selectors: - FB_B(0) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "00" else -- HH Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. - - FB_B(1) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. - - FB_B(2) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "10" else -- LH Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. - - FB_B(3) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. - - INT_CTR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000000" else '0'; -- $10000/4; - INT_ENA_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000001" else '0'; -- $10004/4; - INT_CLEAR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000010" else '0'; -- $10008/4; - INT_LATCH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000011" else '0'; -- $1000C/4; - - P_INT_CTRL : process - -- Interrupt control register: - -- BIT0 = INT5, Bit1 = INT7. - -- Interrupt enabe register: - -- BIT31 = INT7, Bit30 = INT6, Bit29 = INT5, Bit28 = INT4, Bit27 = INT3, Bit26 = INT2 - -- The interrupt clear register is write only; 1 = interrupt clear. - begin - wait until rising_edge(CLK_MAIN); - if INT_CTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - INT_CTR(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif INT_CTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - INT_CTR(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif INT_CTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - INT_CTR(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif INT_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - INT_CTR(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; - -- - if RESETn = '0' then - INT_ENA <= (others => '0'); - elsif INT_ENA_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - INT_ENA(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif INT_ENA_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - INT_ENA(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif INT_ENA_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - INT_ENA(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif INT_ENA_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - INT_ENA(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; - -- - if INT_CLEAR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - INT_CLEAR(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif INT_CLEAR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - INT_CLEAR(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif INT_CLEAR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - INT_CLEAR(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif INT_CLEAR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - INT_CLEAR(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; - end process P_INT_CTRL; - - -- Interrupt latch register: read only. - IRQn(2) <= '0' when HSYNC = '1' and INT_ENA(26) = '1' else '1'; - IRQn(3) <= '0' when INT_CTR(0) = '1' and INT_ENA(27) = '1' else '1'; - IRQn(4) <= '0' when VSYNC = '1' and INT_ENA(28) = '1' else '1'; - IRQn(5) <= '0' when INT_LATCH /= x"00000000" and INT_ENA(29) = '1' else '1'; - IRQn(6) <= '0' when MFP_INTn = '0' and INT_ENA(30) = '1' else '1'; - IRQn(7) <= '0' when PSEUDO_BUS_ERROR = '1' and INT_ENA(31) = '1' else '1'; - - PSEUDO_BUS_ERROR <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F8C8" else -- SCC - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F8E0" else -- VME - -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F920" else -- PADDLE - -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F921" else -- PADDLE - -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F922" else -- PADDLE - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2 - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA9" else -- MFP2 - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFAA" else -- MFP2 - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2 - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 8) = x"F87" else -- TT SCSI - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC2" else -- ST UHR - '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC3" else '0'; -- ST UHR - -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F890" else -- DMA SOUND - -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F891" else -- DMA SOUND - -- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND - - -- IF video ADR changes: - TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = 19x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2. - - P_INT_LATCH : process - begin - wait until rising_edge(CLK_MAIN); - if RESETn = '0' then - INT_L <= (others => '0'); - else - INT_L(0) <= PIC_INT and INT_ENA(0); - INT_L(1) <= E0_INT and INT_ENA(1); - INT_L(2) <= DVI_INT and INT_ENA(2); - INT_L(3) <= not PCI_INTAn and INT_ENA(3); - INT_L(4) <= not PCI_INTBn and INT_ENA(4); - INT_L(5) <= not PCI_INTCn and INT_ENA(5); - INT_L(6) <= not PCI_INTDn and INT_ENA(6); - INT_L(7) <= DSP_INT and INT_ENA(7); - INT_L(8) <= VSYNC and INT_ENA(8); - INT_L(9) <= HSYNC and INT_ENA(9); - end if; - - for i in 0 to 9 loop - if INT_ENA(i) = '1' and RESETn = '1' then - INT_LA(i) <= x"0"; - elsif INT_L(i) = '1' and INT_LA(i) < x"7" then - INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) + 1); - elsif INT_L(i) = '0' and INT_LA(i) > x"8" then - INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) - 1); - elsif INT_L(i) = '1' and INT_LA(i) > x"6" then - INT_LA(i) <= x"F"; - elsif INT_L(i) = '0' and INT_LA(i) > x"9" then - INT_LA(i) <= x"0"; - end if; - end loop; - - for i in 0 to 31 loop - if INT_CLEAR(i) = '0' and RESETn = '1' then - INT_LATCH(i) <= '0'; - end if; - end loop; - - for i in 0 to 9 loop - if INT_LA(i)(3) = '1' then - INT_LATCH(i) <= '1'; - end if; - end loop; - end process P_INT_LATCH; - - -- INT_IN: - INT_IN(0) <= PIC_INT; - INT_IN(1) <= E0_INT; - INT_IN(2) <= DVI_INT; - INT_IN(3) <= not PCI_INTAn; - INT_IN(4) <= not PCI_INTBn; - INT_IN(5) <= not PCI_INTCn; - INT_IN(6) <= not PCI_INTDn; - INT_IN(7) <= DSP_INT; - INT_IN(8) <= VSYNC; - INT_IN(9) <= HSYNC; - INT_IN(25 downto 10) <= x"0000"; - INT_IN(26) <= HSYNC; - INT_IN(27) <= INT_CTR(0); - INT_IN(28) <= VSYNC; - INT_IN(29) <= '1' when INT_LATCH /= x"00000000"; - INT_IN(30) <= not MFP_INTn; - INT_IN(31) <= DRQ_DMA; - - FBEE_CONF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000001000000000000000000" else '0'; -- $40000/4. - - P_FBEE_CONFIG : process - -- Firebee configuration register: BIT 31 -> 0 = CF 1 = IDE - begin - wait until rising_edge(CLK_MAIN); - if FBEE_CONF_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif FBEE_CONF_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif FBEE_CONF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif FBEE_CONF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; - FBEE_CONF <= FBEE_CONF_REG; - end process P_FBEE_CONFIG; - - -- Data out multiplexers: - FB_AD_EN_31_24 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn; - FB_AD_EN_23_16 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn; - FB_AD_EN_15_8 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn; - FB_AD_EN_7_0 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn; - - FB_AD_OUT(31 downto 24) <= INT_CTR(31 downto 24) when INT_CTR_CS = '1' else - INT_ENA(31 downto 24) when INT_ENA_CS = '1' else - INT_LATCH(31 downto 24) when INT_LATCH_CS = '1' else - INT_IN(31 downto 24) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(31 downto 24); - - FB_AD_OUT(23 downto 16) <= INT_CTR(23 downto 16) when INT_CTR_CS = '1' else - INT_ENA(23 downto 16) when INT_ENA_CS = '1' else - INT_LATCH(23 downto 16) when INT_LATCH_CS = '1' else - INT_IN(23 downto 16) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(23 downto 16); - - FB_AD_OUT(15 downto 8) <= INT_CTR(15 downto 8) when INT_CTR_CS = '1' else - INT_ENA(15 downto 8) when INT_ENA_CS = '1' else - INT_LATCH(15 downto 8) when INT_LATCH_CS = '1' else - INT_CLEAR(15 downto 8) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(15 downto 8); - - FB_AD_OUT(7 downto 0) <= INT_CTR(7 downto 0) when INT_CTR_CS = '1' else - INT_ENA(7 downto 0) when INT_ENA_CS = '1' else - INT_LATCH(7 downto 0) when INT_LATCH_CS = '1' else - INT_CLEAR(7 downto 0) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(7 downto 0); - - INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS; -end architecture BEHAVIOUR; +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- +---- ---- +---- Description: ---- +---- This design unit provides the interruptlogic of the 'Firebee'---- +---- computer. It is optimized for the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- +---- tion of the Firebee configware originally provided by Fredi ---- +---- Ashwanden and Wolfgang Förster. This release is in compa- ---- +---- rision to the first edition completely written in VHDL. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K12B 20120801 WF +-- Initial Release of the second edition. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +-- use ieee.std_logic_arith.all; + +entity INTHANDLER is + port( + CLK_MAIN : in std_logic; + RESETn : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + fb_cs_n : in std_logic_vector(2 downto 1); + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + FB_WRn : in std_logic; + fb_oe_n : in std_logic; + FB_AD_IN : in std_logic_vector(31 downto 0); + FB_AD_OUT : out std_logic_vector(31 downto 0); + FB_AD_EN_31_24 : out std_logic; + FB_AD_EN_23_16 : out std_logic; + FB_AD_EN_15_8 : out std_logic; + FB_AD_EN_7_0 : out std_logic; + PIC_INT : in std_logic; + E0_INT : in std_logic; + DVI_INT : in std_logic; + PCI_INTAn : in std_logic; + PCI_INTBn : in std_logic; + PCI_INTCn : in std_logic; + PCI_INTDn : in std_logic; + MFP_INTn : in std_logic; + DSP_INT : in std_logic; + VSYNC : in std_logic; + HSYNC : in std_logic; + DRQ_DMA : in std_logic; + irq_n : out std_logic_vector(7 downto 2); + INT_HANDLER_TA : out std_logic; + FBEE_CONF : out std_logic_vector(31 downto 0); + TIN0 : out std_logic + ); +end entity INTHANDLER; + +architecture BEHAVIOUR of INTHANDLER is + type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0); + signal INT_LA : INT_LA_TYPE; + signal FB_B : std_logic_vector(3 downto 0); + signal INT_CTR : std_logic_vector(31 downto 0); + signal INT_CTR_CS : std_logic; + signal INT_LATCH : std_logic_vector(31 downto 0); + signal INT_LATCH_CS : std_logic; + signal INT_CLEAR : std_logic_vector(31 downto 0); + signal INT_CLEAR_CS : std_logic; + signal INT_IN : std_logic_vector(31 downto 0); + signal INT_ENA : std_logic_vector(31 downto 0); + signal INT_ENA_CS : std_logic; + signal INT_L : std_logic_vector(9 downto 0); + signal FBEE_CONF_REG : std_logic_vector(31 downto 0); + signal FBEE_CONF_CS : std_logic; + signal PSEUDO_BUS_ERROR : std_logic; +begin + -- Byte selectors: + FB_B(0) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "00" else -- HH Byte. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. + '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + + FB_B(1) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. + '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + + FB_B(2) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "10" else -- LH Byte. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. + '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + + FB_B(3) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. + '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + + INT_CTR_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000000" else '0'; -- $10000/4; + INT_ENA_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000001" else '0'; -- $10004/4; + INT_CLEAR_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000010" else '0'; -- $10008/4; + INT_LATCH_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000011" else '0'; -- $1000C/4; + + P_INT_CTRL : process + -- Interrupt control register: + -- BIT0 = INT5, Bit1 = INT7. + -- Interrupt enabe register: + -- BIT31 = INT7, Bit30 = INT6, Bit29 = INT5, Bit28 = INT4, Bit27 = INT3, Bit26 = INT2 + -- The interrupt clear register is write only; 1 = interrupt clear. + begin + wait until rising_edge(CLK_MAIN); + if INT_CTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then + INT_CTR(31 downto 24) <= FB_AD_IN(31 downto 24); + elsif INT_CTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then + INT_CTR(23 downto 16) <= FB_AD_IN(23 downto 16); + elsif INT_CTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then + INT_CTR(15 downto 8) <= FB_AD_IN(15 downto 8); + elsif INT_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then + INT_CTR(7 downto 0) <= FB_AD_IN(7 downto 0); + end if; + -- + if RESETn = '0' then + INT_ENA <= (others => '0'); + elsif INT_ENA_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then + INT_ENA(31 downto 24) <= FB_AD_IN(31 downto 24); + elsif INT_ENA_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then + INT_ENA(23 downto 16) <= FB_AD_IN(23 downto 16); + elsif INT_ENA_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then + INT_ENA(15 downto 8) <= FB_AD_IN(15 downto 8); + elsif INT_ENA_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then + INT_ENA(7 downto 0) <= FB_AD_IN(7 downto 0); + end if; + -- + if INT_CLEAR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then + INT_CLEAR(31 downto 24) <= FB_AD_IN(31 downto 24); + elsif INT_CLEAR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then + INT_CLEAR(23 downto 16) <= FB_AD_IN(23 downto 16); + elsif INT_CLEAR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then + INT_CLEAR(15 downto 8) <= FB_AD_IN(15 downto 8); + elsif INT_CLEAR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then + INT_CLEAR(7 downto 0) <= FB_AD_IN(7 downto 0); + end if; + end process P_INT_CTRL; + + -- Interrupt latch register: read only. + irq_n(2) <= '0' when HSYNC = '1' and INT_ENA(26) = '1' else '1'; + irq_n(3) <= '0' when INT_CTR(0) = '1' and INT_ENA(27) = '1' else '1'; + irq_n(4) <= '0' when VSYNC = '1' and INT_ENA(28) = '1' else '1'; + irq_n(5) <= '0' when INT_LATCH /= x"00000000" and INT_ENA(29) = '1' else '1'; + irq_n(6) <= '0' when MFP_INTn = '0' and INT_ENA(30) = '1' else '1'; + irq_n(7) <= '0' when PSEUDO_BUS_ERROR = '1' and INT_ENA(31) = '1' else '1'; + + PSEUDO_BUS_ERROR <= '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F8C8" else -- SCC + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F8E0" else -- VME + -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F920" else -- PADDLE + -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F921" else -- PADDLE + -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F922" else -- PADDLE + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2 + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFA9" else -- MFP2 + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFAA" else -- MFP2 + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2 + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 8) = x"F87" else -- TT SCSI + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFC2" else -- ST UHR + '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFC3" else '0'; -- ST UHR + -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F890" else -- DMA SOUND + -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F891" else -- DMA SOUND + -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND + + -- IF video ADR changes: + TIN0 <= '1' when fb_cs_n(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = 19x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2. + + P_INT_LATCH : process + begin + wait until rising_edge(CLK_MAIN); + if RESETn = '0' then + INT_L <= (others => '0'); + else + INT_L(0) <= PIC_INT and INT_ENA(0); + INT_L(1) <= E0_INT and INT_ENA(1); + INT_L(2) <= DVI_INT and INT_ENA(2); + INT_L(3) <= not PCI_INTAn and INT_ENA(3); + INT_L(4) <= not PCI_INTBn and INT_ENA(4); + INT_L(5) <= not PCI_INTCn and INT_ENA(5); + INT_L(6) <= not PCI_INTDn and INT_ENA(6); + INT_L(7) <= DSP_INT and INT_ENA(7); + INT_L(8) <= VSYNC and INT_ENA(8); + INT_L(9) <= HSYNC and INT_ENA(9); + end if; + + for i in 0 to 9 loop + if INT_ENA(i) = '1' and RESETn = '1' then + INT_LA(i) <= x"0"; + elsif INT_L(i) = '1' and INT_LA(i) < x"7" then + INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) + 1); + elsif INT_L(i) = '0' and INT_LA(i) > x"8" then + INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) - 1); + elsif INT_L(i) = '1' and INT_LA(i) > x"6" then + INT_LA(i) <= x"F"; + elsif INT_L(i) = '0' and INT_LA(i) > x"9" then + INT_LA(i) <= x"0"; + end if; + end loop; + + for i in 0 to 31 loop + if INT_CLEAR(i) = '0' and RESETn = '1' then + INT_LATCH(i) <= '0'; + end if; + end loop; + + for i in 0 to 9 loop + if INT_LA(i)(3) = '1' then + INT_LATCH(i) <= '1'; + end if; + end loop; + end process P_INT_LATCH; + + -- INT_IN: + INT_IN(0) <= PIC_INT; + INT_IN(1) <= E0_INT; + INT_IN(2) <= DVI_INT; + INT_IN(3) <= not PCI_INTAn; + INT_IN(4) <= not PCI_INTBn; + INT_IN(5) <= not PCI_INTCn; + INT_IN(6) <= not PCI_INTDn; + INT_IN(7) <= DSP_INT; + INT_IN(8) <= VSYNC; + INT_IN(9) <= HSYNC; + INT_IN(25 downto 10) <= x"0000"; + INT_IN(26) <= HSYNC; + INT_IN(27) <= INT_CTR(0); + INT_IN(28) <= VSYNC; + INT_IN(29) <= '1' when INT_LATCH /= x"00000000"; + INT_IN(30) <= not MFP_INTn; + INT_IN(31) <= DRQ_DMA; + + FBEE_CONF_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000001000000000000000000" else '0'; -- $40000/4. + + P_FBEE_CONFIG : process + -- Firebee configuration register: BIT 31 -> 0 = CF 1 = IDE + begin + wait until rising_edge(CLK_MAIN); + if FBEE_CONF_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then + FBEE_CONF_REG(31 downto 24) <= FB_AD_IN(31 downto 24); + elsif FBEE_CONF_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then + FBEE_CONF_REG(23 downto 16) <= FB_AD_IN(23 downto 16); + elsif FBEE_CONF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then + FBEE_CONF_REG(15 downto 8) <= FB_AD_IN(15 downto 8); + elsif FBEE_CONF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then + FBEE_CONF_REG(7 downto 0) <= FB_AD_IN(7 downto 0); + end if; + FBEE_CONF <= FBEE_CONF_REG; + end process P_FBEE_CONFIG; + + -- Data out multiplexers: + FB_AD_EN_31_24 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; + FB_AD_EN_23_16 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; + FB_AD_EN_15_8 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; + FB_AD_EN_7_0 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; + + FB_AD_OUT(31 downto 24) <= INT_CTR(31 downto 24) when INT_CTR_CS = '1' else + INT_ENA(31 downto 24) when INT_ENA_CS = '1' else + INT_LATCH(31 downto 24) when INT_LATCH_CS = '1' else + INT_IN(31 downto 24) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(31 downto 24); + + FB_AD_OUT(23 downto 16) <= INT_CTR(23 downto 16) when INT_CTR_CS = '1' else + INT_ENA(23 downto 16) when INT_ENA_CS = '1' else + INT_LATCH(23 downto 16) when INT_LATCH_CS = '1' else + INT_IN(23 downto 16) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(23 downto 16); + + FB_AD_OUT(15 downto 8) <= INT_CTR(15 downto 8) when INT_CTR_CS = '1' else + INT_ENA(15 downto 8) when INT_ENA_CS = '1' else + INT_LATCH(15 downto 8) when INT_LATCH_CS = '1' else + INT_CLEAR(15 downto 8) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(15 downto 8); + + FB_AD_OUT(7 downto 0) <= INT_CTR(7 downto 0) when INT_CTR_CS = '1' else + INT_ENA(7 downto 0) when INT_ENA_CS = '1' else + INT_LATCH(7 downto 0) when INT_LATCH_CS = '1' else + INT_CLEAR(7 downto 0) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(7 downto 0); + + INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS; +end architecture BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/RTC/rtc.vhd b/vhdl/rtl/vhdl/RTC/rtc.vhd index f63ec69..e60d16e 100644 --- a/vhdl/rtl/vhdl/RTC/rtc.vhd +++ b/vhdl/rtl/vhdl/RTC/rtc.vhd @@ -1,232 +1,232 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This design unit provides the RTC logic for the 'Firebee' ---- ----- computer. It is optimized for the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- ----- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K12B 20120801 WF --- Initial Release of the second edition. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity RTC is - port( - CLK_MAIN : in std_logic; - FB_ADR : in std_logic_vector(19 downto 0); - FB_CS1n : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; - FB_WRn : in std_logic; - FB_OEn : in std_logic; - FB_AD_IN : in std_logic_vector(23 downto 16); - FB_AD_OUT : out std_logic_vector(23 downto 16); - FB_AD_EN_23_16 : out std_logic; - PIC_INT : in std_logic - ); -end entity RTC; - -architecture BEHAVIOUR of RTC is - type VALUES_TYPE is array(63 downto 0) of std_logic_vector(7 downto 0); - signal VALUES : VALUES_TYPE; - signal FB_B1 : std_logic; - signal FB_B3 : std_logic; - signal UHR_AS : std_logic; - signal UHR_DS : std_logic; - signal RTC_ADR : std_logic_vector(5 downto 0); - signal EIGHTHs_OF_SECOND : std_logic_vector(2 downto 0); - signal PIC_INT_SYNC : std_logic_vector(2 downto 0); - signal INC_SEC : std_logic; - signal INC_MIN : std_logic; - signal INC_HOUR : std_logic; - signal INC_DAY : std_logic; - signal DAYs_PER_MONTH : std_logic_vector(7 downto 0); - signal WINTERTIME : std_logic; - signal SUMMERTIME : std_logic; - signal INC_MONAT : std_logic; - signal INC_JAHR : std_logic; - signal UPDATE_ON : std_logic; -begin - -- Byte selectors: - FB_B1 <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. - - FB_B3 <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. - - UHR_AS <= '1' when FB_B1 = '1' and FB_CS1n = '0' and FB_ADR(19 downto 1) = x"7C4B0" else '0'; -- $FFFF8961. - UHR_DS <= '1' when FB_B3 = '1' and FB_CS1n = '0' and FB_ADR(19 downto 1) = x"7C4B1" else '0'; -- $FFFF8963. - - UPDATE_ON <= not VALUES(11)(7); -- UPDATE ON OFF - - INC_SEC <= '1' when EIGHTHs_OF_SECOND = 7 and PIC_INT_SYNC(2) = '1' and UPDATE_ON = '1' else '0'; - INC_MIN <= '1' when INC_SEC = '1' and VALUES(0) = x"3B" else '0'; -- 59. - INC_HOUR <= '1' when INC_MIN = '1' and VALUES(2) = x"3B" else '0'; -- 59. - INC_DAY <= '1' when INC_HOUR = '1' and VALUES(2) = x"17" else '0'; -- 23. - INC_MONAT <= '1' when INC_DAY = '1' and VALUES(7) = DAYs_PER_MONTH else '0'; - INC_JAHR <= '1' when INC_MONAT = '1' and VALUES(8) = x"C" else '0'; -- 12. - - DAYs_PER_MONTH <= x"1F" when VALUES(8) = x"01" or VALUES(8) = x"03" or VALUES(8) = x"05" or VALUES(8) = x"07" or VALUES(8) = x"08" or VALUES(8) = x"0A" or VALUES(8) = x"0C" else - x"1E" when VALUES(8) = x"04" or VALUES(8) = x"06" or VALUES(8) = x"09" or VALUES(8) = x"0B" else - x"1D" when VALUES(8) = x"02" and VALUES(9)(1 downto 0) = x"00" else x"1C"; - - P_1287 : process - -- C1287: 0 = SEK 2 = MIN 4 = STD 6 = WOCHENTAG 7 = TAG 8 = MONAT 9 = JAHR - variable ADRVAR : std_logic_vector(5 downto 0); - begin - wait until CLK_MAIN = '1' and CLK_MAIN' event; - if UHR_AS = '1' and FB_WRn = '0' then - RTC_ADR <= FB_AD_IN(21 downto 16); - end if; - - for i in 0 to 63 loop - ADRVAR := conv_std_logic_vector(i,6); - if RTC_ADR = ADRVAR and UHR_DS = '1' and FB_WRn = '0' then - VALUES(i) <= FB_AD_IN(23 downto 16); - end if; - end loop; - - PIC_INT_SYNC(0) <= PIC_INT; - PIC_INT_SYNC(1) <= PIC_INT_SYNC(0); - PIC_INT_SYNC(2) <= not PIC_INT_SYNC(1) and PIC_INT_SYNC(0); - - VALUES(10)(6) <= '0'; -- No UIP. - VALUES(11)(2) <= '1'; -- Always binary. - VALUES(11)(1) <= '1'; -- Always 24h format. - VALUES(11)(0) <= '1'; -- Always correction of summertime. - VALUES(13)(7) <= '1'; -- Always true. - - -- Summer- wintertime: bit 0 in the register D provides information wether there is summer- or wintertime. - if VALUES(6)= x"01" and VALUES(4) = x"01" and VALUES(8) = x"04" and VALUES(7) > x"17" then -- Last Sunday in April. - SUMMERTIME <= '1'; - else - SUMMERTIME <= '0'; - end if; - - if VALUES(6)= x"01" and VALUES(4) = x"01" and VALUES(8) = x"0A" and VALUES(7) > x"18" then -- Last Sunday in October. - WINTERTIME <= '1'; - else - WINTERTIME <= '0'; - end if; - - if INC_HOUR = '1' and (SUMMERTIME or WINTERTIME) = '1' then - VALUES(13)(0) <= SUMMERTIME; - end if; - - -- Eighths of a second: - if PIC_INT_SYNC(2) = '1' and UPDATE_ON = '1' then - EIGHTHs_OF_SECOND <= EIGHTHs_OF_SECOND + '1'; - end if; - - -- Seconds: - if INC_SEC = '1' and (RTC_ADR /= "000000" or UHR_DS = '0' or FB_WRn = '1') then - if VALUES(0) = x"3B" then -- 59. - VALUES(0) <= (others => '0'); - else - VALUES(0) <= VALUES(0) + '1'; - end if; - end if; - - -- Minutes: - if INC_MIN = '1' and (RTC_ADR /= "000010" or UHR_DS = '0' or FB_WRn = '1') then - if VALUES(2) = x"3B" then -- 59. - VALUES(2) <= (others => '0'); - else - VALUES(2) <= VALUES(2) + '1'; - end if; - end if; - - -- Hours: - if INC_HOUR = '1' and (WINTERTIME = '0' or VALUES(12)(0) = '0') and (RTC_ADR /= "000100" or UHR_DS = '0' or FB_WRn = '1') then - if VALUES(4) = x"17" then -- 23. - VALUES(4) <= (others => '0'); - elsif SUMMERTIME = '1' then - VALUES(4) <= VALUES(4) + "10"; - else - VALUES(4) <= VALUES(4) + '1'; - end if; - end if; - - -- Day and day of the week: - if INC_DAY = '1' and (RTC_ADR /= "000110" or UHR_DS = '0' or FB_WRn = '1') then - if VALUES(6) = x"07" then - VALUES(6) <= x"01"; - else - VALUES(6) <= VALUES(6) + '1'; - end if; - end if; - - if INC_DAY = '1' and (RTC_ADR /= "000111" or UHR_DS = '0' or FB_WRn = '1') then - if VALUES(7) = DAYs_PER_MONTH then - VALUES(7) <= x"01"; - else - VALUES(7) <= VALUES(7) + '1'; - end if; - end if; - - -- Month: - if INC_MONAT = '1' and (RTC_ADR /= "001000" or UHR_DS = '0' or FB_WRn = '1') then - if VALUES(8) = x"0C" then - VALUES(8) <= x"01"; - else - VALUES(8) <= VALUES(8) + '1'; - end if; - end if; - - -- Year: - if INC_JAHR = '1' and (RTC_ADR /= "001001" or UHR_DS = '0' or FB_WRn = '1') then - if VALUES(9) = x"63" then -- 99. - VALUES(9) <= (others => '0'); - else - VALUES(9) <= VALUES(9) + '1'; - end if; - end if; - end process P_1287; - - -- Data out multiplexers: - FB_AD_EN_23_16 <= (UHR_DS or UHR_AS) and not FB_OEn; - - FB_AD_OUT(23 downto 16) <= VALUES(conv_integer(RTC_ADR)) when UHR_DS = '1' else - "00" & RTC_ADR when UHR_AS = '1' else x"00"; -end architecture BEHAVIOUR; +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- +---- ---- +---- Description: ---- +---- This design unit provides the RTC logic for the 'Firebee' ---- +---- computer. It is optimized for the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- +---- tion of the Firebee configware originally provided by Fredi ---- +---- Ashwanden and Wolfgang Förster. This release is in compa- ---- +---- rision to the first edition completely written in VHDL. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K12B 20120801 WF +-- Initial Release of the second edition. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity RTC is + port( + CLK_MAIN : in std_logic; + FB_ADR : in std_logic_vector(19 downto 0); + FB_CS1n : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + FB_WRn : in std_logic; + fb_oe_n : in std_logic; + FB_AD_IN : in std_logic_vector(23 downto 16); + FB_AD_OUT : out std_logic_vector(23 downto 16); + FB_AD_EN_23_16 : out std_logic; + PIC_INT : in std_logic + ); +end entity RTC; + +architecture BEHAVIOUR of RTC is + type VALUES_TYPE is array(63 downto 0) of std_logic_vector(7 downto 0); + signal VALUES : VALUES_TYPE; + signal FB_B1 : std_logic; + signal FB_B3 : std_logic; + signal UHR_AS : std_logic; + signal UHR_DS : std_logic; + signal RTC_ADR : std_logic_vector(5 downto 0); + signal EIGHTHs_OF_SECOND : std_logic_vector(2 downto 0); + signal PIC_INT_SYNC : std_logic_vector(2 downto 0); + signal INC_SEC : std_logic; + signal INC_MIN : std_logic; + signal INC_HOUR : std_logic; + signal INC_DAY : std_logic; + signal DAYs_PER_MONTH : std_logic_vector(7 downto 0); + signal WINTERTIME : std_logic; + signal SUMMERTIME : std_logic; + signal INC_MONAT : std_logic; + signal INC_JAHR : std_logic; + signal UPDATE_ON : std_logic; +begin + -- Byte selectors: + FB_B1 <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. + '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + + FB_B3 <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte. + '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. + '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + + UHR_AS <= '1' when FB_B1 = '1' and FB_CS1n = '0' and FB_ADR(19 downto 1) = x"7C4B0" else '0'; -- $FFFF8961. + UHR_DS <= '1' when FB_B3 = '1' and FB_CS1n = '0' and FB_ADR(19 downto 1) = x"7C4B1" else '0'; -- $FFFF8963. + + UPDATE_ON <= not VALUES(11)(7); -- UPDATE ON OFF + + INC_SEC <= '1' when EIGHTHs_OF_SECOND = 7 and PIC_INT_SYNC(2) = '1' and UPDATE_ON = '1' else '0'; + INC_MIN <= '1' when INC_SEC = '1' and VALUES(0) = x"3B" else '0'; -- 59. + INC_HOUR <= '1' when INC_MIN = '1' and VALUES(2) = x"3B" else '0'; -- 59. + INC_DAY <= '1' when INC_HOUR = '1' and VALUES(2) = x"17" else '0'; -- 23. + INC_MONAT <= '1' when INC_DAY = '1' and VALUES(7) = DAYs_PER_MONTH else '0'; + INC_JAHR <= '1' when INC_MONAT = '1' and VALUES(8) = x"C" else '0'; -- 12. + + DAYs_PER_MONTH <= x"1F" when VALUES(8) = x"01" or VALUES(8) = x"03" or VALUES(8) = x"05" or VALUES(8) = x"07" or VALUES(8) = x"08" or VALUES(8) = x"0A" or VALUES(8) = x"0C" else + x"1E" when VALUES(8) = x"04" or VALUES(8) = x"06" or VALUES(8) = x"09" or VALUES(8) = x"0B" else + x"1D" when VALUES(8) = x"02" and VALUES(9)(1 downto 0) = x"00" else x"1C"; + + P_1287 : process + -- C1287: 0 = SEK 2 = MIN 4 = STD 6 = WOCHENTAG 7 = TAG 8 = MONAT 9 = JAHR + variable ADRVAR : std_logic_vector(5 downto 0); + begin + wait until CLK_MAIN = '1' and CLK_MAIN' event; + if UHR_AS = '1' and FB_WRn = '0' then + RTC_ADR <= FB_AD_IN(21 downto 16); + end if; + + for i in 0 to 63 loop + ADRVAR := conv_std_logic_vector(i,6); + if RTC_ADR = ADRVAR and UHR_DS = '1' and FB_WRn = '0' then + VALUES(i) <= FB_AD_IN(23 downto 16); + end if; + end loop; + + PIC_INT_SYNC(0) <= PIC_INT; + PIC_INT_SYNC(1) <= PIC_INT_SYNC(0); + PIC_INT_SYNC(2) <= not PIC_INT_SYNC(1) and PIC_INT_SYNC(0); + + VALUES(10)(6) <= '0'; -- No UIP. + VALUES(11)(2) <= '1'; -- Always binary. + VALUES(11)(1) <= '1'; -- Always 24h format. + VALUES(11)(0) <= '1'; -- Always correction of summertime. + VALUES(13)(7) <= '1'; -- Always true. + + -- Summer- wintertime: bit 0 in the register D provides information wether there is summer- or wintertime. + if VALUES(6)= x"01" and VALUES(4) = x"01" and VALUES(8) = x"04" and VALUES(7) > x"17" then -- Last Sunday in April. + SUMMERTIME <= '1'; + else + SUMMERTIME <= '0'; + end if; + + if VALUES(6)= x"01" and VALUES(4) = x"01" and VALUES(8) = x"0A" and VALUES(7) > x"18" then -- Last Sunday in October. + WINTERTIME <= '1'; + else + WINTERTIME <= '0'; + end if; + + if INC_HOUR = '1' and (SUMMERTIME or WINTERTIME) = '1' then + VALUES(13)(0) <= SUMMERTIME; + end if; + + -- Eighths of a second: + if PIC_INT_SYNC(2) = '1' and UPDATE_ON = '1' then + EIGHTHs_OF_SECOND <= EIGHTHs_OF_SECOND + '1'; + end if; + + -- Seconds: + if INC_SEC = '1' and (RTC_ADR /= "000000" or UHR_DS = '0' or FB_WRn = '1') then + if VALUES(0) = x"3B" then -- 59. + VALUES(0) <= (others => '0'); + else + VALUES(0) <= VALUES(0) + '1'; + end if; + end if; + + -- Minutes: + if INC_MIN = '1' and (RTC_ADR /= "000010" or UHR_DS = '0' or FB_WRn = '1') then + if VALUES(2) = x"3B" then -- 59. + VALUES(2) <= (others => '0'); + else + VALUES(2) <= VALUES(2) + '1'; + end if; + end if; + + -- Hours: + if INC_HOUR = '1' and (WINTERTIME = '0' or VALUES(12)(0) = '0') and (RTC_ADR /= "000100" or UHR_DS = '0' or FB_WRn = '1') then + if VALUES(4) = x"17" then -- 23. + VALUES(4) <= (others => '0'); + elsif SUMMERTIME = '1' then + VALUES(4) <= VALUES(4) + "10"; + else + VALUES(4) <= VALUES(4) + '1'; + end if; + end if; + + -- Day and day of the week: + if INC_DAY = '1' and (RTC_ADR /= "000110" or UHR_DS = '0' or FB_WRn = '1') then + if VALUES(6) = x"07" then + VALUES(6) <= x"01"; + else + VALUES(6) <= VALUES(6) + '1'; + end if; + end if; + + if INC_DAY = '1' and (RTC_ADR /= "000111" or UHR_DS = '0' or FB_WRn = '1') then + if VALUES(7) = DAYs_PER_MONTH then + VALUES(7) <= x"01"; + else + VALUES(7) <= VALUES(7) + '1'; + end if; + end if; + + -- Month: + if INC_MONAT = '1' and (RTC_ADR /= "001000" or UHR_DS = '0' or FB_WRn = '1') then + if VALUES(8) = x"0C" then + VALUES(8) <= x"01"; + else + VALUES(8) <= VALUES(8) + '1'; + end if; + end if; + + -- Year: + if INC_JAHR = '1' and (RTC_ADR /= "001001" or UHR_DS = '0' or FB_WRn = '1') then + if VALUES(9) = x"63" then -- 99. + VALUES(9) <= (others => '0'); + else + VALUES(9) <= VALUES(9) + '1'; + end if; + end if; + end process P_1287; + + -- Data out multiplexers: + FB_AD_EN_23_16 <= (UHR_DS or UHR_AS) and not fb_oe_n; + + FB_AD_OUT(23 downto 16) <= VALUES(conv_integer(RTC_ADR)) when UHR_DS = '1' else + "00" & RTC_ADR when UHR_AS = '1' else x"00"; +end architecture BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd index cde164a..00a0ac6 100644 --- a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd +++ b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd @@ -49,9 +49,9 @@ use ieee.numeric_std.all; entity VIDEO_CTRL is port( CLK_MAIN : in std_logic; - FB_CSn : in std_logic_vector(2 downto 1); + fb_cs_n : in std_logic_vector(2 downto 1); fb_wr_n : in std_logic; - FB_OEn : in std_logic; + fb_oe_n : in std_logic; FB_SIZE : in std_logic_vector(1 downto 0); FB_ADR : in std_logic_vector(31 downto 0); CLK33M : in std_logic; @@ -71,9 +71,9 @@ entity VIDEO_CTRL is CLUT_MUX_ADR : out std_logic_vector(3 downto 0); HSYNC : out std_logic; VSYNC : out std_logic; - BLANKn : out std_logic; - SYNCn : out std_logic; - PD_VGAn : out std_logic; + blank_n : out std_logic; + sync_n : out std_logic; + pd_vga_n : out std_logic; FIFO_RDE : out std_logic; COLOR2 : out std_logic; COLOR4 : out std_logic; @@ -270,8 +270,8 @@ begin '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else '0'; -- No byte. -- Firebee CLUT: - FBEE_CLUT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 10) = "000000000000000000" else '0'; -- 0-3FF/1024 - FBEE_CLUT_RD <= '1' when FBEE_CLUT_CS = '1' and FB_OEn = '0' else '0'; + FBEE_CLUT_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 10) = "000000000000000000" else '0'; -- 0-3FF/1024 + FBEE_CLUT_RD <= '1' when FBEE_CLUT_CS = '1' and fb_oe_n = '0' else '0'; FBEE_CLUT_WR <= FB_B when FBEE_CLUT_CS = '1' and fb_wr_n = '0' else x"0"; P_CLUT_TA : process @@ -289,24 +289,24 @@ begin end process P_CLUT_TA; --Falcon CLUT: - FALCON_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 10) = "1111100110" else '0'; -- $F9800/$400 - FALCON_CLUT_RDH <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '0' else '0'; -- High word. - FALCON_CLUT_RDL <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '1' else '0'; -- Low word. + FALCON_CLUT_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 10) = "1111100110" else '0'; -- $F9800/$400 + FALCON_CLUT_RDH <= '1' when FALCON_CLUT_CS = '1' and fb_oe_n = '0' and FB_ADR(1) = '0' else '0'; -- High word. + FALCON_CLUT_RDL <= '1' when FALCON_CLUT_CS = '1' and fb_oe_n = '0' and FB_ADR(1) = '1' else '0'; -- Low word. FALCON_CLUT_WR(1 downto 0) <= FB_16B when FB_ADR(1) = '0' and FALCON_CLUT_CS = '1' and fb_wr_n = '0' else "00"; FALCON_CLUT_WR(3 downto 2) <= FB_16B when FB_ADR(1) = '1' and FALCON_CLUT_CS = '1' and fb_wr_n = '0' else "00"; -- ST CLUT: - ST_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 5) = "111110000010010" else '0'; -- $F8240/$2 - CLUT_ST_RD <= '1' when ST_CLUT_CS = '1' and FB_OEn = '0' else '0'; + ST_CLUT_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 5) = "111110000010010" else '0'; -- $F8240/$2 + CLUT_ST_RD <= '1' when ST_CLUT_CS = '1' and fb_oe_n = '0' else '0'; CLUT_ST_WR <= FB_16B when ST_CLUT_CS = '1' and fb_wr_n = '0' else "00"; - ST_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110000" else '0'; -- $F8260/$2. - FALCON_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110011" else '0'; -- $F8266/$2. - FBEE_VCTR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000000" else '0'; -- $400/$4 - ATARI_HH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000100" else '0'; -- $410/4 - ATARI_VH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000101" else '0'; -- $414/4 - ATARI_HL_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000110" else '0'; -- $418/4 - ATARI_VL_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000111" else '0'; -- $41C/4 + ST_SHIFT_MODE_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110000" else '0'; -- $F8260/$2. + FALCON_SHIFT_MODE_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110011" else '0'; -- $F8266/$2. + FBEE_VCTR_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000000" else '0'; -- $400/$4 + ATARI_HH_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000100" else '0'; -- $410/4 + ATARI_VH_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000101" else '0'; -- $414/4 + ATARI_HL_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000110" else '0'; -- $418/4 + ATARI_VL_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000111" else '0'; -- $41C/4 P_VIDEO_CONTROL : process begin @@ -398,7 +398,7 @@ begin end process P_VIDEO_CONTROL; CLUT_OFF <= FALCON_SHIFT_MODE(3 downto 0) when COLOR4_I = '1' else x"0"; - PD_VGAn <= FBEE_VCTR(1); + pd_vga_n <= FBEE_VCTR(1); FBEE_VIDEO_ON <= FBEE_VCTR(0); ATARI_SYNC <= FBEE_VCTR(26); -- If 1 -> automatic resolution. @@ -420,8 +420,8 @@ begin COLOR8 <= COLOR8_I; -- VIDEO PLL config and reconfig: - VIDEO_PLL_CONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_B(1) = '1' and FB_ADR(27 downto 9) = "0000000000000000011" else '0'; -- $(F)000'0600-7FF -> 6/2 word and long only. - VIDEO_PLL_RECONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_ADR(27 downto 0) = x"0000800" else '0'; -- $(F)000'0800. + VIDEO_PLL_CONFIG_CS <= '1' when fb_cs_n(2) = '0' and FB_B(0) = '1' and FB_B(1) = '1' and FB_ADR(27 downto 9) = "0000000000000000011" else '0'; -- $(F)000'0600-7FF -> 6/2 word and long only. + VIDEO_PLL_RECONFIG_CS <= '1' when fb_cs_n(2) = '0' and FB_B(0) = '1' and FB_ADR(27 downto 0) = x"0000800" else '0'; -- $(F)000'0800. VR_RD_I <= '1' when VIDEO_PLL_CONFIG_CS = '1' and fb_wr_n = '0' and VR_BUSY = '0' else '0'; P_VIDEO_CONFIG: process @@ -466,24 +466,24 @@ begin ST_CLUT <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_CLUT = '0' and COLOR1_I = '0' else '0'; -- Several (video)-registers: - CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR = x"f0000404" else '0'; -- $F0000404 - Firebee video border color - SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0'; -- $FF8006 - Falcon monitor type register - VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo. - VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo. - VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo. - VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo. - VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo. - VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo. - VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo. - VDL_HSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828c" else '0'; -- $FF828C/D - position hsync (HSS). - VDL_VFT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a2" else '0'; -- $FF82A2/3 - video frequency timer (VFT). - VDL_VBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a4" else '0'; -- $FF82A4/5 - vertical blank on (in half line steps). - VDL_VBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a6" else '0'; -- $FF82A6/7 - vertical blank off (in half line steps). - VDL_VDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a8" else '0'; -- $FF82A8/9 - vertical display begin (VDB). - VDL_VDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82aa" else '0'; -- $FF82AA/B - vertical display end (VDE). - VDL_VSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82ac" else '0'; -- $FF82AC/D - position vsync (VSS). - VDL_VCT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c0" else '0'; -- $FF82C0/1 - clock control (VCO). - VDL_VMD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c2" else '0'; -- $FF82C2/3 - resolution control. + CCR_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR = x"f0000404" else '0'; -- $F0000404 - Firebee video border color + SYS_CTR_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0'; -- $FF8006 - Falcon monitor type register + VDL_LOF_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo. + VDL_LWD_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo. + VDL_HHT_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo. + VDL_HBE_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo. + VDL_HDB_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo. + VDL_HDE_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo. + VDL_HBB_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo. + VDL_HSS_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828c" else '0'; -- $FF828C/D - position hsync (HSS). + VDL_VFT_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a2" else '0'; -- $FF82A2/3 - video frequency timer (VFT). + VDL_VBB_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a4" else '0'; -- $FF82A4/5 - vertical blank on (in half line steps). + VDL_VBE_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a6" else '0'; -- $FF82A6/7 - vertical blank off (in half line steps). + VDL_VDB_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a8" else '0'; -- $FF82A8/9 - vertical display begin (VDB). + VDL_VDE_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82aa" else '0'; -- $FF82AA/B - vertical display end (VDE). + VDL_VSS_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82ac" else '0'; -- $FF82AC/D - position vsync (VSS). + VDL_VCT_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c0" else '0'; -- $FF82C0/1 - clock control (VCO). + VDL_VMD_CS <= '1' when fb_cs_n(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c2" else '0'; -- $FF82C2/3 - resolution control. P_MISC_CTRL : process begin @@ -657,9 +657,9 @@ begin DATA_EN_H <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or CCR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or VIDEO_PLL_RECONFIG_CS or - VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS) and not FB_OEn; + VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS) and not fb_oe_n; - DATA_EN_L <= (FBEE_VCTR_CS or CCR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS ) and not FB_OEn; + DATA_EN_L <= (FBEE_VCTR_CS or CCR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS ) and not fb_oe_n; VIDEO_MOD_TA_I <= CLUT_TA or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or @@ -889,10 +889,10 @@ begin VERZ_0 <= VERZ_0(8 downto 0) & DISP_ON; - BLANKn <= VERZ_0(8); + blank_n <= VERZ_0(8); HSYNC <= VERZ_1(9); VSYNC <= VERZ_2(9); - SYNCn <= not(VERZ_2(9) or VERZ_1(9)); + sync_n <= not(VERZ_2(9) or VERZ_1(9)); -- border colours: BORDER <= BORDER(5 downto 0) & (DISP_ON and not VDTRON and FBEE_VCTR(25)); diff --git a/vhdl/rtl/vhdl/Video/Video_Top.vhd b/vhdl/rtl/vhdl/Video/Video_Top.vhd index 495e0e1..ee24473 100644 --- a/vhdl/rtl/vhdl/Video/Video_Top.vhd +++ b/vhdl/rtl/vhdl/Video/Video_Top.vhd @@ -70,8 +70,8 @@ ENTITY VIDEO_SYSTEM IS FB_AD_EN_31_16 : OUT STD_LOGIC; -- Hi word. FB_AD_EN_15_0 : OUT STD_LOGIC; -- Low word. FB_ALE : IN STD_LOGIC; - FB_CSn : IN STD_LOGIC_VECTOR(3 DOWNTO 1); - FB_OEn : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; FB_SIZE1 : IN STD_LOGIC; FB_SIZE0 : IN STD_LOGIC; @@ -87,10 +87,10 @@ ENTITY VIDEO_SYSTEM IS BLUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VSYNC : OUT STD_LOGIC; HSYNC : OUT STD_LOGIC; - SYNCn : OUT STD_LOGIC; - BLANKn : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; - PD_VGAn : OUT STD_LOGIC; + pd_vga_n : OUT STD_LOGIC; VIDEO_MOD_TA : OUT STD_LOGIC; VD_VZ : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); @@ -500,10 +500,10 @@ BEGIN I_VIDEO_CTRL: VIDEO_CTRL PORT map( CLK_MAIN => CLK_MAIN, - FB_CSn(1) => FB_CSn(1), - FB_CSn(2) => FB_CSn(2), + fb_cs_n(1) => fb_cs_n(1), + fb_cs_n(2) => fb_cs_n(2), fb_wr_n => fb_wr_n, - FB_OEn => FB_OEn, + fb_oe_n => fb_oe_n, FB_SIZE(0) => FB_SIZE0, FB_SIZE(1) => FB_SIZE1, FB_ADR => FB_ADR, @@ -524,9 +524,9 @@ BEGIN CLUT_MUX_ADR => CLUT_ADR_MUX, HSYNC => HSYNC, VSYNC => VSYNC, - BLANKn => BLANKn, - SYNCn => SYNCn, - PD_VGAn => PD_VGAn, + blank_n => blank_n, + sync_n => sync_n, + pd_vga_n => pd_vga_n, FIFO_RDE => FIFO_RDE, COLOR2 => COLOR2, COLOR4 => COLOR4, diff --git a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd index 0afcd9f..034a799 100644 --- a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd +++ b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd @@ -80,7 +80,7 @@ entity WF68901IP_INTERRUPTS is IACKn : in std_logic; IEIn : in std_logic; IEOn : out std_logic; - IRQn : out std_logic; + irq_n : out std_logic; -- Interrupt sources: GP_INT : in std_logic_vector(7 downto 0); @@ -157,7 +157,7 @@ begin IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1'; -- Interrupt request: - IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1'; + irq_n <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1'; EDGE_ENA: process(RESETn, CLK) -- These are the 16 edge detectors of the 16 interrupt input sources. This diff --git a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd index a1ae64d..1790b7b 100644 --- a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd +++ b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd @@ -192,7 +192,7 @@ component WF68901IP_INTERRUPTS IACKn : in std_logic; IEIn : in std_logic; IEOn : out std_logic; - IRQn : out std_logic; + irq_n : out std_logic; GP_INT : in std_logic_vector(7 downto 0); AER_4 : in std_logic; AER_3 : in std_logic; diff --git a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd index 166dcf9..753a036 100644 --- a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd +++ b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd @@ -84,7 +84,7 @@ entity WF68901IP_TOP is IACKn : in std_logic; IEIn : in std_logic; IEOn : out std_logic; - IRQn : out std_logic; + irq_n : out std_logic; -- Timers and timer control: XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. @@ -125,7 +125,7 @@ component WF68901IP_TOP_SOC IACKn : in std_logic; IEIn : in std_logic; IEOn : out std_logic; - IRQn : out std_logic; + irq_n : out std_logic; XTAL1 : in std_logic; TAI : in std_logic; TBI : in std_logic; @@ -154,7 +154,7 @@ signal SO_I : std_logic; signal SO_EN : std_logic; begin DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain. - IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. + irq_n <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); @@ -194,7 +194,7 @@ begin IACKn => IACKn, IEIn => IEIn, IEOn => IEOn, - IRQn => IRQ_In, + irq_n => IRQ_In, XTAL1 => XTAL1, TAI => TAI, TBI => TBI, diff --git a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd index 6db180b..2c23491 100644 --- a/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd +++ b/vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd @@ -93,7 +93,7 @@ entity WF68901IP_TOP_SOC is IACKn : in std_logic; IEIn : in std_logic; IEOn : out std_logic; - IRQn : out std_logic; + irq_n : out std_logic; -- Timers and timer control: XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. @@ -151,7 +151,7 @@ signal TA_PWM_I : std_logic; signal TB_PWM_I : std_logic; begin -- Interrupt request (open drain): - IRQn <= IRQ_In; + irq_n <= IRQ_In; -- Serial data output: SO <= SO_I; @@ -242,7 +242,7 @@ begin IACKn => IACKn, IEIn => IEIn, IEOn => IEOn, - IRQn => IRQ_In, + irq_n => IRQ_In, GP_INT => GP_INT_I, AER_4 => AER_4_I, AER_3 => AER_3_I, diff --git a/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd index cc173b0..8bf25de 100644 --- a/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +++ b/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd @@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is CDS : out std_logic_vector(1 downto 0); -- Clock control. WS : out std_logic_vector(2 downto 0); -- Word select. TC : out std_logic_vector(1 downto 0); -- Transmit control. - IRQn : buffer std_logic -- Interrupt request. + irq_n : buffer std_logic -- Interrupt request. ); end entity WF6850IP_CTRL_STATUS; @@ -109,7 +109,7 @@ begin CTS_In <= CTSn; DCD_In <= DCDn; -- immer 0 - STATUS_REG(7) <= not IRQn; + STATUS_REG(7) <= not irq_n; STATUS_REG(6) <= PE; STATUS_REG(5) <= OVR; STATUS_REG(4) <= FE; @@ -133,25 +133,25 @@ begin begin if rising_edge(CLK) then if RESETn = '0' or MCLR = '1' then - IRQn <= '1'; + irq_n <= '1'; else -- Transmitter interrupt: if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then - IRQn <= '0'; + irq_n <= '0'; end if; -- Receiver interrupts: if RDRF = '1' and RIE = '1' then - IRQn <= '0'; + irq_n <= '0'; end if; -- Overrun if OVR = '1' and RIE = '1' then - IRQn <= '0'; + irq_n <= '0'; end if; -- The reset of the IRQ status flag: -- Clear by writing to the transmit data register. -- Clear by reading the receive data register. if CS = "011" and RS = '1' then - IRQn <= '1'; + irq_n <= '1'; end if; end if; end if; diff --git a/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd b/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd index 28d6898..65af1fd 100644 --- a/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd +++ b/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd @@ -76,7 +76,7 @@ entity WF6850IP_TOP is CTSn : in std_logic; DCDn : in std_logic; - IRQn : out std_logic; + irq_n : out std_logic; TXDATA : out std_logic; RTSn : out std_logic ); @@ -99,7 +99,7 @@ component WF6850IP_TOP_SOC RXDATA : in std_logic; CTSn : in std_logic; DCDn : in std_logic; - IRQn : out std_logic; + irq_n : out std_logic; TXDATA : out std_logic; RTSn : out std_logic ); @@ -109,7 +109,7 @@ signal DATA_EN : std_logic; signal IRQ_In : std_logic; begin DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); - IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. + irq_n <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. I_UART: WF6850IP_TOP_SOC port map(CLK => CLK, @@ -128,7 +128,7 @@ begin RXDATA => RXDATA, CTSn => CTSn, DCDn => DCDn, - IRQn => IRQ_In, + irq_n => IRQ_In, TXDATA => TXDATA, RTSn => RTSn ); diff --git a/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd b/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd index b7061c2..06c6a74 100644 --- a/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd +++ b/vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -83,7 +83,7 @@ ENTITY WF6850IP_TOP_SOC IS CTSn : IN STD_LOGIC; DCDn : IN STD_LOGIC; - IRQn : OUT STD_LOGIC; + irq_n : OUT STD_LOGIC; TXDATA : OUT STD_LOGIC; RTSn : OUT STD_LOGIC ); @@ -113,7 +113,7 @@ ARCHITECTURE STRUCTURE of WF6850IP_TOP_SOC IS CDS : OUT STD_LOGIC_VECTOR(1 downto 0); WS : OUT STD_LOGIC_VECTOR(2 downto 0); TC : OUT STD_LOGIC_VECTOR(1 downto 0); - IRQn : OUT STD_LOGIC + irq_n : OUT STD_LOGIC ); END COMPONENT; @@ -180,7 +180,7 @@ BEGIN DATA_OUT <= (DATA_RX) WHEN DATA_RX_EN = '1' ELSE (DATA_CTRL) WHEN DATA_CTRL_EN = '1' ELSE (others => '0'); - IRQn <= '0' WHEN IRQ_In = '0' ELSE '1'; + irq_n <= '0' WHEN IRQ_In = '0' ELSE '1'; I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS PORT MAP( @@ -207,7 +207,7 @@ BEGIN CDS => CDS_I, WS => WS_I, TC => TC_I, - IRQn => IRQ_In + irq_n => IRQ_In ); I_UART_RECEIVE: WF6850IP_RECEIVE diff --git a/vhdl/testbenches/ddr2_ram_model.vhd b/vhdl/testbenches/ddr2_ram_model.vhd index faa21fd..bd07421 100644 --- a/vhdl/testbenches/ddr2_ram_model.vhd +++ b/vhdl/testbenches/ddr2_ram_model.vhd @@ -7,7 +7,6 @@ LIBRARY work; PACKAGE ddr2_ram_model_pkg IS -- DDR2 RAM timing constants - CONSTANT TMRD : TIME := 2 ps; -- load mode register command cycle time CONSTANT TRFC_MIN : TIME := 105000 ps; -- refresh to refresh command minimum value CONSTANT TRFC_MAX : TIME := 70000000 ps; -- refresh to refresh command maximum value CONSTANT TRP : TIME := 13125 ps; -- precharge period @@ -16,8 +15,9 @@ PACKAGE ddr2_ram_model_pkg IS CONSTANT TRAS_MIN : TIME := 40000 ps; -- minimum active to precharge command time CONSTANT TRAS_MAX : TIME := 70000000 ps; -- maximum active to precharge command time CONSTANT TRRD : TIME := 10000 ps; -- tRRD: active bank to active bank command time - CONSTANT TFAW : INTEGER := 45000; - + CONSTANT TFAW : TIME := 45000 ps; -- four bank activate window + CONSTANT TWR : TIME := 15000 ps; -- write recovery time + CONSTANT RANDOM_SEED : INTEGER := 711689044; -- seed value for random generator COMPONENT ddr2_ram_model IS @@ -68,6 +68,7 @@ ENTITY ddr2_ram_model IS GENERIC ( VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output + CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick BA_BITS : INTEGER := 2; -- number of banks ADDR_BITS : INTEGER := 13; -- number of address bits @@ -100,7 +101,6 @@ ARCHITECTURE rtl OF ddr2_ram_model IS CONSTANT MEM_BITS : INTEGER := 10; -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024 CONSTANT AP : INTEGER := 10; -- the address bit that controls auto-precharge and precharge-all CONSTANT TDLLK : INTEGER := 200; - CONSTANT BUS_DELAY : TIME := 0 ps; CONSTANT BANKS : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS)); CONSTANT ROW_BITS : INTEGER := 13; CONSTANT COL_BITS : INTEGER := 10; @@ -110,6 +110,13 @@ ARCHITECTURE rtl OF ddr2_ram_model IS CONSTANT MAX_BITS : INTEGER := BA_BITS + ROW_BITS + COL_BITS - BL_BITS; + -- time constants + CONSTANT BUS_DELAY : TIME := 0 ps; + + -- time constants (in tCK's) + CONSTANT TMRD : INTEGER := 2; -- load mode register command cycle time + CONSTANT TCCD : INTEGER := 2; -- CAS to CAS command delay + CONSTANT DQ_PER_DQS : INTEGER := DQ_BITS / DQS_BITS; CONSTANT MAX_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS + ROW_BITS + COL_BITS - BL_BITS)); CONSTANT MEM_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), MEM_BITS)); @@ -160,10 +167,10 @@ ARCHITECTURE rtl OF ddr2_ram_model IS SIGNAL dqs_n_en : STD_LOGIC; SIGNAL rdqs_en : STD_LOGIC; SIGNAL out_en : STD_LOGIC; - SIGNAL read_latency : INTEGER; + SIGNAL READ_CMD_latency : INTEGER; SIGNAL write_latency : INTEGER; - TYPE cmd_type_t IS (LOAD_MODE, REFRESH, PRECHARGE, ACTIVATE, WRITE_CMD, READ, NOP, PWR_DOWN, SELF_REF); + TYPE cmd_type_t IS (LOAD_MODE, REFRESH, PRECHARGE, ACTIVATE, WRITE_CMD, READ_CMD, NOP, PWR_DOWN, SELF_REF); TYPE cmd_type_encoding_array_t IS ARRAY(cmd_type_t) OF STD_LOGIC_VECTOR(3 DOWNTO 0); CONSTANT cmd_type_encoding : cmd_type_encoding_array_t := ( @@ -205,7 +212,7 @@ ARCHITECTURE rtl OF ddr2_ram_model IS -- cmd timers/counters SIGNAL ref_cntr : INTEGER; SIGNAL ck_cntr : INTEGER; - SIGNAL ck_load_mode : TIME; + SIGNAL ck_load_mode : INTEGER; SIGNAL ck_write : INTEGER; SIGNAL ck_read : INTEGER; SIGNAL ck_write_ap : INTEGER; @@ -310,9 +317,12 @@ ARCHITECTURE rtl OF ddr2_ram_model IS ); -- memory storage --- only for MAX_MEM for now TYPE mem_t IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (BL_MAX * DQ_BITS - 1 DOWNTO 0); - SIGNAL memory : mem_t(0 TO MAX_SIZE - 1); + SIGNAL memory : mem_t(0 TO MEM_SIZE - 1); + TYPE adr_t IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (MAX_BITS - 1 DOWNTO 0); + SIGNAL address : adr_t(0 TO MEM_SIZE - 1); + SIGNAL memory_index : STD_LOGIC_VECTOR(MEM_BITS DOWNTO 0); + SIGNAL memory_used : STD_LOGIC_VECTOR(MEM_BITS DOWNTO 0); SIGNAL ck_in : STD_LOGIC; SIGNAL ck_n_in : STD_LOGIC; @@ -376,7 +386,7 @@ ARCHITECTURE rtl OF ddr2_ram_model IS -- memory(addr) <= data; END memory_write; - PROCEDURE memory_read( + PROCEDURE memory_READ_CMD( SIGNAL bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0); SIGNAL row : IN UNSIGNED (ROW_BITS - 1 DOWNTO 0); SIGNAL col : IN UNSIGNED (COL_BITS - 1 DOWNTO 0); @@ -387,7 +397,7 @@ ARCHITECTURE rtl OF ddr2_ram_model IS addr <= (bank & row & col) / BL_MAX; -- TODO: only the MAX_MEM defined functionality defined yet -- data <= memory(addr); - END memory_read; + END memory_READ_CMD; PROCEDURE cmd_task( cke : IN STD_LOGIC; @@ -646,31 +656,31 @@ BEGIN -- all matching case expression will be evaluated CASE? (STD_LOGIC_VECTOR'(samebank & fromcmd & cmd)) IS - WHEN "1" & cmd_type_encoding(LOAD_MODE) & "0---" => + WHEN "0" & cmd_type_encoding(LOAD_MODE) & "0---" => IF ck_cntr - ck_load_mode < TMRD THEN REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tMRD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd)))); END IF; - WHEN "1" & cmd_type_encoding(LOAD_MODE) & "100-" => + WHEN "0" & cmd_type_encoding(LOAD_MODE) & "100-" => IF ck_cntr - ck_load_mode < TMRD THEN REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Load Mode to Reset Condition"); END IF; - WHEN "1" & cmd_type_encoding(REFRESH) & "0---" => + WHEN "0" & cmd_type_encoding(REFRESH) & "0---" => IF NOW - tm_refresh < TRFC_MIN THEN REPORT("tRFC violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd)))); END IF; - WHEN "1" & cmd_type_encoding(REFRESH) & cmd_type_encoding(PWR_DOWN) => + WHEN "0" & cmd_type_encoding(REFRESH) & cmd_type_encoding(PWR_DOWN) => -- 1 tCK_avg - WHEN "1" & cmd_type_encoding(REFRESH) & cmd_type_encoding(SELF_REF) => + WHEN "0" & cmd_type_encoding(REFRESH) & cmd_type_encoding(SELF_REF) => IF NOW - tm_refresh < TRFC_MIN THEN REPORT("at time " & TIME'IMAGE(NOW) & "INFO: Refresh to Reset condition"); END IF; init_done <= '0'; - WHEN "1" & cmd_type_encoding(PRECHARGE) & "000-" => + WHEN "0" & cmd_type_encoding(PRECHARGE) & "000-" => IF NOW - tm_precharge_all < TRPA THEN REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRPA violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd)))); END IF; @@ -696,16 +706,16 @@ BEGIN & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank)))); END IF; - WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PWR_DOWN) => + WHEN "0" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PWR_DOWN) => -- 1 tCK, can be concurrent with auto precharge - WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(SELF_REF) => + WHEN "0" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(SELF_REF) => IF NOW - tm_precharge_all < TRPA OR NOW - tm_precharge < TRP THEN REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge to reset condition"); init_done <= '0'; END IF; - WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(REFRESH) => + WHEN "0" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(REFRESH) => IF NOW - tm_activate < TRC THEN REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRC violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd)))); END IF; @@ -720,7 +730,7 @@ BEGIN " to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank)))); END IF; - WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(ACTIVATE) => + WHEN "0" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(ACTIVATE) => IF NOW - tm_activate < TRRD THEN REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRRD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank)))); @@ -742,20 +752,24 @@ BEGIN IF ck_cntr - ck_bank_write(TO_INTEGER(UNSIGNED(bank))) <= write_latency + TO_INTEGER(UNSIGNED(burst_length)) + 2 OR NOW - tm_bank_write_end(TO_INTEGER(UNSIGNED(bank))) < TWR THEN - REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWR violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank)))); + REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWR violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & + " to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank)))); END IF; - WHEN "1" & cmd_type_enconding(WRITE_CMD) & cmd_type_encoding(WRITE_CMD) => + WHEN "0" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(WRITE_CMD) => IF ck_cntr - ck_write < TCCD THEN - REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tCCD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " & INTEGER'IMAGE(TO_INTEGER(bank))); + REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tCCD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & + " to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank)))); END IF; - WHEN "1" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(READ) => - IF ck_load_mode < ck_write AND ck_cntr - ck_write < write_latency + burst_length / 2 + 2 - additive_latency THEN - REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWTR violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " & INTEGER'IMAGE(TO_INTEGER(bank))); + WHEN "0" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(READ_CMD) => + IF ck_load_mode < ck_write AND ck_cntr - ck_write < write_latency + TO_INTEGER(UNSIGNED(burst_length)) / 2 + 2 - additive_latency THEN + REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWTR violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & + " to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank)))); END IF; - WHEN "1" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PWR_DOWN) => + WHEN "0" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PWR_DOWN) => + WHEN OTHERS => -- do nothing