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This version is working again, except network. For some reason, the DMA

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interrupts don't seem to be triggered.
This commit is contained in:
Markus Fröschle
2015-01-09 20:12:03 +00:00
parent 6da4e0f182
commit 388ff72886
13 changed files with 475 additions and 472 deletions
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1
BaS_gcc/BaS_gcc.files
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@@ -195,3 +195,4 @@ util/bas_printf.c
util/bas_string.c
util/printf_helper.S
util/wait.c
bas.lk.in

3
BaS_gcc/Makefile
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@@ -31,8 +31,8 @@ NATIVECC=gcc
INCLUDE=-Iinclude
CFLAGS=-mcpu=5474 \
-Wall \
-g \
-Wall \
-fomit-frame-pointer \
-ffreestanding \
-fleading-underscore \
@@ -41,6 +41,7 @@ CFLAGS=-mcpu=5474 \
CFLAGS_OPTIMIZED = -mcpu=5474 \
-Wall \
-O2 \
-g \
-fomit-frame-pointer \
-ffreestanding \
-fleading-underscore \

10
BaS_gcc/dma/dma.c
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@@ -86,9 +86,8 @@ static struct dma_channel dma_channel[NCHANNELS] =
void dma_irq_enable(uint8_t lvl, uint8_t pri)
{
/* Setup the DMA ICR (#48) */
MCF_INTC_ICR48 = 0
| MCF_INTC_ICR_IP(pri)
| MCF_INTC_ICR_IL(lvl);
MCF_INTC_ICR48 = MCF_INTC_ICR_IP(pri) |
MCF_INTC_ICR_IL(lvl);
dbg("DMA irq assigned level %d, priority %d\r\n", lvl, pri);
/* Unmask all task interrupts */
@@ -479,7 +478,9 @@ int dma_set_channel(int requestor, void (*handler)(void))
/* Check to see if this requestor is already assigned to a channel */
dbg("check if requestor %d is already assigned to a channel\r\n", requestor);
if ((i = dma_get_channel(requestor)) != -1)
{
return i;
}
for (i = 0; i < NCHANNELS; ++i)
{
@@ -571,10 +572,11 @@ int dma_interrupt_handler(void *arg1, void *arg2)
/* Make sure we are here for a reason */
if (interrupts == 0)
{
dbg("not DMA interrupt!\r\n");
err("not DMA interrupt!\r\n");
return 0;
}
dbg("");
/* Clear the interrupt in the pending register */
MCF_DMA_DIPR = interrupts;

17
BaS_gcc/include/interrupts.h
View File

@@ -79,25 +79,22 @@
#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
#define FEC0_INTC_LVL 5 /* interrupt level for FEC0 */
#define FEC0_INTC_PRI 1 /* interrupt priority for FEC0 */
#define FEC0_INTC_LVL 6 /* interrupt level for FEC0 */
#define FEC0_INTC_PRI 7 /* interrupt priority for FEC0 */
#define FEC1_INTC_LVL 5 /* interrupt level for FEC1 */
#define FEC1_INTC_PRI 0 /* interrupt priority for FEC1 */
#define FEC1_INTC_LVL 6 /* interrupt level for FEC1 */
#define FEC1_INTC_PRI 6 /* interrupt priority for FEC1 */
#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
#define FEC0RX_DMA_PRI 5
#define FEC1RX_DMA_PRI 3
#define FEC1RX_DMA_PRI 4
#define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
#define FEC0TX_DMA_PRI 6
#define FEC1TX_DMA_PRI 4
#define FEC0TX_DMA_PRI 2
#define FEC1TX_DMA_PRI 1
#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
#define ISR_DBUG_ISR 0x01
#define ISR_USER_ISR 0x02
#if defined(MACHINE_FIREBEE)
/* Firebee FPGA interrupt controller */

2
BaS_gcc/include/version.h
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@@ -29,7 +29,7 @@
*/
#define MAJOR_VERSION 0
#define MINOR_VERSION 86
#define MINOR_VERSION 87
#endif /* VERSION_H_ */

6
BaS_gcc/net/fec.c
View File

@@ -1133,9 +1133,8 @@ void fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri)
/*
* Setup the appropriate ICR
*/
MCF_INTC_ICR((ch == 0) ? 39 : 38) = (uint8_t)(0
| MCF_INTC_ICR_IP(pri)
| MCF_INTC_ICR_IL(lvl));
MCF_INTC_ICR((ch == 0) ? 39 : 38) = MCF_INTC_ICR_IP(pri) |
MCF_INTC_ICR_IL(lvl);
/*
* Clear any pending FEC interrupt events
@@ -1257,7 +1256,6 @@ static void fec_irq_handler(uint8_t ch)
{
fec_log[ch].txf++;
dbg("TXF\r\n");
fec_log_dump(0);
}
if (event & MCF_FEC_EIR_GRA)

14
BaS_gcc/net/net_timer.c
View File

@@ -62,23 +62,29 @@ void timer_irq_enable(uint8_t ch)
/*
* Setup the appropriate ICR
*/
MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) =
(uint8_t)(0
| MCF_INTC_ICR_IP(net_timer[ch].pri)
| MCF_INTC_ICR_IL(net_timer[ch].lvl));
MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) = MCF_INTC_ICR_IP(net_timer[ch].pri) |
MCF_INTC_ICR_IL(net_timer[ch].lvl);
/*
* Unmask the FEC interrupt in the interrupt controller
*/
if (ch == 3)
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59;
}
else if (ch == 2)
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60;
}
else if (ch == 1)
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61;
}
else
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62;
}
}
bool timer_set_secs(uint8_t ch, uint32_t secs)
{

1
BaS_gcc/pci/pci.c
View File

@@ -1093,7 +1093,6 @@ void pci_scan(void)
PCI_DEVICE_FROM_HANDLE(handle),
PCI_FUNCTION_FROM_HANDLE(handle));
}
handle = pci_find_device(0x0, 0xFFFF, ++index);
}
xprintf("\r\n...finished\r\n");

50
BaS_gcc/sys/BaS.c
View File

@@ -231,7 +231,7 @@ void enable_coldfire_interrupts()
MCF_GPT_GMS_IEN |
MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */
MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
MCF_INTC_ICR_IP(7); /* interrupt level 7, interrupt priority 7 */
MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
@@ -282,8 +282,7 @@ void init_isr(void)
*/
if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1))
{
dbg("unable to register isr for FEC0\r\n");
return;
err("unable to register isr for FEC0\r\n");
}
/*
@@ -292,19 +291,18 @@ void init_isr(void)
if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL, NULL))
{
dbg("Error: Unable to register isr for DMA\r\n");
return;
err("Error: Unable to register isr for DMA\r\n");
}
dma_irq_enable(5, 3); /* TODO: need to match the FEC driver's specs in MiNT? */
dma_irq_enable(7, 7); /* TODO: need to match the FEC driver's specs in MiNT? */
#ifdef _NOT_USED_
/*
* register the PIC interrupt handler
*/
if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
if (!isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register ISR for PSC3\r\n");
return;
err("Error: unable to register ISR for PSC3\r\n");
}
/*
@@ -312,11 +310,12 @@ void init_isr(void)
*/
if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, xlbpci_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register isr for XLB PCI interrupts\r\n");
return;
err("Error: unable to register isr for XLB PCI interrupts\r\n");
}
MCF_INTC_ICR43 = MCF_INTC_ICR_IL(5) | /* level 5, priority 1 */
MCF_INTC_ICR_IP(1);
MCF_INTC_ICR43 = MCF_INTC_ICR_IL(7) | /* level 7, priority 6 */
MCF_INTC_ICR_IP(6);
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK43; /* enable XLB PCI interrupts in DMA controller */
MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
@@ -328,15 +327,17 @@ void init_isr(void)
if (!isr_register_handler(64 + INT_SOURCE_PCIARB, pciarb_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register isr for PCIARB interrupts\r\n");
err("Error: unable to register isr for PCIARB interrupts\r\n");
return;
}
MCF_INTC_ICR41 = MCF_INTC_ICR_IL(5) | /* level 5, priority 0 */
MCF_INTC_ICR_IP(0);
MCF_INTC_ICR41 = MCF_INTC_ICR_IL(7) | /* level 5, priority 0 */
MCF_INTC_ICR_IP(5);
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK41; /* enable PCIARB interrupts in DMA controller */
MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
#endif /* _NOT_USED_ */
}
void BaS(void)
@@ -349,6 +350,10 @@ void BaS(void)
nvram_init();
#endif /* MACHINE_FIREBEE */
xprintf("initialize MMU: ");
mmu_init();
xprintf("finished\r\n");
xprintf("copy EmuTOS: ");
/* copy EMUTOS */
@@ -356,10 +361,6 @@ void BaS(void)
dma_memcpy(dst, src, EMUTOS_SIZE);
xprintf("finished\r\n");
xprintf("initialize MMU: ");
mmu_init();
xprintf("finished\r\n");
xprintf("initialize exception vector table: ");
vec_init();
xprintf("finished\r\n");
@@ -440,14 +441,13 @@ void BaS(void)
xprintf("BaS initialization finished, enable interrupts\r\n");
init_isr();
enable_coldfire_interrupts();
init_pci();
video_init();
set_ipl(0); /* enable interrupts */
//init_pci();
// video_init();
/* initialize USB devices */
init_usb();
//init_usb();
//set_ipl(7); /* disable interrupts */
set_ipl(7); /* disable interrupts */
xprintf("call EmuTOS\r\n");
struct rom_header *os_header = (struct rom_header *) TOS;

8
BaS_gcc/sys/exceptions.S
View File

@@ -190,7 +190,7 @@ init_vec_loop:
lea _get_bas_drivers(pc),a1
move.l a1,0x80(a0) // trap #0 exception vector
// MFP non-autovector interrupt handlers. Those are rerouted to their autovector counterparts
// MFP non-autovector interrupt handlers. Those are just rerouted to their autovector counterparts
lea irq1(pc),a1
move.l a1,0x104(a0)
@@ -451,13 +451,13 @@ irq6: move.w #0x2700,sr // disable interrupt
rte
irq6_forward:
move.l 0xf0020000,a0 // fetch "MFP interrupt vector from FPGA"
move.l 0xf0020000,a0 // fetch "MFP interrupt vector" from FPGA
add.l _rt_vbr,a0 // add runtime VBR
move.l (a0),8(a6) // fetch handler address and put it on "extra space"
move.l (a0),4(a6) // fetch handler address and put it on "extra space"
movem.l (sp),d0-d1/a0-a1
unlk a6
move.w #0x2600,sr // set interrupt level
move.w #0x2600,sr // set interrupt mask to MFP level
rts // jump through vector

12
BaS_gcc/sys/fault_vectors.c
View File

@@ -138,22 +138,22 @@ void fault_handler(uint32_t pc, uint32_t format_status)
xprintf("spurious interrupt");
break;
default:
if ( ((fault_status >= 6) && (fault_status <= 7)) ||
((fault_status >= 16) && (fault_status <= 23)))
if ( ((vector >= 6) && (vector <= 7)) ||
((vector >= 16) && (vector <= 23)))
{
xprintf("reserved");
}
else if ((fault_status >= 25) && (fault_status <= 31))
else if ((vector >= 25) && (vector <= 31))
{
xprintf("level %d autovectored interrupt", fault_status - 24);
}
else if ((fault_status >= 32) && (fault_status <= 47))
else if ((vector >= 32) && (vector <= 47))
{
xprintf("trap #%d", fault_status - 32);
xprintf("trap #%d", vector - 32);
}
else
{
xprintf("unknown fault status");
xprintf("unknown vector\r\n");
}
}
xprintf(")\r\n");

6
BaS_gcc/sys/interrupts.c
View File

@@ -145,6 +145,8 @@ bool isr_execute_handler(int vector)
int index;
bool retval = false;
dbg("vector = 0x%x\r\n", vector);
/*
* locate an Interrupt Service Routine handler.
*/
@@ -312,7 +314,7 @@ bool irq6_handler(uint32_t sf1, uint32_t sf2)
{
bool handled = false;
err("IRQ6!\r\n");
// err("IRQ6!\r\n");
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
@@ -377,6 +379,8 @@ void irq7_handler(void)
*/
void gpt0_interrupt_handler(void)
{
dbg("handler called\n\r");
MCF_GPT0_GMS &= ~1; /* rearm trigger */
NOP();
MCF_GPT0_GMS |= 1;

15
BaS_gcc/sys/sysinit.c
View File

@@ -267,7 +267,8 @@ void init_serial(void)
MCF_PSC3_PSCCR = 0x05;
#endif /* MACHINE_FIREBEE */
MCF_INTC_ICR32 = 0x3F; /* PSC3 interrupt vector. Do we need it? */
MCF_INTC_ICR32 = MCF_INTC_ICR_IL(7) |
MCF_INTC_ICR_IL(4); /* PSC3 interrupt vector. Do we need it? */
xprintf("\r\nserial interfaces initialization: finished\r\n");
}
@@ -645,7 +646,7 @@ static bool i2c_transfer_finished(void)
static void wait_i2c_transfer_finished(void)
{
waitfor(10000, i2c_transfer_finished); /* wait until interrupt bit has been set */
waitfor(1000, i2c_transfer_finished); /* wait until interrupt bit has been set */
MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF; /* clear interrupt bit (byte transfer finished */
}
@@ -680,9 +681,10 @@ void dvi_on(void)
receivedByte = MCF_I2C_I2DR; /* read a byte */
MCF_I2C_I2SR = 0x0; /* clear status register */
MCF_I2C_I2CR = 0x0; /* disable i2c */
MCF_I2C_I2CR = 0x0; /* clear control register */
MCF_I2C_I2ICR = MCF_I2C_I2ICR_IE; /* route i2c interrupts to cpu */
/* i2c enable, master mode, transmit acknowledge */
MCF_I2C_I2CR = MCF_I2C_I2CR_IEN | MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX;
@@ -1111,13 +1113,6 @@ void initialize_hardware(void)
#endif /* MACHINE_FIREBEE */
driver_mem_init();
init_pci();
video_init();
/* do not try to init USB for now on the Firebee, it hangs the machine */
#ifndef MACHINE_FIREBEE
//init_usb();
#endif
#if MACHINE_FIREBEE
init_ac97();