diff --git a/BaS_gcc/BaS_gcc.files b/BaS_gcc/BaS_gcc.files index c25011a..be2ea1f 100644 --- a/BaS_gcc/BaS_gcc.files +++ b/BaS_gcc/BaS_gcc.files @@ -195,3 +195,4 @@ util/bas_printf.c util/bas_string.c util/printf_helper.S util/wait.c +bas.lk.in diff --git a/BaS_gcc/Makefile b/BaS_gcc/Makefile index 12cf3ba..f67ee07 100644 --- a/BaS_gcc/Makefile +++ b/BaS_gcc/Makefile @@ -31,8 +31,8 @@ NATIVECC=gcc INCLUDE=-Iinclude CFLAGS=-mcpu=5474 \ + -g \ -Wall \ - -g \ -fomit-frame-pointer \ -ffreestanding \ -fleading-underscore \ @@ -41,6 +41,7 @@ CFLAGS=-mcpu=5474 \ CFLAGS_OPTIMIZED = -mcpu=5474 \ -Wall \ -O2 \ + -g \ -fomit-frame-pointer \ -ffreestanding \ -fleading-underscore \ diff --git a/BaS_gcc/dma/dma.c b/BaS_gcc/dma/dma.c index 16fe0e6..c79660a 100644 --- a/BaS_gcc/dma/dma.c +++ b/BaS_gcc/dma/dma.c @@ -86,9 +86,8 @@ static struct dma_channel dma_channel[NCHANNELS] = void dma_irq_enable(uint8_t lvl, uint8_t pri) { /* Setup the DMA ICR (#48) */ - MCF_INTC_ICR48 = 0 - | MCF_INTC_ICR_IP(pri) - | MCF_INTC_ICR_IL(lvl); + MCF_INTC_ICR48 = MCF_INTC_ICR_IP(pri) | + MCF_INTC_ICR_IL(lvl); dbg("DMA irq assigned level %d, priority %d\r\n", lvl, pri); /* Unmask all task interrupts */ @@ -479,7 +478,9 @@ int dma_set_channel(int requestor, void (*handler)(void)) /* Check to see if this requestor is already assigned to a channel */ dbg("check if requestor %d is already assigned to a channel\r\n", requestor); if ((i = dma_get_channel(requestor)) != -1) + { return i; + } for (i = 0; i < NCHANNELS; ++i) { @@ -560,7 +561,7 @@ int dma_interrupt_handler(void *arg1, void *arg2) int i, interrupts; uint32_t ipl; - ipl = set_ipl(7); /* do not disturb */ + ipl = set_ipl(7); /* do not disturb */ /* * Determine which interrupt(s) triggered by AND'ing the @@ -571,10 +572,11 @@ int dma_interrupt_handler(void *arg1, void *arg2) /* Make sure we are here for a reason */ if (interrupts == 0) { - dbg("not DMA interrupt!\r\n"); + err("not DMA interrupt!\r\n"); return 0; } + dbg(""); /* Clear the interrupt in the pending register */ MCF_DMA_DIPR = interrupts; @@ -593,7 +595,7 @@ int dma_interrupt_handler(void *arg1, void *arg2) set_ipl(ipl); - return 1; /* handled */ + return 1; /* handled */ } /********************************************************************/ @@ -674,7 +676,7 @@ int dma_init(void) } // test - dma_memcpy((void *) 0x10000, (void *) 0x03e00000, 0x00100000); /* copy one megabyte of flash to RAM */ + dma_memcpy((void *) 0x10000, (void *) 0x03e00000, 0x00100000); /* copy one megabyte of flash to RAM */ return 0; } diff --git a/BaS_gcc/include/interrupts.h b/BaS_gcc/include/interrupts.h index d0d1184..ed9e67a 100644 --- a/BaS_gcc/include/interrupts.h +++ b/BaS_gcc/include/interrupts.h @@ -27,83 +27,80 @@ #include /* interrupt sources */ -#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1 -#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2 -#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3 -#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4 -#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5 -#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6 -#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7 -#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt -#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt -#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt -#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt -#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt -#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt -#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt -#define INT_SOURCE_USB_USBISR 22 // USB general interrupt -#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt -#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts -#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow -#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt -#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt -#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt -#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt -#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt -#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt -#define INT_SOURCE_PSC3 32 // PSC3 interrupt -#define INT_SOURCE_PSC2 33 // PSC2 interrupt -#define INT_SOURCE_PSC1 34 // PSC1 interrupt -#define INT_SOURCE_PSC0 35 // PSC0 interrupt -#define INT_SOURCE_CTIMERS 36 // combined source for comm timers -#define INT_SOURCE_SEC 37 // SEC interrupt -#define INT_SOURCE_FEC1 38 // FEC1 interrupt -#define INT_SOURCE_FEC0 39 // FEC0 interrupt -#define INT_SOURCE_I2C 40 // I2C interrupt -#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt -#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt -#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt -#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt -#define INT_SOURCE_DMA 48 // multichannel DMA interrupt -#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt -#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt -#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt -#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt -#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt -#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt -#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt -#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt -#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt -#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt -#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt -#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt +#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1 +#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2 +#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3 +#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4 +#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5 +#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6 +#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7 +#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt +#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt +#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt +#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt +#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt +#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt +#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt +#define INT_SOURCE_USB_USBISR 22 // USB general interrupt +#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt +#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts +#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow +#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt +#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt +#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt +#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt +#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt +#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt +#define INT_SOURCE_PSC3 32 // PSC3 interrupt +#define INT_SOURCE_PSC2 33 // PSC2 interrupt +#define INT_SOURCE_PSC1 34 // PSC1 interrupt +#define INT_SOURCE_PSC0 35 // PSC0 interrupt +#define INT_SOURCE_CTIMERS 36 // combined source for comm timers +#define INT_SOURCE_SEC 37 // SEC interrupt +#define INT_SOURCE_FEC1 38 // FEC1 interrupt +#define INT_SOURCE_FEC0 39 // FEC0 interrupt +#define INT_SOURCE_I2C 40 // I2C interrupt +#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt +#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt +#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt +#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt +#define INT_SOURCE_DMA 48 // multichannel DMA interrupt +#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt +#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt +#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt +#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt +#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt +#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt +#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt +#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt +#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt +#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt +#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt +#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt -#define FEC0_INTC_LVL 5 /* interrupt level for FEC0 */ -#define FEC0_INTC_PRI 1 /* interrupt priority for FEC0 */ +#define FEC0_INTC_LVL 6 /* interrupt level for FEC0 */ +#define FEC0_INTC_PRI 7 /* interrupt priority for FEC0 */ -#define FEC1_INTC_LVL 5 /* interrupt level for FEC1 */ -#define FEC1_INTC_PRI 0 /* interrupt priority for FEC1 */ +#define FEC1_INTC_LVL 6 /* interrupt level for FEC1 */ +#define FEC1_INTC_PRI 6 /* interrupt priority for FEC1 */ -#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL) -#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI) +#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL) +#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI) #define FEC0RX_DMA_PRI 5 -#define FEC1RX_DMA_PRI 3 +#define FEC1RX_DMA_PRI 4 #define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI) -#define FEC0TX_DMA_PRI 6 -#define FEC1TX_DMA_PRI 4 +#define FEC0TX_DMA_PRI 2 +#define FEC1TX_DMA_PRI 1 #define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI) -#define ISR_DBUG_ISR 0x01 -#define ISR_USER_ISR 0x02 - #if defined(MACHINE_FIREBEE) /* Firebee FPGA interrupt controller */ -#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000) -#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004) -#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008) +#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000) +#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004) +#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008) #define FBEE_INTR_PENDING * ((volatile uint32_t *) 0xff01000c) /* register bits for Firebee FPGA-based interrupt controller */ @@ -137,13 +134,13 @@ #define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15) #ifdef _NOT_USED_ -#define vbasehi * ((volatile uint8_t *) 0xffff8201) -#define vbasemid * ((volatile uint8_t *) 0xffff8203) -#define vbaselow * ((volatile uint8_t *) 0xffff820d) +#define vbasehi * ((volatile uint8_t *) 0xffff8201) +#define vbasemid * ((volatile uint8_t *) 0xffff8203) +#define vbaselow * ((volatile uint8_t *) 0xffff820d) -#define vwrap * ((volatile uint16_t *) 0xffff8210) -#define vde * ((volatile uint16_t *) 0xffff82aa) -#define vdb * ((volatile uint16_t *) 0xffff82a8) +#define vwrap * ((volatile uint16_t *) 0xffff8210) +#define vde * ((volatile uint16_t *) 0xffff82aa) +#define vdb * ((volatile uint16_t *) 0xffff82a8) #endif /* _NOT_USED_ */ #endif /* MACHINE_FIREBEE */ diff --git a/BaS_gcc/include/version.h b/BaS_gcc/include/version.h index 39704bd..53f03ab 100644 --- a/BaS_gcc/include/version.h +++ b/BaS_gcc/include/version.h @@ -29,7 +29,7 @@ */ #define MAJOR_VERSION 0 -#define MINOR_VERSION 86 +#define MINOR_VERSION 87 #endif /* VERSION_H_ */ diff --git a/BaS_gcc/net/fec.c b/BaS_gcc/net/fec.c index 77e9250..7abb16b 100644 --- a/BaS_gcc/net/fec.c +++ b/BaS_gcc/net/fec.c @@ -1133,9 +1133,8 @@ void fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri) /* * Setup the appropriate ICR */ - MCF_INTC_ICR((ch == 0) ? 39 : 38) = (uint8_t)(0 - | MCF_INTC_ICR_IP(pri) - | MCF_INTC_ICR_IL(lvl)); + MCF_INTC_ICR((ch == 0) ? 39 : 38) = MCF_INTC_ICR_IP(pri) | + MCF_INTC_ICR_IL(lvl); /* * Clear any pending FEC interrupt events @@ -1257,7 +1256,6 @@ static void fec_irq_handler(uint8_t ch) { fec_log[ch].txf++; dbg("TXF\r\n"); - fec_log_dump(0); } if (event & MCF_FEC_EIR_GRA) diff --git a/BaS_gcc/net/net_timer.c b/BaS_gcc/net/net_timer.c index f8787a5..78fdcc8 100644 --- a/BaS_gcc/net/net_timer.c +++ b/BaS_gcc/net/net_timer.c @@ -31,166 +31,172 @@ static NET_TIMER net_timer[4] = { - {0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0} + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0} }; int timer_default_isr(void *not_used, NET_TIMER *t) { - (void) not_used; + (void) not_used; - /* - * Clear the pending event - */ - MCF_GPT_GMS(t->ch) = 0; + /* + * Clear the pending event + */ + MCF_GPT_GMS(t->ch) = 0; - dbg("timer isr called for timer channel %d\r\n"); + dbg("timer isr called for timer channel %d\r\n"); - /* - * Clear the reference - the desired seconds have expired - */ - t->reference = 0; + /* + * Clear the reference - the desired seconds have expired + */ + t->reference = 0; - return 1; + return 1; } void timer_irq_enable(uint8_t ch) { - /* - * Setup the appropriate ICR - */ - MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) = - (uint8_t)(0 - | MCF_INTC_ICR_IP(net_timer[ch].pri) - | MCF_INTC_ICR_IL(net_timer[ch].lvl)); + /* + * Setup the appropriate ICR + */ + MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) = MCF_INTC_ICR_IP(net_timer[ch].pri) | + MCF_INTC_ICR_IL(net_timer[ch].lvl); - /* - * Unmask the FEC interrupt in the interrupt controller - */ - if (ch == 3) - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59; - else if (ch == 2) - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60; - else if (ch == 1) - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61; - else - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62; + /* + * Unmask the FEC interrupt in the interrupt controller + */ + if (ch == 3) + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59; + } + else if (ch == 2) + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60; + } + else if (ch == 1) + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61; + } + else + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62; + } } bool timer_set_secs(uint8_t ch, uint32_t secs) { - uint16_t timeout; + uint16_t timeout; - /* - * Reset the timer - */ - MCF_GPT_GMS(ch) = 0; + /* + * Reset the timer + */ + MCF_GPT_GMS(ch) = 0; - /* - * Get the timeout in seconds - */ - timeout = (uint16_t)(secs * net_timer[ch].cnt); + /* + * Get the timeout in seconds + */ + timeout = (uint16_t)(secs * net_timer[ch].cnt); - /* - * Set the reference indicating that we have not yet reached the - * desired timeout - */ - net_timer[ch].reference = 1; + /* + * Set the reference indicating that we have not yet reached the + * desired timeout + */ + net_timer[ch].reference = 1; - /* - * Enable timer interrupt to the processor - */ - timer_irq_enable(ch); + /* + * Enable timer interrupt to the processor + */ + timer_irq_enable(ch); - /* - * Enable the timer using the pre-calculated values - */ - MCF_GPT_GCIR(ch) = (0 - | MCF_GPT_GCIR_CNT(timeout) - | MCF_GPT_GCIR_PRE(net_timer[ch].pre) - ); - MCF_GPT_GMS(ch) = net_timer[ch].gms; + /* + * Enable the timer using the pre-calculated values + */ + MCF_GPT_GCIR(ch) = (0 + | MCF_GPT_GCIR_CNT(timeout) + | MCF_GPT_GCIR_PRE(net_timer[ch].pre) + ); + MCF_GPT_GMS(ch) = net_timer[ch].gms; - return true; + return true; } uint32_t timer_get_reference(uint8_t ch) { - return (uint32_t) net_timer[ch].reference; + return (uint32_t) net_timer[ch].reference; } bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri) { - /* - * Initialize the timer to expire after one second - * - * This routine should only be called by the project (board) specific - * initialization code. - */ - if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7))) - { - dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri); + /* + * Initialize the timer to expire after one second + * + * This routine should only be called by the project (board) specific + * initialization code. + */ + if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7))) + { + dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri); - return false; - } + return false; + } - /* - * Reset the timer - */ - MCF_GPT_GMS(ch) = 0; + /* + * Reset the timer + */ + MCF_GPT_GMS(ch) = 0; - /* - * Save off the channel, and interrupt lvl/pri information - */ - net_timer[ch].ch = ch; - net_timer[ch].lvl = lvl; - net_timer[ch].pri = pri; + /* + * Save off the channel, and interrupt lvl/pri information + */ + net_timer[ch].ch = ch; + net_timer[ch].lvl = lvl; + net_timer[ch].pri = pri; - /* - * Register the timer interrupt handler - */ - if (!isr_register_handler(TIMER_VECTOR(ch), - (int (*)(void *,void *)) timer_default_isr, - NULL, - (void *) &net_timer[ch]) - ) - { - dbg("could not register timer interrupt handler\r\n"); - return false; - } - dbg("timer handler registered\r\n", __FUNCTION__); + /* + * Register the timer interrupt handler + */ + if (!isr_register_handler(TIMER_VECTOR(ch), + (int (*)(void *,void *)) timer_default_isr, + NULL, + (void *) &net_timer[ch]) + ) + { + dbg("could not register timer interrupt handler\r\n"); + return false; + } + dbg("timer handler registered\r\n", __FUNCTION__); - /* - * Calculate the require CNT value to get a 1 second timeout - * - * 1 sec = CNT * Clk Period * PRE - * CNT = 1 sec / (Clk Period * PRE) - * CNT = Clk Freq / PRE - * - * The system clock frequency is defined as SYSTEM_CLOCK and - * is given in MHz. We need to multiple it by 1000000 to get the - * true value. If we assume PRE to be the maximum of 0xFFFF, - * then the CNT value needed to achieve a 1 second timeout is - * given by: - * - * CNT = SYSTEM_CLOCK * (1000000/0xFFFF) - */ - net_timer[ch].pre = 0xFFFF; - net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF)); + /* + * Calculate the require CNT value to get a 1 second timeout + * + * 1 sec = CNT * Clk Period * PRE + * CNT = 1 sec / (Clk Period * PRE) + * CNT = Clk Freq / PRE + * + * The system clock frequency is defined as SYSTEM_CLOCK and + * is given in MHz. We need to multiple it by 1000000 to get the + * true value. If we assume PRE to be the maximum of 0xFFFF, + * then the CNT value needed to achieve a 1 second timeout is + * given by: + * + * CNT = SYSTEM_CLOCK * (1000000/0xFFFF) + */ + net_timer[ch].pre = 0xFFFF; + net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF)); - /* - * Save off the appropriate mode select register value - */ - net_timer[ch].gms = (0 - | MCF_GPT_GMS_TMS_GPIO - | MCF_GPT_GMS_IEN - | MCF_GPT_GMS_SC - | MCF_GPT_GMS_CE - ); + /* + * Save off the appropriate mode select register value + */ + net_timer[ch].gms = (0 + | MCF_GPT_GMS_TMS_GPIO + | MCF_GPT_GMS_IEN + | MCF_GPT_GMS_SC + | MCF_GPT_GMS_CE + ); - return true; + return true; } diff --git a/BaS_gcc/pci/pci.c b/BaS_gcc/pci/pci.c index e8d83cb..664c790 100644 --- a/BaS_gcc/pci/pci.c +++ b/BaS_gcc/pci/pci.c @@ -1,7 +1,7 @@ /* * pci.c * - * Purpose: PCI configuration for the Coldfire builtin PCI bridge. + * Purpose: PCI configuration for the Coldfire builtin PCI bridge. * * Notes: * @@ -74,8 +74,8 @@ static struct pci_class }; static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class); -#define NUM_CARDS 10 -#define NUM_RESOURCES 7 +#define NUM_CARDS 10 +#define NUM_RESOURCES 7 /* holds the handle of a card at position = array index */ static int32_t handles[NUM_CARDS]; @@ -97,7 +97,7 @@ struct pci_interrupt struct pci_interrupt *next; }; -#define MAX_INTERRUPTS (NUM_CARDS * 3) +#define MAX_INTERRUPTS (NUM_CARDS * 3) static struct pci_interrupt interrupts[MAX_INTERRUPTS]; static inline __attribute__((aligned(16))) void chip_errata_135(void) @@ -123,17 +123,17 @@ static inline __attribute__((aligned(16))) void chip_errata_135(void) */ __asm__ __volatile( - " .extern __MBAR \n\t" - " clr.l d0 \n\t" - " move.l d0,__MBAR+0xF0C \n\t" /* Must use direct addressing. write to EPORT module */ + " .extern __MBAR \n\t" + " clr.l d0 \n\t" + " move.l d0,__MBAR+0xF0C \n\t" /* Must use direct addressing. write to EPORT module */ /* xlbus -> slavebus -> eport, writing '0' to register */ /* has no effect */ - " rts \n\t" - " tpf.l #0x0 \n\t" - " tpf.l #0x0 \n\t" - " tpf.l #0x0 \n\t" - " tpf.l #0x0 \n\t" - " tpf.l #0x0 \n\t" + " rts \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" ::: "memory"); } @@ -144,14 +144,14 @@ static inline void chip_errata_055(int32_t handle) return; /* test */ /* initiate PCI configuration access to device */ - MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ MCF_PCI_PCICAR_BUSNUM(3) | /* note: invalid bus number */ - MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ - MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ MCF_PCI_PCICAR_DWORD(0); /* issue a dummy read to an unsupported bus number (will fail) */ - dummy = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */ + dummy = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */ /* silently clear the PCI errors we produced just now */ MCF_PCI_PCIISR = 0xffffffff; /* clear all errors */ @@ -207,7 +207,7 @@ int32_t pci_call_interrupt_chain(int32_t handle, int32_t data) return 1; } } - return data; /* unmodified - means: not handled */ + return data; /* unmodified - means: not handled */ } #pragma GCC diagnostic pop @@ -321,12 +321,12 @@ uint32_t pci_read_config_longword(int32_t handle, int offset) MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ - MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ MCF_PCI_PCICAR_DWORD(offset / 4); NOP(); - value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */ + value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */ NOP(); @@ -345,7 +345,7 @@ uint16_t pci_read_config_word(int32_t handle, int offset) /* * initiate PCI configuration space access to device */ - MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration space special cycle */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration space special cycle */ MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | @@ -370,10 +370,10 @@ uint8_t pci_read_config_byte(int32_t handle, int offset) uint8_t value; /* initiate PCI configuration access to device */ - MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | - MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ - MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ MCF_PCI_PCICAR_DWORD(offset / 4); NOP(); @@ -397,15 +397,15 @@ uint8_t pci_read_config_byte(int32_t handle, int offset) int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value) { /* initiate PCI configuration access to device */ - MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | - MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ - MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ MCF_PCI_PCICAR_DWORD(offset / 4); NOP(); - * (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */ + * (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */ chip_errata_135(); NOP(); @@ -424,7 +424,7 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value) int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value) { /* initiate PCI configuration access to device */ - MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | @@ -518,7 +518,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index) handle = PCI_HANDLE(bus, device, 0); value = pci_read_config_longword(handle, PCIIDR); - if (value != 0xffffffff) /* we have a device at this position */ + if (value != 0xffffffff) /* we have a device at this position */ { if (vendor_id == 0xffff || (PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id)) @@ -543,7 +543,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index) { handle = PCI_HANDLE(bus, device, function); value = pci_read_config_longword(handle, PCIIDR); - if (value != 0xffffffff) /* device found */ + if (value != 0xffffffff) /* device found */ { if (vendor_id == 0xffff || (PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id)) @@ -589,7 +589,7 @@ int32_t pci_find_classcode(uint32_t classcode, int index) value = pci_read_config_longword(handle, PCIIDR); - if (value != 0xffffffff) /* device found */ + if (value != 0xffffffff) /* device found */ { value = pci_read_config_longword(handle, PCICCR); @@ -618,7 +618,7 @@ int32_t pci_find_classcode(uint32_t classcode, int index) handle = PCI_HANDLE(bus, device, function); value = pci_read_config_longword(handle, PCIIDR); - if (value != 0xffffffff) /* device found */ + if (value != 0xffffffff) /* device found */ { value = pci_read_config_longword(handle, PCICCR); @@ -884,13 +884,13 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function) */ cr = swpw(pci_read_config_word(handle, PCICSR)); - cr &= ~3; /* disable device response to address */ + cr &= ~3; /* disable device response to address */ pci_write_config_word(handle, PCICSR, swpw(cr)); int barnum = 0; descriptors = resource_descriptors[index]; - for (i = 0; i < 6 * 4; i += 4) /* for all bars */ + for (i = 0; i < 6 * 4; i += 4) /* for all bars */ { /* * write all bits of BAR[i] @@ -902,7 +902,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function) */ address = swpl(pci_read_config_longword(handle, PCIBAR0 + i)); - if (address) /* is bar in use? */ + if (address) /* is bar in use? */ { /* * resource descriptor for this device @@ -1093,7 +1093,6 @@ void pci_scan(void) PCI_DEVICE_FROM_HANDLE(handle), PCI_FUNCTION_FROM_HANDLE(handle)); } - handle = pci_find_device(0x0, 0xFFFF, ++index); } xprintf("\r\n...finished\r\n"); @@ -1105,7 +1104,7 @@ void init_eport(void) /* configure IRQ1-7 pins on EPORT falling edge triggered */ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_FALLING) | MCF_EPORT_EPPAR_EPPA6(MCF_EPORT_EPPAR_FALLING) | -#if MACHINE_FIREBEE /* irq5 level triggered on FireBee */ +#if MACHINE_FIREBEE /* irq5 level triggered on FireBee */ MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_LEVEL) | #elif MACHINE_M5484LITE MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_FALLING) | @@ -1114,9 +1113,9 @@ void init_eport(void) MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_FALLING) | MCF_EPORT_EPPAR_EPPA2(MCF_EPORT_EPPAR_FALLING) | MCF_EPORT_EPPAR_EPPA1(MCF_EPORT_EPPAR_FALLING); - MCF_EPORT_EPDDR = 0; /* clear data direction register. All pins as input */ - MCF_EPORT_EPFR = -1; /* clear all EPORT interrupt flags */ - MCF_EPORT_EPIER = 0xfe; /* enable all EPORT interrupts (for now) */ + MCF_EPORT_EPDDR = 0; /* clear data direction register. All pins as input */ + MCF_EPORT_EPFR = -1; /* clear all EPORT interrupt flags */ + MCF_EPORT_EPIER = 0xfe; /* enable all EPORT interrupts (for now) */ } void init_xlbus_arbiter(void) @@ -1151,12 +1150,12 @@ void init_xlbus_arbiter(void) * M3 = PCI target interface */ - MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 | /* activate programmed priority for Coldfire core */ - MCF_XLB_XARB_PRIEN_M2 | /* activate programmed priority for Multichannel DMA */ - MCF_XLB_XARB_PRIEN_M3; /* activate programmed priority for PCI target interface */ - MCF_XLB_XARB_PRI = MCF_XLB_XARB_PRI_M0P(7) | /* Coldfire core gets lowest */ - MCF_XLB_XARB_PRI_M2P(5) | /* Multichannel DMA mid priority */ - MCF_XLB_XARB_PRI_M3P(3); /* PCI target interface is highest priority */ + MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 | /* activate programmed priority for Coldfire core */ + MCF_XLB_XARB_PRIEN_M2 | /* activate programmed priority for Multichannel DMA */ + MCF_XLB_XARB_PRIEN_M3; /* activate programmed priority for PCI target interface */ + MCF_XLB_XARB_PRI = MCF_XLB_XARB_PRI_M0P(7) | /* Coldfire core gets lowest */ + MCF_XLB_XARB_PRI_M2P(5) | /* Multichannel DMA mid priority */ + MCF_XLB_XARB_PRI_M3P(3); /* PCI target interface is highest priority */ } void init_pci(void) @@ -1170,15 +1169,15 @@ void init_pci(void) init_eport(); init_xlbus_arbiter(); - MCF_PCI_PCIGSCR = 1; /* reset PCI */ + MCF_PCI_PCIGSCR = 1; /* reset PCI */ /* * setup the PCI arbiter */ - MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI /* internal master priority: high */ - | MCF_PCIARB_PACR_EXTMPRI(0xf) /* external master priority: high */ - | MCF_PCIARB_PACR_INTMINTEN /* enable "internal master broken" interrupt */ - | MCF_PCIARB_PACR_EXTMINTEN(0x0f); /* enable "external master broken" interrupt */ + MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI /* internal master priority: high */ + | MCF_PCIARB_PACR_EXTMPRI(0xf) /* external master priority: high */ + | MCF_PCIARB_PACR_INTMINTEN /* enable "internal master broken" interrupt */ + | MCF_PCIARB_PACR_EXTMINTEN(0x0f); /* enable "external master broken" interrupt */ #if defined(MACHINE_FIREBEE) MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST | @@ -1197,10 +1196,10 @@ void init_pci(void) #endif /* MACHINE_FIREBEE */ MCF_PCI_PCISCR = MCF_PCI_PCISCR_M | /* memory access control enabled */ - MCF_PCI_PCISCR_B | /* bus master enabled */ - MCF_PCI_PCISCR_M | /* mem access enable */ - MCF_PCI_PCISCR_MA | /* clear master abort error */ - MCF_PCI_PCISCR_MW; /* memory write and invalidate enabled */ + MCF_PCI_PCISCR_B | /* bus master enabled */ + MCF_PCI_PCISCR_M | /* mem access enable */ + MCF_PCI_PCISCR_MA | /* clear master abort error */ + MCF_PCI_PCISCR_MW; /* memory write and invalidate enabled */ /* Setup burst parameters */ @@ -1210,16 +1209,16 @@ void init_pci(void) MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(1) | MCF_PCI_PCICR2_MAXLAT(32); - // MCF_PCI_PCICR2 = 0; /* this is what Linux does */ + // MCF_PCI_PCICR2 = 0; /* this is what Linux does */ /* error signaling */ - MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE | /* target abort enable */ - MCF_PCI_PCIICR_IAE; /* initiator abort enable */ + MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE | /* target abort enable */ + MCF_PCI_PCIICR_IAE; /* initiator abort enable */ - // MCF_PCI_PCIICR = 0; /* this is what Linux does */ + // MCF_PCI_PCIICR = 0; /* this is what Linux does */ - MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; /* system error interrupt enable */ + MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; /* system error interrupt enable */ /* Configure Initiator Windows */ @@ -1246,9 +1245,9 @@ void init_pci(void) * Initialize target control register. * Used when an external bus master accesses the Coldfire PCI as target */ - MCF_PCI_PCIBAR0 = 0x40000000; /* 256 kB window */ - MCF_PCI_PCITBATR0 = (uint32_t) &_MBAR[0] | MCF_PCI_PCITBATR0_EN; /* target base address translation register 0 */ - MCF_PCI_PCIBAR1 = 0; /* 1GB window */ + MCF_PCI_PCIBAR0 = 0x40000000; /* 256 kB window */ + MCF_PCI_PCITBATR0 = (uint32_t) &_MBAR[0] | MCF_PCI_PCITBATR0_EN; /* target base address translation register 0 */ + MCF_PCI_PCIBAR1 = 0; /* 1GB window */ MCF_PCI_PCITBATR1 = MCF_PCI_PCITBATR1_EN; /* reset PCI devices */ diff --git a/BaS_gcc/sys/BaS.c b/BaS_gcc/sys/BaS.c index bb554d7..9143f82 100644 --- a/BaS_gcc/sys/BaS.c +++ b/BaS_gcc/sys/BaS.c @@ -231,7 +231,7 @@ void enable_coldfire_interrupts() MCF_GPT_GMS_IEN | MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */ MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) | - MCF_INTC_ICR_IP(7); /* interrupt level 7, interrupt priority 7 */ + MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */ MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ @@ -282,29 +282,27 @@ void init_isr(void) */ if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1)) { - dbg("unable to register isr for FEC0\r\n"); - return; + err("unable to register isr for FEC0\r\n"); } /* * Register the DMA interrupt handler */ - if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL)) + if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL, NULL)) { - dbg("Error: Unable to register isr for DMA\r\n"); - return; + err("Error: Unable to register isr for DMA\r\n"); } - dma_irq_enable(5, 3); /* TODO: need to match the FEC driver's specs in MiNT? */ + dma_irq_enable(7, 7); /* TODO: need to match the FEC driver's specs in MiNT? */ +#ifdef _NOT_USED_ /* * register the PIC interrupt handler */ - if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL)) + if (!isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL)) { - dbg("Error: unable to register ISR for PSC3\r\n"); - return; + err("Error: unable to register ISR for PSC3\r\n"); } /* @@ -312,15 +310,16 @@ void init_isr(void) */ if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, xlbpci_interrupt_handler, NULL, NULL)) { - dbg("Error: unable to register isr for XLB PCI interrupts\r\n"); - return; + err("Error: unable to register isr for XLB PCI interrupts\r\n"); } - MCF_INTC_ICR43 = MCF_INTC_ICR_IL(5) | /* level 5, priority 1 */ - MCF_INTC_ICR_IP(1); + + MCF_INTC_ICR43 = MCF_INTC_ICR_IL(7) | /* level 7, priority 6 */ + MCF_INTC_ICR_IP(6); + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK43; /* enable XLB PCI interrupts in DMA controller */ MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */ - MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */ - MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */ + MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */ + MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */ MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */ MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */ MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */ @@ -328,15 +327,17 @@ void init_isr(void) if (!isr_register_handler(64 + INT_SOURCE_PCIARB, pciarb_interrupt_handler, NULL, NULL)) { - dbg("Error: unable to register isr for PCIARB interrupts\r\n"); + err("Error: unable to register isr for PCIARB interrupts\r\n"); return; } - MCF_INTC_ICR41 = MCF_INTC_ICR_IL(5) | /* level 5, priority 0 */ - MCF_INTC_ICR_IP(0); + MCF_INTC_ICR41 = MCF_INTC_ICR_IL(7) | /* level 5, priority 0 */ + MCF_INTC_ICR_IP(5); + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK41; /* enable PCIARB interrupts in DMA controller */ MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */ - MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */ + MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */ +#endif /* _NOT_USED_ */ } void BaS(void) @@ -349,6 +350,10 @@ void BaS(void) nvram_init(); #endif /* MACHINE_FIREBEE */ + xprintf("initialize MMU: "); + mmu_init(); + xprintf("finished\r\n"); + xprintf("copy EmuTOS: "); /* copy EMUTOS */ @@ -356,10 +361,6 @@ void BaS(void) dma_memcpy(dst, src, EMUTOS_SIZE); xprintf("finished\r\n"); - xprintf("initialize MMU: "); - mmu_init(); - xprintf("finished\r\n"); - xprintf("initialize exception vector table: "); vec_init(); xprintf("finished\r\n"); @@ -440,14 +441,13 @@ void BaS(void) xprintf("BaS initialization finished, enable interrupts\r\n"); init_isr(); enable_coldfire_interrupts(); - init_pci(); - video_init(); - set_ipl(0); /* enable interrupts */ + //init_pci(); + // video_init(); /* initialize USB devices */ - init_usb(); + //init_usb(); - //set_ipl(7); /* disable interrupts */ + set_ipl(7); /* disable interrupts */ xprintf("call EmuTOS\r\n"); struct rom_header *os_header = (struct rom_header *) TOS; diff --git a/BaS_gcc/sys/exceptions.S b/BaS_gcc/sys/exceptions.S index b6a2af7..1090077 100644 --- a/BaS_gcc/sys/exceptions.S +++ b/BaS_gcc/sys/exceptions.S @@ -190,7 +190,7 @@ init_vec_loop: lea _get_bas_drivers(pc),a1 move.l a1,0x80(a0) // trap #0 exception vector -// MFP non-autovector interrupt handlers. Those are rerouted to their autovector counterparts +// MFP non-autovector interrupt handlers. Those are just rerouted to their autovector counterparts lea irq1(pc),a1 move.l a1,0x104(a0) @@ -451,13 +451,13 @@ irq6: move.w #0x2700,sr // disable interrupt rte irq6_forward: - move.l 0xf0020000,a0 // fetch "MFP interrupt vector from FPGA" + move.l 0xf0020000,a0 // fetch "MFP interrupt vector" from FPGA add.l _rt_vbr,a0 // add runtime VBR - move.l (a0),8(a6) // fetch handler address and put it on "extra space" + move.l (a0),4(a6) // fetch handler address and put it on "extra space" movem.l (sp),d0-d1/a0-a1 unlk a6 - move.w #0x2600,sr // set interrupt level + move.w #0x2600,sr // set interrupt mask to MFP level rts // jump through vector diff --git a/BaS_gcc/sys/fault_vectors.c b/BaS_gcc/sys/fault_vectors.c index 44c5e6f..702cbdd 100644 --- a/BaS_gcc/sys/fault_vectors.c +++ b/BaS_gcc/sys/fault_vectors.c @@ -30,173 +30,173 @@ extern exception_handler SDRAM_VECTOR_TABLE[]; */ void fault_handler(uint32_t pc, uint32_t format_status) { - int format; - int fault_status; - int vector; - int sr; + int format; + int fault_status; + int vector; + int sr; - xprintf("\007\007exception! Processor halted.\r\n"); - xprintf("format_status: %lx\r\n", format_status); - xprintf("pc: %lx\r\n", pc); + xprintf("\007\007exception! Processor halted.\r\n"); + xprintf("format_status: %lx\r\n", format_status); + xprintf("pc: %lx\r\n", pc); - /* - * extract info from format-/status word - */ - format = (format_status & 0b11110000000000000000000000000000) >> 28; - fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) | - ((format_status & 0b00000000000000110000000000000000) >> 16); - vector = (format_status & 0b00000011111111000000000000000000) >> 18; - sr = (format_status & 0b00000000000000001111111111111111); + /* + * extract info from format-/status word + */ + format = (format_status & 0b11110000000000000000000000000000) >> 28; + fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) | + ((format_status & 0b00000000000000110000000000000000) >> 16); + vector = (format_status & 0b00000011111111000000000000000000) >> 18; + sr = (format_status & 0b00000000000000001111111111111111); - xprintf("format: %x\r\n", format); - xprintf("fault_status: %x (", fault_status); - switch (fault_status) - { - case 0: - xprintf("not an access or address error nor an interrupted debug service routine"); - break; - case 1: - case 3: - case 11: - xprintf("reserved"); - break; - case 2: - xprintf("interrupt during a debug service routine for faults other than access errors"); - break; - case 4: - xprintf("error (for example, protection fault) on instruction fetch"); - break; - case 5: - xprintf("TLB miss on opword or instruction fetch"); - break; - case 6: - xprintf("TLB miss on extension word of instruction fetch"); - break; - case 7: - xprintf("IFP access error while executing in emulator mode"); - break; - case 8: - xprintf("error on data write"); - break; - case 9: - xprintf("error on attempted write to write-protected space"); - break; - case 10: - xprintf("TLB miss on data write"); - break; - case 12: - xprintf("error on data read"); - break; - case 13: - xprintf("attempted read, read-modify-write of protected space"); - break; - case 14: - xprintf("TLB miss on data read or read-modify-write"); - break; - case 15: - xprintf("OEP access error while executing in emulator mode"); - } - xprintf(")\r\n"); + xprintf("format: %x\r\n", format); + xprintf("fault_status: %x (", fault_status); + switch (fault_status) + { + case 0: + xprintf("not an access or address error nor an interrupted debug service routine"); + break; + case 1: + case 3: + case 11: + xprintf("reserved"); + break; + case 2: + xprintf("interrupt during a debug service routine for faults other than access errors"); + break; + case 4: + xprintf("error (for example, protection fault) on instruction fetch"); + break; + case 5: + xprintf("TLB miss on opword or instruction fetch"); + break; + case 6: + xprintf("TLB miss on extension word of instruction fetch"); + break; + case 7: + xprintf("IFP access error while executing in emulator mode"); + break; + case 8: + xprintf("error on data write"); + break; + case 9: + xprintf("error on attempted write to write-protected space"); + break; + case 10: + xprintf("TLB miss on data write"); + break; + case 12: + xprintf("error on data read"); + break; + case 13: + xprintf("attempted read, read-modify-write of protected space"); + break; + case 14: + xprintf("TLB miss on data read or read-modify-write"); + break; + case 15: + xprintf("OEP access error while executing in emulator mode"); + } + xprintf(")\r\n"); - xprintf("vector = %02x (", vector); - switch (vector) - { - case 2: - xprintf("access error"); - break; - case 3: - xprintf("address error"); - break; - case 4: - xprintf("illegal instruction"); - break; - case 5: - xprintf("divide by zero"); - break; - case 8: - xprintf("privilege violation"); - break; - case 9: - xprintf("trace"); - break; - case 10: - xprintf("unimplemented line-a opcode"); - break; - case 11: - xprintf("unimplemented line-f opcode"); - break; - case 12: - xprintf("non-PC breakpoint debug interrupt"); - break; - case 13: - xprintf("PC breakpoint debug interrupt"); - break; - case 14: - xprintf("format error"); - break; - case 24: - xprintf("spurious interrupt"); - break; - default: - if ( ((fault_status >= 6) && (fault_status <= 7)) || - ((fault_status >= 16) && (fault_status <= 23))) - { - xprintf("reserved"); - } - else if ((fault_status >= 25) && (fault_status <= 31)) - { - xprintf("level %d autovectored interrupt", fault_status - 24); - } - else if ((fault_status >= 32) && (fault_status <= 47)) - { - xprintf("trap #%d", fault_status - 32); - } - else - { - xprintf("unknown fault status"); - } - } - xprintf(")\r\n"); - xprintf("sr=%4x\r\n", sr); + xprintf("vector = %02x (", vector); + switch (vector) + { + case 2: + xprintf("access error"); + break; + case 3: + xprintf("address error"); + break; + case 4: + xprintf("illegal instruction"); + break; + case 5: + xprintf("divide by zero"); + break; + case 8: + xprintf("privilege violation"); + break; + case 9: + xprintf("trace"); + break; + case 10: + xprintf("unimplemented line-a opcode"); + break; + case 11: + xprintf("unimplemented line-f opcode"); + break; + case 12: + xprintf("non-PC breakpoint debug interrupt"); + break; + case 13: + xprintf("PC breakpoint debug interrupt"); + break; + case 14: + xprintf("format error"); + break; + case 24: + xprintf("spurious interrupt"); + break; + default: + if ( ((vector >= 6) && (vector <= 7)) || + ((vector >= 16) && (vector <= 23))) + { + xprintf("reserved"); + } + else if ((vector >= 25) && (vector <= 31)) + { + xprintf("level %d autovectored interrupt", fault_status - 24); + } + else if ((vector >= 32) && (vector <= 47)) + { + xprintf("trap #%d", vector - 32); + } + else + { + xprintf("unknown vector\r\n"); + } + } + xprintf(")\r\n"); + xprintf("sr=%4x\r\n", sr); } void __attribute__((interrupt)) handler(void) { - /* - * Prepare exception stack contents so it can be handled by a C routine. - * - * For standard routines, we'd have to save registers here. - * Since we do not intend to return anyway, we just ignore that requirement. - */ - __asm__ __volatile__("move.l (sp),-(sp)\n\t"\ - "move.l 8(sp),-(sp)\n\t"\ - "bsr _fault_handler\n\t"\ - "halt\n\t"\ - : : : "memory"); + /* + * Prepare exception stack contents so it can be handled by a C routine. + * + * For standard routines, we'd have to save registers here. + * Since we do not intend to return anyway, we just ignore that requirement. + */ + __asm__ __volatile__("move.l (sp),-(sp)\n\t"\ + "move.l 8(sp),-(sp)\n\t"\ + "bsr _fault_handler\n\t"\ + "halt\n\t"\ + : : : "memory"); } void setup_vectors(void) { - int i; + int i; - xprintf("\r\ninstall early exception vector table:"); + xprintf("\r\ninstall early exception vector table:"); - for (i = 8; i < 256; i++) - { - SDRAM_VECTOR_TABLE[i] = &handler; - } + for (i = 8; i < 256; i++) + { + SDRAM_VECTOR_TABLE[i] = &handler; + } - /* - * make sure VBR points to our table - */ - __asm__ __volatile__("clr.l d0\n\t"\ - "movec.l d0,VBR\n\t"\ - "nop\n\t"\ - "move.l d0,_rt_vbr" + /* + * make sure VBR points to our table + */ + __asm__ __volatile__("clr.l d0\n\t"\ + "movec.l d0,VBR\n\t"\ + "nop\n\t"\ + "move.l d0,_rt_vbr" : /* outputs */ : /* inputs */ : "d0", "memory", "cc" /* clobbered registers */ ); - xprintf("finished.\r\n"); + xprintf("finished.\r\n"); } diff --git a/BaS_gcc/sys/interrupts.c b/BaS_gcc/sys/interrupts.c index 84e05d5..0a4e350 100644 --- a/BaS_gcc/sys/interrupts.c +++ b/BaS_gcc/sys/interrupts.c @@ -38,7 +38,7 @@ #include "pci.h" extern void (*rt_vbr[])(void); -#define VBR rt_vbr +#define VBR rt_vbr #define IRQ_DEBUG #if defined(IRQ_DEBUG) @@ -145,6 +145,8 @@ bool isr_execute_handler(int vector) int index; bool retval = false; + dbg("vector = 0x%x\r\n", vector); + /* * locate an Interrupt Service Routine handler. */ @@ -176,7 +178,7 @@ int pic_interrupt_handler(void *arg1, void *arg2) uint8_t rcv_byte; rcv_byte = MCF_PSC3_PSCRB_8BIT; - if (rcv_byte == 2) // PIC requests RTC data + if (rcv_byte == 2) // PIC requests RTC data { uint8_t *rtc_reg = (uint8_t *) 0xffff8961; uint8_t *rtc_data = (uint8_t *) 0xffff8963; @@ -184,7 +186,7 @@ int pic_interrupt_handler(void *arg1, void *arg2) err("PIC interrupt: requesting RTC data\r\n"); - MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC + MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC do { *rtc_reg = 0; @@ -312,8 +314,8 @@ bool irq6_handler(uint32_t sf1, uint32_t sf2) { bool handled = false; - err("IRQ6!\r\n"); - MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */ + // err("IRQ6!\r\n"); + MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */ if (FALCON_MFP_IPRA || FALCON_MFP_IPRB) { @@ -377,7 +379,9 @@ void irq7_handler(void) */ void gpt0_interrupt_handler(void) { - MCF_GPT0_GMS &= ~1; /* rearm trigger */ + dbg("handler called\n\r"); + + MCF_GPT0_GMS &= ~1; /* rearm trigger */ NOP(); MCF_GPT0_GMS |= 1; } diff --git a/BaS_gcc/sys/sysinit.c b/BaS_gcc/sys/sysinit.c index b5b1640..afec9dd 100644 --- a/BaS_gcc/sys/sysinit.c +++ b/BaS_gcc/sys/sysinit.c @@ -267,7 +267,8 @@ void init_serial(void) MCF_PSC3_PSCCR = 0x05; #endif /* MACHINE_FIREBEE */ - MCF_INTC_ICR32 = 0x3F; /* PSC3 interrupt vector. Do we need it? */ + MCF_INTC_ICR32 = MCF_INTC_ICR_IL(7) | + MCF_INTC_ICR_IL(4); /* PSC3 interrupt vector. Do we need it? */ xprintf("\r\nserial interfaces initialization: finished\r\n"); } @@ -645,7 +646,7 @@ static bool i2c_transfer_finished(void) static void wait_i2c_transfer_finished(void) { - waitfor(10000, i2c_transfer_finished); /* wait until interrupt bit has been set */ + waitfor(1000, i2c_transfer_finished); /* wait until interrupt bit has been set */ MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF; /* clear interrupt bit (byte transfer finished */ } @@ -660,7 +661,7 @@ static bool i2c_bus_free(void) void dvi_on(void) { uint8_t receivedByte; - uint8_t dummyByte; /* only used for a dummy read */ + uint8_t dummyByte; /* only used for a dummy read */ int num_tries = 0; xprintf("DVI digital video output initialization: "); @@ -678,11 +679,12 @@ void dvi_on(void) /* repeat start, transmit acknowledge */ MCF_I2C_I2CR = MCF_I2C_I2CR_RSTA | MCF_I2C_I2CR_TXAK; - receivedByte = MCF_I2C_I2DR; /* read a byte */ - MCF_I2C_I2SR = 0x0; /* clear status register */ - MCF_I2C_I2CR = 0x0; /* disable i2c */ + receivedByte = MCF_I2C_I2DR; /* read a byte */ + MCF_I2C_I2SR = 0x0; /* clear status register */ + MCF_I2C_I2CR = 0x0; /* clear control register */ + + MCF_I2C_I2ICR = MCF_I2C_I2ICR_IE; /* route i2c interrupts to cpu */ - MCF_I2C_I2ICR = MCF_I2C_I2ICR_IE; /* route i2c interrupts to cpu */ /* i2c enable, master mode, transmit acknowledge */ MCF_I2C_I2CR = MCF_I2C_I2CR_IEN | MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX; @@ -1111,13 +1113,6 @@ void initialize_hardware(void) #endif /* MACHINE_FIREBEE */ driver_mem_init(); - init_pci(); - video_init(); - - /* do not try to init USB for now on the Firebee, it hangs the machine */ -#ifndef MACHINE_FIREBEE - //init_usb(); -#endif #if MACHINE_FIREBEE init_ac97();