deleted cfg directory which is not needed for gcc
This commit is contained in:
Markus Fröschle
@@ -1,57 +0,0 @@
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; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
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; $RCSfile: M5475EVB.cfg,v $
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; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
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; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
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ResetHalt
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;Set VBR - debugger must know this in order
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; to do exception capture
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writecontrolreg 0x0801 0x00000000
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; If MBAR changes all following writes must change
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; and if a memory configuration file is used,
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; the reserved areas in the register block must
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; change also.
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;Turn on MBAR at 0xFF00_0000
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writecontrolreg 0x0C0F 0xFF000000
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;Turn on RAMBAR0 at address FF10_0000
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writecontrolreg 0x0C04 0xFF100035
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;Turn on RAMBAR1 at address FF10_1000
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writecontrolreg 0x0C05 0xFF101035
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;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
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writemem.l 0xFF000500 0xE0000000;
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writemem.l 0xFF000508 0x00101980; 16-bit port
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writemem.l 0xFF000504 0x007F0001;
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;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
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writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration
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writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
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writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
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writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
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writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
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;writemem.l 0xFF000108 0x73611730; SDCFG1
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writemem.l 0xFF000108 0x53611730; SDCFG1
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;writemem.l 0xFF00010C 0x46770000; SDCFG2
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writemem.l 0xFF00010C 0x24730000; SDCFG2
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;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL
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writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
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writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR)
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;writemem.l 0xFF000100 0x048D0000; SDMR (write to LMR)
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writemem.l 0xFF000100 0x04890000; SDMR (write to LMR)
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;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL
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writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
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;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (first refresh)
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writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
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;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (second refresh)
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writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
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;writemem.l 0xFF000100 0x008D0000; SDMR (write to LMR)
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writemem.l 0xFF000100 0x00890000; SDMR (write to LMR)
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;writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh)
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writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh)
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delay 1000
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@@ -1,47 +0,0 @@
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// Memory Configuration File
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//
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// Description:
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// A memory configuration file contains commands that define the legally accessible
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// areas of memory for your specific board. Useful for example when the debugger
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// tries to display the content of a "char *" variable, that has not yet been initialized.
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// In this case the debugger may try to read from a bogus address, which could cause a
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// bus error.
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//
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// Board:
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// LogicPD COLDARI1
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//
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// Reference:
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// MCF5475RM.pdf
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// All reserved ranges read back 0xBABA...
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reservedchar 0xBA
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address MBAR_BASE 0xFF000000
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address MMUBAR_BASE 0xFF040000
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usederivative "MCF5475"
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// Memory Map:
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// ----------------------------------------------------------------------
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range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM
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reserved 0x20000000 0x5FFFFFFF
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range 0x60000000 0x7FFFFFFF 4 ReadWrite
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range 0x80000000 0xCFFFFFFF 4 ReadWrite
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range 0xD0000000 0xFBFFFFFF 4 ReadWrite
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reserved 0xFC000000 $MBAR_BASE-1
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$MBAR_BASE $MBAR_BASE+0x3FFFF // Memory Mapped Registers
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range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM
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range $MMUBAR_BASE $MMUBAR_BASE+0xFFFF
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reserved $MMUBAR_BASE+1x0000 0xFF0FFFFF // Added to fill gap in MMR
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range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0)
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range 0xFF101000 0xFFFFFFFF 4 ReadWrite // 4K SRAM1 (RAMBAR1)
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@@ -1,11 +0,0 @@
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; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
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; $RCSfile: M5475EVB.cfg,v $
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; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
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; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
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;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes)
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writemem.l 0xFF000500 0xFE000000;
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writemem.l 0xFF000508 0x00101980; 16-bit port
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writemem.l 0xFF000504 0x007F0001;
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@@ -1,48 +0,0 @@
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; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
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; $RCSfile: M5475EVB.cfg,v $
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; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
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; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
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ResetHalt
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;Set VBR - debugger must know this in order
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; to do exception capture
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writecontrolreg 0x0801 0x00000000
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; If MBAR changes all following writes must change
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; and if a memory configuration file is used,
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; the reserved areas in the register block must
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; change also.
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;Turn on MBAR at 0xFF00_0000
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writecontrolreg 0x0C0F 0xFF000000
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;Turn on RAMBAR0 at address FF10_0000
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writecontrolreg 0x0C04 0xFF100035
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;Turn on RAMBAR1 at address FF10_1000
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writecontrolreg 0x0C05 0xFF101035
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;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
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writemem.l 0xFF000500 0xE0000000;
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writemem.l 0xFF000508 0x00001180; 16-bit port
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writemem.l 0xFF000504 0x007F0001;
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;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
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writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration
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writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
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writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
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writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
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writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
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writemem.l 0xFF000108 0x53722938; SDCFG1
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writemem.l 0xFF00010C 0x24330000; SDCFG2
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writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
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writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR)
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writemem.l 0xFF000100 0x05890000; SDRM (write to LMR)
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writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
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writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
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writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (second refresh)
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writemem.l 0xFF000100 0x01890000; SDMR (write to LMR)
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writemem.l 0xFF000104 0x710F0F00; SDCR (lock SDMR and enable refresh)
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delay 1000
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@@ -1,38 +0,0 @@
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// Memory Configuration File
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//
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// Description:
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// A memory configuration file contains commands that define the legally accessible
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// areas of memory for your specific board. Useful for example when the debugger
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// tries to display the content of a "char *" variable, that has not yet been initialized.
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// In this case the debugger may try to read from a bogus address, which could cause a
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// bus error.
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//
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// Board:
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// LogicPD COLDARI1
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//
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// Reference:
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// MCF5475RM.pdf
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// All reserved ranges read back 0xBABA...
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reservedchar 0xBA
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address MBAR_BASE 0xFF000000
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address MMUBAR_BASE 0xFF040000
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usederivative "MCF5475"
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// Memory Map:
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// ----------------------------------------------------------------------
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range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM
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reserved 0x20000000 $MBAR_BASE-1
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$MBAR_BASE $MBAR_BASE+0x3FFFF 4 ReadWrite // Memory Mapped Registers
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range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM
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reserved $MBAR_BASE+0x17FFD $MBAR_BASE+0x1FFBF
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$MMUBAR_BASE $MMUBAR_BASE+0x001B
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reserved $MMUBAR_BASE+0x001C 0xFF0FFFFF
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range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0)
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range 0xFF101000 0xFF101FFF 4 ReadWrite // 4K SRAM1 (RAMBAR1)
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Block a user