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tried less restrictive option to speed up synthesis

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Markus Fröschle
2014-06-10 06:52:16 +00:00
parent 3b6fc36db1
commit 2c29f6a232
2 changed files with 33 additions and 34 deletions
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2
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -48,7 +48,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

65
vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd
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@@ -50,44 +50,43 @@ use ieee.numeric_std.all;
entity FBEE_BLITTER is entity FBEE_BLITTER is
port( port(
RESETn : in std_logic; RESETn : in std_logic;
CLK_MAIN : in std_logic; CLK_MAIN : in std_logic;
CLK_DDR0 : in std_logic; CLK_DDR0 : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0); FB_ADR : in std_logic_vector(31 downto 0);
FB_ALE : in std_logic; FB_ALE : in std_logic;
FB_SIZE1 : in std_logic; FB_SIZE1 : in std_logic;
FB_SIZE0 : in std_logic; FB_SIZE0 : in std_logic;
FB_CSn : in std_logic_vector(3 downto 1); FB_CSn : in std_logic_vector(3 downto 1);
FB_OEn : in std_logic; FB_OEn : in std_logic;
FB_WRn : in std_logic; FB_WRn : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0); DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0); DATA_OUT : out std_logic_vector(31 downto 0);
DATA_EN : out std_logic; DATA_EN : out std_logic;
BLITTER_ON : in std_logic; BLITTER_ON : in std_logic;
BLITTER_DIN : in std_logic_vector(127 downto 0); BLITTER_DIN : in std_logic_vector(127 downto 0);
BLITTER_DACK_SR : in std_logic; BLITTER_DACK_SR : in std_logic;
BLITTER_RUN : out std_logic; BLITTER_RUN : out std_logic;
BLITTER_DOUT : out std_logic_vector(127 downto 0); BLITTER_DOUT : out std_logic_vector(127 downto 0);
BLITTER_ADR : out std_logic_vector(31 downto 0); BLITTER_ADR : out std_logic_vector(31 downto 0);
BLITTER_SIG : out std_logic; BLITTER_SIG : out std_logic;
BLITTER_WR : out std_logic; BLITTER_WR : out std_logic;
BLITTER_TA : out std_logic BLITTER_TA : out std_logic
); );
end entity FBEE_BLITTER; end entity FBEE_BLITTER;
architecture BEHAVIOUR of FBEE_BLITTER is architecture BEHAVIOUR of FBEE_BLITTER is
signal BLITTER_DACK : std_logic_vector(4 downto 0); signal BLITTER_DACK : std_logic_vector(4 downto 0);
signal BLITTER_DIN_I : std_logic_vector(127 downto 0); signal BLITTER_DIN_I : std_logic_vector(127 downto 0);
begin begin
P_BLITTER_DACK: process
P_BLITTER_DACK: process begin
begin wait until CLK_DDR0 = '1' and CLK_DDR0' event;
wait until CLK_DDR0 = '1' and CLK_DDR0' event; BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 downto 1);
BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 downto 1); if BLITTER_DACK(0) = '1' then
if BLITTER_DACK(0) = '1' then BLITTER_DIN_I <= BLITTER_DIN;
BLITTER_DIN_I <= BLITTER_DIN; end if;
end if; end process P_BLITTER_DACK;
end process P_BLITTER_DACK;
BLITTER_RUN <= '0'; BLITTER_RUN <= '0';