From 2c29f6a232d0ef8c0b0bdde18d0de2bcfd35f1bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 10 Jun 2014 06:52:16 +0000 Subject: [PATCH] tried less restrictive option to speed up synthesis --- vhdl/backend/Altera/Firebee/firebee.qsf | 2 +- vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd | 65 ++++++++++++------------- 2 files changed, 33 insertions(+), 34 deletions(-) diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index 9534b16..099a825 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -48,7 +48,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top diff --git a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd index c7274f2..fee6e65 100644 --- a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd +++ b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd @@ -50,44 +50,43 @@ use ieee.numeric_std.all; entity FBEE_BLITTER is port( - RESETn : in std_logic; - CLK_MAIN : in std_logic; - CLK_DDR0 : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - FB_ALE : in std_logic; - FB_SIZE1 : in std_logic; - FB_SIZE0 : in std_logic; - FB_CSn : in std_logic_vector(3 downto 1); - FB_OEn : in std_logic; - FB_WRn : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_EN : out std_logic; - BLITTER_ON : in std_logic; - BLITTER_DIN : in std_logic_vector(127 downto 0); - BLITTER_DACK_SR : in std_logic; - BLITTER_RUN : out std_logic; - BLITTER_DOUT : out std_logic_vector(127 downto 0); - BLITTER_ADR : out std_logic_vector(31 downto 0); - BLITTER_SIG : out std_logic; - BLITTER_WR : out std_logic; - BLITTER_TA : out std_logic + RESETn : in std_logic; + CLK_MAIN : in std_logic; + CLK_DDR0 : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + FB_ALE : in std_logic; + FB_SIZE1 : in std_logic; + FB_SIZE0 : in std_logic; + FB_CSn : in std_logic_vector(3 downto 1); + FB_OEn : in std_logic; + FB_WRn : in std_logic; + DATA_IN : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_EN : out std_logic; + BLITTER_ON : in std_logic; + BLITTER_DIN : in std_logic_vector(127 downto 0); + BLITTER_DACK_SR : in std_logic; + BLITTER_RUN : out std_logic; + BLITTER_DOUT : out std_logic_vector(127 downto 0); + BLITTER_ADR : out std_logic_vector(31 downto 0); + BLITTER_SIG : out std_logic; + BLITTER_WR : out std_logic; + BLITTER_TA : out std_logic ); end entity FBEE_BLITTER; architecture BEHAVIOUR of FBEE_BLITTER is -signal BLITTER_DACK : std_logic_vector(4 downto 0); -signal BLITTER_DIN_I : std_logic_vector(127 downto 0); + signal BLITTER_DACK : std_logic_vector(4 downto 0); + signal BLITTER_DIN_I : std_logic_vector(127 downto 0); begin - - P_BLITTER_DACK: process - begin - wait until CLK_DDR0 = '1' and CLK_DDR0' event; - BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 downto 1); - if BLITTER_DACK(0) = '1' then - BLITTER_DIN_I <= BLITTER_DIN; - end if; - end process P_BLITTER_DACK; + P_BLITTER_DACK: process + begin + wait until CLK_DDR0 = '1' and CLK_DDR0' event; + BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 downto 1); + if BLITTER_DACK(0) = '1' then + BLITTER_DIN_I <= BLITTER_DIN; + end if; + end process P_BLITTER_DACK; BLITTER_RUN <= '0';