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tried less restrictive option to speed up synthesis

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Markus Fröschle
2014-06-10 06:52:16 +00:00
parent 3b6fc36db1
commit 2c29f6a232
2 changed files with 33 additions and 34 deletions
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2
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -48,7 +48,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

1
vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd
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@@ -79,7 +79,6 @@ architecture BEHAVIOUR of FBEE_BLITTER is
signal BLITTER_DACK : std_logic_vector(4 downto 0); signal BLITTER_DACK : std_logic_vector(4 downto 0);
signal BLITTER_DIN_I : std_logic_vector(127 downto 0); signal BLITTER_DIN_I : std_logic_vector(127 downto 0);
begin begin
P_BLITTER_DACK: process P_BLITTER_DACK: process
begin begin
wait until CLK_DDR0 = '1' and CLK_DDR0' event; wait until CLK_DDR0 = '1' and CLK_DDR0' event;