fixed a bug in wiring of I_RECONFIG (data_in was connected to FB_ADR(24 downto 16) instead ot FB_AD(24 downto 16) and reformatted files

vhdl/backend/Altera/Firebee/firebee.sdc

@@ -17,9 +17,9 @@
 
 ## VENDOR  "Altera"
 ## PROGRAM "Quartus II"
-## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
-## DATE    "Mon Jun  9 15:23:23 2014"
+## DATE    "Fri Aug  8 11:08:03 2014"
 
 ##
 ## DEVICE  "EP3C40F484C6"
@@ -71,110 +71,12 @@ create_generated_clock -name {altpll4:I_PLL4|altpll:altpll_component|altpll4_alt
 # Set Clock Uncertainty
 #**************************************************************
 
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
@@ -183,12 +85,12 @@ set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.070  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.070  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
@@ -197,20 +99,6 @@ set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.070  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.070  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -219,14 +107,14 @@ set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -235,22 +123,30 @@ set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -263,14 +159,6 @@ set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -279,14 +167,14 @@ set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -295,6 +183,16 @@ set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -303,8 +201,8 @@ set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -313,8 +211,12 @@ set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -323,12 +225,12 @@ set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -hold 0.080  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -337,12 +239,8 @@ set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -351,8 +249,8 @@ set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -361,8 +259,6 @@ set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
@@ -387,6 +283,110 @@ set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.100  
 
 
 #**************************************************************
@@ -835,12 +835,7 @@ set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}]  5.000 [get_ports
 # Set False Path
 #**************************************************************
 
-set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
-set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
-set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
-set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
 set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
-set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]
 set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]
 
 

vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd

@@ -156,8 +156,8 @@ architecture BEHAVIOUR of VIDEO_CTRL is
 	signal VERZ_2                   : std_logic_vector(9 downto 0);
 	signal VERZ_1                   : std_logic_vector(9 downto 0);
 	signal VERZ_0                   : std_logic_vector(9 downto 0);
-	signal RAND                     : std_logic_vector(6 downto 0);
+	signal BORDER                     : std_logic_vector(6 downto 0);
-	signal RAND_ON                  : std_logic;
+	signal BORDER_ON                : std_logic;
 	signal START_ZEILE              : std_logic;
 	signal SYNC_PIX                 : std_logic;
 	signal SYNC_PIX1                : std_logic;
@@ -310,7 +310,7 @@ begin
 
 	P_VIDEO_CONTROL : process
 	begin
-		wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
 		if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(0) = '1' then
 			ST_SHIFT_MODE <= DATA_IN(25 downto 24);
 		end if;
@@ -418,6 +418,7 @@ begin
 	COLOR2 <= COLOR2_I;
 	COLOR4 <= COLOR4_I;
 	COLOR8 <= COLOR8_I;
+	
 	-- VIDEO PLL config and reconfig:
 	VIDEO_PLL_CONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_B(1) = '1' and FB_ADR(27 downto 9) = "0000000000000000011" else '0'; -- $(F)000'0600-7FF -> 6/2 word and long only.
 	VIDEO_PLL_RECONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_ADR(27 downto 0) = x"0000800" else '0'; -- $(F)000'0800. 
@@ -426,7 +427,8 @@ begin
 	P_VIDEO_CONFIG: process
 		variable LOCK : boolean;
 	begin
-		wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
+
 		if VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and VR_WR_I = '0' then
 			VR_WR_I <= '1'; -- This is a strobe.
 		else
@@ -452,507 +454,506 @@ begin
 		end if;
 	end process P_VIDEO_CONFIG;
     
-    VIDEO_RAM_CTR <= FBEE_VCTR(31 downto 16);
+	VIDEO_RAM_CTR <= FBEE_VCTR(31 downto 16);
     
-    -- Firebee colour modi: 
+	-- Firebee colour modi: 
-    FBEE_CLUT <= '1' when FBEE_VIDEO_ON = '1' and (COLOR1_I = '1' or COLOR8_I = '1') else
+	FBEE_CLUT <= '1' when FBEE_VIDEO_ON = '1' and (COLOR1_I = '1' or COLOR8_I = '1') else
-                 '1' when ST_VIDEO = '1' and COLOR1_I = '1';
+						'1' when ST_VIDEO = '1' and COLOR1_I = '1';
                  
-    FALCON_VIDEO <= FBEE_VCTR(7);
+	FALCON_VIDEO <= FBEE_VCTR(7);
-    FALCON_CLUT <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and COLOR16_I = '0' else '0';
+	FALCON_CLUT <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and COLOR16_I = '0' else '0';
-    ST_VIDEO <= FBEE_VCTR(6);
+	ST_VIDEO <= FBEE_VCTR(6);
-    ST_CLUT <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_CLUT = '0' and COLOR1_I = '0' else '0';
+	ST_CLUT <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_CLUT = '0' and COLOR1_I = '0' else '0';
 
     -- Several (video)-registers:
-    CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR = x"f0000404" else '0';	-- $F0000404 - Firebee video border color
+	CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR = x"f0000404" else '0';	-- $F0000404 - Firebee video border color
-    SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0';	-- $FF8006 - Falcon monitor type register
+	SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0';	-- $FF8006 - Falcon monitor type register
-    VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo.
+	VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo.
-    VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo.
+	VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo.
-    VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo.
+	VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo.
-    VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo.
+	VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo.
-    VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo.
+	VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo.
-    VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo.
+	VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo.
-    VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo.
+	VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo.
-    VDL_HSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000110" else '0'; -- $828C/2.
+	VDL_HSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828c" else '0'; -- $FF828C/D - position hsync (HSS).
-    VDL_VBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010011" else '0'; -- $82A6/2.
+	VDL_VFT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a2" else '0'; -- $FF82A2/3 - video frequency timer (VFT).
-    VDL_VDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010100" else '0'; -- $82A8/2.
+	VDL_VBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) & '0' = x"ff82a4" else '0'; -- $FF82A4/5 - vertical blank on (in half line steps).
-    VDL_VDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010101" else '0'; -- $82AA/2.
+	VDL_VBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a6" else '0'; -- $FF82A6/7 - vertical blank off (in half line steps).
-    VDL_VBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010010" else '0'; -- $82A4/2.
+	VDL_VDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a8" else '0'; -- $FF82A8/9 - vertical display begin (VDB).
-    VDL_VSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010110" else '0'; -- $82AC/2.
+	VDL_VDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82aa" else '0'; -- $FF82AA/B - vertical display end (VDE).
-    VDL_VFT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010001" else '0'; -- $82A2/2.
+	VDL_VSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82ac" else '0'; -- $FF82AC/D - position vsync (VSS).
-    VDL_VCT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101100000" else '0'; -- $82C0/2.
+	VDL_VCT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c0" else '0'; -- $FF82C0/1 - clock control (VCO).
-    VDL_VMD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101100001" else '0'; -- $82C2/2.
+	VDL_VMD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c2" else '0'; -- $FF82C2/3 - resolution control.
 
-    P_MISC_CTRL : process
+	P_MISC_CTRL : process
-    begin
+	begin
-        wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
-		  
+        
-        -- Colour of video borders
+		-- Colour of video borders
-        if CCR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		if CCR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            CCR_I(23 downto 16) <= DATA_IN(23 downto 16);
+			CCR_I(23 downto 16) <= DATA_IN(23 downto 16);
-        elsif CCR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		elsif CCR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            CCR_I(15 downto 8) <= DATA_IN(15 downto 8);
+			CCR_I(15 downto 8) <= DATA_IN(15 downto 8);
-        elsif CCR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		elsif CCR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            CCR_I(7 downto 0) <= DATA_IN(7 downto 0);
+			CCR_I(7 downto 0) <= DATA_IN(7 downto 0);
-        end if;
+		end if;
 
-        --SYS CTRL:
+		-- SYS CTRL:
-        if SYS_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		if SYS_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            SYS_CTR <= DATA_IN(22 downto 16);
+			SYS_CTR <= DATA_IN(22 downto 16);
-        end if;
+		end if;
 
-        --VDL_LOF:
+		--VDL_LOF:
-        if VDL_LOF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		if VDL_LOF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_LOF(15 downto 8) <= DATA_IN(31 downto 24);
+			VDL_LOF(15 downto 8) <= DATA_IN(31 downto 24);
-        elsif VDL_LOF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		elsif VDL_LOF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_LOF(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_LOF(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        --VDL_LWD
+		--VDL_LWD
-        if VDL_LWD_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_LWD_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_LWD(15 downto 8) <= DATA_IN(31 downto 24);
+			VDL_LWD(15 downto 8) <= DATA_IN(31 downto 24);
-        elsif VDL_LWD_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_LWD_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_LWD(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_LWD(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- Horizontal:
+		-- Horizontal:
-        -- VDL_HHT:
+		-- VDL_HHT:
-        if VDL_HHT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		if VDL_HHT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_HHT(11 downto 8) <= DATA_IN(27 downto 24);
+			VDL_HHT(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HHT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		elsif VDL_HHT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_HHT(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_HHT(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_HBE:
+		-- VDL_HBE:
-        if VDL_HBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		if VDL_HBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_HBE(11 downto 8) <= DATA_IN(27 downto 24);
+			VDL_HBE(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		elsif VDL_HBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_HBE(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_HBE(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_HDB:
+		-- VDL_HDB:
-        if VDL_HDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_HDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_HDB(11 downto 8) <= DATA_IN(27 downto 24);
+			VDL_HDB(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_HDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_HDB(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_HDB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_HDE:
+		-- VDL_HDE:
-        if VDL_HDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		if VDL_HDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_HDE(11 downto 8) <= DATA_IN(27 downto 24);
+			VDL_HDE(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		elsif VDL_HDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_HDE(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_HDE(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_HBB:
+		-- VDL_HBB:
-        if VDL_HBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_HBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_HBB(11 downto 8) <= DATA_IN(27 downto 24);
+			VDL_HBB(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_HBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_HBB(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_HBB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_HSS:
+		-- VDL_HSS:
-        if VDL_HSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_HSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_HSS(11 downto 8) <= DATA_IN(27 downto 24);
+			VDL_HSS(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_HSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_HSS(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_HSS(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- Vertical:
+		-- Vertical:
-        -- VDL_VBE:
+		-- VDL_VBE:
-        if VDL_VBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		if VDL_VBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_VBE(10 downto 8) <= DATA_IN(26 downto 24);
+			VDL_VBE(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		elsif VDL_VBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_VBE(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_VBE(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_VDB:
+		-- VDL_VDB:
-        if VDL_VDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_VDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VDB(10 downto 8) <= DATA_IN(26 downto 24);
+			VDL_VDB(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_VDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VDB(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_VDB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
-        -- VDL_VDE:
+        
-        if VDL_VDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		-- VDL_VDE:
-            VDL_VDE(10 downto 8) <= DATA_IN(26 downto 24);
+		if VDL_VDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-        elsif VDL_VDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_VDE(10 downto 8) <= DATA_IN(26 downto 24);
-            VDL_VDE(7 downto 0) <= DATA_IN(23 downto 16);
+		elsif VDL_VDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-        end if;
+			VDL_VDE(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_VBB:
+		-- VDL_VBB:
-        if VDL_VBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_VBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VBB(10 downto 8) <= DATA_IN(26 downto 24);
+			VDL_VBB(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_VBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VBB(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_VBB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_VSS
+		-- VDL_VSS
-        if VDL_VSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_VSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VSS(10 downto 8) <= DATA_IN(26 downto 24);
+			VDL_VSS(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_VSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VSS(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_VSS(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_VFT
+		-- VDL_VFT
-        if VDL_VFT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+		if VDL_VFT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_VFT(10 downto 8) <= DATA_IN(26 downto 24);
+			VDL_VFT(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VFT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		elsif VDL_VFT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_VFT(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_VFT(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_VCT(2): 1 = 32MHz CLK_PIXEL, 0 = 25MHZ; VDL_VCT(0): 1 = linedoubling.
+		-- VDL_VCT(2): 1 = 32MHz CLK_PIXEL, 0 = 25MHZ; VDL_VCT(0): 1 = linedoubling.
-        if VDL_VCT_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+		if VDL_VCT_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VCT(8) <= DATA_IN(24);
+			VDL_VCT(8) <= DATA_IN(24);
-        elsif VDL_VCT_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+		elsif VDL_VCT_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VCT(7 downto 0) <= DATA_IN(23 downto 16);
+			VDL_VCT(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		end if;
 
-        -- VDL_VMD(2): 1 = CLK_PIXEL/2.
+		-- VDL_VMD(2): 1 = CLK_PIXEL/2.
-        if VDL_VMD_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+		if VDL_VMD_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_VMD <= DATA_IN(19 downto 16);
+			VDL_VMD <= DATA_IN(19 downto 16);
-        end if;
+		end if;
-    end process P_MISC_CTRL;
+	end process P_MISC_CTRL;
 
-    BLITTER_ON <= not SYS_CTR(3);
+	BLITTER_ON <= not SYS_CTR(3);
     
-    -- Register out:
+	-- Register out:
-    DATA_OUT(31 downto 16) <= "000000" & ST_SHIFT_MODE & x"00" when ST_SHIFT_MODE_CS = '1' else
+	DATA_OUT(31 downto 16) <= "000000" & ST_SHIFT_MODE & x"00" when ST_SHIFT_MODE_CS = '1' else
-                              "00000" & FALCON_SHIFT_MODE when FALCON_SHIFT_MODE_CS = '1' else
+										"00000" & FALCON_SHIFT_MODE when FALCON_SHIFT_MODE_CS = '1' else
-                              "100000000" & SYS_CTR(6 downto 4) & not BLITTER_RUN & SYS_CTR(2 downto 0) when SYS_CTR_CS = '1' else
+										"100000000" & SYS_CTR(6 downto 4) & not BLITTER_RUN & SYS_CTR(2 downto 0) when SYS_CTR_CS = '1' else
-                              VDL_LOF when VDL_LOF_CS = '1' else
+										VDL_LOF when VDL_LOF_CS = '1' else
-                              VDL_LWD when VDL_LWD_CS = '1' else
+										VDL_LWD when VDL_LWD_CS = '1' else
-                              x"0" & VDL_HBE when VDL_HBE_CS = '1' else
+										x"0" & VDL_HBE when VDL_HBE_CS = '1' else
-                              x"0" & VDL_HDB when VDL_HDB_CS = '1' else
+										x"0" & VDL_HDB when VDL_HDB_CS = '1' else
-                              x"0" & VDL_HDE when VDL_HDE_CS = '1' else
+										x"0" & VDL_HDE when VDL_HDE_CS = '1' else
-                              x"0" & VDL_HBB when VDL_HBB_CS = '1' else
+										x"0" & VDL_HBB when VDL_HBB_CS = '1' else
-                              x"0" & VDL_HSS when VDL_HSS_CS = '1' else
+										x"0" & VDL_HSS when VDL_HSS_CS = '1' else
-                              x"0" & VDL_HHT when VDL_HHT_CS = '1' else
+										x"0" & VDL_HHT when VDL_HHT_CS = '1' else
-                              "00000" & VDL_VBE when VDL_VBE_CS = '1' else
+										"00000" & VDL_VBE when VDL_VBE_CS = '1' else
-                              "00000" & VDL_VDB when VDL_VDB_CS = '1' else
+										"00000" & VDL_VDB when VDL_VDB_CS = '1' else
-                              "00000" & VDL_VDE when VDL_VDE_CS = '1' else
+										"00000" & VDL_VDE when VDL_VDE_CS = '1' else
-                              "00000" & VDL_VBB when VDL_VBB_CS = '1' else
+										"00000" & VDL_VBB when VDL_VBB_CS = '1' else
-                              "00000" & VDL_VSS when VDL_VSS_CS = '1' else
+										"00000" & VDL_VSS when VDL_VSS_CS = '1' else
-                              "00000" & VDL_VFT when VDL_VFT_CS = '1' else
+										"00000" & VDL_VFT when VDL_VFT_CS = '1' else
-                              "0000000" & VDL_VCT when VDL_VCT_CS = '1' else    
+										"0000000" & VDL_VCT when VDL_VCT_CS = '1' else    
-                              x"000" & VDL_VMD when VDL_VMD_CS = '1' else
+										x"000" & VDL_VMD when VDL_VMD_CS = '1' else
-                              FBEE_VCTR(31 downto 16) when FBEE_VCTR_CS = '1' else
+										FBEE_VCTR(31 downto 16) when FBEE_VCTR_CS = '1' else
-                              ATARI_HH(31 downto 16) when ATARI_HH_CS = '1' else
+										ATARI_HH(31 downto 16) when ATARI_HH_CS = '1' else
-                              ATARI_VH(31 downto 16) when ATARI_VH_CS = '1' else
+										ATARI_VH(31 downto 16) when ATARI_VH_CS = '1' else
-                              ATARI_HL(31 downto 16) when ATARI_HL_CS = '1' else
+										ATARI_HL(31 downto 16) when ATARI_HL_CS = '1' else
-                              ATARI_VL(31 downto 16) when ATARI_VL_CS = '1' else
+										ATARI_VL(31 downto 16) when ATARI_VL_CS = '1' else
-                              x"00" & CCR_I(23 downto 16) when CCR_CS = '1' else 
+										x"00" & CCR_I(23 downto 16) when CCR_CS = '1' else 
-                              "0000000" & VR_DOUT when VIDEO_PLL_CONFIG_CS = '1' else
+										"0000000" & VR_DOUT when VIDEO_PLL_CONFIG_CS = '1' else
-                              VR_BUSY & "0000" & VR_WR_I & VR_RD_I & VIDEO_RECONFIG_I & x"FA" when VIDEO_PLL_RECONFIG_CS = '1' else (others => '0');
+										VR_BUSY & "0000" & VR_WR_I & VR_RD_I & VIDEO_RECONFIG_I & x"FA" when VIDEO_PLL_RECONFIG_CS = '1' else (others => '0');
     
-    DATA_OUT(15 downto 0) <= FBEE_VCTR(15 downto 0) when FBEE_VCTR_CS = '1' else
+	DATA_OUT(15 downto 0) <= FBEE_VCTR(15 downto 0) when FBEE_VCTR_CS = '1' else
-                             ATARI_HH(15 downto 0) when ATARI_HH_CS = '1' else
+										ATARI_HH(15 downto 0) when ATARI_HH_CS = '1' else
-                             ATARI_VH(15 downto 0) when ATARI_VH_CS = '1' else
+										ATARI_VH(15 downto 0) when ATARI_VH_CS = '1' else
-                             ATARI_HL(15 downto 0) when ATARI_HL_CS = '1' else
+										ATARI_HL(15 downto 0) when ATARI_HL_CS = '1' else
-                             ATARI_VL(15 downto 0) when ATARI_VL_CS = '1' else
+										ATARI_VL(15 downto 0) when ATARI_VL_CS = '1' else
-                             CCR_I(15 downto 0) when CCR_CS = '1' else (others => '0');
+										CCR_I(15 downto 0) when CCR_CS = '1' else (others => '0');
 
-    DATA_EN_H <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or CCR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
+	DATA_EN_H <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or CCR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
-                  VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
+						VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
-                  ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or VIDEO_PLL_RECONFIG_CS or
+						ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or VIDEO_PLL_RECONFIG_CS or
-                  VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS) and not FB_OEn;
+						VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS) and not FB_OEn;
 
-    DATA_EN_L <= (FBEE_VCTR_CS or CCR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS ) and not FB_OEn;
+	DATA_EN_L <= (FBEE_VCTR_CS or CCR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS ) and not FB_OEn;
 
-    VIDEO_MOD_TA_I <= CLUT_TA or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
+	VIDEO_MOD_TA_I <= CLUT_TA or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
-                      VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
+							VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
-                      ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or
+							ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or
-                      VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS;
+							VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS;
     
-    P_CLK_16M5 : process
+	P_CLK_16M5 : process
-    begin
+	begin
-        wait until CLK33M = '1' and CLK33M' event;
+		wait until rising_edge(CLK33M);
-        CLK17M <= not CLK17M;
+		CLK17M <= not CLK17M;
-    end process P_CLK_16M5;
+	end process P_CLK_16M5;
 
-    P_CLK_12M5 : process
+	P_CLK_12M5 : process
-    begin
+	begin
-        wait until CLK25M = '1' and CLK25M' event;
+		wait until rising_edge(CLK25M);
-        CLK13M <= not CLK13M;
+		CLK13M <= not CLK13M;
-    end process P_CLK_12M5;
+	end process P_CLK_12M5;
 
-    CLK_PIXEL_I <= CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' else
+	CLK_PIXEL_I <= CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' else
-                   CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' else
+						CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' else
-                   CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' else
+						CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' else
-                   CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' else
+						CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' else
-                   CLK25M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' else
+						CLK25M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' else
-                   CLK33M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' else
+						CLK33M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' else
-                   CLK25M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" else
+						CLK25M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" else
-                   CLK33M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" else
+						CLK33M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" else
-                   CLK_VIDEO when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' else '0';
+						CLK_VIDEO when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' else '0';
 
-    P_HSYN_LEN  : process
+	P_HSYN_LEN  : process
-    -- Horizontal SYNC in CLK_PIXEL:
+		-- Horizontal SYNC in CLK_PIXEL:
-    begin
+	begin
-        wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
-        if FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' then
+		if FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' then
-            HSY_LEN <= x"0E";
+			HSY_LEN <= x"0E";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' then
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' then
-            HSY_LEN <= x"0E";
+			HSY_LEN <= x"0E";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' then
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' then
-            HSY_LEN <= x"10";
+			HSY_LEN <= x"10";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' then
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' then
-            HSY_LEN <= x"10";
+			HSY_LEN <= x"10";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' then
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' then
-            HSY_LEN <= x"1C";
+			HSY_LEN <= x"1C";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' then
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' then
-            HSY_LEN <= x"20";
+			HSY_LEN <= x"20";
-        elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" then
+		elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" then
-            HSY_LEN <= x"1C";
+			HSY_LEN <= x"1C";
-        elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" then
+		elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" then
-            HSY_LEN <= x"20";
+			HSY_LEN <= x"20";
-        elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' then
+		elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' then
-            HSY_LEN <= std_logic_vector(unsigned'(x"10") + unsigned('0' & VR_FRQ(7 downto 1))); -- HSYNC pulse length in pixels = frequency/500ns.
+			HSY_LEN <= std_logic_vector(unsigned'(x"10") + unsigned('0' & VR_FRQ(7 downto 1))); -- HSYNC pulse length in pixels = frequency/500ns.
-        else
+		else
-            HSY_LEN <= x"00";
+			HSY_LEN <= x"00";
-        end if;
+		end if;
-    end process P_HSYN_LEN;
+	end process P_HSYN_LEN;
 
-    MULF <= "000010" when ST_VIDEO = '0' and VDL_VMD(2) = '1' else -- Multiplier.
+	MULF <= "000010" when ST_VIDEO = '0' and VDL_VMD(2) = '1' else -- Multiplier.
-            "000100" when ST_VIDEO = '0' and VDL_VMD(2) = '0' else
+				"000100" when ST_VIDEO = '0' and VDL_VMD(2) = '0' else
-            "010000" when ST_VIDEO = '1' and VDL_VMD(2) = '1' else
+				"010000" when ST_VIDEO = '1' and VDL_VMD(2) = '1' else
-            "100000" when ST_VIDEO = '1' and VDL_VMD(2) = '0' else "000000";
+				"100000" when ST_VIDEO = '1' and VDL_VMD(2) = '0' else "000000";
 
-    HDIS_LEN <= x"140" when VDL_VMD(2) = '1' else x"280"; -- Width in pixels (320 / 640).
+	HDIS_LEN <= x"140" when VDL_VMD(2) = '1' else x"280"; -- Width in pixels (320 / 640).
 
-    P_DOUBLE_LINE_1   : process
+	P_DOUBLE_LINE_1   : process
-    begin
+	begin
-        wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
-        DOP_ZEI <= VDL_VMD(0) and ST_VIDEO; -- Line doubling on off.
+		DOP_ZEI <= VDL_VMD(0) and ST_VIDEO; -- Line doubling on off.
-    end process P_DOUBLE_LINE_1;
+	end process P_DOUBLE_LINE_1;
 
-    P_DOUBLE_LINE_2   : process
+	P_DOUBLE_LINE_2   : process
-    begin
+	begin
-        wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I'event;
+		wait until rising_edge(CLK_PIXEL_I);
-        if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < std_logic_vector(unsigned(HDIS_END) - 1) then        
+		if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < std_logic_vector(unsigned(HDIS_END) - 1) then        
-            INTER_ZEI_I <= '1'; -- Switch insertion line to "double". Line zero due to SYNC.
+			INTER_ZEI_I <= '1'; -- Switch insertion line to "double". Line zero due to SYNC.
-        elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > std_logic_vector(unsigned(HDIS_END) - 10) then
+		elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > std_logic_vector(unsigned(HDIS_END) - 10) then
-            INTER_ZEI_I <= '1'; -- Switch insertion mode to "normal". Lines and line zero due to SYNC.
+			INTER_ZEI_I <= '1'; -- Switch insertion mode to "normal". Lines and line zero due to SYNC.
-        else
+		else
-            INTER_ZEI_I <= '0';
+			INTER_ZEI_I <= '0';
-        end if;
+		end if;
-        --
+		--
-        DOP_FIFO_CLR <= INTER_ZEI_I and HSYNC_START and SYNC_PIX; -- Double line info erase at the end of a double line and at main FIFO start.
+		DOP_FIFO_CLR <= INTER_ZEI_I and HSYNC_START and SYNC_PIX; -- Double line info erase at the end of a double line and at main FIFO start.
-    end process P_DOUBLE_LINE_2;
+	end process P_DOUBLE_LINE_2;
 
     -- The following multiplications change every time the video resolution is changed.
-    MUL1 <= unsigned(VDL_HBE) * unsigned(MULF(5 downto 1));
+	MUL1 <= unsigned(VDL_HBE) * unsigned(MULF(5 downto 1));
-    MUL2 <= unsigned(VDL_HHT) + 1 + unsigned(VDL_HSS) * unsigned(MULF(5 downto 1));
+	MUL2 <= unsigned(VDL_HHT) + 1 + unsigned(VDL_HSS) * unsigned(MULF(5 downto 1));
-    MUL3 <= resize(unsigned(VDL_HHT) + 10 * unsigned(MULF(5 downto 1)), MUL3'length);
+	MUL3 <= resize(unsigned(VDL_HHT) + 10 * unsigned(MULF(5 downto 1)), MUL3'length);
 
-    BORDER_LEFT <= VDL_HBE when FBEE_VIDEO_ON = '1' else 
+	BORDER_LEFT <= VDL_HBE when FBEE_VIDEO_ON = '1' else 
-                  x"015" when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+						x"015" when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-                  x"02A" when ATARI_SYNC = '1' else std_logic_vector(MUL1(16 downto 5));
+						x"02A" when ATARI_SYNC = '1' else std_logic_vector(MUL1(16 downto 5));
-    HDIS_START <= VDL_HDB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + 1);
+	HDIS_START <= VDL_HDB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + 1);
-    HDIS_END <= VDL_HDE when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + unsigned(HDIS_LEN));
+	HDIS_END <= VDL_HDE when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + unsigned(HDIS_LEN));
-    BORDER_RIGHT <= VDL_HBB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(HDIS_END) + 1);
+	BORDER_RIGHT <= VDL_HBB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(HDIS_END) + 1);
-    HS_START <= VDL_HSS when FBEE_VIDEO_ON = '1' else
+	HS_START <= VDL_HSS when FBEE_VIDEO_ON = '1' else
-                ATARI_HL(11 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_HL(11 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-                ATARI_HH(11 downto 0) when VDL_VMD(2) = '1' else std_logic_vector(MUL2(16 downto 5));
+					ATARI_HH(11 downto 0) when VDL_VMD(2) = '1' else std_logic_vector(MUL2(16 downto 5));
-    H_TOTAL <= VDL_HHT when FBEE_VIDEO_ON = '1' else
+	H_TOTAL <= VDL_HHT when FBEE_VIDEO_ON = '1' else
-               ATARI_HL(27 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_HL(27 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-               ATARI_HH(27 downto 16) when ATARI_SYNC = '1' else std_logic_vector(MUL3(16 downto 5));
+					ATARI_HH(27 downto 16) when ATARI_SYNC = '1' else std_logic_vector(MUL3(16 downto 5));
-    BORDER_TOP <= VDL_VBE when FBEE_VIDEO_ON = '1' else
+	BORDER_TOP <= VDL_VBE when FBEE_VIDEO_ON = '1' else
-                 "00000011111" when ATARI_SYNC = '1' else '0' & VDL_VBE(10 downto 1);
+						"00000011111" when ATARI_SYNC = '1' else '0' & VDL_VBE(10 downto 1);
-    VDIS_START <= VDL_VDB when FBEE_VIDEO_ON = '1' else
+	VDIS_START <= VDL_VDB when FBEE_VIDEO_ON = '1' else
-                  "00000100000" when ATARI_SYNC = '1' else '0' & VDL_VDB(10 downto 1);
+						"00000100000" when ATARI_SYNC = '1' else '0' & VDL_VDB(10 downto 1);
-    VDIS_END <= VDL_VDE when FBEE_VIDEO_ON = '1' else
+	VDIS_END <= VDL_VDE when FBEE_VIDEO_ON = '1' else
-                "00110101111" when ATARI_SYNC = '1' and ST_VIDEO = '1' else -- 431.
+					"00110101111" when ATARI_SYNC = '1' and ST_VIDEO = '1' else -- 431.
-                "00111111111" when ATARI_SYNC = '1' else '0' & VDL_VDE(10 downto 1); -- 511.
+					"00111111111" when ATARI_SYNC = '1' else '0' & VDL_VDE(10 downto 1); -- 511.
-    BORDER_BOTTOM <= VDL_VBB when FBEE_VIDEO_ON = '1' else
+	BORDER_BOTTOM <= VDL_VBB when FBEE_VIDEO_ON = '1' else
-                  std_logic_vector(unsigned(VDIS_END) + 1) when ATARI_SYNC = '1' else ('0' & std_logic_vector(unsigned(VDL_VBB(10 downto 1)) + 1));
+						std_logic_vector(unsigned(VDIS_END) + 1) when ATARI_SYNC = '1' else ('0' & std_logic_vector(unsigned(VDL_VBB(10 downto 1)) + 1));
-    VS_START <= VDL_VSS when FBEE_VIDEO_ON = '1' else
+	VS_START <= VDL_VSS when FBEE_VIDEO_ON = '1' else
-                ATARI_VL(10 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_VL(10 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-                ATARI_VH(10 downto 0) when ATARI_SYNC = '1' else '0' & VDL_VSS(10 downto 1);
+					ATARI_VH(10 downto 0) when ATARI_SYNC = '1' else '0' & VDL_VSS(10 downto 1);
-    V_TOTAL <= VDL_VFT when FBEE_VIDEO_ON = '1' else
+	V_TOTAL <= VDL_VFT when FBEE_VIDEO_ON = '1' else
-               ATARI_VL(26 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_VL(26 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-               ATARI_VH(26 downto 16) when ATARI_SYNC = '1' else '0' & VDL_VFT(10 downto 1);
+					ATARI_VH(26 downto 16) when ATARI_SYNC = '1' else '0' & VDL_VFT(10 downto 1);
 
-    LAST <= '1' when VHCNT  = std_logic_vector(unsigned(H_TOTAL) - 10) else '0';
+	LAST <= '1' when VHCNT  = std_logic_vector(unsigned(H_TOTAL) - 10) else '0';
 
-    VIDEO_CLOCK_DOMAIN   : process
+	VIDEO_CLOCK_DOMAIN   : process
-    begin
+	begin
-        wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
+		wait until rising_edge(CLK_PIXEL_I);
+		if ST_CLUT = '1' then
+			CCSEL <= "000"; -- For information only.
+		elsif FALCON_CLUT = '1' then
+			CCSEL <= "001";
+		elsif FBEE_CLUT = '1' then
+			CCSEL <= "100";
+		elsif COLOR16_I = '1' then
+			CCSEL <= "101";
+		elsif COLOR24_I = '1' then
+			CCSEL <= "110";
+		elsif BORDER_ON = '1' then
+			CCSEL <= "111";
+		end if;
+
+		if LAST = '0' then
+			VHCNT <= std_logic_vector(unsigned(VHCNT) + 1);
+		else
+			VHCNT <= (others => '0');
+		end if;
+
+		if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 1) then
+			VVCNT <= (others => '0');
+		elsif LAST = '1' then
+			VVCNT <= std_logic_vector(unsigned(VVCNT) + 1);
+		end if;
+
+		-- Display on/off:
+		if LAST = '1' and VVCNT > std_logic_vector(unsigned(BORDER_TOP) - 1) and VVCNT < std_logic_vector(unsigned(BORDER_BOTTOM) - 1) then
+			DPO_ZL <= '1';
+		elsif LAST = '1' then
+			DPO_ZL <= '0';
+		end if;
         
-        if ST_CLUT = '1' then
+		if VHCNT = BORDER_LEFT then
-            CCSEL <= "000"; -- For information only.
+			DPO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING
-        elsif FALCON_CLUT = '1' then
+		else
-            CCSEL <= "001";
+			DPO_ON <= '0';
-        elsif FBEE_CLUT = '1' then
+		end if;
-            CCSEL <= "100";
-        elsif COLOR16_I = '1' then
-            CCSEL <= "101";
-        elsif COLOR24_I = '1' then
-            CCSEL <= "110";
-        elsif RAND_ON = '1' then
-            CCSEL <= "111";
-        end if;
 
-        if LAST = '0' then
+		if VHCNT = std_logic_vector(unsigned(BORDER_RIGHT) - 1) then
-            VHCNT <= std_logic_vector(unsigned(VHCNT) + 1);
+			DPO_OFF <= '1';
-        else
+		else
-            VHCNT <= (others => '0');
+			DPO_OFF <= '0';
-        end if;
+		end if;
 
-        if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 1) then
+		DISP_ON <= (DISP_ON and not DPO_OFF) or (DPO_ON and DPO_ZL);
-            VVCNT <= (others => '0');
-        elsif LAST = '1' then
-            VVCNT <= std_logic_vector(unsigned(VVCNT) + 1);
-        end if;
 
-        -- Display on/off:
+		-- Data transfer on/off:
-        if LAST = '1' and VVCNT > std_logic_vector(unsigned(BORDER_TOP) - 1) and VVCNT < std_logic_vector(unsigned(BORDER_BOTTOM) - 1) then
+		if VHCNT = std_logic_vector(unsigned(HDIS_START) - 1) then
-            DPO_ZL <= '1';
+			VDO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING.
-        elsif LAST = '1' then
+		else
-            DPO_ZL <= '0';
+			VDO_ON <= '0';
-        end if;
+		end if;
+
+		if VHCNT = HDIS_END then
+			VDO_OFF <= '1';
+		else
+			VDO_OFF <= '0';
+		end if;
+
+		if LAST = '1' and VVCNT >= std_logic_vector(unsigned(VDIS_START) - 1) and VVCNT < VDIS_END then
+			VDO_ZL <= '1'; -- Take over at the end of the line.
+		elsif LAST = '1' then
+			VDO_ZL <= '0'; -- 1 ZEILE DAVOR ON OFF
+		end if;
+
+		VDTRON <= (VDTRON and not VDO_OFF) or (VDO_ON and VDO_ZL);
+
+		-- Delay and SYNC
+		if VHCNT = std_logic_vector(unsigned(HS_START) - 11) then
+			HSYNC_START <= '1';
+		else
+			HSYNC_START <= '0';
+		end if;
         
-        if VHCNT = BORDER_LEFT then
+		if HSYNC_START = '1' then
-            DPO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING
+			HSYNC_I <= std_logic_vector(unsigned(HSY_LEN));
-        else
+		elsif HSYNC_I > x"00" then
-            DPO_ON <= '0';
+			HSYNC_I <= std_logic_vector(unsigned(HSYNC_I) - 1);
-        end if;
+		end if;
 
-        if VHCNT = std_logic_vector(unsigned(BORDER_RIGHT) - 1) then
+		if LAST = '1' and VVCNT = std_logic_vector(unsigned(VS_START) - 11) then
-            DPO_OFF <= '1';
+			VSYNC_START <= '1'; -- start am ende der Zeile vor dem vsync
-        else
+		else
-            DPO_OFF <= '0';
+			VSYNC_START <= '0';
-        end if;
+		end if;
-
-        DISP_ON <= (DISP_ON and not DPO_OFF) or (DPO_ON and DPO_ZL);
-
-        -- Data transfer on/off:
-        if VHCNT = std_logic_vector(unsigned(HDIS_START) - 1) then
-            VDO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING.
-        else
-            VDO_ON <= '0';
-        end if;
-
-        if VHCNT = HDIS_END then
-            VDO_OFF <= '1';
-        else
-            VDO_OFF <= '0';
-        end if;
-
-        if LAST = '1' and VVCNT >= std_logic_vector(unsigned(VDIS_START) - 1) and VVCNT < VDIS_END then
-            VDO_ZL <= '1'; -- Take over at the end of the line.
-        elsif LAST = '1' then
-            VDO_ZL <= '0'; -- 1 ZEILE DAVOR ON OFF
-
-        end if;
-
-        VDTRON <= (VDTRON and not VDO_OFF) or (VDO_ON and VDO_ZL);
-
-        -- Delay and SYNC
-        if VHCNT = std_logic_vector(unsigned(HS_START) - 11) then
-            HSYNC_START <= '1';
-        else
-            HSYNC_START <= '0';
-        end if;
         
-        if HSYNC_START = '1' then
+		if LAST = '1' and VSYNC_START = '1' then -- Start at the end of the line before VSYNC.
-            HSYNC_I <= std_logic_vector(unsigned(HSY_LEN));
+			VSYNC_I <= "011"; -- 3 lines vsync length.
-        elsif HSYNC_I > x"00" then
+		elsif LAST = '1' and VSYNC_I > "000" then
-            HSYNC_I <= std_logic_vector(unsigned(HSYNC_I) - 1);
+			VSYNC_I <= std_logic_vector(unsigned(VSYNC_I) - 1); -- Count down.
-        end if;
+		end if;
 
-        if LAST = '1' and VVCNT = std_logic_vector(unsigned(VS_START) - 11) then
+		if FBEE_VCTR(15) = '1' and VDL_VCT(5) = '1' and VSYNC_I = "000" then
-            VSYNC_START <= '1'; -- start am ende der Zeile vor dem vsync
+			VERZ_2 <= VERZ_2(8 downto 0) & '1';
-        else
+		elsif (FBEE_VCTR(15) = '0' or VDL_VCT(5) = '0') and VSYNC_I /= "000" then
-            VSYNC_START <= '0';
+			VERZ_2 <= VERZ_2(8 downto 0) & '1';
-        end if;
+		else
+			VERZ_2 <= VERZ_2(8 downto 0) & '0';
+		end if;
         
-        if LAST = '1' and VSYNC_START = '1' then -- Start at the end of the line before VSYNC.
+		if HSYNC_I > x"00" then
-            VSYNC_I <= "011"; -- 3 lines vsync length.
+			VERZ_1 <= VERZ_1(8 downto 0) & '1';
-        elsif LAST = '1' and VSYNC_I > "000" then
+		else
-            VSYNC_I <= std_logic_vector(unsigned(VSYNC_I) - 1); -- Count down.
+			VERZ_1 <= VERZ_1(8 downto 0) & '0';
-        end if;
+		end if;
 
-        if FBEE_VCTR(15) = '1' and VDL_VCT(5) = '1' and VSYNC_I = "000" then
+		VERZ_0 <= VERZ_0(8 downto 0) & DISP_ON;
-            VERZ_2 <= VERZ_2(8 downto 0) & '1';
+
-        elsif (FBEE_VCTR(15) = '0' or VDL_VCT(5) = '0') and VSYNC_I /= "000" then
+		BLANKn <=  VERZ_0(8);
-            VERZ_2 <= VERZ_2(8 downto 0) & '1';
+		HSYNC  <=  VERZ_1(9);
-        else
+		VSYNC  <=  VERZ_2(9);
-            VERZ_2 <= VERZ_2(8 downto 0) & '0';
+		SYNCn <= not(VERZ_2(9) or VERZ_1(9));
-        end if;
+
+		-- border colours:
+		BORDER <= BORDER(5 downto 0) & (DISP_ON and not VDTRON and FBEE_VCTR(25));
+		BORDER_ON <= BORDER(6);
+
+		if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 10) then
+			FIFO_CLR <= '1';
+		elsif LAST = '1' then
+			FIFO_CLR <= '0';
+		end if;
+
+		if LAST = '1' and VVCNT = "00000000000" then
+			START_ZEILE <= '1';
+		elsif LAST = '1' then
+			START_ZEILE <= '0';
+		end if;
+
+		if VHCNT = x"003" and START_ZEILE = '1' then
+			SYNC_PIX <= '1';
+		else
+			SYNC_PIX <= '0';
+		end if;
+
+		if VHCNT = x"005" and START_ZEILE = '1' then
+			SYNC_PIX1 <= '1';
+		else
+			SYNC_PIX1 <= '0';
+		end if;
+
+		if VHCNT = x"007" and START_ZEILE = '1' then
+			SYNC_PIX2 <= '1';
+		else
+			SYNC_PIX2 <= '0';
+		end if;
         
-        if HSYNC_I > x"00" then
+		if VDTRON = '1' and SYNC_PIX = '0' then
-            VERZ_1 <= VERZ_1(8 downto 0) & '1';
+			SUB_PIXEL_CNT <= std_logic_vector(unsigned(SUB_PIXEL_CNT) + 1);
-        else
+		elsif VDTRON = '1' then
-            VERZ_1 <= VERZ_1(8 downto 0) & '0';
+			SUB_PIXEL_CNT <= (others => '0');
-        end if;
+		end if;
-
-        VERZ_0 <= VERZ_0(8 downto 0) & DISP_ON;
-
-        BLANKn <=  VERZ_0(8);
-        HSYNC  <=  VERZ_1(9);
-        VSYNC  <=  VERZ_2(9);
-        SYNCn <= not(VERZ_2(9) or VERZ_1(9));
-
-        -- Boarder colours:
-        RAND <= RAND(5 downto 0) & (DISP_ON and not VDTRON and FBEE_VCTR(25));
-        RAND_ON <= RAND(6);
-
-        if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 10) then
-            FIFO_CLR <= '1';
-        elsif LAST = '1' then
-            FIFO_CLR <= '0';
-        end if;
-
-        if LAST = '1' and VVCNT = "00000000000" then
-            START_ZEILE <= '1';
-        elsif LAST = '1' then
-            START_ZEILE <= '0';
-        end if;
-
-        if VHCNT = x"003" and START_ZEILE = '1' then
-            SYNC_PIX <= '1';
-        else
-            SYNC_PIX <= '0';
-        end if;
-
-        if VHCNT = x"005" and START_ZEILE = '1' then
-            SYNC_PIX1 <= '1';
-        else
-            SYNC_PIX1 <= '0';
-        end if;
-
-        if VHCNT = x"007" and START_ZEILE = '1' then
-            SYNC_PIX2 <= '1';
-        else
-            SYNC_PIX2 <= '0';
-        end if;
         
-        if VDTRON = '1' and SYNC_PIX = '0' then
+		if VDTRON = '1' and SUB_PIXEL_CNT(6 downto 0) = "0000001" and COLOR1_I = '1' then
-            SUB_PIXEL_CNT <= std_logic_vector(unsigned(SUB_PIXEL_CNT) + 1);
+			FIFO_RDE <= '1';
-        elsif VDTRON = '1' then
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(5 downto 0) = "000001" and COLOR2_I = '1' then
-            SUB_PIXEL_CNT <= (others => '0');
+			FIFO_RDE <= '1';
-        end if;
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(4 downto 0) = "00001" and COLOR4_I = '1' then
-        
+			FIFO_RDE <= '1';
-        if VDTRON = '1' and SUB_PIXEL_CNT(6 downto 0) = "0000001" and COLOR1_I = '1' then
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(3 downto 0) = "0001" and COLOR8_I = '1' then
-            FIFO_RDE <= '1';
+			FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(5 downto 0) = "000001" and COLOR2_I = '1' then
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(2 downto 0) = "001" and COLOR16_I = '1' then
-            FIFO_RDE <= '1';
+			FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(4 downto 0) = "00001" and COLOR4_I = '1' then
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(1 downto 0) = "01" and COLOR24_I = '1' then
-            FIFO_RDE <= '1';
+			FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(3 downto 0) = "0001" and COLOR8_I = '1' then
+		elsif SYNC_PIX = '1' or SYNC_PIX1 = '1' or SYNC_PIX2 = '1' then
-            FIFO_RDE <= '1';
+			FIFO_RDE <= '1'; -- 3 CLOCK ZUS�TZLICH F�R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(2 downto 0) = "001" and COLOR16_I = '1' then
+		else
-            FIFO_RDE <= '1';
+			FIFO_RDE <= '0';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(1 downto 0) = "01" and COLOR24_I = '1' then
+		end if;
-            FIFO_RDE <= '1';
-        elsif SYNC_PIX = '1' or SYNC_PIX1 = '1' or SYNC_PIX2 = '1' then
-            FIFO_RDE <= '1'; -- 3 CLOCK ZUS�TZLICH F�R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
-        else
-            FIFO_RDE <= '0';
-        end if;
 
-        CLUT_MUX_AV_0 <= SUB_PIXEL_CNT(3 downto 0);
+		CLUT_MUX_AV_0 <= SUB_PIXEL_CNT(3 downto 0);
-        CLUT_MUX_AV_1 <= CLUT_MUX_AV_0;
+		CLUT_MUX_AV_1 <= CLUT_MUX_AV_0;
-        CLUT_MUX_ADR <= CLUT_MUX_AV_1;
+		CLUT_MUX_ADR <= CLUT_MUX_AV_1;
-    end process VIDEO_CLOCK_DOMAIN;
+	end process VIDEO_CLOCK_DOMAIN;
 end architecture BEHAVIOUR;