diff --git a/vhdl/backend/Altera/Firebee/firebee.sdc b/vhdl/backend/Altera/Firebee/firebee.sdc
index 02ccf6e..19d1240 100755
--- a/vhdl/backend/Altera/Firebee/firebee.sdc
+++ b/vhdl/backend/Altera/Firebee/firebee.sdc
@@ -17,9 +17,9 @@
 
 ## VENDOR  "Altera"
 ## PROGRAM "Quartus II"
-## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
-## DATE    "Mon Jun  9 15:23:23 2014"
+## DATE    "Fri Aug  8 11:08:03 2014"
 
 ##
 ## DEVICE  "EP3C40F484C6"
@@ -71,110 +71,12 @@ create_generated_clock -name {altpll4:I_PLL4|altpll:altpll_component|altpll4_alt
 # Set Clock Uncertainty
 #**************************************************************
 
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.10  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
-set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
@@ -183,12 +85,12 @@ set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.070  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.070  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
@@ -197,20 +99,6 @@ set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.070  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.070  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.030  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.160  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -219,14 +107,14 @@ set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -235,22 +123,30 @@ set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -263,14 +159,6 @@ set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -279,14 +167,14 @@ set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
-set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}]  0.020  
@@ -295,6 +183,16 @@ set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -303,8 +201,8 @@ set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -313,8 +211,12 @@ set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -hold 0.080  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -323,12 +225,12 @@ set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -hold 0.080  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -337,12 +239,8 @@ set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}]  0.150  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}]  0.030  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -351,8 +249,8 @@ set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
-set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100  
@@ -361,8 +259,6 @@ set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
-set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}]  0.020  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060  
 set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090  
@@ -387,6 +283,110 @@ set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_compo
 set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.090  
 set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.060  
 set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}]  0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}]  0.100  
 
 
 #**************************************************************
@@ -835,12 +835,7 @@ set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}]  5.000 [get_ports
 # Set False Path
 #**************************************************************
 
-set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
-set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
-set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
-set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
 set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
-set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]
 set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]
 
 
diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
index b315202..2e7dbf4 100644
--- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
+++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
@@ -336,7 +336,7 @@ architecture Structure of firebee is
 	signal BLITTER_SIG          : std_logic;
 	signal BLITTER_TA           : std_logic;
 	signal BLITTER_WR           : std_logic;
-	signal BYTE				    : std_logic; -- When Byte -> 1
+	signal BYTE				    	 : std_logic; -- When Byte -> 1
 	signal CA                   : std_logic_vector(2 downto 0);
 	signal CLK_2M0              : std_logic;
 	signal CLK_2M4576           : std_logic;
@@ -352,13 +352,13 @@ architecture Structure of firebee is
 	signal DATA_EN_H_DDR_CTRL   : std_logic;
 	signal DATA_EN_L_DDR_CTRL   : std_logic;
 	signal DATA_IN_FDC_SCSI     : std_logic_vector(7 downto 0);
-	signal DATA_OUT_ACIA_I		: std_logic_vector(7 downto 0);
-	signal DATA_OUT_ACIA_II		: std_logic_vector(7 downto 0);
+	signal DATA_OUT_ACIA_I		 : std_logic_vector(7 downto 0);
+	signal DATA_OUT_ACIA_II		 : std_logic_vector(7 downto 0);
 	signal DATA_OUT_BLITTER     : std_logic_vector(31 downto 0);
 	signal DATA_OUT_DDR_CTRL    : std_logic_vector(31 downto 16);
-	signal DATA_OUT_FDC			: std_logic_vector(7 downto 0);
-	signal DATA_OUT_MFP			: std_logic_vector(7 downto 0);
-	signal DATA_OUT_SCSI		: std_logic_vector(7 downto 0);
+	signal DATA_OUT_FDC			 : std_logic_vector(7 downto 0);
+	signal DATA_OUT_MFP			 : std_logic_vector(7 downto 0);
+	signal DATA_OUT_SCSI			 : std_logic_vector(7 downto 0);
 	signal DINTn                : std_logic;
 	signal DDR_D_IN_N           : std_logic_vector(31 downto 0);
 	signal DDR_FB               : std_logic_vector(4 downto 0);
@@ -395,24 +395,24 @@ architecture Structure of firebee is
 	signal FB_AD_OUT_RTC        : std_logic_vector(7 downto 0);
 	signal FB_AD_OUT_VIDEO      : std_logic_vector(31 downto 0);
 	signal FB_ADR               : std_logic_vector(31 downto 0);
-	signal FB_B0				: std_logic; -- UPPER Byte BEI 16 std_logic BUS
-	signal FB_B1				: std_logic; -- LOWER Byte BEI 16 std_logic BUS
+	signal FB_B0					 : std_logic; -- UPPER Byte BEI 16 std_logic BUS
+	signal FB_B1					 : std_logic; -- LOWER Byte BEI 16 std_logic BUS
 	signal FB_DDR               : std_logic_vector(127 downto 0);
 	signal FB_LE                : std_logic_vector(3 downto 0);
 	signal FB_VDOE              : std_logic_vector(3 downto 0);
 	signal FBEE_CONF            : std_logic_vector(31 downto 0);
 	signal FD_INT               : std_logic;
-	signal FDC_CSn				: std_logic;
-	signal FDC_WRn				: std_logic;
+	signal FDC_CSn					 : std_logic;
+	signal FDC_WRn					 : std_logic;
 	signal FIFO_CLR             : std_logic;
 	signal FIFO_MW              : std_logic_vector(8 downto 0);
-	signal HD_DD_OUT			: std_logic;
+	signal HD_DD_OUT				 : std_logic;
 	signal HSYNC_I              : std_logic;
 	signal IDE_CF_TA            : std_logic;
 	signal IDE_RES_I            : std_logic;
 	signal INT_HANDLER_TA       : std_logic;
-	signal IRQ_KEYBDn			: std_logic;
-	signal IRQ_MIDIn			: std_logic;
+	signal IRQ_KEYBDn				 : std_logic;
+	signal IRQ_MIDIn				 : std_logic;
 	signal KEYB_RxD			    : std_logic;
 	signal LDS                  : std_logic;
 	signal LOCKED               : std_logic;
@@ -431,21 +431,21 @@ architecture Structure of firebee is
 	signal PLL_SCANDONE         : std_logic;
 	signal PLL_SCANDATAOUT      : std_logic;
 	signal RESETn               : std_logic;
-	signal SCSI_BSY_EN			: std_logic;
-	signal SCSI_BSY_OUTn		: std_logic;
-	signal SCSI_CS 				: std_logic;
-	signal SCSI_CSn				: std_logic;
-	signal SCSI_D_EN			: std_logic;
-	signal SCSI_DACKn			: std_logic;
-	signal SCSI_DBP_EN  		: std_logic;
-	signal SCSI_DBP_OUTn		: std_logic;
-	signal SCSI_DRQ				: std_logic;
+	signal SCSI_BSY_EN			 : std_logic;
+	signal SCSI_BSY_OUTn			 : std_logic;
+	signal SCSI_CS 				 : std_logic;
+	signal SCSI_CSn				 : std_logic;
+	signal SCSI_D_EN				 : std_logic;
+	signal SCSI_DACKn				 : std_logic;
+	signal SCSI_DBP_EN  			 : std_logic;
+	signal SCSI_DBP_OUTn			 : std_logic;
+	signal SCSI_DRQ				 : std_logic;
 	signal SCSI_INT             : std_logic;
-	signal SCSI_D_OUTn			: std_logic_vector(7 downto 0);
-	signal SCSI_RST_EN 			: std_logic;
-	signal SCSI_RST_OUTn		: std_logic;
-	signal SCSI_SEL_EN			: std_logic;
-	signal SCSI_SEL_OUTn		: std_logic;
+	signal SCSI_D_OUTn			 : std_logic_vector(7 downto 0);
+	signal SCSI_RST_EN 			 : std_logic;
+	signal SCSI_RST_OUTn			 : std_logic;
+	signal SCSI_SEL_EN			 : std_logic;
+	signal SCSI_SEL_OUTn			 : std_logic;
 	signal SD_CD_D3_EN          : std_logic;
 	signal SD_CD_D3_OUT         : std_logic;
 	signal SD_CMD_D1_EN         : std_logic;
@@ -458,7 +458,7 @@ architecture Structure of firebee is
 	signal SR_DDRWR_D_SEL       : std_logic;
 	signal SR_FIFO_WRE          : std_logic;
 	signal SR_VDMP              : std_logic_vector(7 downto 0);
-	signal TDO					: std_logic;
+	signal TDO						 : std_logic;
 	signal TIMEBASE             : unsigned (17 downto 0);
 	signal VD_EN                : std_logic;
 	signal VD_EN_I              : std_logic;
@@ -488,29 +488,29 @@ begin
 	I_PLL1: altpll1
 		port map(
 			inclk0      => CLK_MAIN,
-			c0          => CLK_2M4576,
-			c1          => CLK_24M576,
-			c2          => CLK_48M,
+			c0          => CLK_2M4576,			-- 2.4576 MHz
+			c1          => CLK_24M576,			-- 24.576 MHz
+			c2          => CLK_48M,				-- 48 MHz
 			locked      => LOCKED
 		);
 
 	I_PLL2: altpll2
 		port map(
 			inclk0      => CLK_MAIN,
-			c0          => CLK_DDR(0),
-			c1          => CLK_DDR(1),
-			c2          => CLK_DDR(2),
-			c3          => CLK_DDR(3),
-			c4          => DDR_SYNC_66M
+			c0          => CLK_DDR(0),			-- 132 MHz / 240°
+			c1          => CLK_DDR(1),			-- 132 MHz / 0°
+			c2          => CLK_DDR(2),			-- 132 MHz / 180°
+			c3          => CLK_DDR(3),			-- 132 MHz / 105°
+			c4          => DDR_SYNC_66M		-- 66 MHz / 270°
 		);
     
 	I_PLL3: altpll3
 		port map(
 			inclk0      => CLK_MAIN,
-			c0          => CLK_2M0,
-			c1          => CLK_FDC,
-			c2          => CLK_25M_I,
-			c3          => CLK_500K
+			c0          => CLK_2M0,				-- 2 MHz
+			c1          => CLK_FDC,				-- 16 MHz
+			c2          => CLK_25M_I,			-- 25 MHz
+			c3          => CLK_500K				-- 500 KHz
 		);
     
 	I_PLL4: altpll4
@@ -521,18 +521,18 @@ begin
 			scandata        => PLL_SCANDATA,
 			scanclkena      => PLL_SCANCLKENA,
 			configupdate    => PLL_CONFIGUPDATE,
-			c0              => CLK_VIDEO,
+			c0              => CLK_VIDEO,		-- configurable video clk, set to 96 MHz initially
 			scandataout     => PLL_SCANDATAOUT,
 			scandone        => PLL_SCANDONE
 			--locked        => -- Not used.
 		);
 
-	I_RECONFIG: altpll_reconfig1
+	I_RECONFIG: altpll_reconfig1								-- to enable reconfiguration of altpll4 (video clock)
 		port map(
 			reconfig            => VIDEO_RECONFIG,
 			read_param          => VR_RD,
 			write_param         => VR_WR,
-			data_in             => FB_ADR(24 downto 16),
+			data_in             => FB_AD(24 downto 16),	-- FIXED: this looks like a typo. Must be FB_AD(24 downto 16) instead of FB_ADR(24 downto 16)
 			counter_type        => FB_ADR(5 downto 2),
 			counter_param       => FB_ADR(8 downto 6),
 			pll_scandataout     => PLL_SCANDATAOUT,
@@ -557,7 +557,7 @@ begin
 
 	P_TIMEBASE: process
 	begin
-		wait until CLK_500K = '1' and CLK_500K' event;
+		wait until rising_edge(CLK_500K);
 		TIMEBASE <= TIMEBASE + 1;
 	end process P_TIMEBASE;
 
@@ -588,7 +588,7 @@ begin
 	SCSI_BUSYn <= SCSI_BSY_OUTn when SCSI_BSY_EN = '1' else 'Z';
 	SCSI_SELn <= SCSI_SEL_OUTn when SCSI_SEL_EN = '1' else 'Z';
 
-	KEYB_RxD <= '0' when AMKB_RX = '0' or PIC_AMKB_RX = '0' else '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL  // 
+	KEYB_RxD <= '0' when AMKB_RX = '0' or PIC_AMKB_RX = '0' else '1';		-- get keyboard data either from PIC (PS/2) or from Atari keyboard
 
 	SD_D3 <= SD_CD_D3_OUT when SD_CD_D3_EN = '1' else 'Z';
 	SD_CMD_D1 <= SD_CMD_D1_OUT when SD_CMD_D1_EN = '1' else 'Z';
@@ -599,7 +599,7 @@ begin
 	HD_DD_OUT <= FDD_HD_DD when FBEE_CONF(29) = '0' else WDC_BSL0;
 	LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
 	ACIA_IRQn <= IRQ_KEYBDn and IRQ_MIDIn;
-	MFP_INTACK <= '1' when FB_CSn(2) = '0' and FB_ADR(19 downto 0) = x"20000" else '0'; 	--F002'0000
+	MFP_INTACK <= '1' when FB_CSn(2) = '0' and FB_ADR(19 downto 0) = x"20000" else '0';		--F002'0000
 	DINTn <= '0' when IDE_INT = '1' and FBEE_CONF(28) = '1' else
 				'0' when FD_INT = '1' else
 				'0' when SCSI_INT = '1' and FBEE_CONF(28) = '1' else '1';
@@ -680,7 +680,7 @@ begin
 
 	SYNCHRONIZATION: process
 	begin
-		wait until DDR_SYNC_66M = '1' and DDR_SYNC_66M' event;
+		wait until rising_edge(DDR_SYNC_66M);
 		if FB_ALE = '1' then
 			FB_ADR <= FB_AD;
 		end if;
@@ -710,7 +710,7 @@ begin
 
 	VIDEO_OUT: process
 	begin
-		wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
+		wait until rising_edge(CLK_PIXEL_I);
 		VSYNC <= VSYNC_I;
 		HSYNC <= HSYNC_I;
 		BLANKn <= BLANK_In;
@@ -718,7 +718,7 @@ begin
 
 	P_DDR_WR: process
 	begin
-		wait until CLK_DDR(3) = '1' and CLK_DDR(3)' event;
+		wait until rising_edge(CLK_DDR(3));
 		DDR_WR <= SR_DDR_WR;
 		DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL;
 	end process P_DDR_WR;
@@ -734,13 +734,13 @@ begin
 
 	DDR_DATA_IN_N: process
 	begin
-		wait until CLK_DDR(1) = '0' and CLK_DDR(1)' event;
+		wait until rising_edge(CLK_DDR(1));
 		DDR_D_IN_N <= VD;
 	end process DDR_DATA_IN_N;
     --
 	DDR_DATA_IN_P: process
 	begin
-		wait until CLK_DDR(1) = '1' and CLK_DDR(1)' event;
+		wait until rising_edge(CLK_DDR(1));
 		VDP_IN(31 downto 0) <= VD;
 		VDP_IN(63 downto 32) <= DDR_D_IN_N;
 	end process DDR_DATA_IN_P;
@@ -772,7 +772,7 @@ begin
 
 	VDP_Q_BUFFER: process
 	begin
-		wait until CLK_DDR(0) = '1' and CLK_DDR(0)' event;
+		wait until rising_edge(CLK_DDR(0));
 		DDR_FB <= SR_DDR_FB & DDR_FB(4 downto 1);
 		--
 		if DDR_FB(1) = '1' then
@@ -785,322 +785,322 @@ begin
 		end if;
 	end process VDP_Q_BUFFER;
  
-    I_DDR_CTRL: DDR_CTRL_V1
-        port map(
-            CLK_MAIN            => CLK_MAIN,
-            DDR_SYNC_66M        => DDR_SYNC_66M,
-            FB_ADR              => FB_ADR,
-            FB_CS1n             => FB_CSn(1),
-            FB_OEn              => FB_OEn,
-            FB_SIZE0            => FB_SIZE(0),
-            FB_SIZE1            => FB_SIZE(1),
-            FB_ALE              => FB_ALE,
-            FB_WRn              => FB_WRn,
-            BLITTER_ADR         => BLITTER_ADR,
-            BLITTER_SIG         => BLITTER_SIG,
-            BLITTER_WR          => BLITTER_WR,
-            SR_BLITTER_DACK     => BLITTER_DACK_SR,
-            BA                  => BA,
-            VA                  => VA,
-            FB_LE               => FB_LE,
-            CLK_33M             => CLK_33M,
-            VRASn               => VRASn,
-            VCASn               => VCASn,
-            VWEn                => VWEn,
-            VCSn                => VCSn,
-            FIFO_CLR            => FIFO_CLR,
-            DDRCLK0             => CLK_DDR(0),
-            VIDEO_RAM_CTR       => VIDEO_RAM_CTR,
-            VCKE                => VCKE,
-            DATA_IN             => FB_AD,
-            DATA_OUT            => DATA_OUT_DDR_CTRL,
-            DATA_EN_H           => DATA_EN_H_DDR_CTRL,
-            DATA_EN_L           => DATA_EN_L_DDR_CTRL,
-            VDM_SEL             => VDM_SEL,
-            FIFO_MW             => FIFO_MW,
-            FB_VDOE             => FB_VDOE,
-            SR_FIFO_WRE         => SR_FIFO_WRE,
-            SR_DDR_FB           => SR_DDR_FB,
-            SR_DDR_WR           => SR_DDR_WR,
-            SR_DDRWR_D_SEL      => SR_DDRWR_D_SEL,
-            SR_VDMP             => SR_VDMP,
-            VIDEO_DDR_TA        => VIDEO_DDR_TA,
-            DDRWR_D_SEL1        => DDRWR_D_SEL(1)
-        );
-
-    I_BLITTER: FBEE_BLITTER
-        port map(
-            RESETn               => RESETn,
-            CLK_MAIN            => CLK_MAIN,
-            CLK_DDR0            => CLK_DDR(0),
-            FB_ADR              => FB_ADR,
-            FB_ALE              => FB_ALE,
-            FB_SIZE1            => FB_SIZE(1),
-            FB_SIZE0            => FB_SIZE(0),
-            FB_CSn              => FB_CSn,
-            FB_OEn              => FB_OEn,
-            FB_WRn              => FB_WRn,
-            DATA_IN             => FB_AD,
-            DATA_OUT            => DATA_OUT_BLITTER,
-            DATA_EN             => DATA_EN_BLITTER,
-            BLITTER_ADR         => BLITTER_ADR,
-            BLITTER_SIG         => BLITTER_SIG,
-            BLITTER_WR          => BLITTER_WR,
-            BLITTER_ON          => BLITTER_ON,
-            BLITTER_RUN         => BLITTER_RUN,
-            BLITTER_DIN         => VD_VZ,
-            BLITTER_DOUT        => BLITTER_DOUT,
-            BLITTER_TA          => BLITTER_TA,
-            BLITTER_DACK_SR     => BLITTER_DACK_SR
-        );
-
-    I_VIDEOSYSTEM: VIDEO_SYSTEM
-        port map(
-            CLK_MAIN            => CLK_MAIN,
-            CLK_33M             => CLK_33M,
-            CLK_25M             => CLK_25M_I,
-            CLK_VIDEO           => CLK_VIDEO,
-            CLK_DDR3            => CLK_DDR(3),
-            CLK_DDR2            => CLK_DDR(2),
-            CLK_DDR0            => CLK_DDR(0),
-            CLK_PIXEL           => CLK_PIXEL_I,
-            
-            VR_D                => VR_D,
-            VR_BUSY             => VR_BUSY,
-            
-            FB_ADR              => FB_ADR,
-            FB_AD_IN            => FB_AD,
-            FB_AD_OUT           => FB_AD_OUT_VIDEO,
-            FB_AD_EN_31_16      => FB_AD_EN_31_16_VIDEO,
-            FB_AD_EN_15_0       => FB_AD_EN_15_0_VIDEO,
-            FB_ALE              => FB_ALE,
-            FB_CSn              => FB_CSn,
-            FB_OEn              => FB_OEn,
-            FB_WRn              => FB_WRn,
-            FB_SIZE1            => FB_SIZE(1),
-            FB_SIZE0            => FB_SIZE(0),
-
-            VDP_IN              => VDP_IN,
-
-            VR_RD               => VR_RD,
-            VR_WR               => VR_WR,
-            VIDEO_RECONFIG      => VIDEO_RECONFIG,
-
-            RED                 => VR,
-            GREEN               => VG,
-            BLUE                => VB,
-            VSYNC               => VSYNC_I,
-            HSYNC               => HSYNC_I,
-            SYNCn               => SYNCn,
-            BLANKn              => BLANK_In,
-            
-            PD_VGAn             => PD_VGAn,
-            VIDEO_MOD_TA        => VIDEO_MOD_TA,
-
-            VD_VZ               => VD_VZ,
-            SR_FIFO_WRE         => SR_FIFO_WRE,
-            SR_VDMP             => SR_VDMP,
-            FIFO_MW             => FIFO_MW,
-            VDM_SEL             => VDM_SEL,
-            VIDEO_RAM_CTR       => VIDEO_RAM_CTR,
-            FIFO_CLR            => FIFO_CLR,
-            VDM                 => VDM,
-            BLITTER_ON          => BLITTER_ON,
-            BLITTER_RUN         => BLITTER_RUN
-        );
-
-    I_INTHANDLER: INTHANDLER
-        port map(
-            CLK_MAIN            => CLK_MAIN,
-            RESETn              => RESETn,
-            FB_ADR              => FB_ADR,
-            FB_CSn              => FB_CSn(2 downto 1),
-            FB_OEn              => FB_OEn,
-            FB_SIZE0            => FB_SIZE(0),
-            FB_SIZE1            => FB_SIZE(1),
-            FB_WRn              => FB_WRn,
-            FB_AD_IN            => FB_AD,
-            FB_AD_OUT           => FB_AD_OUT_IH,
-            FB_AD_EN_31_24      => FB_AD_EN_31_24_IH,
-            FB_AD_EN_23_16      => FB_AD_EN_23_16_IH,
-            FB_AD_EN_15_8       => FB_AD_EN_15_8_IH,
-            FB_AD_EN_7_0        => FB_AD_EN_7_0_IH,
-            PIC_INT             => PIC_INT,
-            E0_INT              => E0_INT,
-            DVI_INT             => DVI_INT,
-            PCI_INTAn           => PCI_INTAn,
-            PCI_INTBn           => PCI_INTBn,
-            PCI_INTCn           => PCI_INTCn,
-            PCI_INTDn           => PCI_INTDn,
-            MFP_INTn            => MFP_INTn,
-            DSP_INT             => DSP_INT,
-            VSYNC               => VSYNC_I,
-            HSYNC               => HSYNC_I,
-            DRQ_DMA             => DRQ_DMA,
-            IRQn                => IRQn,
-            INT_HANDLER_TA      => INT_HANDLER_TA,
-            FBEE_CONF           => FBEE_CONF,
-            TIN0                => TIN0
-        );
-
-    I_DMA: FBEE_DMA
-        port map(
-            RESET               => not RESETn,
-            CLK_MAIN            => CLK_MAIN,
-            CLK_FDC             => CLK_FDC,
-
-            FB_ADR              => FB_ADR(26 downto 0),
-            FB_ALE              => FB_ALE,
-            FB_SIZE             => FB_SIZE,
-            FB_CSn              => FB_CSn(2 downto 1),
-            FB_OEn              => FB_OEn,
-            FB_WRn              => FB_WRn,
-            FB_AD_IN            => FB_AD,
-            FB_AD_OUT           => FB_AD_OUT_DMA,
-            FB_AD_EN_31_24      => FB_AD_EN_31_24_DMA,
-            FB_AD_EN_23_16      => FB_AD_EN_23_16_DMA,
-            FB_AD_EN_15_8       => FB_AD_EN_15_8_DMA,
-            FB_AD_EN_7_0        => FB_AD_EN_7_0_DMA,
-
-            ACSI_DIR            => ACSI_DIR,
-            ACSI_D_IN           => ACSI_D,
-            ACSI_D_OUT          => ACSI_D_OUT,
-            ACSI_D_EN           => ACSI_D_EN,
-            ACSI_CSn            => ACSI_CSn,
-            ACSI_A1             => ACSI_A1,
-            ACSI_RESETn         => ACSI_RESETn,
-            ACSI_DRQn           => ACSI_DRQn,
-            ACSI_ACKn           => ACSI_ACKn,
-
-            DATA_IN_FDC         => DATA_OUT_FDC,
-            DATA_IN_SCSI        => DATA_OUT_SCSI,
-            DATA_OUT_FDC_SCSI	=> DATA_IN_FDC_SCSI,
-
-            DMA_DRQ_IN          => DRQ_FDC,
-            DMA_DRQ_OUT         => DRQ_DMA,            
-            DMA_DRQ11           => DRQ11_DMA,
-
-            SCSI_DRQ            => SCSI_DRQ,
-            SCSI_DACKn          => SCSI_DACKn,
-            SCSI_INT            => SCSI_INT,
-            SCSI_CSn            => SCSI_CSn,
-            SCSI_CS             => SCSI_CS,
-
-            CA                  => CA,
-            FLOPPY_HD_DD        => FDD_HD_DD,
-            WDC_BSL0            => WDC_BSL0,
-            FDC_CSn             => FDC_CSn,
-            FDC_WRn             => FDC_WRn,
-            FD_INT              => FD_INT,
-            IDE_INT             => IDE_INT,
-            DMA_CS              => DMA_CS
-        );
-
-    I_IDE_CF_SD_ROM: IDE_CF_SD_ROM
-        port map(
-            RESET               => not RESETn,
-            CLK_MAIN            => CLK_MAIN,
-
-            FB_ADR              => FB_ADR(19 downto 5),
-            FB_CS1n             => FB_CSn(1),
-            FB_WRn              => FB_WRn,
-            FB_B0               => FB_B0,
-            FB_B1               => FB_B1,
-
-            FBEE_CONF           => FBEE_CONF(31 downto 30),
-
-            RP_UDSn             => RP_UDSn,
-            RP_LDSn             => RP_LDSn,
-
-            SD_CLK              => SD_CLK,
-            SD_D0               => SD_D0,
-            SD_D1               => SD_D1,
-            SD_D2               => SD_D2,
-            SD_CD_D3_IN         => SD_D3,
-            SD_CD_D3_OUT        => SD_CD_D3_OUT,
-            SD_CD_D3_EN         => SD_CD_D3_EN,
-            SD_CMD_D1_IN        => SD_CMD_D1,
-            SD_CMD_D1_OUT       => SD_CMD_D1_OUT,
-            SD_CMD_D1_EN        => SD_CMD_D1_EN,
-            SD_CARD_DETECT      => SD_CARD_DETECT,
-            SD_WP               => SD_WP,
-
-            IDE_RDY             => IDE_RDY,
-            IDE_WRn             => IDE_WRn,
-            IDE_RDn             => IDE_RDn,
-            IDE_CSn             => IDE_CSn,
-            -- IDE_DRQn         =>, -- Not used.
-            IDE_CF_TA           => IDE_CF_TA,
-
-            ROM4n               => ROM4n,
-            ROM3n               => ROM3n,
-
-            CF_WP               => CF_WP,
-            CF_CSn              => CF_CSn
-        );
-
-    I_DSP: DSP
-        port map(
-            CLK_33M             => CLK_33M,
-            CLK_MAIN            => CLK_MAIN,
-            FB_OEn              => FB_OEn,
-            FB_WRn              => FB_WRn,
-            FB_CS1n             => FB_CSn(1),
-            FB_CS2n             => FB_CSn(2),
-            FB_SIZE0            => FB_SIZE(0),
-            FB_SIZE1            => FB_SIZE(1),
-            FB_BURSTn           => FB_BURSTn,
-            FB_ADR              => FB_ADR,
-            RESETn              => RESETn,
-            FB_CS3n             => FB_CSn(3),
-            SRCSn               => DSP_SRCSn,
-            SRBLEn              => DSP_SRBLEn,
-            SRBHEn              => DSP_SRBHEn,
-            SRWEn               => DSP_SRWEn,
-            SROEn               => DSP_SROEn,
-            DSP_INT             => DSP_INT,
-            DSP_TA              => DSP_TA,
-            FB_AD_IN            => FB_AD,
-            FB_AD_OUT           => FB_AD_OUT_DSP,
-            FB_AD_EN            => FB_AD_EN_DSP,
-            IO_IN               => DSP_IO,
-            IO_OUT              => DSP_IO_OUT,
-            IO_EN               => DSP_IO_EN,
-            SRD_IN              => DSP_SRD,
-            SRD_OUT             => DSP_SRD_OUT,
-            SRD_EN              => DSP_SRD_EN
-        );
-
-    I_SOUND: WF2149IP_TOP_SOC
+	I_DDR_CTRL: DDR_CTRL_V1
 		port map(
-            SYS_CLK				=> CLK_MAIN,
+			CLK_MAIN            => CLK_MAIN,
+			DDR_SYNC_66M        => DDR_SYNC_66M,
+			FB_ADR              => FB_ADR,
+			FB_CS1n             => FB_CSn(1),
+			FB_OEn              => FB_OEn,
+			FB_SIZE0            => FB_SIZE(0),
+			FB_SIZE1            => FB_SIZE(1),
+			FB_ALE              => FB_ALE,
+			FB_WRn              => FB_WRn,
+			BLITTER_ADR         => BLITTER_ADR,
+			BLITTER_SIG         => BLITTER_SIG,
+			BLITTER_WR          => BLITTER_WR,
+			SR_BLITTER_DACK     => BLITTER_DACK_SR,
+			BA                  => BA,
+			VA                  => VA,
+			FB_LE               => FB_LE,
+			CLK_33M             => CLK_33M,
+			VRASn               => VRASn,
+			VCASn               => VCASn,
+			VWEn                => VWEn,
+			VCSn                => VCSn,
+			FIFO_CLR            => FIFO_CLR,
+			DDRCLK0             => CLK_DDR(0),
+			VIDEO_RAM_CTR       => VIDEO_RAM_CTR,
+			VCKE                => VCKE,
+			DATA_IN             => FB_AD,
+			DATA_OUT            => DATA_OUT_DDR_CTRL,
+			DATA_EN_H           => DATA_EN_H_DDR_CTRL,
+			DATA_EN_L           => DATA_EN_L_DDR_CTRL,
+			VDM_SEL             => VDM_SEL,
+			FIFO_MW             => FIFO_MW,
+			FB_VDOE             => FB_VDOE,
+			SR_FIFO_WRE         => SR_FIFO_WRE,
+			SR_DDR_FB           => SR_DDR_FB,
+			SR_DDR_WR           => SR_DDR_WR,
+			SR_DDRWR_D_SEL      => SR_DDRWR_D_SEL,
+			SR_VDMP             => SR_VDMP,
+			VIDEO_DDR_TA        => VIDEO_DDR_TA,
+			DDRWR_D_SEL1        => DDRWR_D_SEL(1)
+		);
+
+	I_BLITTER: FBEE_BLITTER
+		port map(
+			RESETn               => RESETn,
+			CLK_MAIN            => CLK_MAIN,
+			CLK_DDR0            => CLK_DDR(0),
+			FB_ADR              => FB_ADR,
+			FB_ALE              => FB_ALE,
+			FB_SIZE1            => FB_SIZE(1),
+			FB_SIZE0            => FB_SIZE(0),
+			FB_CSn              => FB_CSn,
+			FB_OEn              => FB_OEn,
+			FB_WRn              => FB_WRn,
+			DATA_IN             => FB_AD,
+			DATA_OUT            => DATA_OUT_BLITTER,
+			DATA_EN             => DATA_EN_BLITTER,
+			BLITTER_ADR         => BLITTER_ADR,
+			BLITTER_SIG         => BLITTER_SIG,
+			BLITTER_WR          => BLITTER_WR,
+			BLITTER_ON          => BLITTER_ON,
+			BLITTER_RUN         => BLITTER_RUN,
+			BLITTER_DIN         => VD_VZ,
+			BLITTER_DOUT        => BLITTER_DOUT,
+			BLITTER_TA          => BLITTER_TA,
+			BLITTER_DACK_SR     => BLITTER_DACK_SR
+		);
+
+	I_VIDEOSYSTEM: VIDEO_SYSTEM
+		port map(
+			CLK_MAIN            => CLK_MAIN,
+			CLK_33M             => CLK_33M,
+			CLK_25M             => CLK_25M_I,
+			CLK_VIDEO           => CLK_VIDEO,
+			CLK_DDR3            => CLK_DDR(3),
+			CLK_DDR2            => CLK_DDR(2),
+			CLK_DDR0            => CLK_DDR(0),
+			CLK_PIXEL           => CLK_PIXEL_I,
+
+			VR_D                => VR_D,
+			VR_BUSY             => VR_BUSY,
+
+			FB_ADR              => FB_ADR,
+			FB_AD_IN            => FB_AD,
+			FB_AD_OUT           => FB_AD_OUT_VIDEO,
+			FB_AD_EN_31_16      => FB_AD_EN_31_16_VIDEO,
+			FB_AD_EN_15_0       => FB_AD_EN_15_0_VIDEO,
+			FB_ALE              => FB_ALE,
+			FB_CSn              => FB_CSn,
+			FB_OEn              => FB_OEn,
+			FB_WRn              => FB_WRn,
+			FB_SIZE1            => FB_SIZE(1),
+			FB_SIZE0            => FB_SIZE(0),
+
+			VDP_IN              => VDP_IN,
+
+			VR_RD               => VR_RD,
+			VR_WR               => VR_WR,
+			VIDEO_RECONFIG      => VIDEO_RECONFIG,
+
+			RED                 => VR,
+			GREEN               => VG,
+			BLUE                => VB,
+			VSYNC               => VSYNC_I,
+			HSYNC               => HSYNC_I,
+			SYNCn               => SYNCn,
+			BLANKn              => BLANK_In,
+
+			PD_VGAn             => PD_VGAn,
+			VIDEO_MOD_TA        => VIDEO_MOD_TA,
+
+			VD_VZ               => VD_VZ,
+			SR_FIFO_WRE         => SR_FIFO_WRE,
+			SR_VDMP             => SR_VDMP,
+			FIFO_MW             => FIFO_MW,
+			VDM_SEL             => VDM_SEL,
+			VIDEO_RAM_CTR       => VIDEO_RAM_CTR,
+			FIFO_CLR            => FIFO_CLR,
+			VDM                 => VDM,
+			BLITTER_ON          => BLITTER_ON,
+			BLITTER_RUN         => BLITTER_RUN
+		);
+
+	I_INTHANDLER: INTHANDLER
+		port map(
+			CLK_MAIN            => CLK_MAIN,
+			RESETn              => RESETn,
+			FB_ADR              => FB_ADR,
+			FB_CSn              => FB_CSn(2 downto 1),
+			FB_OEn              => FB_OEn,
+			FB_SIZE0            => FB_SIZE(0),
+			FB_SIZE1            => FB_SIZE(1),
+			FB_WRn              => FB_WRn,
+			FB_AD_IN            => FB_AD,
+			FB_AD_OUT           => FB_AD_OUT_IH,
+			FB_AD_EN_31_24      => FB_AD_EN_31_24_IH,
+			FB_AD_EN_23_16      => FB_AD_EN_23_16_IH,
+			FB_AD_EN_15_8       => FB_AD_EN_15_8_IH,
+			FB_AD_EN_7_0        => FB_AD_EN_7_0_IH,
+			PIC_INT             => PIC_INT,
+			E0_INT              => E0_INT,
+			DVI_INT             => DVI_INT,
+			PCI_INTAn           => PCI_INTAn,
+			PCI_INTBn           => PCI_INTBn,
+			PCI_INTCn           => PCI_INTCn,
+			PCI_INTDn           => PCI_INTDn,
+			MFP_INTn            => MFP_INTn,
+			DSP_INT             => DSP_INT,
+			VSYNC               => VSYNC_I,
+			HSYNC               => HSYNC_I,
+			DRQ_DMA             => DRQ_DMA,
+			IRQn                => IRQn,
+			INT_HANDLER_TA      => INT_HANDLER_TA,
+			FBEE_CONF           => FBEE_CONF,
+			TIN0                => TIN0
+		);
+
+	I_DMA: FBEE_DMA
+		port map(
+			RESET               => not RESETn,
+			CLK_MAIN            => CLK_MAIN,
+			CLK_FDC             => CLK_FDC,
+
+			FB_ADR              => FB_ADR(26 downto 0),
+			FB_ALE              => FB_ALE,
+			FB_SIZE             => FB_SIZE,
+			FB_CSn              => FB_CSn(2 downto 1),
+			FB_OEn              => FB_OEn,
+			FB_WRn              => FB_WRn,
+			FB_AD_IN            => FB_AD,
+			FB_AD_OUT           => FB_AD_OUT_DMA,
+			FB_AD_EN_31_24      => FB_AD_EN_31_24_DMA,
+			FB_AD_EN_23_16      => FB_AD_EN_23_16_DMA,
+			FB_AD_EN_15_8       => FB_AD_EN_15_8_DMA,
+			FB_AD_EN_7_0        => FB_AD_EN_7_0_DMA,
+
+			ACSI_DIR            => ACSI_DIR,
+			ACSI_D_IN           => ACSI_D,
+			ACSI_D_OUT          => ACSI_D_OUT,
+			ACSI_D_EN           => ACSI_D_EN,
+			ACSI_CSn            => ACSI_CSn,
+			ACSI_A1             => ACSI_A1,
+			ACSI_RESETn         => ACSI_RESETn,
+			ACSI_DRQn           => ACSI_DRQn,
+			ACSI_ACKn           => ACSI_ACKn,
+
+			DATA_IN_FDC         => DATA_OUT_FDC,
+			DATA_IN_SCSI        => DATA_OUT_SCSI,
+			DATA_OUT_FDC_SCSI	=> DATA_IN_FDC_SCSI,
+
+			DMA_DRQ_IN          => DRQ_FDC,
+			DMA_DRQ_OUT         => DRQ_DMA,            
+			DMA_DRQ11           => DRQ11_DMA,
+
+			SCSI_DRQ            => SCSI_DRQ,
+			SCSI_DACKn          => SCSI_DACKn,
+			SCSI_INT            => SCSI_INT,
+			SCSI_CSn            => SCSI_CSn,
+			SCSI_CS             => SCSI_CS,
+
+			CA                  => CA,
+			FLOPPY_HD_DD        => FDD_HD_DD,
+			WDC_BSL0            => WDC_BSL0,
+			FDC_CSn             => FDC_CSn,
+			FDC_WRn             => FDC_WRn,
+			FD_INT              => FD_INT,
+			IDE_INT             => IDE_INT,
+			DMA_CS              => DMA_CS
+		);
+
+	I_IDE_CF_SD_ROM: IDE_CF_SD_ROM
+		port map(
+			RESET               => not RESETn,
+			CLK_MAIN            => CLK_MAIN,
+
+			FB_ADR              => FB_ADR(19 downto 5),
+			FB_CS1n             => FB_CSn(1),
+			FB_WRn              => FB_WRn,
+			FB_B0               => FB_B0,
+			FB_B1               => FB_B1,
+
+			FBEE_CONF           => FBEE_CONF(31 downto 30),
+
+			RP_UDSn             => RP_UDSn,
+			RP_LDSn             => RP_LDSn,
+
+			SD_CLK              => SD_CLK,
+			SD_D0               => SD_D0,
+			SD_D1               => SD_D1,
+			SD_D2               => SD_D2,
+			SD_CD_D3_IN         => SD_D3,
+			SD_CD_D3_OUT        => SD_CD_D3_OUT,
+			SD_CD_D3_EN         => SD_CD_D3_EN,
+			SD_CMD_D1_IN        => SD_CMD_D1,
+			SD_CMD_D1_OUT       => SD_CMD_D1_OUT,
+			SD_CMD_D1_EN        => SD_CMD_D1_EN,
+			SD_CARD_DETECT      => SD_CARD_DETECT,
+			SD_WP               => SD_WP,
+
+			IDE_RDY             => IDE_RDY,
+			IDE_WRn             => IDE_WRn,
+			IDE_RDn             => IDE_RDn,
+			IDE_CSn             => IDE_CSn,
+			-- IDE_DRQn         =>, -- Not used.
+			IDE_CF_TA           => IDE_CF_TA,
+
+			ROM4n               => ROM4n,
+			ROM3n               => ROM3n,
+
+			CF_WP               => CF_WP,
+			CF_CSn              => CF_CSn
+		);
+
+	I_DSP: DSP
+		port map(
+			CLK_33M             => CLK_33M,
+			CLK_MAIN            => CLK_MAIN,
+			FB_OEn              => FB_OEn,
+			FB_WRn              => FB_WRn,
+			FB_CS1n             => FB_CSn(1),
+			FB_CS2n             => FB_CSn(2),
+			FB_SIZE0            => FB_SIZE(0),
+			FB_SIZE1            => FB_SIZE(1),
+			FB_BURSTn           => FB_BURSTn,
+			FB_ADR              => FB_ADR,
+			RESETn              => RESETn,
+			FB_CS3n             => FB_CSn(3),
+			SRCSn               => DSP_SRCSn,
+			SRBLEn              => DSP_SRBLEn,
+			SRBHEn              => DSP_SRBHEn,
+			SRWEn               => DSP_SRWEn,
+			SROEn               => DSP_SROEn,
+			DSP_INT             => DSP_INT,
+			DSP_TA              => DSP_TA,
+			FB_AD_IN            => FB_AD,
+			FB_AD_OUT           => FB_AD_OUT_DSP,
+			FB_AD_EN            => FB_AD_EN_DSP,
+			IO_IN               => DSP_IO,
+			IO_OUT              => DSP_IO_OUT,
+			IO_EN               => DSP_IO_EN,
+			SRD_IN              => DSP_SRD,
+			SRD_OUT             => DSP_SRD_OUT,
+			SRD_EN              => DSP_SRD_EN
+		);
+
+	I_SOUND: WF2149IP_TOP_SOC
+		port map(
+			SYS_CLK				=> CLK_MAIN,
 			RESETn				=> RESETn,
 
 			WAV_CLK				=> CLK_2M0,
 			SELn				=> '1',
 
-            BDIR				=> SNDIR_I,
+			BDIR				=> SNDIR_I,
 			BC2					=> '1',
-            BC1					=> SNDCS_I,
+			BC1					=> SNDCS_I,
 
 			A9n					=> '0',
 			A8					=> '1',
-            DA_IN				=> FB_AD(31 downto 24),
-            DA_OUT 				=> DA_OUT_X,
+			DA_IN				=> FB_AD(31 downto 24),
+			DA_OUT 				=> DA_OUT_X,
 
 			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
-            IO_A_OUT(7)			=> IDE_RES_I,
-            IO_A_OUT(6)			=> LP_DIR_X,
-            IO_A_OUT(5)			=> LP_STR,
-            IO_A_OUT(4)			=> DTR,
-            IO_A_OUT(3)			=> RTS,
-            IO_A_OUT(2)		    => RESERVED_1,
-            IO_A_OUT(1)			=> DSA_D,
-            IO_A_OUT(0)			=> FDD_SDSELn,
-            -- IO_A_EN			=> TOUT0n, -- Not required.
-            IO_B_IN				=> LP_D,
-            IO_B_OUT			=> LP_D_X,
-            -- IO_B_EN			=> -- Not used.
+			IO_A_OUT(7)			=> IDE_RES_I,
+			IO_A_OUT(6)			=> LP_DIR_X,
+			IO_A_OUT(5)			=> LP_STR,
+			IO_A_OUT(4)			=> DTR,
+			IO_A_OUT(3)			=> RTS,
+			IO_A_OUT(2)		    => RESERVED_1,
+			IO_A_OUT(1)			=> DSA_D,
+			IO_A_OUT(0)			=> FDD_SDSELn,
+			-- IO_A_EN			=> TOUT0n, -- Not required.
+			IO_B_IN				=> LP_D,
+			IO_B_OUT			=> LP_D_X,
+			-- IO_B_EN			=> -- Not used.
 
 			OUT_A				=> YM_QA,
 			OUT_B				=> YM_QB,
@@ -1110,50 +1110,50 @@ begin
 	I_MFP: WF68901IP_TOP_SOC
 		port map(  
 			-- System control:
-            CLK					=> CLK_MAIN,
+			CLK					=> CLK_MAIN,
 			RESETn				=> RESETn,
 			-- Asynchronous bus control:
-            DSn					=> not LDS,
-            CSn					=> not MFP_CS,
-            RWn					=> FB_WRn,
-            DTACKn				=> DTACK_OUT_MFPn,
-            -- Data and Adresses:
-            RS					=> FB_ADR(5 downto 1),
-            DATA_IN				=> FB_AD(23 downto 16),
-            DATA_OUT			=> DATA_OUT_MFP,
-            -- DATA_EN			=> DATA_EN_MFP, -- Not used.
-            GPIP_IN(7)			=> not DRQ11_DMA,
-            GPIP_IN(6)			=> not RI,
-            GPIP_IN(5)			=> DINTn,
-            GPIP_IN(4)			=> ACIA_IRQn,
-            GPIP_IN(3)			=> DSP_INT,
-            GPIP_IN(2)			=> not CTS,
-            GPIP_IN(1)			=> not DCD,
-            GPIP_IN(0)			=> LP_BUSY,
-            -- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
-            -- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
-            -- Interrupt control:
-            IACKn				=> not MFP_INTACK,
-            IEIn				=> '0',
-            -- IEOn				=>, -- Not used.
-            IRQn				=> MFP_INTn,
-            -- Timers and timer control:
-            XTAL1				=> CLK_2M4576,
-            TAI					=> '0',
-            TBI				   	=> BLANK_In,
-            -- TAO				=>,
-            -- TBO				=>,
-            -- TCO				=>,
-            TDO					=> TDO,
-            -- Serial I/O control:
-            RC					=> TDO,
-            TC					=> TDO,
-            SI					=> RxD, 
-            SO					=> TxD
-            -- SO_EN			=> -- Not used.
-            -- DMA control:
-            -- RRn				=> -- Not used.
-            -- TRn				=> -- Not used.
+			DSn					=> not LDS,
+			CSn					=> not MFP_CS,
+			RWn					=> FB_WRn,
+			DTACKn				=> DTACK_OUT_MFPn,
+			-- Data and Adresses:
+			RS					=> FB_ADR(5 downto 1),
+			DATA_IN				=> FB_AD(23 downto 16),
+			DATA_OUT			=> DATA_OUT_MFP,
+			-- DATA_EN			=> DATA_EN_MFP, -- Not used.
+			GPIP_IN(7)			=> not DRQ11_DMA,
+			GPIP_IN(6)			=> not RI,
+			GPIP_IN(5)			=> DINTn,
+			GPIP_IN(4)			=> ACIA_IRQn,
+			GPIP_IN(3)			=> DSP_INT,
+			GPIP_IN(2)			=> not CTS,
+			GPIP_IN(1)			=> not DCD,
+			GPIP_IN(0)			=> LP_BUSY,
+			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
+			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
+			-- Interrupt control:
+			IACKn				=> not MFP_INTACK,
+			IEIn				=> '0',
+			-- IEOn				=>, -- Not used.
+			IRQn				=> MFP_INTn,
+			-- Timers and timer control:
+			XTAL1				=> CLK_2M4576,
+			TAI					=> '0',
+			TBI				   	=> BLANK_In,
+			-- TAO				=>,
+			-- TBO				=>,
+			-- TCO				=>,
+			TDO					=> TDO,
+			-- Serial I/O control:
+			RC					=> TDO,
+			TC					=> TDO,
+			SI					=> RxD, 
+			SO					=> TxD
+			-- SO_EN			=> -- Not used.
+			-- DMA control:
+			-- RRn				=> -- Not used.
+			-- TRn				=> -- Not used.
 		);
 
 	I_ACIA_MIDI: WF6850IP_TOP_SOC
@@ -1163,52 +1163,52 @@ begin
 
 			CS2n				=> '0',
 			CS1					=> FB_ADR(2),
-            CS0					=> ACIA_CS,
-            E					=> ACIA_CS,
-            RWn					=> FB_WRN,
-            RS					=> FB_ADR(1),
+			CS0					=> ACIA_CS,
+			E					=> ACIA_CS,
+			RWn					=> FB_WRN,
+			RS					=> FB_ADR(1),
 
-            DATA_IN				=> FB_AD(31 downto 24),
-            DATA_OUT			=> DATA_OUT_ACIA_II,
-            -- DATA_EN				=> -- Not used.
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_II,
+			-- DATA_EN				=> -- Not used.
 
-            TXCLK				=> CLK_500K,
-            RXCLK				=> CLK_500K,
-            RXDATA				=> MIDI_IN,
-            CTSn				=> '0',
-            DCDn				=> '0',
+			TXCLK				=> CLK_500K,
+			RXCLK				=> CLK_500K,
+			RXDATA				=> MIDI_IN,
+			CTSn				=> '0',
+			DCDn				=> '0',
 
-            IRQn				=> IRQ_MIDIn,
-            TXDATA				=> MIDI_OUT
-            --RTSn				=> -- Not used.
-	    );                                              
+			IRQn				=> IRQ_MIDIn,
+			TXDATA				=> MIDI_OUT
+			--RTSn				=> -- Not used.
+		);                                              
 
-    I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
-        port map(
+	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
+		port map(
 			CLK					=> CLK_MAIN,
 			RESETn				=> RESETn,
 
 			CS2n				=> FB_ADR(2),
 			CS1					=> '1',
-            CS0					=> ACIA_CS,
-            E					=> ACIA_CS,
-            RWn					=> FB_WRn,
-            RS					=> FB_ADR(1),
+			CS0					=> ACIA_CS,
+			E					=> ACIA_CS,
+			RWn					=> FB_WRn,
+			RS					=> FB_ADR(1),
 
-            DATA_IN				=> FB_AD(31 downto 24),
-            DATA_OUT			=> DATA_OUT_ACIA_I,
-            -- DATA_EN				=> Not used.
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_I,
+			-- DATA_EN				=> Not used.
 
-            TXCLK				=> CLK_500K,
-            RXCLK				=> CLK_500K,
-            RXDATA				=> KEYB_RxD,
+			TXCLK				=> CLK_500K,
+			RXCLK				=> CLK_500K,
+			RXDATA				=> KEYB_RxD,
 
-            CTSn				=> '0',
-            DCDn				=> '0',
+			CTSn				=> '0',
+			DCDn				=> '0',
 
-            IRQn				=> IRQ_KEYBDn,
-            TXDATA				=> AMKB_TX
-            --RTSn				=> -- Not used.
+			IRQn				=> IRQ_KEYBDn,
+			TXDATA				=> AMKB_TX
+			--RTSn				=> -- Not used.
 		);                                              
 
 	I_SCSI: WF5380_TOP_SOC
diff --git a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
index e02861e..4011cea 100644
--- a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
+++ b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
@@ -156,8 +156,8 @@ architecture BEHAVIOUR of VIDEO_CTRL is
 	signal VERZ_2                   : std_logic_vector(9 downto 0);
 	signal VERZ_1                   : std_logic_vector(9 downto 0);
 	signal VERZ_0                   : std_logic_vector(9 downto 0);
-	signal RAND                     : std_logic_vector(6 downto 0);
-	signal RAND_ON                  : std_logic;
+	signal BORDER                     : std_logic_vector(6 downto 0);
+	signal BORDER_ON                : std_logic;
 	signal START_ZEILE              : std_logic;
 	signal SYNC_PIX                 : std_logic;
 	signal SYNC_PIX1                : std_logic;
@@ -310,7 +310,7 @@ begin
 
 	P_VIDEO_CONTROL : process
 	begin
-		wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
 		if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(0) = '1' then
 			ST_SHIFT_MODE <= DATA_IN(25 downto 24);
 		end if;
@@ -418,6 +418,7 @@ begin
 	COLOR2 <= COLOR2_I;
 	COLOR4 <= COLOR4_I;
 	COLOR8 <= COLOR8_I;
+	
 	-- VIDEO PLL config and reconfig:
 	VIDEO_PLL_CONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_B(1) = '1' and FB_ADR(27 downto 9) = "0000000000000000011" else '0'; -- $(F)000'0600-7FF -> 6/2 word and long only.
 	VIDEO_PLL_RECONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_ADR(27 downto 0) = x"0000800" else '0'; -- $(F)000'0800. 
@@ -426,7 +427,8 @@ begin
 	P_VIDEO_CONFIG: process
 		variable LOCK : boolean;
 	begin
-		wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
+
 		if VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and VR_WR_I = '0' then
 			VR_WR_I <= '1'; -- This is a strobe.
 		else
@@ -452,507 +454,506 @@ begin
 		end if;
 	end process P_VIDEO_CONFIG;
     
-    VIDEO_RAM_CTR <= FBEE_VCTR(31 downto 16);
+	VIDEO_RAM_CTR <= FBEE_VCTR(31 downto 16);
     
-    -- Firebee colour modi: 
-    FBEE_CLUT <= '1' when FBEE_VIDEO_ON = '1' and (COLOR1_I = '1' or COLOR8_I = '1') else
-                 '1' when ST_VIDEO = '1' and COLOR1_I = '1';
+	-- Firebee colour modi: 
+	FBEE_CLUT <= '1' when FBEE_VIDEO_ON = '1' and (COLOR1_I = '1' or COLOR8_I = '1') else
+						'1' when ST_VIDEO = '1' and COLOR1_I = '1';
                  
-    FALCON_VIDEO <= FBEE_VCTR(7);
-    FALCON_CLUT <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and COLOR16_I = '0' else '0';
-    ST_VIDEO <= FBEE_VCTR(6);
-    ST_CLUT <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_CLUT = '0' and COLOR1_I = '0' else '0';
+	FALCON_VIDEO <= FBEE_VCTR(7);
+	FALCON_CLUT <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and COLOR16_I = '0' else '0';
+	ST_VIDEO <= FBEE_VCTR(6);
+	ST_CLUT <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_CLUT = '0' and COLOR1_I = '0' else '0';
 
     -- Several (video)-registers:
-    CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR = x"f0000404" else '0';	-- $F0000404 - Firebee video border color
-    SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0';	-- $FF8006 - Falcon monitor type register
-    VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo.
-    VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo.
-    VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo.
-    VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo.
-    VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo.
-    VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo.
-    VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo.
-    VDL_HSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000110" else '0'; -- $828C/2.
-    VDL_VBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010011" else '0'; -- $82A6/2.
-    VDL_VDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010100" else '0'; -- $82A8/2.
-    VDL_VDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010101" else '0'; -- $82AA/2.
-    VDL_VBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010010" else '0'; -- $82A4/2.
-    VDL_VSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010110" else '0'; -- $82AC/2.
-    VDL_VFT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010001" else '0'; -- $82A2/2.
-    VDL_VCT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101100000" else '0'; -- $82C0/2.
-    VDL_VMD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101100001" else '0'; -- $82C2/2.
+	CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR = x"f0000404" else '0';	-- $F0000404 - Firebee video border color
+	SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0';	-- $FF8006 - Falcon monitor type register
+	VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo.
+	VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo.
+	VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo.
+	VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo.
+	VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo.
+	VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo.
+	VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo.
+	VDL_HSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828c" else '0'; -- $FF828C/D - position hsync (HSS).
+	VDL_VFT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a2" else '0'; -- $FF82A2/3 - video frequency timer (VFT).
+	VDL_VBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) & '0' = x"ff82a4" else '0'; -- $FF82A4/5 - vertical blank on (in half line steps).
+	VDL_VBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a6" else '0'; -- $FF82A6/7 - vertical blank off (in half line steps).
+	VDL_VDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82a8" else '0'; -- $FF82A8/9 - vertical display begin (VDB).
+	VDL_VDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82aa" else '0'; -- $FF82AA/B - vertical display end (VDE).
+	VDL_VSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82ac" else '0'; -- $FF82AC/D - position vsync (VSS).
+	VDL_VCT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c0" else '0'; -- $FF82C0/1 - clock control (VCO).
+	VDL_VMD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff82c2" else '0'; -- $FF82C2/3 - resolution control.
 
-    P_MISC_CTRL : process
-    begin
-        wait until CLK_MAIN = '1' and CLK_MAIN' event;
-		  
-        -- Colour of video borders
-        if CCR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            CCR_I(23 downto 16) <= DATA_IN(23 downto 16);
-        elsif CCR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            CCR_I(15 downto 8) <= DATA_IN(15 downto 8);
-        elsif CCR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            CCR_I(7 downto 0) <= DATA_IN(7 downto 0);
-        end if;
+	P_MISC_CTRL : process
+	begin
+		wait until rising_edge(CLK_MAIN);
+        
+		-- Colour of video borders
+		if CCR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			CCR_I(23 downto 16) <= DATA_IN(23 downto 16);
+		elsif CCR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			CCR_I(15 downto 8) <= DATA_IN(15 downto 8);
+		elsif CCR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			CCR_I(7 downto 0) <= DATA_IN(7 downto 0);
+		end if;
 
-        --SYS CTRL:
-        if SYS_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            SYS_CTR <= DATA_IN(22 downto 16);
-        end if;
+		-- SYS CTRL:
+		if SYS_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			SYS_CTR <= DATA_IN(22 downto 16);
+		end if;
 
-        --VDL_LOF:
-        if VDL_LOF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_LOF(15 downto 8) <= DATA_IN(31 downto 24);
-        elsif VDL_LOF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_LOF(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		--VDL_LOF:
+		if VDL_LOF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			VDL_LOF(15 downto 8) <= DATA_IN(31 downto 24);
+		elsif VDL_LOF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_LOF(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        --VDL_LWD
-        if VDL_LWD_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_LWD(15 downto 8) <= DATA_IN(31 downto 24);
-        elsif VDL_LWD_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_LWD(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		--VDL_LWD
+		if VDL_LWD_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_LWD(15 downto 8) <= DATA_IN(31 downto 24);
+		elsif VDL_LWD_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_LWD(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- Horizontal:
-        -- VDL_HHT:
-        if VDL_HHT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_HHT(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HHT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_HHT(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- Horizontal:
+		-- VDL_HHT:
+		if VDL_HHT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			VDL_HHT(11 downto 8) <= DATA_IN(27 downto 24);
+		elsif VDL_HHT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_HHT(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_HBE:
-        if VDL_HBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_HBE(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_HBE(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_HBE:
+		if VDL_HBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			VDL_HBE(11 downto 8) <= DATA_IN(27 downto 24);
+		elsif VDL_HBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_HBE(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_HDB:
-        if VDL_HDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_HDB(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_HDB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_HDB:
+		if VDL_HDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_HDB(11 downto 8) <= DATA_IN(27 downto 24);
+		elsif VDL_HDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_HDB(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_HDE:
-        if VDL_HDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_HDE(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_HDE(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_HDE:
+		if VDL_HDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			VDL_HDE(11 downto 8) <= DATA_IN(27 downto 24);
+		elsif VDL_HDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_HDE(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_HBB:
-        if VDL_HBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_HBB(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_HBB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_HBB:
+		if VDL_HBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_HBB(11 downto 8) <= DATA_IN(27 downto 24);
+		elsif VDL_HBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_HBB(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_HSS:
-        if VDL_HSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_HSS(11 downto 8) <= DATA_IN(27 downto 24);
-        elsif VDL_HSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_HSS(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_HSS:
+		if VDL_HSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_HSS(11 downto 8) <= DATA_IN(27 downto 24);
+		elsif VDL_HSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_HSS(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- Vertical:
-        -- VDL_VBE:
-        if VDL_VBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_VBE(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_VBE(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- Vertical:
+		-- VDL_VBE:
+		if VDL_VBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			VDL_VBE(10 downto 8) <= DATA_IN(26 downto 24);
+		elsif VDL_VBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_VBE(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_VDB:
-        if VDL_VDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VDB(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VDB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
-        -- VDL_VDE:
-        if VDL_VDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_VDE(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_VDE(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_VDB:
+		if VDL_VDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_VDB(10 downto 8) <= DATA_IN(26 downto 24);
+		elsif VDL_VDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_VDB(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
+        
+		-- VDL_VDE:
+		if VDL_VDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			VDL_VDE(10 downto 8) <= DATA_IN(26 downto 24);
+		elsif VDL_VDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_VDE(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_VBB:
-        if VDL_VBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VBB(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VBB(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_VBB:
+		if VDL_VBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_VBB(10 downto 8) <= DATA_IN(26 downto 24);
+		elsif VDL_VBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_VBB(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_VSS
-        if VDL_VSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VSS(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VSS(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_VSS
+		if VDL_VSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_VSS(10 downto 8) <= DATA_IN(26 downto 24);
+		elsif VDL_VSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_VSS(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_VFT
-        if VDL_VFT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
-            VDL_VFT(10 downto 8) <= DATA_IN(26 downto 24);
-        elsif VDL_VFT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_VFT(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_VFT
+		if VDL_VFT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
+			VDL_VFT(10 downto 8) <= DATA_IN(26 downto 24);
+		elsif VDL_VFT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_VFT(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_VCT(2): 1 = 32MHz CLK_PIXEL, 0 = 25MHZ; VDL_VCT(0): 1 = linedoubling.
-        if VDL_VCT_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
-            VDL_VCT(8) <= DATA_IN(24);
-        elsif VDL_VCT_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
-            VDL_VCT(7 downto 0) <= DATA_IN(23 downto 16);
-        end if;
+		-- VDL_VCT(2): 1 = 32MHz CLK_PIXEL, 0 = 25MHZ; VDL_VCT(0): 1 = linedoubling.
+		if VDL_VCT_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
+			VDL_VCT(8) <= DATA_IN(24);
+		elsif VDL_VCT_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
+			VDL_VCT(7 downto 0) <= DATA_IN(23 downto 16);
+		end if;
 
-        -- VDL_VMD(2): 1 = CLK_PIXEL/2.
-        if VDL_VMD_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
-            VDL_VMD <= DATA_IN(19 downto 16);
-        end if;
-    end process P_MISC_CTRL;
+		-- VDL_VMD(2): 1 = CLK_PIXEL/2.
+		if VDL_VMD_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
+			VDL_VMD <= DATA_IN(19 downto 16);
+		end if;
+	end process P_MISC_CTRL;
 
-    BLITTER_ON <= not SYS_CTR(3);
+	BLITTER_ON <= not SYS_CTR(3);
     
-    -- Register out:
-    DATA_OUT(31 downto 16) <= "000000" & ST_SHIFT_MODE & x"00" when ST_SHIFT_MODE_CS = '1' else
-                              "00000" & FALCON_SHIFT_MODE when FALCON_SHIFT_MODE_CS = '1' else
-                              "100000000" & SYS_CTR(6 downto 4) & not BLITTER_RUN & SYS_CTR(2 downto 0) when SYS_CTR_CS = '1' else
-                              VDL_LOF when VDL_LOF_CS = '1' else
-                              VDL_LWD when VDL_LWD_CS = '1' else
-                              x"0" & VDL_HBE when VDL_HBE_CS = '1' else
-                              x"0" & VDL_HDB when VDL_HDB_CS = '1' else
-                              x"0" & VDL_HDE when VDL_HDE_CS = '1' else
-                              x"0" & VDL_HBB when VDL_HBB_CS = '1' else
-                              x"0" & VDL_HSS when VDL_HSS_CS = '1' else
-                              x"0" & VDL_HHT when VDL_HHT_CS = '1' else
-                              "00000" & VDL_VBE when VDL_VBE_CS = '1' else
-                              "00000" & VDL_VDB when VDL_VDB_CS = '1' else
-                              "00000" & VDL_VDE when VDL_VDE_CS = '1' else
-                              "00000" & VDL_VBB when VDL_VBB_CS = '1' else
-                              "00000" & VDL_VSS when VDL_VSS_CS = '1' else
-                              "00000" & VDL_VFT when VDL_VFT_CS = '1' else
-                              "0000000" & VDL_VCT when VDL_VCT_CS = '1' else    
-                              x"000" & VDL_VMD when VDL_VMD_CS = '1' else
-                              FBEE_VCTR(31 downto 16) when FBEE_VCTR_CS = '1' else
-                              ATARI_HH(31 downto 16) when ATARI_HH_CS = '1' else
-                              ATARI_VH(31 downto 16) when ATARI_VH_CS = '1' else
-                              ATARI_HL(31 downto 16) when ATARI_HL_CS = '1' else
-                              ATARI_VL(31 downto 16) when ATARI_VL_CS = '1' else
-                              x"00" & CCR_I(23 downto 16) when CCR_CS = '1' else 
-                              "0000000" & VR_DOUT when VIDEO_PLL_CONFIG_CS = '1' else
-                              VR_BUSY & "0000" & VR_WR_I & VR_RD_I & VIDEO_RECONFIG_I & x"FA" when VIDEO_PLL_RECONFIG_CS = '1' else (others => '0');
+	-- Register out:
+	DATA_OUT(31 downto 16) <= "000000" & ST_SHIFT_MODE & x"00" when ST_SHIFT_MODE_CS = '1' else
+										"00000" & FALCON_SHIFT_MODE when FALCON_SHIFT_MODE_CS = '1' else
+										"100000000" & SYS_CTR(6 downto 4) & not BLITTER_RUN & SYS_CTR(2 downto 0) when SYS_CTR_CS = '1' else
+										VDL_LOF when VDL_LOF_CS = '1' else
+										VDL_LWD when VDL_LWD_CS = '1' else
+										x"0" & VDL_HBE when VDL_HBE_CS = '1' else
+										x"0" & VDL_HDB when VDL_HDB_CS = '1' else
+										x"0" & VDL_HDE when VDL_HDE_CS = '1' else
+										x"0" & VDL_HBB when VDL_HBB_CS = '1' else
+										x"0" & VDL_HSS when VDL_HSS_CS = '1' else
+										x"0" & VDL_HHT when VDL_HHT_CS = '1' else
+										"00000" & VDL_VBE when VDL_VBE_CS = '1' else
+										"00000" & VDL_VDB when VDL_VDB_CS = '1' else
+										"00000" & VDL_VDE when VDL_VDE_CS = '1' else
+										"00000" & VDL_VBB when VDL_VBB_CS = '1' else
+										"00000" & VDL_VSS when VDL_VSS_CS = '1' else
+										"00000" & VDL_VFT when VDL_VFT_CS = '1' else
+										"0000000" & VDL_VCT when VDL_VCT_CS = '1' else    
+										x"000" & VDL_VMD when VDL_VMD_CS = '1' else
+										FBEE_VCTR(31 downto 16) when FBEE_VCTR_CS = '1' else
+										ATARI_HH(31 downto 16) when ATARI_HH_CS = '1' else
+										ATARI_VH(31 downto 16) when ATARI_VH_CS = '1' else
+										ATARI_HL(31 downto 16) when ATARI_HL_CS = '1' else
+										ATARI_VL(31 downto 16) when ATARI_VL_CS = '1' else
+										x"00" & CCR_I(23 downto 16) when CCR_CS = '1' else 
+										"0000000" & VR_DOUT when VIDEO_PLL_CONFIG_CS = '1' else
+										VR_BUSY & "0000" & VR_WR_I & VR_RD_I & VIDEO_RECONFIG_I & x"FA" when VIDEO_PLL_RECONFIG_CS = '1' else (others => '0');
     
-    DATA_OUT(15 downto 0) <= FBEE_VCTR(15 downto 0) when FBEE_VCTR_CS = '1' else
-                             ATARI_HH(15 downto 0) when ATARI_HH_CS = '1' else
-                             ATARI_VH(15 downto 0) when ATARI_VH_CS = '1' else
-                             ATARI_HL(15 downto 0) when ATARI_HL_CS = '1' else
-                             ATARI_VL(15 downto 0) when ATARI_VL_CS = '1' else
-                             CCR_I(15 downto 0) when CCR_CS = '1' else (others => '0');
+	DATA_OUT(15 downto 0) <= FBEE_VCTR(15 downto 0) when FBEE_VCTR_CS = '1' else
+										ATARI_HH(15 downto 0) when ATARI_HH_CS = '1' else
+										ATARI_VH(15 downto 0) when ATARI_VH_CS = '1' else
+										ATARI_HL(15 downto 0) when ATARI_HL_CS = '1' else
+										ATARI_VL(15 downto 0) when ATARI_VL_CS = '1' else
+										CCR_I(15 downto 0) when CCR_CS = '1' else (others => '0');
 
-    DATA_EN_H <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or CCR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
-                  VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
-                  ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or VIDEO_PLL_RECONFIG_CS or
-                  VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS) and not FB_OEn;
+	DATA_EN_H <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or CCR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
+						VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
+						ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or VIDEO_PLL_RECONFIG_CS or
+						VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS) and not FB_OEn;
 
-    DATA_EN_L <= (FBEE_VCTR_CS or CCR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS ) and not FB_OEn;
+	DATA_EN_L <= (FBEE_VCTR_CS or CCR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS ) and not FB_OEn;
 
-    VIDEO_MOD_TA_I <= CLUT_TA or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
-                      VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
-                      ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or
-                      VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS;
+	VIDEO_MOD_TA_I <= CLUT_TA or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or FBEE_VCTR_CS or SYS_CTR_CS or VDL_LOF_CS or VDL_LWD_CS or
+							VDL_HBE_CS or VDL_HDB_CS or VDL_HDE_CS or VDL_HBB_CS or VDL_HSS_CS or VDL_HHT_CS or
+							ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or
+							VDL_VBE_CS or VDL_VDB_CS or VDL_VDE_CS or VDL_VBB_CS or VDL_VSS_CS or VDL_VFT_CS or VDL_VCT_CS or VDL_VMD_CS;
     
-    P_CLK_16M5 : process
-    begin
-        wait until CLK33M = '1' and CLK33M' event;
-        CLK17M <= not CLK17M;
-    end process P_CLK_16M5;
+	P_CLK_16M5 : process
+	begin
+		wait until rising_edge(CLK33M);
+		CLK17M <= not CLK17M;
+	end process P_CLK_16M5;
 
-    P_CLK_12M5 : process
-    begin
-        wait until CLK25M = '1' and CLK25M' event;
-        CLK13M <= not CLK13M;
-    end process P_CLK_12M5;
+	P_CLK_12M5 : process
+	begin
+		wait until rising_edge(CLK25M);
+		CLK13M <= not CLK13M;
+	end process P_CLK_12M5;
 
-    CLK_PIXEL_I <= CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' else
-                   CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' else
-                   CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' else
-                   CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' else
-                   CLK25M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' else
-                   CLK33M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' else
-                   CLK25M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" else
-                   CLK33M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" else
-                   CLK_VIDEO when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' else '0';
+	CLK_PIXEL_I <= CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' else
+						CLK13M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' else
+						CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' else
+						CLK17M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' else
+						CLK25M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' else
+						CLK33M when FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' else
+						CLK25M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" else
+						CLK33M when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" else
+						CLK_VIDEO when FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' else '0';
 
-    P_HSYN_LEN  : process
-    -- Horizontal SYNC in CLK_PIXEL:
-    begin
-        wait until CLK_MAIN = '1' and CLK_MAIN' event;
-        if FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' then
-            HSY_LEN <= x"0E";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' then
-            HSY_LEN <= x"0E";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' then
-            HSY_LEN <= x"10";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' then
-            HSY_LEN <= x"10";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' then
-            HSY_LEN <= x"1C";
-        elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' then
-            HSY_LEN <= x"20";
-        elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" then
-            HSY_LEN <= x"1C";
-        elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" then
-            HSY_LEN <= x"20";
-        elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' then
-            HSY_LEN <= std_logic_vector(unsigned'(x"10") + unsigned('0' & VR_FRQ(7 downto 1))); -- HSYNC pulse length in pixels = frequency/500ns.
-        else
-            HSY_LEN <= x"00";
-        end if;
-    end process P_HSYN_LEN;
+	P_HSYN_LEN  : process
+		-- Horizontal SYNC in CLK_PIXEL:
+	begin
+		wait until rising_edge(CLK_MAIN);
+		if FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(2) = '1' then
+			HSY_LEN <= x"0E";
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO = '1' or ST_VIDEO = '1') and VDL_VMD(2) = '1' and VDL_VCT(0) = '1' then
+			HSY_LEN <= x"0E";
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(2) = '0' then
+			HSY_LEN <= x"10";
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and VDL_VMD(2) = '1' and VDL_VCT(0) = '0' then
+			HSY_LEN <= x"10";
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '1' and VDL_VCT(0) = '0' then
+			HSY_LEN <= x"1C";
+		elsif FBEE_VIDEO_ON = '0' and (FALCON_VIDEO or ST_VIDEO) = '1' and  VDL_VMD(2) = '0' and VDL_VCT(2) = '0' and VDL_VCT(0) = '0' then
+			HSY_LEN <= x"20";
+		elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "00" then
+			HSY_LEN <= x"1C";
+		elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9 downto 8) = "01" then
+			HSY_LEN <= x"20";
+		elsif FBEE_VIDEO_ON = '1' and FBEE_VCTR(9) = '1' then
+			HSY_LEN <= std_logic_vector(unsigned'(x"10") + unsigned('0' & VR_FRQ(7 downto 1))); -- HSYNC pulse length in pixels = frequency/500ns.
+		else
+			HSY_LEN <= x"00";
+		end if;
+	end process P_HSYN_LEN;
 
-    MULF <= "000010" when ST_VIDEO = '0' and VDL_VMD(2) = '1' else -- Multiplier.
-            "000100" when ST_VIDEO = '0' and VDL_VMD(2) = '0' else
-            "010000" when ST_VIDEO = '1' and VDL_VMD(2) = '1' else
-            "100000" when ST_VIDEO = '1' and VDL_VMD(2) = '0' else "000000";
+	MULF <= "000010" when ST_VIDEO = '0' and VDL_VMD(2) = '1' else -- Multiplier.
+				"000100" when ST_VIDEO = '0' and VDL_VMD(2) = '0' else
+				"010000" when ST_VIDEO = '1' and VDL_VMD(2) = '1' else
+				"100000" when ST_VIDEO = '1' and VDL_VMD(2) = '0' else "000000";
 
-    HDIS_LEN <= x"140" when VDL_VMD(2) = '1' else x"280"; -- Width in pixels (320 / 640).
+	HDIS_LEN <= x"140" when VDL_VMD(2) = '1' else x"280"; -- Width in pixels (320 / 640).
 
-    P_DOUBLE_LINE_1   : process
-    begin
-        wait until CLK_MAIN = '1' and CLK_MAIN' event;
-        DOP_ZEI <= VDL_VMD(0) and ST_VIDEO; -- Line doubling on off.
-    end process P_DOUBLE_LINE_1;
+	P_DOUBLE_LINE_1   : process
+	begin
+		wait until rising_edge(CLK_MAIN);
+		DOP_ZEI <= VDL_VMD(0) and ST_VIDEO; -- Line doubling on off.
+	end process P_DOUBLE_LINE_1;
 
-    P_DOUBLE_LINE_2   : process
-    begin
-        wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I'event;
-        if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < std_logic_vector(unsigned(HDIS_END) - 1) then        
-            INTER_ZEI_I <= '1'; -- Switch insertion line to "double". Line zero due to SYNC.
-        elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > std_logic_vector(unsigned(HDIS_END) - 10) then
-            INTER_ZEI_I <= '1'; -- Switch insertion mode to "normal". Lines and line zero due to SYNC.
-        else
-            INTER_ZEI_I <= '0';
-        end if;
-        --
-        DOP_FIFO_CLR <= INTER_ZEI_I and HSYNC_START and SYNC_PIX; -- Double line info erase at the end of a double line and at main FIFO start.
-    end process P_DOUBLE_LINE_2;
+	P_DOUBLE_LINE_2   : process
+	begin
+		wait until rising_edge(CLK_PIXEL_I);
+		if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < std_logic_vector(unsigned(HDIS_END) - 1) then        
+			INTER_ZEI_I <= '1'; -- Switch insertion line to "double". Line zero due to SYNC.
+		elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > std_logic_vector(unsigned(HDIS_END) - 10) then
+			INTER_ZEI_I <= '1'; -- Switch insertion mode to "normal". Lines and line zero due to SYNC.
+		else
+			INTER_ZEI_I <= '0';
+		end if;
+		--
+		DOP_FIFO_CLR <= INTER_ZEI_I and HSYNC_START and SYNC_PIX; -- Double line info erase at the end of a double line and at main FIFO start.
+	end process P_DOUBLE_LINE_2;
 
     -- The following multiplications change every time the video resolution is changed.
-    MUL1 <= unsigned(VDL_HBE) * unsigned(MULF(5 downto 1));
-    MUL2 <= unsigned(VDL_HHT) + 1 + unsigned(VDL_HSS) * unsigned(MULF(5 downto 1));
-    MUL3 <= resize(unsigned(VDL_HHT) + 10 * unsigned(MULF(5 downto 1)), MUL3'length);
+	MUL1 <= unsigned(VDL_HBE) * unsigned(MULF(5 downto 1));
+	MUL2 <= unsigned(VDL_HHT) + 1 + unsigned(VDL_HSS) * unsigned(MULF(5 downto 1));
+	MUL3 <= resize(unsigned(VDL_HHT) + 10 * unsigned(MULF(5 downto 1)), MUL3'length);
 
-    BORDER_LEFT <= VDL_HBE when FBEE_VIDEO_ON = '1' else 
-                  x"015" when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-                  x"02A" when ATARI_SYNC = '1' else std_logic_vector(MUL1(16 downto 5));
-    HDIS_START <= VDL_HDB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + 1);
-    HDIS_END <= VDL_HDE when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + unsigned(HDIS_LEN));
-    BORDER_RIGHT <= VDL_HBB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(HDIS_END) + 1);
-    HS_START <= VDL_HSS when FBEE_VIDEO_ON = '1' else
-                ATARI_HL(11 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-                ATARI_HH(11 downto 0) when VDL_VMD(2) = '1' else std_logic_vector(MUL2(16 downto 5));
-    H_TOTAL <= VDL_HHT when FBEE_VIDEO_ON = '1' else
-               ATARI_HL(27 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-               ATARI_HH(27 downto 16) when ATARI_SYNC = '1' else std_logic_vector(MUL3(16 downto 5));
-    BORDER_TOP <= VDL_VBE when FBEE_VIDEO_ON = '1' else
-                 "00000011111" when ATARI_SYNC = '1' else '0' & VDL_VBE(10 downto 1);
-    VDIS_START <= VDL_VDB when FBEE_VIDEO_ON = '1' else
-                  "00000100000" when ATARI_SYNC = '1' else '0' & VDL_VDB(10 downto 1);
-    VDIS_END <= VDL_VDE when FBEE_VIDEO_ON = '1' else
-                "00110101111" when ATARI_SYNC = '1' and ST_VIDEO = '1' else -- 431.
-                "00111111111" when ATARI_SYNC = '1' else '0' & VDL_VDE(10 downto 1); -- 511.
-    BORDER_BOTTOM <= VDL_VBB when FBEE_VIDEO_ON = '1' else
-                  std_logic_vector(unsigned(VDIS_END) + 1) when ATARI_SYNC = '1' else ('0' & std_logic_vector(unsigned(VDL_VBB(10 downto 1)) + 1));
-    VS_START <= VDL_VSS when FBEE_VIDEO_ON = '1' else
-                ATARI_VL(10 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-                ATARI_VH(10 downto 0) when ATARI_SYNC = '1' else '0' & VDL_VSS(10 downto 1);
-    V_TOTAL <= VDL_VFT when FBEE_VIDEO_ON = '1' else
-               ATARI_VL(26 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
-               ATARI_VH(26 downto 16) when ATARI_SYNC = '1' else '0' & VDL_VFT(10 downto 1);
+	BORDER_LEFT <= VDL_HBE when FBEE_VIDEO_ON = '1' else 
+						x"015" when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+						x"02A" when ATARI_SYNC = '1' else std_logic_vector(MUL1(16 downto 5));
+	HDIS_START <= VDL_HDB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + 1);
+	HDIS_END <= VDL_HDE when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(BORDER_LEFT) + unsigned(HDIS_LEN));
+	BORDER_RIGHT <= VDL_HBB when FBEE_VIDEO_ON = '1' else std_logic_vector(unsigned(HDIS_END) + 1);
+	HS_START <= VDL_HSS when FBEE_VIDEO_ON = '1' else
+					ATARI_HL(11 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_HH(11 downto 0) when VDL_VMD(2) = '1' else std_logic_vector(MUL2(16 downto 5));
+	H_TOTAL <= VDL_HHT when FBEE_VIDEO_ON = '1' else
+					ATARI_HL(27 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_HH(27 downto 16) when ATARI_SYNC = '1' else std_logic_vector(MUL3(16 downto 5));
+	BORDER_TOP <= VDL_VBE when FBEE_VIDEO_ON = '1' else
+						"00000011111" when ATARI_SYNC = '1' else '0' & VDL_VBE(10 downto 1);
+	VDIS_START <= VDL_VDB when FBEE_VIDEO_ON = '1' else
+						"00000100000" when ATARI_SYNC = '1' else '0' & VDL_VDB(10 downto 1);
+	VDIS_END <= VDL_VDE when FBEE_VIDEO_ON = '1' else
+					"00110101111" when ATARI_SYNC = '1' and ST_VIDEO = '1' else -- 431.
+					"00111111111" when ATARI_SYNC = '1' else '0' & VDL_VDE(10 downto 1); -- 511.
+	BORDER_BOTTOM <= VDL_VBB when FBEE_VIDEO_ON = '1' else
+						std_logic_vector(unsigned(VDIS_END) + 1) when ATARI_SYNC = '1' else ('0' & std_logic_vector(unsigned(VDL_VBB(10 downto 1)) + 1));
+	VS_START <= VDL_VSS when FBEE_VIDEO_ON = '1' else
+					ATARI_VL(10 downto 0) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_VH(10 downto 0) when ATARI_SYNC = '1' else '0' & VDL_VSS(10 downto 1);
+	V_TOTAL <= VDL_VFT when FBEE_VIDEO_ON = '1' else
+					ATARI_VL(26 downto 16) when ATARI_SYNC = '1' and VDL_VMD(2) = '1' else
+					ATARI_VH(26 downto 16) when ATARI_SYNC = '1' else '0' & VDL_VFT(10 downto 1);
 
-    LAST <= '1' when VHCNT  = std_logic_vector(unsigned(H_TOTAL) - 10) else '0';
+	LAST <= '1' when VHCNT  = std_logic_vector(unsigned(H_TOTAL) - 10) else '0';
 
-    VIDEO_CLOCK_DOMAIN   : process
-    begin
-        wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
+	VIDEO_CLOCK_DOMAIN   : process
+	begin
+		wait until rising_edge(CLK_PIXEL_I);
+		if ST_CLUT = '1' then
+			CCSEL <= "000"; -- For information only.
+		elsif FALCON_CLUT = '1' then
+			CCSEL <= "001";
+		elsif FBEE_CLUT = '1' then
+			CCSEL <= "100";
+		elsif COLOR16_I = '1' then
+			CCSEL <= "101";
+		elsif COLOR24_I = '1' then
+			CCSEL <= "110";
+		elsif BORDER_ON = '1' then
+			CCSEL <= "111";
+		end if;
+
+		if LAST = '0' then
+			VHCNT <= std_logic_vector(unsigned(VHCNT) + 1);
+		else
+			VHCNT <= (others => '0');
+		end if;
+
+		if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 1) then
+			VVCNT <= (others => '0');
+		elsif LAST = '1' then
+			VVCNT <= std_logic_vector(unsigned(VVCNT) + 1);
+		end if;
+
+		-- Display on/off:
+		if LAST = '1' and VVCNT > std_logic_vector(unsigned(BORDER_TOP) - 1) and VVCNT < std_logic_vector(unsigned(BORDER_BOTTOM) - 1) then
+			DPO_ZL <= '1';
+		elsif LAST = '1' then
+			DPO_ZL <= '0';
+		end if;
         
-        if ST_CLUT = '1' then
-            CCSEL <= "000"; -- For information only.
-        elsif FALCON_CLUT = '1' then
-            CCSEL <= "001";
-        elsif FBEE_CLUT = '1' then
-            CCSEL <= "100";
-        elsif COLOR16_I = '1' then
-            CCSEL <= "101";
-        elsif COLOR24_I = '1' then
-            CCSEL <= "110";
-        elsif RAND_ON = '1' then
-            CCSEL <= "111";
-        end if;
+		if VHCNT = BORDER_LEFT then
+			DPO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING
+		else
+			DPO_ON <= '0';
+		end if;
 
-        if LAST = '0' then
-            VHCNT <= std_logic_vector(unsigned(VHCNT) + 1);
-        else
-            VHCNT <= (others => '0');
-        end if;
+		if VHCNT = std_logic_vector(unsigned(BORDER_RIGHT) - 1) then
+			DPO_OFF <= '1';
+		else
+			DPO_OFF <= '0';
+		end if;
 
-        if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 1) then
-            VVCNT <= (others => '0');
-        elsif LAST = '1' then
-            VVCNT <= std_logic_vector(unsigned(VVCNT) + 1);
-        end if;
+		DISP_ON <= (DISP_ON and not DPO_OFF) or (DPO_ON and DPO_ZL);
 
-        -- Display on/off:
-        if LAST = '1' and VVCNT > std_logic_vector(unsigned(BORDER_TOP) - 1) and VVCNT < std_logic_vector(unsigned(BORDER_BOTTOM) - 1) then
-            DPO_ZL <= '1';
-        elsif LAST = '1' then
-            DPO_ZL <= '0';
-        end if;
+		-- Data transfer on/off:
+		if VHCNT = std_logic_vector(unsigned(HDIS_START) - 1) then
+			VDO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING.
+		else
+			VDO_ON <= '0';
+		end if;
+
+		if VHCNT = HDIS_END then
+			VDO_OFF <= '1';
+		else
+			VDO_OFF <= '0';
+		end if;
+
+		if LAST = '1' and VVCNT >= std_logic_vector(unsigned(VDIS_START) - 1) and VVCNT < VDIS_END then
+			VDO_ZL <= '1'; -- Take over at the end of the line.
+		elsif LAST = '1' then
+			VDO_ZL <= '0'; -- 1 ZEILE DAVOR ON OFF
+		end if;
+
+		VDTRON <= (VDTRON and not VDO_OFF) or (VDO_ON and VDO_ZL);
+
+		-- Delay and SYNC
+		if VHCNT = std_logic_vector(unsigned(HS_START) - 11) then
+			HSYNC_START <= '1';
+		else
+			HSYNC_START <= '0';
+		end if;
         
-        if VHCNT = BORDER_LEFT then
-            DPO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING
-        else
-            DPO_ON <= '0';
-        end if;
+		if HSYNC_START = '1' then
+			HSYNC_I <= std_logic_vector(unsigned(HSY_LEN));
+		elsif HSYNC_I > x"00" then
+			HSYNC_I <= std_logic_vector(unsigned(HSYNC_I) - 1);
+		end if;
 
-        if VHCNT = std_logic_vector(unsigned(BORDER_RIGHT) - 1) then
-            DPO_OFF <= '1';
-        else
-            DPO_OFF <= '0';
-        end if;
-
-        DISP_ON <= (DISP_ON and not DPO_OFF) or (DPO_ON and DPO_ZL);
-
-        -- Data transfer on/off:
-        if VHCNT = std_logic_vector(unsigned(HDIS_START) - 1) then
-            VDO_ON <= '1'; -- BESSER EINZELN WEGEN TIMING.
-        else
-            VDO_ON <= '0';
-        end if;
-
-        if VHCNT = HDIS_END then
-            VDO_OFF <= '1';
-        else
-            VDO_OFF <= '0';
-        end if;
-
-        if LAST = '1' and VVCNT >= std_logic_vector(unsigned(VDIS_START) - 1) and VVCNT < VDIS_END then
-            VDO_ZL <= '1'; -- Take over at the end of the line.
-        elsif LAST = '1' then
-            VDO_ZL <= '0'; -- 1 ZEILE DAVOR ON OFF
-
-        end if;
-
-        VDTRON <= (VDTRON and not VDO_OFF) or (VDO_ON and VDO_ZL);
-
-        -- Delay and SYNC
-        if VHCNT = std_logic_vector(unsigned(HS_START) - 11) then
-            HSYNC_START <= '1';
-        else
-            HSYNC_START <= '0';
-        end if;
+		if LAST = '1' and VVCNT = std_logic_vector(unsigned(VS_START) - 11) then
+			VSYNC_START <= '1'; -- start am ende der Zeile vor dem vsync
+		else
+			VSYNC_START <= '0';
+		end if;
         
-        if HSYNC_START = '1' then
-            HSYNC_I <= std_logic_vector(unsigned(HSY_LEN));
-        elsif HSYNC_I > x"00" then
-            HSYNC_I <= std_logic_vector(unsigned(HSYNC_I) - 1);
-        end if;
+		if LAST = '1' and VSYNC_START = '1' then -- Start at the end of the line before VSYNC.
+			VSYNC_I <= "011"; -- 3 lines vsync length.
+		elsif LAST = '1' and VSYNC_I > "000" then
+			VSYNC_I <= std_logic_vector(unsigned(VSYNC_I) - 1); -- Count down.
+		end if;
 
-        if LAST = '1' and VVCNT = std_logic_vector(unsigned(VS_START) - 11) then
-            VSYNC_START <= '1'; -- start am ende der Zeile vor dem vsync
-        else
-            VSYNC_START <= '0';
-        end if;
+		if FBEE_VCTR(15) = '1' and VDL_VCT(5) = '1' and VSYNC_I = "000" then
+			VERZ_2 <= VERZ_2(8 downto 0) & '1';
+		elsif (FBEE_VCTR(15) = '0' or VDL_VCT(5) = '0') and VSYNC_I /= "000" then
+			VERZ_2 <= VERZ_2(8 downto 0) & '1';
+		else
+			VERZ_2 <= VERZ_2(8 downto 0) & '0';
+		end if;
         
-        if LAST = '1' and VSYNC_START = '1' then -- Start at the end of the line before VSYNC.
-            VSYNC_I <= "011"; -- 3 lines vsync length.
-        elsif LAST = '1' and VSYNC_I > "000" then
-            VSYNC_I <= std_logic_vector(unsigned(VSYNC_I) - 1); -- Count down.
-        end if;
+		if HSYNC_I > x"00" then
+			VERZ_1 <= VERZ_1(8 downto 0) & '1';
+		else
+			VERZ_1 <= VERZ_1(8 downto 0) & '0';
+		end if;
 
-        if FBEE_VCTR(15) = '1' and VDL_VCT(5) = '1' and VSYNC_I = "000" then
-            VERZ_2 <= VERZ_2(8 downto 0) & '1';
-        elsif (FBEE_VCTR(15) = '0' or VDL_VCT(5) = '0') and VSYNC_I /= "000" then
-            VERZ_2 <= VERZ_2(8 downto 0) & '1';
-        else
-            VERZ_2 <= VERZ_2(8 downto 0) & '0';
-        end if;
+		VERZ_0 <= VERZ_0(8 downto 0) & DISP_ON;
+
+		BLANKn <=  VERZ_0(8);
+		HSYNC  <=  VERZ_1(9);
+		VSYNC  <=  VERZ_2(9);
+		SYNCn <= not(VERZ_2(9) or VERZ_1(9));
+
+		-- border colours:
+		BORDER <= BORDER(5 downto 0) & (DISP_ON and not VDTRON and FBEE_VCTR(25));
+		BORDER_ON <= BORDER(6);
+
+		if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 10) then
+			FIFO_CLR <= '1';
+		elsif LAST = '1' then
+			FIFO_CLR <= '0';
+		end if;
+
+		if LAST = '1' and VVCNT = "00000000000" then
+			START_ZEILE <= '1';
+		elsif LAST = '1' then
+			START_ZEILE <= '0';
+		end if;
+
+		if VHCNT = x"003" and START_ZEILE = '1' then
+			SYNC_PIX <= '1';
+		else
+			SYNC_PIX <= '0';
+		end if;
+
+		if VHCNT = x"005" and START_ZEILE = '1' then
+			SYNC_PIX1 <= '1';
+		else
+			SYNC_PIX1 <= '0';
+		end if;
+
+		if VHCNT = x"007" and START_ZEILE = '1' then
+			SYNC_PIX2 <= '1';
+		else
+			SYNC_PIX2 <= '0';
+		end if;
         
-        if HSYNC_I > x"00" then
-            VERZ_1 <= VERZ_1(8 downto 0) & '1';
-        else
-            VERZ_1 <= VERZ_1(8 downto 0) & '0';
-        end if;
-
-        VERZ_0 <= VERZ_0(8 downto 0) & DISP_ON;
-
-        BLANKn <=  VERZ_0(8);
-        HSYNC  <=  VERZ_1(9);
-        VSYNC  <=  VERZ_2(9);
-        SYNCn <= not(VERZ_2(9) or VERZ_1(9));
-
-        -- Boarder colours:
-        RAND <= RAND(5 downto 0) & (DISP_ON and not VDTRON and FBEE_VCTR(25));
-        RAND_ON <= RAND(6);
-
-        if LAST = '1' and VVCNT = std_logic_vector(unsigned(V_TOTAL) - 10) then
-            FIFO_CLR <= '1';
-        elsif LAST = '1' then
-            FIFO_CLR <= '0';
-        end if;
-
-        if LAST = '1' and VVCNT = "00000000000" then
-            START_ZEILE <= '1';
-        elsif LAST = '1' then
-            START_ZEILE <= '0';
-        end if;
-
-        if VHCNT = x"003" and START_ZEILE = '1' then
-            SYNC_PIX <= '1';
-        else
-            SYNC_PIX <= '0';
-        end if;
-
-        if VHCNT = x"005" and START_ZEILE = '1' then
-            SYNC_PIX1 <= '1';
-        else
-            SYNC_PIX1 <= '0';
-        end if;
-
-        if VHCNT = x"007" and START_ZEILE = '1' then
-            SYNC_PIX2 <= '1';
-        else
-            SYNC_PIX2 <= '0';
-        end if;
+		if VDTRON = '1' and SYNC_PIX = '0' then
+			SUB_PIXEL_CNT <= std_logic_vector(unsigned(SUB_PIXEL_CNT) + 1);
+		elsif VDTRON = '1' then
+			SUB_PIXEL_CNT <= (others => '0');
+		end if;
         
-        if VDTRON = '1' and SYNC_PIX = '0' then
-            SUB_PIXEL_CNT <= std_logic_vector(unsigned(SUB_PIXEL_CNT) + 1);
-        elsif VDTRON = '1' then
-            SUB_PIXEL_CNT <= (others => '0');
-        end if;
-        
-        if VDTRON = '1' and SUB_PIXEL_CNT(6 downto 0) = "0000001" and COLOR1_I = '1' then
-            FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(5 downto 0) = "000001" and COLOR2_I = '1' then
-            FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(4 downto 0) = "00001" and COLOR4_I = '1' then
-            FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(3 downto 0) = "0001" and COLOR8_I = '1' then
-            FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(2 downto 0) = "001" and COLOR16_I = '1' then
-            FIFO_RDE <= '1';
-        elsif VDTRON = '1' and SUB_PIXEL_CNT(1 downto 0) = "01" and COLOR24_I = '1' then
-            FIFO_RDE <= '1';
-        elsif SYNC_PIX = '1' or SYNC_PIX1 = '1' or SYNC_PIX2 = '1' then
-            FIFO_RDE <= '1'; -- 3 CLOCK ZUS�TZLICH F�R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
-        else
-            FIFO_RDE <= '0';
-        end if;
+		if VDTRON = '1' and SUB_PIXEL_CNT(6 downto 0) = "0000001" and COLOR1_I = '1' then
+			FIFO_RDE <= '1';
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(5 downto 0) = "000001" and COLOR2_I = '1' then
+			FIFO_RDE <= '1';
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(4 downto 0) = "00001" and COLOR4_I = '1' then
+			FIFO_RDE <= '1';
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(3 downto 0) = "0001" and COLOR8_I = '1' then
+			FIFO_RDE <= '1';
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(2 downto 0) = "001" and COLOR16_I = '1' then
+			FIFO_RDE <= '1';
+		elsif VDTRON = '1' and SUB_PIXEL_CNT(1 downto 0) = "01" and COLOR24_I = '1' then
+			FIFO_RDE <= '1';
+		elsif SYNC_PIX = '1' or SYNC_PIX1 = '1' or SYNC_PIX2 = '1' then
+			FIFO_RDE <= '1'; -- 3 CLOCK ZUS�TZLICH F�R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+		else
+			FIFO_RDE <= '0';
+		end if;
 
-        CLUT_MUX_AV_0 <= SUB_PIXEL_CNT(3 downto 0);
-        CLUT_MUX_AV_1 <= CLUT_MUX_AV_0;
-        CLUT_MUX_ADR <= CLUT_MUX_AV_1;
-    end process VIDEO_CLOCK_DOMAIN;
+		CLUT_MUX_AV_0 <= SUB_PIXEL_CNT(3 downto 0);
+		CLUT_MUX_AV_1 <= CLUT_MUX_AV_0;
+		CLUT_MUX_ADR <= CLUT_MUX_AV_1;
+	end process VIDEO_CLOCK_DOMAIN;
 end architecture BEHAVIOUR;