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bumped version for release

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This commit is contained in:
Markus Fröschle
2014-08-06 06:23:30 +00:00
parent e3e202a7cc
commit 1e471ec8cd
4 changed files with 10 additions and 6 deletions
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2
include/version.h
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@@ -29,7 +29,7 @@
*/ */
#define MAJOR_VERSION 0 #define MAJOR_VERSION 0
#define MINOR_VERSION 85 #define MINOR_VERSION 86
#endif /* VERSION_H_ */ #endif /* VERSION_H_ */

2
tos/jtagwait/jtagwait.creator.user
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@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE QtCreatorProject> <!DOCTYPE QtCreatorProject>
<!-- Written by QtCreator 3.0.1, 2014-07-31T19:42:50. --> <!-- Written by QtCreator 3.0.1, 2014-08-04T18:51:58. -->
<qtcreator> <qtcreator>
<data> <data>
<variable>ProjectExplorer.Project.ActiveTarget</variable> <variable>ProjectExplorer.Project.ActiveTarget</variable>

1
tos/jtagwait/jtagwait.files
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@@ -1,2 +1,3 @@
include/driver_vec.h include/driver_vec.h
sources/jtagwait.c sources/jtagwait.c
Makefile

9
tos/jtagwait/sources/jtagwait.c
View File

@@ -5,7 +5,7 @@
#include "driver_vec.h" #include "driver_vec.h"
#define FPGA_JTAG_LOADED_FLAG ((volatile int32_t *) 0xFF101000) #define FPGA_JTAG_LOADED_FLAG ((volatile bool *) 0xFF101000)
#define _MBAR ((volatile uint8_t *) 0xFF000000) #define _MBAR ((volatile uint8_t *) 0xFF000000)
#define MCF_GPIO_PDDR_FEC1L ((volatile uint8_t *)(&_MBAR[0xA17])) #define MCF_GPIO_PDDR_FEC1L ((volatile uint8_t *)(&_MBAR[0xA17]))
@@ -30,7 +30,7 @@ static inline uint32_t set_ipl(uint32_t ipl)
" lsr.l #8,%[ret]\r\n" /* shift them to position */ " lsr.l #8,%[ret]\r\n" /* shift them to position */
: [ret] "=&d" (ret) /* output */ : [ret] "=&d" (ret) /* output */
: [ipl] "d" (ipl) /* input */ : [ipl] "d" (ipl) /* input */
: "d0" /* clobber */ : "d0", "cc" /* clobber */
); );
return ret; return ret;
@@ -53,8 +53,11 @@ void wait_for_jtag(void)
while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONFIG)); /* wait for JTAG config load starting */ while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONFIG)); /* wait for JTAG config load starting */
while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */ while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
*FPGA_JTAG_LOADED_FLAG = 1; /* indicate jtag loaded FPGA config to BaS */ *FPGA_JTAG_LOADED_FLAG = true; /* indicate jtag loaded FPGA config to BaS */
/*
* reboot after configuration finished
*/
__asm__ __volatile__( __asm__ __volatile__(
"jmp 0xE0000000\n\t" "jmp 0xE0000000\n\t"
); );