diff --git a/include/version.h b/include/version.h
index 303fb95..39704bd 100644
--- a/include/version.h
+++ b/include/version.h
@@ -29,7 +29,7 @@
  */
 
 #define MAJOR_VERSION	0
-#define MINOR_VERSION	85
+#define MINOR_VERSION	86
 
 
 #endif /* VERSION_H_ */
diff --git a/tos/jtagwait/jtagwait.creator.user b/tos/jtagwait/jtagwait.creator.user
index e0172af..93f26ca 100644
--- a/tos/jtagwait/jtagwait.creator.user
+++ b/tos/jtagwait/jtagwait.creator.user
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE QtCreatorProject>
-<!-- Written by QtCreator 3.0.1, 2014-07-31T19:42:50. -->
+<!-- Written by QtCreator 3.0.1, 2014-08-04T18:51:58. -->
 <qtcreator>
  <data>
   <variable>ProjectExplorer.Project.ActiveTarget</variable>
diff --git a/tos/jtagwait/jtagwait.files b/tos/jtagwait/jtagwait.files
index dcdeec8..198470f 100644
--- a/tos/jtagwait/jtagwait.files
+++ b/tos/jtagwait/jtagwait.files
@@ -1,2 +1,3 @@
 include/driver_vec.h
-sources/jtagwait.c
\ No newline at end of file
+sources/jtagwait.c
+Makefile
diff --git a/tos/jtagwait/sources/jtagwait.c b/tos/jtagwait/sources/jtagwait.c
index 3a4f7c8..72e40e6 100644
--- a/tos/jtagwait/sources/jtagwait.c
+++ b/tos/jtagwait/sources/jtagwait.c
@@ -5,7 +5,7 @@
 
 #include "driver_vec.h"
 
-#define FPGA_JTAG_LOADED_FLAG               ((volatile int32_t *) 0xFF101000)
+#define FPGA_JTAG_LOADED_FLAG               ((volatile bool *) 0xFF101000)
 
 #define _MBAR                               ((volatile uint8_t *) 0xFF000000)
 #define MCF_GPIO_PDDR_FEC1L                 ((volatile uint8_t *)(&_MBAR[0xA17]))
@@ -30,7 +30,7 @@ static inline uint32_t set_ipl(uint32_t ipl)
         "		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
         : [ret] "=&d" (ret)		/* output */
         : [ipl] "d" (ipl)		/* input */
-        : "d0"	/* clobber */
+        : "d0", "cc"	/* clobber */
     );
 
     return ret;
@@ -53,8 +53,11 @@ void wait_for_jtag(void)
     while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONFIG));        /* wait for JTAG config load starting */
     while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));     /* wait for JTAG config load finished */
 
-    *FPGA_JTAG_LOADED_FLAG = 1;     /* indicate jtag loaded FPGA config to BaS */
+    *FPGA_JTAG_LOADED_FLAG = true;     /* indicate jtag loaded FPGA config to BaS */
 
+    /*
+     * reboot after configuration finished
+     */
     __asm__ __volatile__(
         "jmp    0xE0000000\n\t"
     );