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Fixed ACRs for running BaS in flash (hang on MMU enable)

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This commit is contained in:
Markus Fröschle
2014-09-29 19:08:38 +00:00
parent 2637d39c67
commit 12620d8b5e
2 changed files with 611 additions and 606 deletions
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2
BaS_gcc/dma/dma.c
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@@ -39,7 +39,7 @@
#error "unknown machine!"
#endif /* MACHINE_FIREBEE */
#define DBG_DMA
//#define DBG_DMA
#ifdef DBG_DMA
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else

21
BaS_gcc/sys/mmu.c
View File

@@ -63,12 +63,12 @@
#error "unknown machine!"
#endif /* MACHINE_FIREBEE */
// #define DEBUG_MMU
#ifdef DEBUG_MMU
//#define DBG_MMU
#ifdef DBG_MMU
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else
#define dbg(format, arg...) do {;} while (0)
#endif /* DEBUG_MMU */
#endif /* DBG_MMU */
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); xprintf("system halted\r\n"); } while(0); while(1)
/*
@@ -505,11 +505,14 @@ void mmu_init(void)
#endif /* MACHINE_FIREBEE */
// set_acr1(0x601fc000);
/* data access attributes for BaS in flash */
set_acr1(ACR_W(0) |
ACR_SP(0) |
ACR_CM(0) |
#if defined(MACHINE_FIREBEE)
ACR_CM(ACR_CM_CACHEABLE_WT) | /* video RAM on the Firebee */
ACR_CM(ACR_CM_CACHEABLE_WT) | /* flash on the Firebee */
#elif defined(MACHINE_M5484LITE)
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* Compact Flash on the M548xLITE */
#elif defined(MACHINE_M54455)
@@ -521,11 +524,14 @@ void mmu_init(void)
ACR_S(ACR_S_ALL) |
ACR_E(1) |
ACR_ADMSK(0x1f) |
ACR_BA(0x60000000));
ACR_BA(0xe0000000));
/* set instruction access attributes in ACR2 and ACR3 */
//set_acr2(0xe007c400);
/* instruction access attribute for BaS in flash */
set_acr2(ACR_W(0) |
ACR_SP(0) |
ACR_CM(0) |
@@ -537,8 +543,7 @@ void mmu_init(void)
ACR_BA(0xe0000000));
/* disable ACR1 - 3, essentially disabling all of the above */
set_acr1(0x0);
set_acr2(0x0);
set_acr3(0x0);
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
@@ -630,7 +635,7 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc,
{
uint32_t fault = format_status & 0xc030000;
dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", address, format_status, pc);
dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc);
// flush_and_invalidate_caches();
switch (fault)