From 12620d8b5e6535ddd0df868e4e374481f9ec7371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 29 Sep 2014 19:08:38 +0000 Subject: [PATCH] Fixed ACRs for running BaS in flash (hang on MMU enable) --- BaS_gcc/dma/dma.c | 872 +++++++++++++++++++++++----------------------- BaS_gcc/sys/mmu.c | 345 +++++++++--------- 2 files changed, 611 insertions(+), 606 deletions(-) diff --git a/BaS_gcc/dma/dma.c b/BaS_gcc/dma/dma.c index 1f1f62e..45447dd 100644 --- a/BaS_gcc/dma/dma.c +++ b/BaS_gcc/dma/dma.c @@ -39,7 +39,7 @@ #error "unknown machine!" #endif /* MACHINE_FIREBEE */ -#define DBG_DMA +//#define DBG_DMA #ifdef DBG_DMA #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #else @@ -51,28 +51,28 @@ extern char _SYS_SRAM[]; struct dma_channel { - int req; - void (*handler)(void); + int req; + void (*handler)(void); }; static char used_reqs[32] = { - DMA_ALWAYS, DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0, - DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0, DMA_USB_EP1, - DMA_USB_EP2, DMA_USB_EP3, DMA_PCI_TX, DMA_PCI_RX, - DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 + DMA_ALWAYS, DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0, + DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0, DMA_USB_EP1, + DMA_USB_EP2, DMA_USB_EP3, DMA_PCI_TX, DMA_PCI_RX, + DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 }; static struct dma_channel dma_channel[NCHANNELS] = { - {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, - {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, - {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, - {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, + {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, + {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, + {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, + {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL}, }; /* @@ -84,22 +84,22 @@ static struct dma_channel dma_channel[NCHANNELS] = */ void dma_irq_enable(uint8_t lvl, uint8_t pri) { - /* Setup the DMA ICR (#48) */ - MCF_INTC_ICR48 = 0 - | MCF_INTC_ICR_IP(pri) - | MCF_INTC_ICR_IL(lvl); - dbg("DMA irq assigned level %d, priority %d\r\n", lvl, pri); + /* Setup the DMA ICR (#48) */ + MCF_INTC_ICR48 = 0 + | MCF_INTC_ICR_IP(pri) + | MCF_INTC_ICR_IL(lvl); + dbg("DMA irq assigned level %d, priority %d\r\n", lvl, pri); - /* Unmask all task interrupts */ - MCF_DMA_DIMR = 0; + /* Unmask all task interrupts */ + MCF_DMA_DIMR = 0; - /* Clear the interrupt pending register */ - MCF_DMA_DIPR = 0; + /* Clear the interrupt pending register */ + MCF_DMA_DIPR = 0; - /* Unmask the DMA interrupt in the interrupt controller */ - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48; + /* Unmask the DMA interrupt in the interrupt controller */ + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48; - dbg("DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n"); + dbg("DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n"); } /* @@ -107,311 +107,311 @@ void dma_irq_enable(uint8_t lvl, uint8_t pri) */ void dma_irq_disable(void) { - /* Mask all task interrupts */ - MCF_DMA_DIMR = (uint32_t) ~0; + /* Mask all task interrupts */ + MCF_DMA_DIMR = (uint32_t) ~0; - /* Clear any pending task interrupts */ - MCF_DMA_DIPR = (uint32_t) ~0; + /* Clear any pending task interrupts */ + MCF_DMA_DIPR = (uint32_t) ~0; - /* Mask the DMA interrupt in the interrupt controller */ - MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48; + /* Mask the DMA interrupt in the interrupt controller */ + MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48; - dbg("DMA interrupts masked and disabled\r\n"); + dbg("DMA interrupts masked and disabled\r\n"); } int dma_set_initiator(int initiator) { - switch (initiator) - { - /* these initiators are always active */ - case DMA_ALWAYS: - case DMA_DSPI_RXFIFO: - case DMA_DSPI_TXFIFO: - case DMA_DREQ0: - case DMA_PSC0_RX: - case DMA_PSC0_TX: - case DMA_USB_EP0: - case DMA_USB_EP1: - case DMA_USB_EP2: - case DMA_USB_EP3: - case DMA_PCI_TX: - case DMA_PCI_RX: - case DMA_PSC1_RX: - case DMA_I2C_RX: - case DMA_I2C_TX: - break; + switch (initiator) + { + /* these initiators are always active */ + case DMA_ALWAYS: + case DMA_DSPI_RXFIFO: + case DMA_DSPI_TXFIFO: + case DMA_DREQ0: + case DMA_PSC0_RX: + case DMA_PSC0_TX: + case DMA_USB_EP0: + case DMA_USB_EP1: + case DMA_USB_EP2: + case DMA_USB_EP3: + case DMA_PCI_TX: + case DMA_PCI_RX: + case DMA_PSC1_RX: + case DMA_I2C_RX: + case DMA_I2C_TX: + break; - case DMA_FEC0_RX: - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC16(3)) | MCF_DMA_IMCR_IMC16_FEC0RX; - used_reqs[16] = DMA_FEC0_RX; - break; + case DMA_FEC0_RX: + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC16(3)) | MCF_DMA_IMCR_IMC16_FEC0RX; + used_reqs[16] = DMA_FEC0_RX; + break; - case DMA_FEC0_TX: - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC17(3)) | MCF_DMA_IMCR_IMC17_FEC0TX; - used_reqs[17] = DMA_FEC0_TX; - break; + case DMA_FEC0_TX: + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC17(3)) | MCF_DMA_IMCR_IMC17_FEC0TX; + used_reqs[17] = DMA_FEC0_TX; + break; - case DMA_FEC1_RX: - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC20(3)) | MCF_DMA_IMCR_IMC20_FEC1RX; - used_reqs[20] = DMA_FEC1_RX; - break; + case DMA_FEC1_RX: + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC20(3)) | MCF_DMA_IMCR_IMC20_FEC1RX; + used_reqs[20] = DMA_FEC1_RX; + break; - case DMA_FEC1_TX: - if (used_reqs[21] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_FEC1TX; - used_reqs[21] = DMA_FEC1_TX; - } - else if (used_reqs[25] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_FEC1TX; - used_reqs[25] = DMA_FEC1_TX; - } - else if (used_reqs[31] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_FEC1TX; - used_reqs[31] = DMA_FEC1_TX; - } - else /* No empty slots */ - { - dbg("no free slot found\r\n"); + case DMA_FEC1_TX: + if (used_reqs[21] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_FEC1TX; + used_reqs[21] = DMA_FEC1_TX; + } + else if (used_reqs[25] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_FEC1TX; + used_reqs[25] = DMA_FEC1_TX; + } + else if (used_reqs[31] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_FEC1TX; + used_reqs[31] = DMA_FEC1_TX; + } + else /* No empty slots */ + { + dbg("no free slot found\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_DREQ1: - if (used_reqs[29] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_DREQ1; - used_reqs[29] = DMA_DREQ1; - } - else if (used_reqs[21] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_DREQ1; - used_reqs[21] = DMA_DREQ1; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_DREQ1: + if (used_reqs[29] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_DREQ1; + used_reqs[29] = DMA_DREQ1; + } + else if (used_reqs[21] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_DREQ1; + used_reqs[21] = DMA_DREQ1; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM0: - if (used_reqs[24] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC24(3)) | MCF_DMA_IMCR_IMC24_CTM0; - used_reqs[24] = DMA_CTM0; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM0: + if (used_reqs[24] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC24(3)) | MCF_DMA_IMCR_IMC24_CTM0; + used_reqs[24] = DMA_CTM0; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM1: - if (used_reqs[25] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_CTM1; - used_reqs[25] = DMA_CTM1; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM1: + if (used_reqs[25] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_CTM1; + used_reqs[25] = DMA_CTM1; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM2: - if (used_reqs[26] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_CTM2; - used_reqs[26] = DMA_CTM2; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM2: + if (used_reqs[26] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_CTM2; + used_reqs[26] = DMA_CTM2; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM3: - if (used_reqs[27] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_CTM3; - used_reqs[27] = DMA_CTM3; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM3: + if (used_reqs[27] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_CTM3; + used_reqs[27] = DMA_CTM3; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM4: - if (used_reqs[28] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_CTM4; - used_reqs[28] = DMA_CTM4; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM4: + if (used_reqs[28] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_CTM4; + used_reqs[28] = DMA_CTM4; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM5: - if (used_reqs[29] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_CTM5; - used_reqs[29] = DMA_CTM5; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM5: + if (used_reqs[29] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_CTM5; + used_reqs[29] = DMA_CTM5; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM6: - if (used_reqs[30] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_CTM6; - used_reqs[30] = DMA_CTM6; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM6: + if (used_reqs[30] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_CTM6; + used_reqs[30] = DMA_CTM6; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_CTM7: - if (used_reqs[31] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_CTM7; - used_reqs[31] = DMA_CTM7; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_CTM7: + if (used_reqs[31] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_CTM7; + used_reqs[31] = DMA_CTM7; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_USBEP4: - if (used_reqs[26] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_USBEP4; - used_reqs[26] = DMA_USBEP4; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_USBEP4: + if (used_reqs[26] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_USBEP4; + used_reqs[26] = DMA_USBEP4; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_USBEP5: - if (used_reqs[27] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_USBEP5; - used_reqs[27] = DMA_USBEP5; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_USBEP5: + if (used_reqs[27] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_USBEP5; + used_reqs[27] = DMA_USBEP5; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_USBEP6: - if (used_reqs[28] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_USBEP6; - used_reqs[28] = DMA_USBEP6; - } - else /* No empty slots */ - return 1; - break; + case DMA_USBEP6: + if (used_reqs[28] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_USBEP6; + used_reqs[28] = DMA_USBEP6; + } + else /* No empty slots */ + return 1; + break; - case DMA_PSC2_RX: - if (used_reqs[28] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_PSC2RX; - used_reqs[28] = DMA_PSC2_RX; } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_PSC2_RX: + if (used_reqs[28] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_PSC2RX; + used_reqs[28] = DMA_PSC2_RX; } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_PSC2_TX: - if (used_reqs[29] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_PSC2TX; - used_reqs[29] = DMA_PSC2_TX; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_PSC2_TX: + if (used_reqs[29] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_PSC2TX; + used_reqs[29] = DMA_PSC2_TX; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_PSC3_RX: - if (used_reqs[30] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_PSC3RX; - used_reqs[30] = DMA_PSC3_RX; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_PSC3_RX: + if (used_reqs[30] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_PSC3RX; + used_reqs[30] = DMA_PSC3_RX; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - case DMA_PSC3_TX: - if (used_reqs[31] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_PSC3TX; - used_reqs[31] = DMA_PSC3_TX; - } - else /* No empty slots */ - { - dbg("no free slot\r\n"); + case DMA_PSC3_TX: + if (used_reqs[31] == 0) + { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_PSC3TX; + used_reqs[31] = DMA_PSC3_TX; + } + else /* No empty slots */ + { + dbg("no free slot\r\n"); - return 1; - } - break; + return 1; + } + break; - default: - { - dbg("don't know what to do\r\n"); + default: + { + dbg("don't know what to do\r\n"); - return 1; - } - } - return 0; + return 1; + } + } + return 0; } /* @@ -426,16 +426,16 @@ int dma_set_initiator(int initiator) */ uint32_t dma_get_initiator(int requestor) { - uint32_t i; + uint32_t i; - for (i = 0; i < sizeof(used_reqs); ++i) - { - if (used_reqs[i] == requestor) - return i; - } - dbg("no initiator found for requestor %d\r\n", requestor); + for (i = 0; i < sizeof(used_reqs); ++i) + { + if (used_reqs[i] == requestor) + return i; + } + dbg("no initiator found for requestor %d\r\n", requestor); - return 0; + return 0; } /* @@ -446,17 +446,17 @@ uint32_t dma_get_initiator(int requestor) */ void dma_free_initiator(int requestor) { - uint32_t i; + uint32_t i; - for (i = 16; i < sizeof(used_reqs); ++i) - { - if (used_reqs[i] == requestor) - { - used_reqs[i] = 0; - break; - } - } - dbg("DMA requestor %d freed\r\n", requestor); + for (i = 16; i < sizeof(used_reqs); ++i) + { + if (used_reqs[i] == requestor) + { + used_reqs[i] = 0; + break; + } + } + dbg("DMA requestor %d freed\r\n", requestor); } /* @@ -470,37 +470,37 @@ void dma_free_initiator(int requestor) */ int dma_set_channel(int requestor, void (*handler)(void)) { - int i; + int i; - /* Check to see if this requestor is already assigned to a channel */ - dbg("check if requestor %d is already assigned to a channel\r\n", requestor); - if ((i = dma_get_channel(requestor)) != -1) - return i; + /* Check to see if this requestor is already assigned to a channel */ + dbg("check if requestor %d is already assigned to a channel\r\n", requestor); + if ((i = dma_get_channel(requestor)) != -1) + return i; - for (i = 0; i < NCHANNELS; ++i) - { - if (dma_channel[i].req == -1) - { - dma_channel[i].req = requestor; - dma_channel[i].handler = handler; - dbg("assigned channel %d to requestor %d\r\n", i, requestor); - return i; - } - } - dbg("no free DMA channel found for requestor %d\r\n", requestor); + for (i = 0; i < NCHANNELS; ++i) + { + if (dma_channel[i].req == -1) + { + dma_channel[i].req = requestor; + dma_channel[i].handler = handler; + dbg("assigned channel %d to requestor %d\r\n", i, requestor); + return i; + } + } + dbg("no free DMA channel found for requestor %d\r\n", requestor); - /* All channels taken */ - return -1; + /* All channels taken */ + return -1; } void dma_clear_channel(int channel) { - if(channel >= 0 && channel < NCHANNELS) - { - dma_channel[channel].req = -1; - dma_channel[channel].handler = NULL; - dbg("cleared DMA channel %d\r\n", channel); - } + if(channel >= 0 && channel < NCHANNELS) + { + dma_channel[channel].req = -1; + dma_channel[channel].handler = NULL; + dbg("cleared DMA channel %d\r\n", channel); + } } /* @@ -515,15 +515,15 @@ void dma_clear_channel(int channel) */ int dma_get_channel(int requestor) { - uint32_t i; + uint32_t i; - for (i = 0; i < NCHANNELS; ++i) - { - if (dma_channel[i].req == requestor) - return i; - } - dbg("no channel occupied by requestor %d\r\n", requestor); - return -1; + for (i = 0; i < NCHANNELS; ++i) + { + if (dma_channel[i].req == requestor) + return i; + } + dbg("no channel occupied by requestor %d\r\n", requestor); + return -1; } /* @@ -535,17 +535,17 @@ int dma_get_channel(int requestor) */ void dma_free_channel(int requestor) { - uint32_t i; + uint32_t i; - for (i = 0; i < NCHANNELS; ++i) - { - if (dma_channel[i].req == requestor) - { - dma_channel[i].req = -1; - dma_channel[i].handler = NULL; - break; - } - } + for (i = 0; i < NCHANNELS; ++i) + { + if (dma_channel[i].req == requestor) + { + dma_channel[i].req = -1; + dma_channel[i].handler = NULL; + break; + } + } } /* @@ -553,125 +553,125 @@ void dma_free_channel(int requestor) */ int dma_interrupt_handler(void *arg1, void *arg2) { - int i, interrupts; - uint32_t ipl; + int i, interrupts; + uint32_t ipl; - ipl = set_ipl(7); /* do not disturb */ + ipl = set_ipl(7); /* do not disturb */ - /* - * Determine which interrupt(s) triggered by AND'ing the - * pending interrupts with those that aren't masked. - */ - interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR; + /* + * Determine which interrupt(s) triggered by AND'ing the + * pending interrupts with those that aren't masked. + */ + interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR; - /* Make sure we are here for a reason */ - if (interrupts == 0) - { - dbg("not DMA interrupt! Spurious?\r\n"); - return 0; - } + /* Make sure we are here for a reason */ + if (interrupts == 0) + { + dbg("not DMA interrupt! Spurious?\r\n"); + return 0; + } - /* Clear the interrupt in the pending register */ - MCF_DMA_DIPR = interrupts; + /* Clear the interrupt in the pending register */ + MCF_DMA_DIPR = interrupts; - for (i = 0; i < 16; ++i, interrupts >>= 1) - { - if (interrupts & 0x1) - { - /* If there is a handler, call it */ - if (dma_channel[i].handler != NULL) - { - dbg("call handler for DMA channel %d (%p)\r\n", i, dma_channel[i].handler); - dma_channel[i].handler(); - } - } - } + for (i = 0; i < 16; ++i, interrupts >>= 1) + { + if (interrupts & 0x1) + { + /* If there is a handler, call it */ + if (dma_channel[i].handler != NULL) + { + dbg("call handler for DMA channel %d (%p)\r\n", i, dma_channel[i].handler); + dma_channel[i].handler(); + } + } + } - set_ipl(ipl); + set_ipl(ipl); - return 1; /* handled */ + return 1; /* handled */ } /********************************************************************/ void *dma_memcpy(void *dst, void *src, size_t n) { - int ret; + int ret; #ifdef DBG_DMA - int32_t time; - int32_t start; - int32_t end; + int32_t time; + int32_t start; + int32_t end; - start = MCF_SLT0_SCNT; + start = MCF_SLT0_SCNT; #endif /* DBG_DMA */ - ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0); - if (ret == MCD_OK) - { - dbg("DMA on channel 1 successfully started\r\n"); - } + ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0); + if (ret == MCD_OK) + { + dbg("DMA on channel 1 successfully started\r\n"); + } - do - { - ret = MCD_dmaStatus(1); + do + { + ret = MCD_dmaStatus(1); #ifdef _NOT_USED_ /* suppress annoying printout for now */ - switch (ret) - { - case MCD_NO_DMA: - xprintf("MCD_NO_DMA: no DMA active on this channel\r\n"); - return NULL; - break; - case MCD_IDLE: - xprintf("MCD_IDLE: DMA defined but not active (initiator not ready)\r\n"); - break; - case MCD_RUNNING: - xprintf("MCD_RUNNING: DMA active and working on this channel\r\n"); - break; - case MCD_PAUSED: - xprintf("MCD_PAUSED: DMA defined and enabled, but currently paused\r\n"); - break; - case MCD_HALTED: - xprintf("MCD_HALTED: DMA killed\r\n"); - return NULL; - break; - case MCD_DONE: - xprintf("MCD_DONE: DMA finished\r\n"); - break; - case MCD_CHANNEL_INVALID: - xprintf("MCD_CHANNEL_INVALID: invalid DMA channel\r\n"); - return NULL; - break; - default: - xprintf("unknown DMA status %d\r\n", ret); - break; - } + switch (ret) + { + case MCD_NO_DMA: + xprintf("MCD_NO_DMA: no DMA active on this channel\r\n"); + return NULL; + break; + case MCD_IDLE: + xprintf("MCD_IDLE: DMA defined but not active (initiator not ready)\r\n"); + break; + case MCD_RUNNING: + xprintf("MCD_RUNNING: DMA active and working on this channel\r\n"); + break; + case MCD_PAUSED: + xprintf("MCD_PAUSED: DMA defined and enabled, but currently paused\r\n"); + break; + case MCD_HALTED: + xprintf("MCD_HALTED: DMA killed\r\n"); + return NULL; + break; + case MCD_DONE: + xprintf("MCD_DONE: DMA finished\r\n"); + break; + case MCD_CHANNEL_INVALID: + xprintf("MCD_CHANNEL_INVALID: invalid DMA channel\r\n"); + return NULL; + break; + default: + xprintf("unknown DMA status %d\r\n", ret); + break; + } #endif - } while (ret != MCD_DONE); + } while (ret != MCD_DONE); #ifdef DBG_DMA - end = MCF_SLT0_SCNT; - time = (start - end) / (SYSCLK / 1000) / 1000; + end = MCF_SLT0_SCNT; + time = (start - end) / (SYSCLK / 1000) / 1000; #endif /* DBG_DMA */ - dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0); + dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0); - return dst; + return dst; } int dma_init(void) { - int res; + int res; - dbg("MCD DMA API initialization: "); - res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN); - if (res != MCD_OK) - { - dbg("DMA API initialization failed (0x%x)\r\n", res); - return 0; - } + dbg("MCD DMA API initialization: "); + res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN); + if (res != MCD_OK) + { + dbg("DMA API initialization failed (0x%x)\r\n", res); + return 0; + } - // test - dma_memcpy((void *) 0x10000, (void *) 0x03e00000, 0x00100000); /* copy one megabyte of flash to RAM */ + // test + dma_memcpy((void *) 0x10000, (void *) 0x03e00000, 0x00100000); /* copy one megabyte of flash to RAM */ - return 0; + return 0; } diff --git a/BaS_gcc/sys/mmu.c b/BaS_gcc/sys/mmu.c index bdcf8e7..797d445 100644 --- a/BaS_gcc/sys/mmu.c +++ b/BaS_gcc/sys/mmu.c @@ -63,12 +63,12 @@ #error "unknown machine!" #endif /* MACHINE_FIREBEE */ -// #define DEBUG_MMU -#ifdef DEBUG_MMU +//#define DBG_MMU +#ifdef DBG_MMU #define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0) #else #define dbg(format, arg...) do {;} while (0) -#endif /* DEBUG_MMU */ +#endif /* DBG_MMU */ #define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); xprintf("system halted\r\n"); } while(0); while(1) /* @@ -77,19 +77,19 @@ */ inline uint32_t set_asid(uint32_t value) { - extern long rt_asid; - uint32_t ret = rt_asid; + extern long rt_asid; + uint32_t ret = rt_asid; - __asm__ __volatile__( - "movec %[value],ASID\n\t" - : /* no output */ - : [value] "r" (value) - : - ); + __asm__ __volatile__( + "movec %[value],ASID\n\t" + : /* no output */ + : [value] "r" (value) + : + ); - rt_asid = value; + rt_asid = value; - return ret; + return ret; } @@ -99,18 +99,18 @@ inline uint32_t set_asid(uint32_t value) */ inline uint32_t set_acr0(uint32_t value) { - extern uint32_t rt_acr0; - uint32_t ret = rt_acr0; + extern uint32_t rt_acr0; + uint32_t ret = rt_acr0; - __asm__ __volatile__( - "movec %[value],ACR0\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr0 = value; + __asm__ __volatile__( + "movec %[value],ACR0\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr0 = value; - return ret; + return ret; } /* @@ -119,18 +119,18 @@ inline uint32_t set_acr0(uint32_t value) */ inline uint32_t set_acr1(uint32_t value) { - extern uint32_t rt_acr1; - uint32_t ret = rt_acr1; + extern uint32_t rt_acr1; + uint32_t ret = rt_acr1; - __asm__ __volatile__( - "movec %[value],ACR1\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr1 = value; + __asm__ __volatile__( + "movec %[value],ACR1\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr1 = value; - return ret; + return ret; } @@ -140,18 +140,18 @@ inline uint32_t set_acr1(uint32_t value) */ inline uint32_t set_acr2(uint32_t value) { - extern uint32_t rt_acr2; - uint32_t ret = rt_acr2; + extern uint32_t rt_acr2; + uint32_t ret = rt_acr2; - __asm__ __volatile__( - "movec %[value],ACR2\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr2 = value; + __asm__ __volatile__( + "movec %[value],ACR2\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr2 = value; - return ret; + return ret; } /* @@ -160,35 +160,35 @@ inline uint32_t set_acr2(uint32_t value) */ inline uint32_t set_acr3(uint32_t value) { - extern uint32_t rt_acr3; - uint32_t ret = rt_acr3; + extern uint32_t rt_acr3; + uint32_t ret = rt_acr3; - __asm__ __volatile__( - "movec %[value],ACR3\n\t" - : /* not output */ - : [value] "r" (value) - : - ); - rt_acr3 = value; + __asm__ __volatile__( + "movec %[value],ACR3\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr3 = value; - return ret; + return ret; } inline uint32_t set_mmubar(uint32_t value) { - extern uint32_t rt_mmubar; - uint32_t ret = rt_mmubar; + extern uint32_t rt_mmubar; + uint32_t ret = rt_mmubar; - __asm__ __volatile__( - "movec %[value],MMUBAR\n\t" - : /* no output */ - : [value] "r" (value) - : /* no clobber */ - ); - rt_mmubar = value; - NOP(); + __asm__ __volatile__( + "movec %[value],MMUBAR\n\t" + : /* no output */ + : [value] "r" (value) + : /* no clobber */ + ); + rt_mmubar = value; + NOP(); - return ret; + return ret; } @@ -359,64 +359,64 @@ int mmu_map_data_page(uint32_t virt, uint8_t asid) */ int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct page_descriptor *flags) { - int size_mask; + int size_mask; int ipl; - switch (sz) - { - case MMU_PAGE_SIZE_1M: + switch (sz) + { + case MMU_PAGE_SIZE_1M: size_mask = ~ (SIZE_1M - 1); - break; + break; - case MMU_PAGE_SIZE_8K: + case MMU_PAGE_SIZE_8K: size_mask = ~ (SIZE_8K - 1); - break; + break; - case MMU_PAGE_SIZE_4K: + case MMU_PAGE_SIZE_4K: size_mask = ~ (SIZE_4K - 1); - break; + break; - case MMU_PAGE_SIZE_1K: + case MMU_PAGE_SIZE_1K: size_mask = ~ (SIZE_1K - 1); - break; + break; - default: - dbg("illegal map size %d\r\n", sz); - return 0; - } + default: + dbg("illegal map size %d\r\n", sz); + return 0; + } - /* - * add page to TLB - */ + /* + * add page to TLB + */ ipl = set_ipl(7); /* do not disturb */ - MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */ + MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */ MCF_MMU_MMUTR_ID(page_id) | /* address space id (ASID) */ (flags->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ + MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */ - MCF_MMU_MMUDR_SZ(sz) | /* page size */ - MCF_MMU_MMUDR_CM(flags->cache_mode) | + MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */ + MCF_MMU_MMUDR_SZ(sz) | /* page size */ + MCF_MMU_MMUDR_CM(flags->cache_mode) | (flags->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */ (flags->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */ (flags->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */ - (flags->locked ? MCF_MMU_MMUDR_LK : 0); + (flags->locked ? MCF_MMU_MMUDR_LK : 0); - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - NOP(); + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + NOP(); - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ + MCF_MMU_MMUOR_ACC | /* access TLB */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ set_ipl(ipl); - dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys); + dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys); - return 1; + return 1; } void mmu_init(void) @@ -482,86 +482,91 @@ void mmu_init(void) pages[0].supervisor_protect = 0; /* protect system vectors */ } - set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */ + set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */ - /* set data access attributes in ACR0 and ACR1 */ - set_acr0(ACR_W(0) | /* read and write accesses permitted */ - ACR_SP(0) | /* supervisor and user mode access permitted */ - ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */ - ACR_AMM(0) | /* control region > 16 MB */ - ACR_S(ACR_S_ALL) | /* match addresses in user and supervisor mode */ - ACR_E(1) | /* enable ACR */ + /* set data access attributes in ACR0 and ACR1 */ + set_acr0(ACR_W(0) | /* read and write accesses permitted */ + ACR_SP(0) | /* supervisor and user mode access permitted */ + ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */ + ACR_AMM(0) | /* control region > 16 MB */ + ACR_S(ACR_S_ALL) | /* match addresses in user and supervisor mode */ + ACR_E(1) | /* enable ACR */ #if defined(MACHINE_FIREBEE) - ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */ - ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */ + ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */ + ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */ #elif defined(MACHINE_M5484LITE) - ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */ - ACR_BA(0x80000000)); + ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */ + ACR_BA(0x80000000)); #elif defined(MACHINE_M54455) - ACR_ADMSK(0x7f) | - ACR_BA(0x80000000)); /* FIXME: not determined yet */ + ACR_ADMSK(0x7f) | + ACR_BA(0x80000000)); /* FIXME: not determined yet */ #else #error unknown machine! #endif /* MACHINE_FIREBEE */ - // set_acr1(0x601fc000); - set_acr1(ACR_W(0) | - ACR_SP(0) | - ACR_CM(0) | + // set_acr1(0x601fc000); + + /* data access attributes for BaS in flash */ + + set_acr1(ACR_W(0) | + ACR_SP(0) | + ACR_CM(0) | #if defined(MACHINE_FIREBEE) - ACR_CM(ACR_CM_CACHEABLE_WT) | /* video RAM on the Firebee */ + ACR_CM(ACR_CM_CACHEABLE_WT) | /* flash on the Firebee */ #elif defined(MACHINE_M5484LITE) - ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* Compact Flash on the M548xLITE */ + ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* Compact Flash on the M548xLITE */ #elif defined(MACHINE_M54455) - ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* FIXME: not determined yet */ + ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* FIXME: not determined yet */ #else #error unknown machine! #endif /* MACHINE_FIREBEE */ - ACR_AMM(0) | - ACR_S(ACR_S_ALL) | - ACR_E(1) | - ACR_ADMSK(0x1f) | - ACR_BA(0x60000000)); + ACR_AMM(0) | + ACR_S(ACR_S_ALL) | + ACR_E(1) | + ACR_ADMSK(0x1f) | + ACR_BA(0xe0000000)); - /* set instruction access attributes in ACR2 and ACR3 */ + /* set instruction access attributes in ACR2 and ACR3 */ - //set_acr2(0xe007c400); - set_acr2(ACR_W(0) | - ACR_SP(0) | - ACR_CM(0) | - ACR_CM(ACR_CM_CACHEABLE_WT) | - ACR_AMM(1) | - ACR_S(ACR_S_ALL) | - ACR_E(1) | - ACR_ADMSK(0x7) | - ACR_BA(0xe0000000)); + //set_acr2(0xe007c400); + + /* instruction access attribute for BaS in flash */ + + set_acr2(ACR_W(0) | + ACR_SP(0) | + ACR_CM(0) | + ACR_CM(ACR_CM_CACHEABLE_WT) | + ACR_AMM(1) | + ACR_S(ACR_S_ALL) | + ACR_E(1) | + ACR_ADMSK(0x7) | + ACR_BA(0xe0000000)); /* disable ACR1 - 3, essentially disabling all of the above */ - set_acr1(0x0); - set_acr2(0x0); - set_acr3(0x0); - set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */ + set_acr3(0x0); - /* create locked TLB entries */ + set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */ - flags.cache_mode = CACHE_COPYBACK; + /* create locked TLB entries */ + + flags.cache_mode = CACHE_COPYBACK; flags.supervisor_protect = 0; flags.read = 1; flags.write = 1; flags.execute = 1; - flags.locked = true; + flags.locked = true; /* 0x00000000 - 0x00100000 (first MB of physical memory) locked virt = phys */ mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, 0, &flags); #if defined(MACHINE_FIREBEE) - /* + /* * 0x00d00000 - 0x00e00000 (last megabyte of ST RAM = Falcon video memory) locked ID = 6 - * mapped to physical address 0x60d0'0000 (FPGA video memory) - * video RAM: read write execute normal write true - */ - flags.cache_mode = CACHE_WRITETHROUGH; + * mapped to physical address 0x60d0'0000 (FPGA video memory) + * video RAM: read write execute normal write true + */ + flags.cache_mode = CACHE_WRITETHROUGH; flags.supervisor_protect = 0; flags.read = 1; flags.write = 1; @@ -569,15 +574,15 @@ void mmu_init(void) flags.locked = true; mmu_map_page(0x00d00000, 0x60d00000, MMU_PAGE_SIZE_1M, SCA_PAGE_ID, &flags); - video_tlb = 0x2000; /* set page as video page */ - video_sbt = 0x0; /* clear time */ + video_tlb = 0x2000; /* set page as video page */ + video_sbt = 0x0; /* clear time */ #endif /* MACHINE_FIREBEE */ - /* - * Make the TOS (in SDRAM) read-only - * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address - */ - flags.cache_mode = CACHE_COPYBACK; + /* + * Make the TOS (in SDRAM) read-only + * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address + */ + flags.cache_mode = CACHE_COPYBACK; flags.supervisor_protect = 0; flags.read = 1; flags.write = 0; @@ -586,11 +591,11 @@ void mmu_init(void) mmu_map_page(0xe00000, 0xe00000, MMU_PAGE_SIZE_1M, 0, &flags); #if defined(MACHINE_FIREBEE) - /* - * Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O - * area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee - */ - flags.cache_mode = CACHE_NOCACHE_PRECISE; + /* + * Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O + * area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee + */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; flags.supervisor_protect = 1; flags.read = 1; flags.write = 1; @@ -599,11 +604,11 @@ void mmu_init(void) mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, 0, &flags); #endif /* MACHINE_FIREBEE */ - /* - * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same - * virtual address. This is also used (completely) when BaS is in RAM - */ - flags.cache_mode = CACHE_COPYBACK; + /* + * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same + * virtual address. This is also used (completely) when BaS is in RAM + */ + flags.cache_mode = CACHE_COPYBACK; flags.supervisor_protect = 1; flags.read = 1; flags.write = 1; @@ -611,11 +616,11 @@ void mmu_init(void) flags.locked = 1; mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00200000, SDRAM_START + SDRAM_SIZE - 0x00200000, MMU_PAGE_SIZE_1M, 0, &flags); - /* - * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same - * virtual address. Used uncached for drivers. - */ - flags.cache_mode = CACHE_NOCACHE_PRECISE; + /* + * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same + * virtual address. Used uncached for drivers. + */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; flags.supervisor_protect = 1; flags.read = 1; flags.write = 1; @@ -630,11 +635,11 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, { uint32_t fault = format_status & 0xc030000; - dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", address, format_status, pc); - // flush_and_invalidate_caches(); + dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc); + // flush_and_invalidate_caches(); switch (fault) - { + { /* if we have a real TLB miss, map the offending page */ case 0x04010000: /* TLB miss on opword of instruction fetch */