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reformatted.

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This commit is contained in:
Markus Fröschle
2015-09-20 14:54:16 +00:00
parent 73c94ea144
commit 0c0d96f4bd
5 changed files with 1104 additions and 916 deletions
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9
FPGA_quartus_ori/firebee1.sdc
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@@ -19,7 +19,7 @@
## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sun Sep 20 10:41:57 2015"
## DATE "Sun Sep 20 14:58:25 2015"
##
## DEVICE "EP3C40F484C6"
@@ -47,6 +47,7 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por
derive_pll_clocks
#**************************************************************
# Set Clock Latency
#**************************************************************
@@ -83,6 +84,10 @@ set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {M
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
@@ -94,7 +99,9 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip
# Set Multicycle Path
#**************************************************************
set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] 8
set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2
set_multicycle_path -setup -end -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|VDL_VMD[2]}] -to [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|DPO_OFF}] 8
#**************************************************************