From 0c0d96f4bd29e42689861eed2b6852ba8bc4ab50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 14:54:16 +0000 Subject: [PATCH] reformatted. --- .../FalconIO_SDCard_IDE_CF.vhd | 1160 +++++++++-------- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 207 ++- FPGA_quartus_ori/Video/Video.bdf | 580 +++++---- FPGA_quartus_ori/firebee1.bdf | 64 +- FPGA_quartus_ori/firebee1.sdc | 9 +- 5 files changed, 1104 insertions(+), 916 deletions(-) diff --git a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index b2b8dbb..f0c67ac 100644 --- a/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_quartus_ori/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -1,5 +1,5 @@ -- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in +-- editor IF you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2008 Altera Corporation @@ -33,333 +33,333 @@ use ieee.std_logic_unsigned.all; -- Entity Declaration -ENTITY FalconIO_SDCard_IDE_CF IS +ENTITY falconio_sdcard_ide_cf IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - CLK2M : IN STD_LOGIC; - CLK500k : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - LP_BUSY : IN STD_LOGIC; - nACSI_DRQ : IN STD_LOGIC; - nACSI_INT : IN STD_LOGIC; - nSCSI_DRQ : IN STD_LOGIC; - nSCSI_MSG : IN STD_LOGIC; - MIDI_IN : IN STD_LOGIC; - RxD : IN STD_LOGIC; - CTS : IN STD_LOGIC; - RI : IN STD_LOGIC; - DCD : IN STD_LOGIC; - AMKB_RX : IN STD_LOGIC; - PIC_AMKB_RX : IN STD_LOGIC; - IDE_RDY : IN STD_LOGIC; - IDE_INT : IN STD_LOGIC; - WP_CS_CARD : IN STD_LOGIC; - nINDEX : IN STD_LOGIC; - TRACK00 : IN STD_LOGIC; - nRD_DATA : IN STD_LOGIC; - nDCHG : IN STD_LOGIC; - SD_DATA0 : IN STD_LOGIC; - SD_DATA1 : IN STD_LOGIC; - SD_DATA2 : IN STD_LOGIC; - SD_CARD_DEDECT : IN STD_LOGIC; - SD_WP : IN STD_LOGIC; - nDACK0 : IN STD_LOGIC; - nFB_WR : INOUT STD_LOGIC; - WP_CF_CARD : IN STD_LOGIC; - nWP : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - HD_DD : IN STD_LOGIC; - nSCSI_C_D : IN STD_LOGIC; - nSCSI_I_O : IN STD_LOGIC; - CLK2M4576 : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - VSYNC : IN STD_LOGIC; - HSYNC : IN STD_LOGIC; - DSP_INT : IN STD_LOGIC; - nBLANK : IN STD_LOGIC; - FDC_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); - nIDE_CS1 : OUT STD_LOGIC; - nIDE_CS0 : OUT STD_LOGIC; - LP_STR : OUT STD_LOGIC; - LP_DIR : OUT STD_LOGIC; - nACSI_ACK : OUT STD_LOGIC; - nACSI_RESET : OUT STD_LOGIC; - nACSI_CS : OUT STD_LOGIC; - ACSI_DIR : OUT STD_LOGIC; - ACSI_A1 : OUT STD_LOGIC; - nSCSI_ACK : OUT STD_LOGIC; - nSCSI_ATN : OUT STD_LOGIC; - SCSI_DIR : OUT STD_LOGIC; - SD_CLK : OUT STD_LOGIC; - YM_QA : OUT STD_LOGIC; - YM_QC : OUT STD_LOGIC; - YM_QB : OUT STD_LOGIC; - nSDSEL : OUT STD_LOGIC; - STEP : OUT STD_LOGIC; - MOT_ON : OUT STD_LOGIC; - nRP_LDS : OUT STD_LOGIC; - nRP_UDS : OUT STD_LOGIC; - nROM4 : OUT STD_LOGIC; - nROM3 : OUT STD_LOGIC; - nCF_CS1 : OUT STD_LOGIC; - nCF_CS0 : OUT STD_LOGIC; - nIDE_RD : INOUT STD_LOGIC; - nIDE_WR : INOUT STD_LOGIC; - AMKB_TX : OUT STD_LOGIC; - IDE_RES : OUT STD_LOGIC; - DTR : OUT STD_LOGIC; - RTS : OUT STD_LOGIC; - TxD : OUT STD_LOGIC; - MIDI_OLR : OUT STD_LOGIC; - MIDI_TLR : OUT STD_LOGIC; - nDREQ0 : OUT STD_LOGIC; - DSA_D : OUT STD_LOGIC; - nMFP_INT : OUT STD_LOGIC; - FALCON_IO_TA : OUT STD_LOGIC; - STEP_DIR : OUT STD_LOGIC; - WR_DATA : OUT STD_LOGIC; - WR_GATE : OUT STD_LOGIC; - DMA_DRQ : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_PAR : INOUT STD_LOGIC; - nSCSI_SEL : INOUT STD_LOGIC; - nSCSI_BUSY : INOUT STD_LOGIC; - nSCSI_RST : INOUT STD_LOGIC; - SD_CD_DATA3 : INOUT STD_LOGIC; - SD_CDM_D1 : INOUT STD_LOGIC + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + CLK2M : IN std_logic; + CLK500k : IN std_logic; + nFB_CS1 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + LP_BUSY : IN std_logic; + nACSI_DRQ : IN std_logic; + nACSI_INT : IN std_logic; + nSCSI_DRQ : IN std_logic; + nSCSI_MSG : IN std_logic; + MIDI_IN : IN std_logic; + RxD : IN std_logic; + CTS : IN std_logic; + RI : IN std_logic; + DCD : IN std_logic; + AMKB_RX : IN std_logic; + PIC_AMKB_RX : IN std_logic; + IDE_RDY : IN std_logic; + IDE_INT : IN std_logic; + WP_CS_CARD : IN std_logic; + nINDEX : IN std_logic; + TRACK00 : IN std_logic; + nRD_DATA : IN std_logic; + nDCHG : IN std_logic; + SD_DATA0 : IN std_logic; + SD_DATA1 : IN std_logic; + SD_DATA2 : IN std_logic; + SD_CARD_DEDECT : IN std_logic; + SD_WP : IN std_logic; + nDACK0 : IN std_logic; + nFB_WR : INOUT std_logic; + WP_CF_CARD : IN std_logic; + nWP : IN std_logic; + nFB_CS2 : IN std_logic; + nRSTO : IN std_logic; + HD_DD : IN std_logic; + nSCSI_C_D : IN std_logic; + nSCSI_I_O : IN std_logic; + CLK2M4576 : IN std_logic; + nFB_OE : IN std_logic; + VSYNC : IN std_logic; + HSYNC : IN std_logic; + DSP_INT : IN std_logic; + nBLANK : IN std_logic; + FDC_CLK : IN std_logic; + FB_ALE : IN std_logic; + ACP_CONF : IN std_logic_vector(31 DOWNTO 24); + nIDE_CS1 : OUT std_logic; + nIDE_CS0 : OUT std_logic; + LP_STR : OUT std_logic; + LP_DIR : OUT std_logic; + nACSI_ACK : OUT std_logic; + nACSI_RESET : OUT std_logic; + nACSI_CS : OUT std_logic; + ACSI_DIR : OUT std_logic; + ACSI_A1 : OUT std_logic; + nSCSI_ACK : OUT std_logic; + nSCSI_ATN : OUT std_logic; + SCSI_DIR : OUT std_logic; + SD_CLK : OUT std_logic; + YM_QA : OUT std_logic; + YM_QC : OUT std_logic; + YM_QB : OUT std_logic; + nSDSEL : OUT std_logic; + STEP : OUT std_logic; + MOT_ON : OUT std_logic; + nRP_LDS : OUT std_logic; + nRP_UDS : OUT std_logic; + nROM4 : OUT std_logic; + nROM3 : OUT std_logic; + nCF_CS1 : OUT std_logic; + nCF_CS0 : OUT std_logic; + nIDE_RD : INOUT std_logic; + nIDE_WR : INOUT std_logic; + AMKB_TX : OUT std_logic; + IDE_RES : OUT std_logic; + DTR : OUT std_logic; + RTS : OUT std_logic; + TxD : OUT std_logic; + MIDI_OLR : OUT std_logic; + MIDI_TLR : OUT std_logic; + nDREQ0 : OUT std_logic; + DSA_D : OUT std_logic; + nMFP_INT : OUT std_logic; + FALCON_IO_TA : OUT std_logic; + STEP_DIR : OUT std_logic; + WR_DATA : OUT std_logic; + WR_GATE : OUT std_logic; + DMA_DRQ : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + LP_D : INOUT std_logic_vector(7 DOWNTO 0); + ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_PAR : INOUT std_logic; + nSCSI_SEL : INOUT std_logic; + nSCSI_BUSY : INOUT std_logic; + nSCSI_RST : INOUT std_logic; + SD_CD_DATA3 : INOUT std_logic; + SD_CDM_D1 : INOUT std_logic ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -END FalconIO_SDCard_IDE_CF; +END falconio_sdcard_ide_cf; -- Architecture Body -ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS --- system -signal SYS_CLK : STD_LOGIC; -signal RESETn : STD_LOGIC; -signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS -signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS -signal BYT : STD_LOGIC; -- WENN BYT -> 1 -signal LONG : STD_LOGIC; -- WENN -> 1 --- KEYBOARD MIDI -signal ACIA_CS_I : STD_LOGIC; -signal IRQ_KEYBDn : STD_LOGIC; -signal IRQ_MIDIn : STD_LOGIC; -signal KEYB_RxD : STD_LOGIC; -signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); -signal MIDI_OUT : STD_LOGIC; -signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); -signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); --- MFP -signal MFP_CS : STD_LOGIC; -signal MFP_INTACK : STD_LOGIC; -signal LDS : STD_LOGIC; -signal DTACK_OUT_MFPn : STD_LOGIC; -signal IRQ_ACIAn : STD_LOGIC; -signal DINTn : STD_LOGIC; -signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); -signal TDO : STD_LOGIC; --- SOUND -signal SNDCS : STD_LOGIC; -signal SNDCS_I : STD_LOGIC; -signal SNDIR_I : STD_LOGIC; -signal LP_DIR_X : STD_LOGIC; -signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); -signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); --- DIV -signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE -signal ROM_CS : STD_LOGIC; --- DMA UND FLOPPY -signal DMA_DATEN_CS : STD_LOGIC; -signal DMA_MODUS_CS : STD_LOGIC; -signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); -signal WDC_BSL_CS : STD_LOGIC; -signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); -signal HD_DD_OUT : STD_LOGIC; -signal FDCS_In : STD_LOGIC; -signal CA0 : STD_LOGIC; -signal CA1 : STD_LOGIC; -signal CA2 : STD_LOGIC; -signal FDINT : STD_LOGIC; -signal FDRQ : STD_LOGIC; -signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_TOP_CS : STD_LOGIC; -signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_HIGH_CS : STD_LOGIC; -signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_MID_CS : STD_LOGIC; -signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_LOW_CS : STD_LOGIC; -signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_DIRM_CS : STD_LOGIC; -signal DMA_ADR_CS : STD_LOGIC; -signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); -signal DMA_DIR_OLD : STD_LOGIC; -signal DMA_BYT_CNT_CS : STD_LOGIC; -signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); -signal CLR_FIFO : STD_LOGIC; -signal DMA_DRQ_I : STD_LOGIC; -signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); -signal DMA_DRQQ : STD_LOGIC; -signal DMA_DRQ_Q : STD_LOGIC; -signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); -signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal RDF_RDE : STD_LOGIC; -signal RDF_WRE : STD_LOGIC; -signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal WRF_RDE : STD_LOGIC; -signal WRF_WRE : STD_LOGIC; -signal nFDC_WR : STD_LOGIC; -type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); -signal FCF_STATE : FCF_STATES; -signal NEXT_FCF_STATE : FCF_STATES; -signal DMA_REQ : STD_LOGIC; -signal FDC_CS : STD_LOGIC; -signal FCF_CS : STD_LOGIC; -signal FCF_APH : STD_LOGIC; -signal DMA_AZ_CS : STD_LOGIC; -signal DMA_ACTIV : STD_LOGIC; -signal DMA_ACTIV_NEW : STD_LOGIC; -signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); --- SCSI -signal SCSI_CS : STD_LOGIC; -signal SCSI_CSn : STD_LOGIC; -signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal nSCSI_DACK : STD_LOGIC; -signal SCSI_DRQ : STD_LOGIC; -signal SCSI_INT : STD_LOGIC; -signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); -signal DB_EN : STD_LOGIC; -signal DBP_OUTn : STD_LOGIC; -signal DBP_EN : STD_LOGIC; -signal RST_OUTn : STD_LOGIC; -signal RST_EN : STD_LOGIC; -signal BSY_OUTn : STD_LOGIC; -signal BSY_EN : STD_LOGIC; -signal SEL_OUTn : STD_LOGIC; -signal SEL_EN : STD_LOGIC; --- IDE -signal nnIDE_RES : STD_LOGIC; -signal IDE_CF_CS : STD_LOGIC; -signal IDE_CF_TA : STD_LOGIC; -signal NEXT_nIDE_RD : STD_LOGIC; -signal NEXT_nIDE_WR : STD_LOGIC; -type CMD_STATES is( IDLE, T1, T6, T7); -signal CMD_STATE : CMD_STATES; -signal NEXT_CMD_STATE : CMD_STATES; - - + ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS + -- system + SIGNAL SYS_CLK : std_logic; + SIGNAL RESETn : std_logic; + SIGNAL FB_B0 : std_logic; -- UPPER BYT BEI 16BIT BUS + SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS + SIGNAL BYT : std_logic; -- WENN BYT -> 1 + SIGNAL LONG : std_logic; -- WENN -> 1 + -- KEYBOARD MIDI + SIGNAL ACIA_CS_I : std_logic; + SIGNAL IRQ_KEYBDn : std_logic; + SIGNAL IRQ_MIDIn : std_logic; + SIGNAL KEYB_RxD : std_logic; + SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); + SIGNAL MIDI_OUT : std_logic; + SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); + SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); + -- MFP + SIGNAL MFP_CS : std_logic; + SIGNAL MFP_INTACK : std_logic; + SIGNAL LDS : std_logic; + SIGNAL DTACK_OUT_MFPn : std_logic; + SIGNAL IRQ_ACIAn : std_logic; + SIGNAL DINTn : std_logic; + SIGNAL DATA_OUT_MFP : std_logic_vector(7 DOWNTO 0); + SIGNAL TDO : std_logic; + -- SOUND + SIGNAL SNDCS : std_logic; + SIGNAL SNDCS_I : std_logic; + SIGNAL SNDIR_I : std_logic; + SIGNAL LP_DIR_X : std_logic; + SIGNAL DA_OUT_X : std_logic_vector(7 DOWNTO 0); + SIGNAL LP_D_X : std_logic_vector(7 DOWNTO 0); + -- DIV + SIGNAL SUB_BUS : std_logic; -- SUB BUS MIT ROM-PORT, CF UND IDE + SIGNAL ROM_CS : std_logic; + -- DMA UND FLOPPY + SIGNAL DMA_DATEN_CS : std_logic; + SIGNAL DMA_MODUS_CS : std_logic; + SIGNAL DMA_MODUS : std_logic_vector(15 DOWNTO 0); + SIGNAL WDC_BSL_CS : std_logic; + SIGNAL WDC_BSL : std_logic_vector(1 DOWNTO 0); + SIGNAL HD_DD_OUT : std_logic; + SIGNAL FDCS_In : std_logic; + SIGNAL CA0 : std_logic; + SIGNAL CA1 : std_logic; + SIGNAL CA2 : std_logic; + SIGNAL FDINT : std_logic; + SIGNAL FDRQ : std_logic; + SIGNAL CD_OUT_FDC : std_logic_vector(7 DOWNTO 0); + SIGNAL CD_IN_FDC : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_TOP_CS : std_logic; + SIGNAL DMA_TOP : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_HIGH_CS : std_logic; + SIGNAL DMA_HIGH : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_MID_CS : std_logic; + SIGNAL DMA_MID : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_LOW_CS : std_logic; + SIGNAL DMA_LOW : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_DIRM_CS : std_logic; + SIGNAL DMA_ADR_CS : std_logic; + SIGNAL DMA_STATUS : std_logic_vector(2 DOWNTO 0); + SIGNAL DMA_DIR_OLD : std_logic; + SIGNAL DMA_BYT_CNT_CS : std_logic; + SIGNAL DMA_BYT_CNT : std_logic_vector(31 DOWNTO 0); + SIGNAL CLR_FIFO : std_logic; + SIGNAL DMA_DRQ_I : std_logic; + SIGNAL DMA_DRQ_REG : std_logic_vector(1 DOWNTO 0); + SIGNAL DMA_DRQQ : std_logic; + SIGNAL DMA_DRQ_Q : std_logic; + SIGNAL RDF_DOUT : std_logic_vector(31 DOWNTO 0); + SIGNAL RDF_AZ : std_logic_vector(9 DOWNTO 0); + SIGNAL RDF_RDE : std_logic; + SIGNAL RDF_WRE : std_logic; + SIGNAL RDF_DIN : std_logic_vector(7 DOWNTO 0); + SIGNAL WRF_DOUT : std_logic_vector(7 DOWNTO 0); + SIGNAL WRF_AZ : std_logic_vector(9 DOWNTO 0); + SIGNAL WRF_RDE : std_logic; + SIGNAL WRF_WRE : std_logic; + SIGNAL nFDC_WR : std_logic; + type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); + SIGNAL FCF_STATE : FCF_STATES; + SIGNAL NEXT_FCF_STATE : FCF_STATES; + SIGNAL DMA_REQ : std_logic; + SIGNAL FDC_CS : std_logic; + SIGNAL FCF_CS : std_logic; + SIGNAL FCF_APH : std_logic; + SIGNAL DMA_AZ_CS : std_logic; + SIGNAL DMA_ACTIV : std_logic; + SIGNAL DMA_ACTIV_NEW : std_logic; + SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0); + -- SCSI + SIGNAL SCSI_CS : std_logic; + SIGNAL SCSI_CSn : std_logic; + SIGNAL SCSI_DOUT : std_logic_vector(7 DOWNTO 0); + SIGNAL nSCSI_DACK : std_logic; + SIGNAL SCSI_DRQ : std_logic; + SIGNAL SCSI_INT : std_logic; + SIGNAL DB_OUTn : std_logic_vector(7 DOWNTO 0); + SIGNAL DB_EN : std_logic; + SIGNAL DBP_OUTn : std_logic; + SIGNAL DBP_EN : std_logic; + SIGNAL RST_OUTn : std_logic; + SIGNAL RST_EN : std_logic; + SIGNAL BSY_OUTn : std_logic; + SIGNAL BSY_EN : std_logic; + SIGNAL SEL_OUTn : std_logic; + SIGNAL SEL_EN : std_logic; + -- IDE + SIGNAL nnIDE_RES : std_logic; + SIGNAL IDE_CF_CS : std_logic; + SIGNAL IDE_CF_TA : std_logic; + SIGNAL NEXT_nIDE_RD : std_logic; + SIGNAL NEXT_nIDE_WR : std_logic; + type CMD_STATES is( IDLE, T1, T6, T7); + SIGNAL CMD_STATE : CMD_STATES; + SIGNAL NEXT_CMD_STATE : CMD_STATES; + + BEGIN -LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; -BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; -FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; -FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; - -FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' - or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; -SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE - '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE - '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; -nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; -nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; -nDREQ0 <= '0'; ----------------------------------------------------------------------------- --- SD ----------------------------------------------------------------------------- -SD_CLK <= 'Z'; -SD_CD_DATA3 <= 'Z'; -SD_CDM_D1 <= 'Z'; ----------------------------------------------------------------------------- --- IDE ----------------------------------------------------------------------------- -CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) - begin - if nRSTO = '0' then + LONG <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '0' ELSE '0'; + BYT <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '1' ELSE '0'; + FB_B0 <= '1' WHEN FB_ADR(0) = '0' or BYT = '0' ELSE '0'; + FB_B1 <= '1' WHEN FB_ADR(0) = '1' or BYT = '0' ELSE '0'; + + FALCON_IO_TA <= '1' WHEN SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' ELSE '0'; + SUB_BUS <= '1' WHEN nFB_WR = '1' and ROM_CS = '1' ELSE + '1' WHEN nFB_WR = '1' and IDE_CF_CS = '1' ELSE + '1' WHEN nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; + nRP_UDS <= '0' WHEN SUB_BUS = '1' and FB_B0 = '1' ELSE '1'; + nRP_LDS <= '0' WHEN SUB_BUS = '1' and FB_B1 = '1' ELSE '1'; + nDREQ0 <= '0'; + ---------------------------------------------------------------------------- + -- SD + ---------------------------------------------------------------------------- + SD_CLK <= 'Z'; + SD_CD_DATA3 <= 'Z'; + SD_CDM_D1 <= 'Z'; + ---------------------------------------------------------------------------- + -- IDE + ---------------------------------------------------------------------------- + CMD_REG: PROCESS(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) + BEGIN + IF nRSTO = '0' THEN CMD_STATE <= IDLE; - elsif rising_edge(MAIN_CLK) then + ELSIF rising_edge(MAIN_CLK) THEN CMD_STATE <= NEXT_CMD_STATE; -- go to next nIDE_RD <= NEXT_nIDE_RD; -- go to next nIDE_WR <= NEXT_nIDE_WR; -- go to next - else + ELSE CMD_STATE <= CMD_STATE; -- halten nIDE_RD <= nIDE_RD; -- halten nIDE_WR <= nIDE_WR; -- halten - end if; - end process CMD_REG; + END IF; + END PROCESS CMD_REG; - CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) - begin + CMD_DECODER: PROCESS(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) + BEGIN case CMD_STATE is - when IDLE => + WHEN IDLE => IDE_CF_TA <= '0'; - if IDE_CF_CS = '1' then + IF IDE_CF_CS = '1' THEN NEXT_nIDE_RD <= not nFB_WR; NEXT_nIDE_WR <= nFB_WR; NEXT_CMD_STATE <= T1; - else + ELSE NEXT_nIDE_RD <= '1'; NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= IDLE; - end if; - when T1 => + END IF; + WHEN T1 => IDE_CF_TA <= '0'; NEXT_nIDE_RD <= not nFB_WR; NEXT_nIDE_WR <= nFB_WR; NEXT_CMD_STATE <= T6; - when T6 => - IF IDE_RDY = '1' then + WHEN T6 => + IF IDE_RDY = '1' THEN IDE_CF_TA <= '1'; NEXT_nIDE_RD <= '1'; NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= T7; - else + ELSE IDE_CF_TA <= '0'; NEXT_nIDE_RD <= not nFB_WR; NEXT_nIDE_WR <= nFB_WR; NEXT_CMD_STATE <= T6; - end if; - when T7 => + END IF; + WHEN T7 => IDE_CF_TA <= '0'; NEXT_nIDE_RD <= '1'; NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= IDLE; - end case; - end process CMD_DECODER; + END CASE; + END PROCESS CMD_DECODER; -IDE_RES <= not nnIDE_RES and nRSTO; -IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 -nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F -nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F -nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F -nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F ------------------------------------------------------------------------------------------------------------------------------------------ --- ACSI, SCSI UND FLOPPY WD1772 -------------------------------------------------------------------------------------------------------------------------------------------- --- daten read fifo + IDE_RES <= not nnIDE_RES and nRSTO; + IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80 + nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F + '0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F + nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F + '0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F + nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F + '0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F + nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F + '0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F + ----------------------------------------------------------------------------------------------------------------------------------------- + -- ACSI, SCSI UND FLOPPY WD1772 + ------------------------------------------------------------------------------------------------------------------------------------------- + -- daten read fifo RDF: dcfifo0 - port map( + PORT MAP( aclr => CLR_FIFO, data => RDF_DIN, rdclk => MAIN_CLK, @@ -369,16 +369,16 @@ nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else q => RDF_DOUT, wrusedw => RDF_AZ ); -FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY -FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY -RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE -FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; --- daten write fifo + FCF_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"0020110" and LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY + FCF_APH <= '1' WHEN FB_ALE = '1' and FB_AD(31 DOWNTO 0) = x"F0020110" and LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY + RDF_RDE <= '1' WHEN FCF_APH = '1' and nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE + FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; + -- daten write fifo WRF: dcfifo1 - port map( + PORT MAP( aclr => CLR_FIFO, - data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), + data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), rdclk => FDC_CLK, rdreq => WRF_RDE, wrclk => MAIN_CLK, @@ -386,84 +386,86 @@ RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; q => WRF_DOUT, rdusedw => WRF_AZ ); -CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB -DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG -FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- - process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) - begin - if nRSTO = '0' THEN + + CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB + DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG + FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; + + -- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + BEGIN + IF nRSTO = '0' THEN WRF_WRE <= '0'; - elsif rising_edge(MAIN_CLK) then - IF FCF_APH = '1' and nFB_WR = '0' then - WRF_WRE <= '1'; - else - WRF_WRE <= '0'; - end if; - else - WRF_WRE <= WRF_WRE; - end if; + ELSIF rising_edge(MAIN_CLK) THEN + IF FCF_APH = '1' and nFB_WR = '0' THEN + WRF_WRE <= '1'; + ELSE + WRF_WRE <= '0'; + END IF; + ELSE + WRF_WRE <= WRF_WRE; + END IF; END PROCESS; -FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) - begin - if nRSTO = '0' then + FCF_REG: PROCESS(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) + BEGIN + IF nRSTO = '0' THEN FCF_STATE <= FCF_IDLE; DMA_ACTIV <= '0'; - elsif rising_edge(FDC_CLK) then - FCF_STATE <= NEXT_FCF_STATE; -- go to next - DMA_ACTIV <= DMA_ACTIV_NEW; - else - FCF_STATE <= FCF_STATE; -- halten - DMA_ACTIV <= DMA_ACTIV; - end if; - end process FCF_REG; + ELSIF rising_edge(FDC_CLK) THEN + FCF_STATE <= NEXT_FCF_STATE; -- go to next + DMA_ACTIV <= DMA_ACTIV_NEW; + ELSE + FCF_STATE <= FCF_STATE; -- halten + DMA_ACTIV <= DMA_ACTIV; + END IF; + END PROCESS FCF_REG; -FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) - begin - if nRSTO = '0' then + FDC_REG: PROCESS(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) + BEGIN + IF nRSTO = '0' THEN FDC_OUT <= x"00"; - elsif rising_edge(FDC_CLK) and FDCS_In = '0' then - FDC_OUT <= CD_OUT_FDC; -- set - else - FDC_OUT <= FDC_OUT; -- halten - end if; - end process FDC_REG; + ELSIF rising_edge(FDC_CLK) and FDCS_In = '0' THEN + FDC_OUT <= CD_OUT_FDC; -- set + ELSE + FDC_OUT <= FDC_OUT; -- halten + END IF; + END PROCESS FDC_REG; -DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; -FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; -SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; + DMA_REQ <= '1' WHEN ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' ELSE '0'; + FDC_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and FB_B1 = '1' ELSE '0'; + SCSI_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and FB_B1 = '1' ELSE '0'; - FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) - begin + FCF_DECODER: PROCESS(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) + BEGIN case FCF_STATE is - when FCF_IDLE => + WHEN FCF_IDLE => SCSI_CSn <= '1'; FDCS_In <= '1'; RDF_WRE <= '0'; WRF_RDE <= '0'; nSCSI_DACK <= '1'; - if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then + IF DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' THEN DMA_ACTIV_NEW <= DMA_REQ; NEXT_FCF_STATE <= FCF_T0; - else + ELSE DMA_ACTIV_NEW <= '0'; NEXT_FCF_STATE <= FCF_IDLE; - end if; - when FCF_T0 => + END IF; + WHEN FCF_T0 => SCSI_CSn <= '1'; FDCS_In <= '1'; RDF_WRE <= '0'; nSCSI_DACK <= '1'; DMA_ACTIV_NEW <= DMA_REQ; WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO - if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? + IF DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start - else + ELSE NEXT_FCF_STATE <= FCF_T1; - end if; - when FCF_T1 => + END IF; + WHEN FCF_T1 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; @@ -471,7 +473,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; NEXT_FCF_STATE <= FCF_T2; - when FCF_T2 => + WHEN FCF_T2 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; @@ -479,7 +481,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; NEXT_FCF_STATE <= FCF_T3; - when FCF_T3 => + WHEN FCF_T3 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; @@ -487,7 +489,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; NEXT_FCF_STATE <= FCF_T6; - when FCF_T6 => + WHEN FCF_T6 => WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; SCSI_CSn <= not SCSI_CS; @@ -495,23 +497,23 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO NEXT_FCF_STATE <= FCF_T7; - when FCF_T7 => + WHEN FCF_T7 => SCSI_CSn <= '1'; FDCS_In <= '1'; RDF_WRE <= '0'; WRF_RDE <= '0'; nSCSI_DACK <= '1'; DMA_ACTIV_NEW <= '0'; - if FDC_CS = '1' and DMA_REQ = '0' then + IF FDC_CS = '1' and DMA_REQ = '0' THEN NEXT_FCF_STATE <= FCF_T7; - else + ELSE NEXT_FCF_STATE <= FCF_IDLE; - end if; - end case; - end process FCF_DECODER; + END IF; + END CASE; + END PROCESS FCF_DECODER; I_FDC: WF1772IP_TOP_SOC - port map( + PORT MAP( CLK => FDC_CLK, RESETn => nRSTO, CSn => FDCS_In, @@ -535,165 +537,187 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ DRQ => DMA_DRQ_I, INTRQ => FDINT ); -DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 -DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 -WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 -HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); -nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; -CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); -CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); -CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); -FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else - SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else - DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ---- WDC BSL REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN + + DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2 + DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2 + WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2 + + HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); + nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR; + + CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0); + CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); + CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); + + FB_AD(23 DOWNTO 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and nFB_OE = '0' ELSE + SCSI_DOUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and nFB_OE = '0' ELSE + DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + + --- WDC BSL REGISTER ------------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) + BEGIN + IF nRSTO = '0' THEN WDC_BSL <= "00"; - elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then + ELSIF rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' THEN IF FB_B0 = '1' THEN WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); - else + ELSE WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); - end if; - end if; + END IF; + END IF; END PROCESS; + --- DMA MODUS REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN + PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) + BEGIN + IF nRSTO = '0' THEN DMA_MODUS <= x"0000"; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then + ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' THEN IF FB_B0 = '1' THEN - DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); - else - DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); - end if; + DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24); + ELSE + DMA_MODUS(15 DOWNTO 8) <= DMA_MODUS(15 DOWNTO 8); + END IF; IF FB_B1 = '1' THEN - DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); - else - DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); - end if; - else + DMA_MODUS(7 DOWNTO 0) <= FB_AD(23 DOWNTO 16); + ELSE + DMA_MODUS(7 DOWNTO 0) <= DMA_MODUS(7 DOWNTO 0); + END IF; + ELSE DMA_MODUS <= DMA_MODUS; - end if; + END IF; END PROCESS; --- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) - begin - if nRSTO = '0' or CLR_FIFO = '1' THEN + + -- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) + BEGIN + IF nRSTO = '0' or CLR_FIFO = '1' THEN DMA_BYT_CNT <= x"00000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then - DMA_BYT_CNT(31 downto 17) <= "000000000000000"; - DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); - DMA_BYT_CNT(8 downto 0) <= "000000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then - DMA_BYT_CNT <= FB_AD; - else - DMA_BYT_CNT <= DMA_BYT_CNT; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' THEN + DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z'); + DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); + DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z'); + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' THEN + DMA_BYT_CNT <= FB_AD; + ELSE + DMA_BYT_CNT <= DMA_BYT_CNT; + END IF; END PROCESS; --------------------------------------------------------------------- -FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -DMA_STATUS(0) <= '1'; -- DMA OK -DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS -DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; -DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else - '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; -DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ - process(FDC_CLK, nRSTO, DMA_DRQ_REG) - begin - if nRSTO = '0' THEN + -------------------------------------------------------------------- + FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + + DMA_STATUS(0) <= '1'; -- DMA OK + DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS + DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' or SCSI_DRQ = '1' ELSE '0'; + DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' ELSE + '1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' ELSE '0'; + DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; + + -- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG) + BEGIN + IF nRSTO = '0' THEN DMA_DRQ_REG <= "00"; - elsif rising_edge(FDC_CLK) then - DMA_DRQ_REG(0) <= DMA_DRQQ; - DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; - else - DMA_DRQ_REG <= DMA_DRQ_REG; - end if; + ELSIF rising_edge(FDC_CLK) THEN + DMA_DRQ_REG(0) <= DMA_DRQQ; + DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; + ELSE + DMA_DRQ_REG <= DMA_DRQ_REG; + END IF; END PROCESS; --- DMA ADRESSE ------------------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN + + -- DMA ADRESSE ------------------------------------------------------ + PROCESS(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) + BEGIN + IF nRSTO = '0' THEN DMA_TOP <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then - DMA_TOP <= FB_AD(31 downto 24); - else - DMA_TOP <= DMA_TOP; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') THEN + DMA_TOP <= FB_AD(31 DOWNTO 24); + ELSE + DMA_TOP <= DMA_TOP; + END IF; END PROCESS; - process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN + + PROCESS(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) + BEGIN + IF nRSTO = '0' THEN DMA_HIGH <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then - DMA_HIGH <= FB_AD(23 downto 16); - else - DMA_HIGH <= DMA_HIGH; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') THEN + DMA_HIGH <= FB_AD(23 DOWNTO 16); + ELSE + DMA_HIGH <= DMA_HIGH; + END IF; END PROCESS; - process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) - begin + + PROCESS(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) + BEGIN DMA_MID <= DMA_MID; - if nRSTO = '0' THEN + IF nRSTO = '0' THEN DMA_MID <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_MID_CS = '1' then - DMA_MID <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_MID <= FB_AD(15 downto 8); - end if; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN + IF DMA_MID_CS = '1' THEN + DMA_MID <= FB_AD(23 DOWNTO 16); + ELSIF DMA_ADR_CS = '1' THEN + DMA_MID <= FB_AD(15 DOWNTO 8); + END IF; + END IF; END PROCESS; - process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) - begin + + PROCESS(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) + BEGIN DMA_LOW <= DMA_LOW; - if nRSTO = '0' THEN + IF nRSTO = '0' THEN DMA_LOW <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_LOW_CS = '1'then - DMA_LOW <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_LOW <= FB_AD(7 downto 0); - end if; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN + IF DMA_LOW_CS = '1'THEN + DMA_LOW <= FB_AD(23 DOWNTO 16); + ELSIF DMA_ADR_CS = '1' THEN + DMA_LOW <= FB_AD(7 DOWNTO 0); + END IF; + END IF; END PROCESS; --------------------------------------------------------------------------------------------- -DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 -DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 -DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 -DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 -FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- DIRECTZUGRIFF -DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD -DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG -DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG -FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; --- DMA RW TOGGLE ------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) - begin - if nRSTO = '0' THEN + + -------------------------------------------------------------------------------------------- + DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B0 = '1' ELSE '0'; -- F8608/2 + DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B1 = '1' ELSE '0'; -- F8609/2 + DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C305" and FB_B1 = '1' ELSE '0'; -- F860B/2 + DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C306" and FB_B1 = '1' ELSE '0'; -- F860D/2 + + FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + -- DIRECTZUGRIFF + DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD + DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG + DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG + + FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + + + -- DMA RW TOGGLE ------------------------------------------ + + PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) + BEGIN + IF nRSTO = '0' THEN DMA_DIR_OLD <= '0'; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then + ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' THEN DMA_DIR_OLD <= DMA_MODUS(8); - else + ELSE DMA_DIR_OLD <= DMA_DIR_OLD; - end if; + END IF; END PROCESS; -CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; --- SCSI ---------------------------------------------------------------------------------- + + CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; + + -- SCSI ---------------------------------------------------------------------------------- I_SCSI: WF5380_TOP_SOC - port map( + PORT MAP( CLK => FDC_CLK, RESETn => nRSTO, ADR => CA2 & CA1 & CA0, @@ -744,30 +768,35 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; -- MSG_OUTn => MSG_OUTn, -- MSG_EN => MSG_EN ); --- SCSI ACSI --------------------------------------------------------------- -SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; -SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET -SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; -nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; -nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; -nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; -ACSI_DIR <= '0'; -ACSI_D <= "ZZZZZZZZ"; -nACSI_CS <= '1'; -ACSI_A1 <= CA1; -nACSI_RESET <= nRSTO; -nACSI_ACK <= '1'; ----------------------------------------------------------------------------- --- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns ----------------------------------------------------------------------------- -ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 -nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; -nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; ----------------------------------------------------------------------------- --- ACIA KEYBOARD ----------------------------------------------------------------------------- + + -- SCSI ACSI --------------------------------------------------------------- + SCSI_D <= DB_OUTn WHEN DB_EN = '1' ELSE (OTHERS => 'Z'); + SCSI_DIR <= '1'; --'0' WHEN DB_EN = '1' ELSE '1'; --ABGESCHALTET + SCSI_PAR <= DBP_OUTn WHEN DBP_EN = '1' ELSE 'Z'; + nSCSI_RST <= RST_OUTn WHEN RST_EN = '1' ELSE 'Z'; + nSCSI_BUSY <= BSY_OUTn WHEN BSY_EN = '1' ELSE 'Z'; + nSCSI_SEL <= SEL_OUTn WHEN SEL_EN = '1' ELSE 'Z'; + ACSI_DIR <= '0'; + ACSI_D <= (OTHERS => 'Z'); + nACSI_CS <= '1'; + ACSI_A1 <= CA1; + nACSI_RESET <= nRSTO; + nACSI_ACK <= '1'; + + + ---------------------------------------------------------------------------- + -- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns + ---------------------------------------------------------------------------- + ROM_CS <= '1' WHEN nFB_CS1 = '0' AND nFB_WR = '1' AND FB_ADR(19 DOWNTO 17) = x"5" ELSE '0'; -- FFF A'0000/2'0000 + nROM4 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '0' ELSE '1'; + nROM3 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '1' ELSE '1'; + + + ---------------------------------------------------------------------------- + -- ACIA KEYBOARD + ---------------------------------------------------------------------------- I_ACIA_KEYBOARD: WF6850IP_TOP_SOC - port map( + PORT MAP( CLK => MAIN_CLK, RESETn => nRSTO, @@ -778,7 +807,7 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 downto 24), + DATA_IN => FB_AD(31 DOWNTO 24), DATA_OUT => DATA_OUT_ACIA_I, -- DATA_EN => DATA_EN_ACIA_I, @@ -793,13 +822,15 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; TXDATA => AMKB_TX --RTSn => -- Not used. ); -ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 -KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL -FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; --- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ - process(CLK2M, AMKB_RX, AMKB_REG) - begin - if rising_edge(CLK2M) then + + ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8 + KEYB_RxD <= '1' WHEN AMKB_REG(3) = '1' OR PIC_AMKB_RX = '0' ELSE '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '0' AND nFB_OE = '0' ELSE "ZZZZZZZZ"; + + -- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(CLK2M, AMKB_RX, AMKB_REG) + BEGIN + IF rising_edge(CLK2M) THEN IF AMKB_RX = '0' THEN IF AMKB_REG < 16 THEN AMKB_REG <= "00000"; @@ -815,13 +846,14 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' END IF; ELSE AMKB_REG <= AMKB_REG; - end if; + END IF; END PROCESS; ----------------------------------------------------------------------------- --- ACIA MIDI ----------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + -- ACIA MIDI + ---------------------------------------------------------------------------- I_ACIA_MIDI: WF6850IP_TOP_SOC - port map( + PORT MAP( CLK => MAIN_CLK, RESETn => nRSTO, @@ -832,7 +864,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 downto 24), + DATA_IN => FB_AD(31 DOWNTO 24), DATA_OUT => DATA_OUT_ACIA_II, -- DATA_EN => DATA_EN_ACIA_II, @@ -845,15 +877,17 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' IRQn => IRQ_MIDIn, TXDATA => MIDI_OUT --RTSn => -- Not used. - ); -MIDI_TLR <= MIDI_OUT; -MIDI_OLR <= MIDI_OUT; -FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ----------------------------------------------------------------------------- --- MFP ----------------------------------------------------------------------------- + ); + + MIDI_TLR <= MIDI_OUT; + MIDI_OLR <= MIDI_OUT; + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + ---------------------------------------------------------------------------- + -- MFP + ---------------------------------------------------------------------------- I_MFP: WF68901IP_TOP_SOC - port map( + PORT MAP( -- System control: CLK => MAIN_CLK, RESETn => nRSTO, @@ -863,8 +897,8 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' RWn => nFB_WR, DTACKn => DTACK_OUT_MFPn, -- Data and Adresses: - RS => FB_ADR(5 downto 1), - DATA_IN => FB_AD(23 downto 16), + RS => FB_ADR(5 DOWNTO 1), + DATA_IN => FB_AD(23 DOWNTO 16), DATA_OUT => DATA_OUT_MFP, -- DATA_EN => DATA_EN_MFP, GPIP_IN(7) => not DMA_DRQ_Q, @@ -901,32 +935,36 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' -- TRn => ); -MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 -MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 -LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; -FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; -DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else - '0' when FDINT = '1' else - '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1'; --- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ - process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) - begin - if nRSTO = '0' THEN + MFP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 6) = x"3FE8" ELSE '0'; -- FFA00/40 + MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 + LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0'; + + FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 10) <= (OTHERS => '0') WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z') ; + FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ"; + + DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE + '0' WHEN FDINT = '1' ELSE + '0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1'; + + -- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(MAIN_CLK, nRSTO, IRQ_ACIAn, IRQ_KEYBDn, IRQ_MIDIn) + BEGIN + IF nRSTO = '0' THEN IRQ_ACIAn <= '1'; - elsif rising_edge(MAIN_CLK) then - IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; - else + ELSIF rising_edge(MAIN_CLK) THEN + IRQ_ACIAn <= IRQ_KEYBDn AND IRQ_MIDIn; + ELSE IRQ_ACIAn <= IRQ_ACIAn; - end if; + END IF; END PROCESS; ----------------------------------------------------------------------------- --- Sound ----------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + -- Sound + ---------------------------------------------------------------------------- I_SOUND: WF2149IP_TOP_SOC - port map( + PORT MAP( SYS_CLK => MAIN_CLK, RESETn => nRSTO, @@ -939,7 +977,7 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else A9n => '0', A8 => '1', - DA_IN => FB_AD(31 downto 24), + DA_IN => FB_AD(31 DOWNTO 24), DA_OUT => DA_OUT_X, IO_A_IN => x"00", -- All port pins are dedicated outputs. @@ -951,21 +989,21 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else -- IO_A_OUT(2) => FDD_D1SEL, IO_A_OUT(1) => DSA_D, IO_A_OUT(0) => nSDSEL, - -- IO_A_EN =>, -- Not required. +-- IO_A_EN =>, -- Not required. IO_B_IN => LP_D, IO_B_OUT => LP_D_X, - -- IO_B_EN => IO_B_EN, +-- IO_B_EN => IO_B_EN, OUT_A => YM_QA, OUT_B => YM_QB, OUT_C => YM_QC ); -SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 -SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; -SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; -FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; -LP_DIR <= LP_DIR_X; - -END FalconIO_SDCard_IDE_CF_architecture; + SNDCS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4 + SNDCS_I <= '1' WHEN SNDCS = '1' and FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; + SNDIR_I <= '1' WHEN SNDCS = '1' and nFB_WR = '0' ELSE '0'; + FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + + LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z'); + LP_DIR <= LP_DIR_X; +END rtl; diff --git a/FPGA_quartus_ori/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_quartus_ori/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index eafe6c2..40b2fe6 100644 --- a/FPGA_quartus_ori/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_quartus_ori/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -98,12 +98,12 @@ VARIABLE VDL_LWD[15..0] :DFFE; VDL_LWD_CS :NODE; -- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT + CLUT_TA :DFF; -- needs one wait state HSYNC :DFF; HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- L�NGE HSYNC PULS IN PIXEL_CLK + HSY_LEN[7..0] :DFF; -- length of hsync pulse in pixel_clk HSYNC_START :DFF; - LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT + LAST :DFF; -- reached last pixel of a line VSYNC :DFF; VSYNC_START :DFFE; VSYNC_I[2..0] :DFFE; @@ -194,7 +194,7 @@ VARIABLE ACP_VCTR6_DUP : NODE; BEGIN --- BYT SELECT 32 BIT + -- BYT SELECT 32 BIT FB_B0 = FB_ADR[1..0]==0; -- ADR==0 FB_B1 = FB_ADR[1..0]==1 -- ADR==1 # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD @@ -204,46 +204,75 @@ BEGIN FB_B3 = FB_ADR[1..0]==3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT + + -- BYT SELECT 16 BIT FB_16B0 = FB_ADR[0]==0; -- ADR==0 FB_16B1 = FB_ADR[0]==1 -- ADR==1 # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT --- ACP CLUT -- + + -- ACP CLUT -- ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; + + CLUT_TA.CLK = MAIN_CLK; CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; ---FALCON CLUT -- + + + --FALCON CLUT -- FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; --- ST CLUT -- + + + -- ST CLUT -- ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; --- ST SHIFT MODE + + + -- ST SHIFT MODE ST_SHIFT_MODE[].CLK = MAIN_CLK; ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 ST_SHIFT_MODE[] = FB_AD[25..24]; ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO + + COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN --- FALCON SHIFT MODE + + + -- FALCON SHIFT MODE FALCON_SHIFT_MODE[].CLK = MAIN_CLK; FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 FALCON_SHIFT_MODE[] = FB_AD[26..16]; FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; + + CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; + + COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; --- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS + + + -- ACP VIDEO CONTROL + -- BIT 0=ACP VIDEO ON, + -- 1=POWER ON VIDEO DAC, + -- 2=ACP 24BIT, + -- 3=ACP 16BIT, + -- 4=ACP 8BIT, + -- 5=ACP 1BIT, + -- 6=FALCON SHIFT MODE, + -- 7=ST SHIFT MODE, + -- 9..8= VCLK FREQUENZ, + -- 15=-SYNC ALLOWED, + -- 31..16=VIDEO_RAM_CTR, + -- 25=RANDFARBE EINSCHALTEN, + -- 26=STANDARD ATARI SYNCS ACP_VCTR[].CLK = MAIN_CLK; ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 ACP_VCTR[31..8] = FB_AD[31..8]; @@ -254,9 +283,11 @@ BEGIN ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; - -- ATARI MODUS + + -- ATARI MODUS ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL�SUNG - -- HORIZONTAL TIMING 640x480 + + -- HORIZONTAL TIMING 640x480 ATARI_HH[].CLK = MAIN_CLK; ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 ATARI_HH[] = FB_AD[]; @@ -264,7 +295,8 @@ BEGIN ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 640x480 + + -- VERTIKAL TIMING 640x480 ATARI_VH[].CLK = MAIN_CLK; ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 ATARI_VH[] = FB_AD[]; @@ -272,7 +304,8 @@ BEGIN ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - -- HORIZONTAL TIMING 320x240 + + -- HORIZONTAL TIMING 320x240 ATARI_HL[].CLK = MAIN_CLK; ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 ATARI_HL[] = FB_AD[]; @@ -280,7 +313,8 @@ BEGIN ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 320x240 + + -- VERTIKAL TIMING 320x240 ATARI_VL[].CLK = MAIN_CLK; ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 ATARI_VL[] = FB_AD[]; @@ -288,7 +322,9 @@ BEGIN ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; --- VIDEO PLL CONFIG + + + -- VIDEO PLL CONFIG VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY VR_WR.CLK = MAIN_CLK; VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; @@ -299,22 +335,26 @@ BEGIN VR_FRQ[].CLK = MAIN_CLK; VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; VR_FRQ[] = FB_AD[23..16]; --- VIDEO PLL RECONFIG + + -- VIDEO PLL RECONFIG VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 VIDEO_RECONFIG.CLK = MAIN_CLK; VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; ------------------------------------------------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------------------------------------------------ VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; --------------- COLOR MODE IM ACP SETZEN + + -------------- COLOR MODE IM ACP SETZEN COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; --- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + + -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - -- duplicate ACP_VCTR6 according to TimeQuest reccomendations + -- duplicate ACP_VCTR6 according to TimeQuest recommendations ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR6 = ACP_VCTR6_DUP; ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; @@ -329,118 +369,140 @@ BEGIN # B"101" & COLOR16 # B"110" & COLOR24 # B"111" & RAND_ON; --- DIVERSE (VIDEO)-REGISTER ---------------------------- --- RANDFARBE + + -- DIVERSE (VIDEO)-REGISTER ---------------------------- + + -- RANDFARBE CCR[].CLK = MAIN_CLK; CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 CCR[] = FB_AD[23..0]; CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; ---SYS CTR + + --SYS CTR SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; BLITTER_ON = !SYS_CTR3; ---VDL_LOF + + --VDL_LOF VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 VDL_LOF[].CLK = MAIN_CLK; VDL_LOF[] = FB_AD[31..16]; VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; ---VDL_LWD + + --VDL_LWD VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 VDL_LWD[].CLK = MAIN_CLK; VDL_LWD[] = FB_AD[31..16]; VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; --- HORIZONTAL --- VDL_HHT + + -- HORIZONTAL + + -- VDL_HHT VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 VDL_HHT[].CLK = MAIN_CLK; VDL_HHT[] = FB_AD[27..16]; VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; --- VDL_HBE + + -- VDL_HBE VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 VDL_HBE[].CLK = MAIN_CLK; VDL_HBE[] = FB_AD[27..16]; VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; --- VDL_HDB + + -- VDL_HDB VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 VDL_HDB[].CLK = MAIN_CLK; VDL_HDB[] = FB_AD[27..16]; VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; --- VDL_HDE + + -- VDL_HDE VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 VDL_HDE[].CLK = MAIN_CLK; VDL_HDE[] = FB_AD[27..16]; VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; --- VDL_HBB + + -- VDL_HBB VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 VDL_HBB[].CLK = MAIN_CLK; VDL_HBB[] = FB_AD[27..16]; VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; --- VDL_HSS + + -- VDL_HSS VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 VDL_HSS[].CLK = MAIN_CLK; VDL_HSS[] = FB_AD[27..16]; VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; --- VERTIKAL --- VDL_VBE + + -- VERTIKAL + + -- VDL_VBE VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 VDL_VBE[].CLK = MAIN_CLK; VDL_VBE[] = FB_AD[26..16]; VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; --- VDL_VDB + + -- VDL_VDB VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 VDL_VDB[].CLK = MAIN_CLK; VDL_VDB[] = FB_AD[26..16]; VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; --- VDL_VDE + + -- VDL_VDE VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 VDL_VDE[].CLK = MAIN_CLK; VDL_VDE[] = FB_AD[26..16]; VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; --- VDL_VBB + + -- VDL_VBB VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 VDL_VBB[].CLK = MAIN_CLK; VDL_VBB[] = FB_AD[26..16]; VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; --- VDL_VSS + + -- VDL_VSS VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 VDL_VSS[].CLK = MAIN_CLK; VDL_VSS[] = FB_AD[26..16]; VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; --- VDL_VFT + + -- VDL_VFT VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 VDL_VFT[].CLK = MAIN_CLK; VDL_VFT[] = FB_AD[26..16]; VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; --- VDL_VCT + + -- VDL_VCT VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 VDL_VCT[].CLK = MAIN_CLK; VDL_VCT[] = FB_AD[24..16]; VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; --- VDL_VMD + + -- VDL_VMD VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 VDL_VMD[].CLK = MAIN_CLK; VDL_VMD[] = FB_AD[19..16]; VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; ---- REGISTER OUT + + --- REGISTER OUT FB_AD[31..16] = lpm_bustri_WORD( ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) @@ -488,7 +550,8 @@ BEGIN # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; --- VIDEO AUSGABE SETZEN + + -- VIDEO AUSGABE SETZEN CLK17M.CLK = CLK33M; CLK17M = !CLK17M; CLK13M.CLK = CLK25M; @@ -500,9 +563,10 @@ BEGIN # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; --------------------------------------------------------------- --- HORIZONTALE SYNC L�NGE in PIXEL_CLK ----------------------------------------------------------------- + + -------------------------------------------------------------- + -- HORIZONTALE SYNC L�NGE in PIXEL_CLK + ---------------------------------------------------------------- HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) @@ -521,7 +585,8 @@ BEGIN HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN # 640 & !VDL_VMD2; --- DOPPELZEILENMODUS + + -- DOPPELZEILENMODUS DOP_ZEI.CLK = MAIN_CLK; DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS INTER_ZEI.CLK = PIXEL_CLK; @@ -570,7 +635,8 @@ BEGIN # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --- Z�HLER + + -- Z�HLER LAST.CLK = PIXEL_CLK; LAST = VHCNT[]==(H_TOTAL[]-2); VHCNT[].CLK = PIXEL_CLK; @@ -578,7 +644,8 @@ BEGIN VVCNT[].CLK = PIXEL_CLK; VVCNT[].ENA = LAST; VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); --- DISPLAY ON OFF + + -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]