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added clock signals

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This commit is contained in:
Markus Fröschle
2014-06-11 17:52:44 +00:00
parent 8d0ede14c8
commit 05a13bdf16
2 changed files with 68 additions and 61 deletions
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102
vhdl/testbenches/ddr_ctlr_tb.vhd
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@@ -54,46 +54,46 @@ architecture beh of ddr_ctlr_tb is
component DDR_CTRL_V1
port(
CLK_MAIN : in std_logic;
DDR_SYNC_66M : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0);
FB_CS1n : in std_logic;
FB_OEn : in std_logic;
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
FB_ALE : in std_logic;
FB_WRn : in std_logic;
FIFO_CLR : in std_logic;
VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
BLITTER_ADR : in std_logic_vector(31 downto 0);
BLITTER_SIG : in std_logic;
BLITTER_WR : in std_logic;
DDRCLK0 : in std_logic;
CLK_33M : in std_logic;
FIFO_MW : in std_logic_vector(8 downto 0);
VA : out std_logic_vector(12 downto 0);
VWEn : out std_logic;
VRASn : out std_logic;
VCSn : out std_logic;
VCKE : out std_logic;
VCASn : out std_logic;
FB_LE : out std_logic_vector(3 downto 0);
FB_VDOE : out std_logic_vector(3 downto 0);
SR_FIFO_WRE : out std_logic;
SR_DDR_FB : out std_logic;
SR_DDR_WR : out std_logic;
SR_DDRWR_D_SEL : out std_logic;
SR_VDMP : out std_logic_vector(7 downto 0);
VIDEO_DDR_TA : out std_logic;
SR_BLITTER_DACK : out std_logic;
BA : out std_logic_vector(1 downto 0);
DDRWR_D_SEL1 : out std_logic;
VDM_SEL : out std_logic_vector(3 downto 0);
DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 16);
DATA_EN_H : out std_logic;
DATA_EN_L : out std_logic
);
CLK_MAIN : in std_logic;
DDR_SYNC_66M : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0);
FB_CS1n : in std_logic;
FB_OEn : in std_logic;
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
FB_ALE : in std_logic;
FB_WRn : in std_logic;
FIFO_CLR : in std_logic;
VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
BLITTER_ADR : in std_logic_vector(31 downto 0);
BLITTER_SIG : in std_logic;
BLITTER_WR : in std_logic;
DDRCLK0 : in std_logic;
CLK_33M : in std_logic;
FIFO_MW : in std_logic_vector(8 downto 0);
VA : out std_logic_vector(12 downto 0);
VWEn : out std_logic;
VRASn : out std_logic;
VCSn : out std_logic;
VCKE : out std_logic;
VCASn : out std_logic;
FB_LE : out std_logic_vector(3 downto 0);
FB_VDOE : out std_logic_vector(3 downto 0);
SR_FIFO_WRE : out std_logic;
SR_DDR_FB : out std_logic;
SR_DDR_WR : out std_logic;
SR_DDRWR_D_SEL : out std_logic;
SR_VDMP : out std_logic_vector(7 downto 0);
VIDEO_DDR_TA : out std_logic;
SR_BLITTER_DACK : out std_logic;
BA : out std_logic_vector(1 downto 0);
DDRWR_D_SEL1 : out std_logic;
VDM_SEL : out std_logic_vector(3 downto 0);
DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 16);
DATA_EN_H : out std_logic;
DATA_EN_L : out std_logic
);
end component;
begin
t : DDR_CTRL_V1
@@ -140,19 +140,31 @@ begin
DATA_EN_L => DATA_EN_L
);
stimulate_clock : process
stimulate_main_clock : process
begin
wait for 5 ps;
wait for 4.31 ns;
clock <= not clock;
end process;
stimulate_33mHz_clock : process
begin
wait for 30.3 ns;
clock_33 <= not clock_33;
end process;
stimulate_66MHz_clock : process
begin
wait for 66.6 ns;
DDR_SYNC_66M <= not DDR_SYNC_66M;
end process;
stimulate : process
begin
FB_ADR <= "00000000000000000000000000000001";
wait for 20 ps;
wait for 20 ns;
FB_ADR <= "10000000000000000000000000000000";
wait for 20 ps;
wait for 20 ns;
FB_ADR <= "00000000000000000000000000000101";
wait for 20 ps;
wait for 20 ns;
end process;
end beh;