171 lines
4.8 KiB
VHDL
171 lines
4.8 KiB
VHDL
library work;
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use work.firebee_pkg.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ddr_ctlr_tb is
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end ddr_ctlr_tb;
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architecture beh of ddr_ctlr_tb is
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signal clock : std_logic := '0'; -- main clock
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signal clock_33 : std_logic := '0'; -- 33 MHz clock
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signal ddr_clk : std_logic := '0'; -- ddr clock
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signal FB_ADR : std_logic_vector(31 downto 0);
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signal DDR_SYNC_66M : std_logic;
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signal FB_CS1n : std_logic;
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signal FB_OEn : std_logic;
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signal FB_SIZE0 : std_logic;
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signal FB_SIZE1 : std_logic;
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signal FB_ALE : std_logic;
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signal FB_WRn : std_logic;
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signal FIFO_CLR : std_logic;
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signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0);
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signal BLITTER_ADR : std_logic_vector(31 downto 0);
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signal BLITTER_SIG : std_logic;
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signal BLITTER_WR : std_logic;
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signal DDRCLK0 : std_logic;
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signal CLK_33M : std_logic;
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signal FIFO_MW : std_logic_vector(8 downto 0);
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signal VA : std_logic_vector(12 downto 0);
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signal VWEn : std_logic;
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signal VRASn : std_logic;
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signal VCSn : std_logic;
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signal VCKE : std_logic;
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signal VCASn : std_logic;
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signal FB_LE : std_logic_vector(3 downto 0);
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signal FB_VDOE : std_logic_vector(3 downto 0);
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signal SR_FIFO_WRE : std_logic;
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signal SR_DDR_FB : std_logic;
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signal SR_DDR_WR : std_logic;
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signal SR_DDRWR_D_SEL: std_logic;
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signal SR_VDMP : std_logic_vector(7 downto 0);
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signal VIDEO_DDR_TA : std_logic;
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signal SR_BLITTER_DACK : std_logic;
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signal BA : std_logic_vector(1 downto 0);
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signal DDRWR_D_SEL1 : std_logic;
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signal VDM_SEL : std_logic_vector(3 downto 0);
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signal DATA_IN : std_logic_vector(31 downto 0);
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signal DATA_OUT : std_logic_vector(31 downto 16);
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signal DATA_EN_H : std_logic;
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signal DATA_EN_L : std_logic;
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component DDR_CTRL_V1
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port(
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CLK_MAIN : in std_logic;
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DDR_SYNC_66M : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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FB_CS1n : in std_logic;
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FB_OEn : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_ALE : in std_logic;
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FB_WRn : in std_logic;
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FIFO_CLR : in std_logic;
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VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
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BLITTER_ADR : in std_logic_vector(31 downto 0);
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BLITTER_SIG : in std_logic;
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BLITTER_WR : in std_logic;
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DDRCLK0 : in std_logic;
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CLK_33M : in std_logic;
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FIFO_MW : in std_logic_vector(8 downto 0);
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VA : out std_logic_vector(12 downto 0);
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VWEn : out std_logic;
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VRASn : out std_logic;
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VCSn : out std_logic;
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VCKE : out std_logic;
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VCASn : out std_logic;
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FB_LE : out std_logic_vector(3 downto 0);
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FB_VDOE : out std_logic_vector(3 downto 0);
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SR_FIFO_WRE : out std_logic;
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SR_DDR_FB : out std_logic;
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SR_DDR_WR : out std_logic;
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SR_DDRWR_D_SEL : out std_logic;
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SR_VDMP : out std_logic_vector(7 downto 0);
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VIDEO_DDR_TA : out std_logic;
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SR_BLITTER_DACK : out std_logic;
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BA : out std_logic_vector(1 downto 0);
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DDRWR_D_SEL1 : out std_logic;
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VDM_SEL : out std_logic_vector(3 downto 0);
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DATA_IN : in std_logic_vector(31 downto 0);
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DATA_OUT : out std_logic_vector(31 downto 16);
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DATA_EN_H : out std_logic;
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DATA_EN_L : out std_logic
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);
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end component;
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begin
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t : DDR_CTRL_V1
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port map
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(
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CLK_MAIN => clock,
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DDR_SYNC_66M => DDR_SYNC_66M,
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FB_ADR => FB_ADR,
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FB_CS1n => FB_CS1n,
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FB_OEn => FB_OEn,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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FB_ALE => FB_ALE,
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FB_WRn => FB_WRn,
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FIFO_CLR => FIFO_CLR,
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VIDEO_RAM_CTR => VIDEO_RAM_CTR,
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BLITTER_ADR => BLITTER_ADR,
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BLITTER_SIG => BLITTER_SIG,
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BLITTER_WR => BLITTER_WR,
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DDRCLK0 => DDRCLK0,
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CLK_33M => CLK_33M,
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FIFO_MW => FIFO_MW,
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VA => VA,
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VWEn => VWEn,
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VRASn => VRASn,
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VCSn => VCSn,
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VCKE => VCKE,
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VCASn => VCASn,
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FB_LE => FB_LE,
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FB_VDOE => FB_VDOE,
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SR_FIFO_WRE => SR_FIFO_WRE,
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SR_DDR_FB => SR_DDR_FB,
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SR_DDR_WR => SR_DDR_WR,
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SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
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SR_VDMP => SR_VDMP,
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VIDEO_DDR_TA => VIDEO_DDR_TA,
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SR_BLITTER_DACK => SR_BLITTER_DACK,
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BA => BA,
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DDRWR_D_SEL1 => DDRWR_D_SEL1,
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VDM_SEL => VDM_SEL,
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DATA_IN => DATA_IN,
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DATA_OUT => DATA_OUT,
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DATA_EN_H => DATA_EN_H,
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DATA_EN_L => DATA_EN_L
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);
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stimulate_main_clock : process
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begin
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wait for 4.31 ns;
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clock <= not clock;
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end process;
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stimulate_33mHz_clock : process
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begin
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wait for 30.3 ns;
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clock_33 <= not clock_33;
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end process;
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stimulate_66MHz_clock : process
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begin
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wait for 66.6 ns;
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DDR_SYNC_66M <= not DDR_SYNC_66M;
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end process;
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stimulate : process
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begin
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FB_ADR <= "00000000000000000000000000000001";
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wait for 20 ns;
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FB_ADR <= "10000000000000000000000000000000";
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wait for 20 ns;
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FB_ADR <= "00000000000000000000000000000101";
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wait for 20 ns;
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end process;
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end beh;
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