Firebee/FPGA_Config
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Markus Fröschle b35e12b329 add more DDR clk signals to sdc
2016-01-11 17:05:39 +00:00
FPGA_Quartus_13.1
add more DDR clk signals to sdc
2016-01-11 17:05:39 +00:00
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10 MiB
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VHDL 83.4%
Verilog 13.1%
PHP 2.1%
Tcl 0.6%
Assembly 0.4%
Other 0.4%