Markus Fröschle
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fa4a3f686c
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simplify and fix errors
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2016-04-26 16:39:22 +00:00 |
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Markus Fröschle
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a7f6d4191e
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add function f_addr_cmp()
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2016-04-26 06:14:03 +00:00 |
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Markus Fröschle
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6a0eebf068
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change formatting
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2016-04-25 19:09:52 +00:00 |
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Markus Fröschle
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fb71e53c7e
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fix timing violation at border color assignment
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2016-04-14 18:11:14 +00:00 |
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Markus Fröschle
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8114dcadf3
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fix hsync len calculation for Firebee mode
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2016-04-14 05:56:39 +00:00 |
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Markus Fröschle
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accc7e85f0
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make it compile again
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2016-02-10 17:06:57 +00:00 |
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Markus Fröschle
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5f55a6738a
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cast to std_logic_vector
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2016-01-19 17:36:29 +00:00 |
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Markus Fröschle
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752b4cd0ad
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modify to use WHEN statements instead of binary logic
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2016-01-19 15:50:36 +00:00 |
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Markus Fröschle
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1846f7eff2
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remove specialised clocks
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2016-01-19 07:27:27 +00:00 |
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Markus Fröschle
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2724be31d1
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removed more "indirect" clocks
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2016-01-19 07:07:31 +00:00 |
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Markus Fröschle
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9f01c704dc
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saved
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2016-01-18 18:45:17 +00:00 |
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Markus Fröschle
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e2ab4af020
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get rid of BUFFER parameters
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2016-01-18 18:32:50 +00:00 |
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Markus Fröschle
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652dd1c124
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hold time fix test
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2016-01-18 18:15:02 +00:00 |
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Markus Fröschle
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e623e668c2
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more flexbus_register work
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2016-01-18 07:40:08 +00:00 |
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Markus Fröschle
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47f6884bbe
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add more functionality
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2016-01-17 21:45:53 +00:00 |
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Markus Fröschle
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b9c3ec9366
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modify indent
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2016-01-17 20:39:25 +00:00 |
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Markus Fröschle
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21a4a80fb7
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start of flexbus_register implementation to simplify that
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2016-01-17 20:28:18 +00:00 |
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Markus Fröschle
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ddad975d6f
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fix 13MHz clock sdc
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2016-01-17 08:43:20 +00:00 |
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Markus Fröschle
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91791dfb5d
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do not automatically insert delay chains
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2016-01-16 22:11:51 +00:00 |
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Markus Fröschle
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58a69ffc5f
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reformat
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2016-01-16 22:04:05 +00:00 |
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Markus Fröschle
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7bf4d912a0
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fix timing
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2016-01-16 21:38:17 +00:00 |
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Markus Fröschle
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0fe61bedef
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fix output delay
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2016-01-15 17:38:29 +00:00 |
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Markus Fröschle
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11bd410c15
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simplify processes
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2016-01-15 08:37:40 +00:00 |
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Markus Fröschle
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f11629ac29
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fix video base address and video counter register
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2016-01-14 22:02:44 +00:00 |
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Markus Fröschle
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c4d56bb652
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reformat
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2016-01-14 16:49:11 +00:00 |
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Markus Fröschle
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b7a34c8abf
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reformat
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2016-01-14 07:17:08 +00:00 |
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Markus Fröschle
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69c107ef32
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remove unused connections
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2016-01-14 06:45:15 +00:00 |
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Markus Fröschle
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52e1b53192
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formatting
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2016-01-14 06:44:52 +00:00 |
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Markus Fröschle
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4ed4616156
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remove unused generated signals
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2016-01-13 16:43:54 +00:00 |
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Markus Fröschle
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97a48bf636
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reactivated delay chain
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2016-01-13 15:04:24 +00:00 |
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Markus Fröschle
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fd5abf8b4a
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reformat
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2016-01-13 13:23:46 +00:00 |
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Markus Fröschle
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90c0f7758d
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remove AHDL files
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2016-01-13 12:54:00 +00:00 |
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Markus Fröschle
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5183d08d60
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finish conversion to vhdl
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2016-01-13 12:53:03 +00:00 |
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Markus Fröschle
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79a14e2a70
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reformat internal signals
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2016-01-13 07:27:57 +00:00 |
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Markus Fröschle
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621e2267a7
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renamed pixel_clk_i
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2016-01-13 07:16:24 +00:00 |
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Markus Fröschle
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c8b693d755
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add file
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2016-01-12 17:11:58 +00:00 |
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Markus Fröschle
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29df555945
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reformat
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2016-01-12 17:11:07 +00:00 |
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Markus Fröschle
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f1f893bc44
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fix ports
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2016-01-12 17:10:19 +00:00 |
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Markus Fröschle
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87100a7d62
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fix formatting
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2016-01-12 08:00:20 +00:00 |
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Markus Fröschle
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703d95ee75
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fix wire loop
still works (kind of) - pixel errors in MiNT, does not boot (no picture) with "pure" EmuTOS?
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2016-01-12 07:58:07 +00:00 |
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Markus Fröschle
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7d2430a62c
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reformat converted VHDL
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2016-01-12 07:14:33 +00:00 |
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Markus Fröschle
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3ec978dff5
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translate DDR_CTR to vhd
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2016-01-11 17:55:18 +00:00 |
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Markus Fröschle
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35d70dc637
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fix min instead of max
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2016-01-11 17:07:35 +00:00 |
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Markus Fröschle
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b35e12b329
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add more DDR clk signals to sdc
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2016-01-11 17:05:39 +00:00 |
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Markus Fröschle
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476825a3ba
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translate interrupt_controller to vhd
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2016-01-11 16:11:04 +00:00 |
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Markus Fröschle
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98a362dc90
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replace video.bdf with video.vhd
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2016-01-11 08:43:42 +00:00 |
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Markus Fröschle
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f6aa56ac7a
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convert firebee1.bdf to vhdl
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2016-01-11 08:18:06 +00:00 |
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Markus Fröschle
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b3edfcd457
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reformat
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2016-01-11 07:13:36 +00:00 |
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Markus Fröschle
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9cfde26eef
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modify settings
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2016-01-10 19:05:15 +00:00 |
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Markus Fröschle
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7296970eb6
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rename Video.bdf to lower case
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2016-01-10 10:24:30 +00:00 |
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