Markus Fröschle
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11bd410c15
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simplify processes
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2016-01-15 08:37:40 +00:00 |
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Markus Fröschle
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f1f893bc44
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fix ports
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2016-01-12 17:10:19 +00:00 |
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Markus Fröschle
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7d2430a62c
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reformat converted VHDL
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2016-01-12 07:14:33 +00:00 |
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Markus Fröschle
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35d70dc637
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fix min instead of max
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2016-01-11 17:07:35 +00:00 |
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Markus Fröschle
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b35e12b329
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add more DDR clk signals to sdc
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2016-01-11 17:05:39 +00:00 |
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Markus Fröschle
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476825a3ba
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translate interrupt_controller to vhd
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2016-01-11 16:11:04 +00:00 |
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Markus Fröschle
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b3edfcd457
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reformat
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2016-01-11 07:13:36 +00:00 |
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Markus Fröschle
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5c933580a2
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fix ACP web address
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2015-11-18 06:41:49 +00:00 |
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Markus Fröschle
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fc8034d93b
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patch with Fredi's lp fix (and others)
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2015-10-26 06:48:18 +00:00 |
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Markus Fröschle
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56adcdd218
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added another false path to fix timing
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2015-10-18 01:02:05 +00:00 |
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Markus Fröschle
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8b7fe5f731
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fix timing (set_false_path was missing)
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2015-10-18 00:57:04 +00:00 |
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Markus Fröschle
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9180cca701
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basically working config. Resolution changes still scramble the screen, however
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2015-10-17 09:40:48 +00:00 |
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Markus Fröschle
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7e2181fbc9
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improved timing, added timing constraints, got rid of CLK_33M
Design compiles and runs, but still has issues with different screen resolutions and video clocks
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2015-09-23 09:49:05 +00:00 |
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Markus Fröschle
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6f0464a1c7
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added derive_clock_uncertainty
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2015-09-20 19:50:38 +00:00 |
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Markus Fröschle
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d9364d9da5
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more false_path settings
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2015-09-20 19:24:59 +00:00 |
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Markus Fröschle
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5d4920f849
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upgrade lpm components
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2015-09-20 18:08:31 +00:00 |
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Markus Fröschle
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bb0f702a45
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reformatted, forced tighter timing
Config works, but screen is still scrambled
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2015-09-20 17:13:10 +00:00 |
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Markus Fröschle
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fb3fcdf996
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add false paths to design constraints
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2015-09-20 16:23:52 +00:00 |
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Markus Fröschle
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6288a1e16b
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reformatted.
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2015-09-20 14:54:16 +00:00 |
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Markus Fröschle
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f416539480
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get rid of CLK33M
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2015-09-20 12:32:02 +00:00 |
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Markus Fröschle
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8ec08da1fd
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add TimeQuest Synopsis Design Constraint file
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2015-09-20 07:01:21 +00:00 |
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