basically working config. Resolution changes still scramble the screen, however
This commit is contained in:
Markus Fröschle
@@ -1,117 +1,117 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 304 248)
|
||||
(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 229 31 244)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 72)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 72)(pt 272 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 96)
|
||||
(output)
|
||||
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 96)(pt 272 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 120)
|
||||
(output)
|
||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 120)(pt 272 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 144)
|
||||
(output)
|
||||
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 144)(pt 272 144)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 168)
|
||||
(output)
|
||||
(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 168)(pt 272 168)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 229 230 277 244)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
||||
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
|
||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
||||
(text "Ratio" (rect 85 111 109 125)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 119 111 154 125)(font "Arial" ))
|
||||
(text "DC (%)" (rect 164 111 199 125)(font "Arial" ))
|
||||
(text "c0" (rect 63 129 75 143)(font "Arial" ))
|
||||
(text "4/1" (rect 91 129 106 143)(font "Arial" ))
|
||||
(text "240.00" (rect 120 129 153 143)(font "Arial" ))
|
||||
(text "50.00" (rect 169 129 196 143)(font "Arial" ))
|
||||
(text "c1" (rect 63 147 75 161)(font "Arial" ))
|
||||
(text "4/1" (rect 91 147 106 161)(font "Arial" ))
|
||||
(text "0.00" (rect 127 147 148 161)(font "Arial" ))
|
||||
(text "50.00" (rect 169 147 196 161)(font "Arial" ))
|
||||
(text "c2" (rect 63 165 75 179)(font "Arial" ))
|
||||
(text "4/1" (rect 91 165 106 179)(font "Arial" ))
|
||||
(text "180.00" (rect 120 165 153 179)(font "Arial" ))
|
||||
(text "50.00" (rect 169 165 196 179)(font "Arial" ))
|
||||
(text "c3" (rect 63 183 75 197)(font "Arial" ))
|
||||
(text "4/1" (rect 91 183 106 197)(font "Arial" ))
|
||||
(text "105.00" (rect 120 183 153 197)(font "Arial" ))
|
||||
(text "50.00" (rect 169 183 196 197)(font "Arial" ))
|
||||
(text "c4" (rect 63 201 75 215)(font "Arial" ))
|
||||
(text "2/1" (rect 91 201 106 215)(font "Arial" ))
|
||||
(text "270.00" (rect 120 201 153 215)(font "Arial" ))
|
||||
(text "50.00" (rect 169 201 196 215)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 305 0)(line_width 1))
|
||||
(line (pt 305 0)(pt 305 249)(line_width 1))
|
||||
(line (pt 0 249)(pt 305 249)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 249)(line_width 1))
|
||||
(line (pt 56 108)(pt 206 108)(line_width 1))
|
||||
(line (pt 56 125)(pt 206 125)(line_width 1))
|
||||
(line (pt 56 143)(pt 206 143)(line_width 1))
|
||||
(line (pt 56 161)(pt 206 161)(line_width 1))
|
||||
(line (pt 56 179)(pt 206 179)(line_width 1))
|
||||
(line (pt 56 197)(pt 206 197)(line_width 1))
|
||||
(line (pt 56 215)(pt 206 215)(line_width 1))
|
||||
(line (pt 56 108)(pt 56 215)(line_width 1))
|
||||
(line (pt 82 108)(pt 82 215)(line_width 3))
|
||||
(line (pt 116 108)(pt 116 215)(line_width 3))
|
||||
(line (pt 161 108)(pt 161 215)(line_width 3))
|
||||
(line (pt 205 108)(pt 205 215)(line_width 1))
|
||||
(line (pt 48 56)(pt 272 56)(line_width 1))
|
||||
(line (pt 272 56)(pt 272 232)(line_width 1))
|
||||
(line (pt 48 232)(pt 272 232)(line_width 1))
|
||||
(line (pt 48 56)(pt 48 232)(line_width 1))
|
||||
)
|
||||
)
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2014 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 0 0 256 200)
|
||||
(text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 185 26 196)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 40 64))
|
||||
)
|
||||
(port
|
||||
(pt 256 64)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 256 80)
|
||||
(output)
|
||||
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
|
||||
(text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 256 96)
|
||||
(output)
|
||||
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||
(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 256 112)
|
||||
(output)
|
||||
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||
(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 256 128)
|
||||
(output)
|
||||
(text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||
(text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8)))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 198 186 442 382)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
|
||||
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
|
||||
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
|
||||
(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 97 91 225 192)(font "Arial" ))
|
||||
(text "DC (%)" (rect 132 91 296 192)(font "Arial" ))
|
||||
(text "c0" (rect 54 104 119 218)(font "Arial" ))
|
||||
(text "4/1" (rect 76 104 165 218)(font "Arial" ))
|
||||
(text "240.00" (rect 98 104 225 218)(font "Arial" ))
|
||||
(text "50.00" (rect 136 104 296 218)(font "Arial" ))
|
||||
(text "c1" (rect 54 117 118 244)(font "Arial" ))
|
||||
(text "4/1" (rect 76 117 165 244)(font "Arial" ))
|
||||
(text "0.00" (rect 103 117 225 244)(font "Arial" ))
|
||||
(text "50.00" (rect 136 117 296 244)(font "Arial" ))
|
||||
(text "c2" (rect 54 130 119 270)(font "Arial" ))
|
||||
(text "4/1" (rect 76 130 165 270)(font "Arial" ))
|
||||
(text "180.00" (rect 98 130 224 270)(font "Arial" ))
|
||||
(text "50.00" (rect 136 130 296 270)(font "Arial" ))
|
||||
(text "c3" (rect 54 143 119 296)(font "Arial" ))
|
||||
(text "4/1" (rect 76 143 165 296)(font "Arial" ))
|
||||
(text "105.00" (rect 98 143 224 296)(font "Arial" ))
|
||||
(text "50.00" (rect 136 143 296 296)(font "Arial" ))
|
||||
(text "c4" (rect 54 156 119 322)(font "Arial" ))
|
||||
(text "2/1" (rect 76 156 165 322)(font "Arial" ))
|
||||
(text "270.00" (rect 98 156 225 322)(font "Arial" ))
|
||||
(text "50.00" (rect 136 156 296 322)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 257 0))
|
||||
(line (pt 257 0)(pt 257 201))
|
||||
(line (pt 0 201)(pt 257 201))
|
||||
(line (pt 0 0)(pt 0 201))
|
||||
(line (pt 48 89)(pt 164 89))
|
||||
(line (pt 48 101)(pt 164 101))
|
||||
(line (pt 48 114)(pt 164 114))
|
||||
(line (pt 48 127)(pt 164 127))
|
||||
(line (pt 48 140)(pt 164 140))
|
||||
(line (pt 48 153)(pt 164 153))
|
||||
(line (pt 48 166)(pt 164 166))
|
||||
(line (pt 48 89)(pt 48 166))
|
||||
(line (pt 68 89)(pt 68 166)(line_width 3))
|
||||
(line (pt 94 89)(pt 94 166)(line_width 3))
|
||||
(line (pt 129 89)(pt 129 166)(line_width 3))
|
||||
(line (pt 163 89)(pt 163 166))
|
||||
(line (pt 40 48)(pt 223 48))
|
||||
(line (pt 223 48)(pt 223 183))
|
||||
(line (pt 40 183)(pt 223 183))
|
||||
(line (pt 40 48)(pt 40 183))
|
||||
(line (pt 255 64)(pt 223 64))
|
||||
(line (pt 255 80)(pt 223 80))
|
||||
(line (pt 255 96)(pt 223 96))
|
||||
(line (pt 255 112)(pt 223 112))
|
||||
(line (pt 255 128)(pt 223 128))
|
||||
)
|
||||
)
|
||||
|
||||
@@ -1,26 +1,26 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component altpll2
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC ;
|
||||
c4 : OUT STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component altpll2
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC ;
|
||||
c4 : OUT STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
@@ -1,27 +1,27 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll2
|
||||
(
|
||||
inclk0
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3,
|
||||
c4
|
||||
);
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll2
|
||||
(
|
||||
inclk0
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3,
|
||||
c4
|
||||
);
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
<pin name="c4" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
<pin name="c4" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]
|
||||
|
||||
@@ -1,477 +1,477 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll2.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altpll2 IS
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC ;
|
||||
c4 : OUT STD_LOGIC
|
||||
);
|
||||
END altpll2;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altpll2 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC ;
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
clk3_divide_by : NATURAL;
|
||||
clk3_duty_cycle : NATURAL;
|
||||
clk3_multiply_by : NATURAL;
|
||||
clk3_phase_shift : STRING;
|
||||
clk4_divide_by : NATURAL;
|
||||
clk4_duty_cycle : NATURAL;
|
||||
clk4_multiply_by : NATURAL;
|
||||
clk4_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire8_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
|
||||
sub_wire5 <= sub_wire0(4);
|
||||
sub_wire4 <= sub_wire0(3);
|
||||
sub_wire3 <= sub_wire0(2);
|
||||
sub_wire2 <= sub_wire0(1);
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
c0 <= sub_wire1;
|
||||
c1 <= sub_wire2;
|
||||
c2 <= sub_wire3;
|
||||
c3 <= sub_wire4;
|
||||
c4 <= sub_wire5;
|
||||
sub_wire6 <= inclk0;
|
||||
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 1,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 4,
|
||||
clk0_phase_shift => "5051",
|
||||
clk1_divide_by => 1,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 4,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 1,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 4,
|
||||
clk2_phase_shift => "3788",
|
||||
clk3_divide_by => 1,
|
||||
clk3_duty_cycle => 50,
|
||||
clk3_multiply_by => 4,
|
||||
clk3_phase_shift => "2210",
|
||||
clk4_divide_by => 1,
|
||||
clk4_duty_cycle => 50,
|
||||
clk4_multiply_by => 2,
|
||||
clk4_phase_shift => "11364",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 30303,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "SOURCE_SYNCHRONOUS",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_UNUSED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_USED",
|
||||
port_clk4 => "PORT_USED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
inclk => sub_wire7,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
|
||||
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll2.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altpll2 IS
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC ;
|
||||
c4 : OUT STD_LOGIC
|
||||
);
|
||||
END altpll2;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altpll2 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC ;
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
clk3_divide_by : NATURAL;
|
||||
clk3_duty_cycle : NATURAL;
|
||||
clk3_multiply_by : NATURAL;
|
||||
clk3_phase_shift : STRING;
|
||||
clk4_divide_by : NATURAL;
|
||||
clk4_duty_cycle : NATURAL;
|
||||
clk4_multiply_by : NATURAL;
|
||||
clk4_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire8_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
|
||||
sub_wire5 <= sub_wire0(4);
|
||||
sub_wire4 <= sub_wire0(2);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire2 <= sub_wire0(3);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
c3 <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
c2 <= sub_wire4;
|
||||
c4 <= sub_wire5;
|
||||
sub_wire6 <= inclk0;
|
||||
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 1,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 4,
|
||||
clk0_phase_shift => "5051",
|
||||
clk1_divide_by => 1,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 4,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 1,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 4,
|
||||
clk2_phase_shift => "3788",
|
||||
clk3_divide_by => 1,
|
||||
clk3_duty_cycle => 50,
|
||||
clk3_multiply_by => 4,
|
||||
clk3_phase_shift => "2210",
|
||||
clk4_divide_by => 1,
|
||||
clk4_duty_cycle => 50,
|
||||
clk4_multiply_by => 2,
|
||||
clk4_phase_shift => "11364",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 30303,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "SOURCE_SYNCHRONOUS",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_UNUSED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_USED",
|
||||
port_clk4 => "PORT_USED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
inclk => sub_wire7,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
|
||||
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -1,30 +1,47 @@
|
||||
## Generated SDC file "firebee1.sdc"
|
||||
|
||||
## Copyright (C) 1991-2014 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
|
||||
|
||||
## DATE "Mon Sep 21 20:39:03 2015"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C40F484C6"
|
||||
##
|
||||
|
||||
#--------------------------------------------------------------#
|
||||
# #
|
||||
# Synopsis design constraints for the Firebee project #
|
||||
# #
|
||||
# This file is part of the Firebee ACP project. #
|
||||
# http://www.experiment-s.de #
|
||||
# #
|
||||
# Description: #
|
||||
# timing constraints for the Firebee VHDL config #
|
||||
# #
|
||||
# #
|
||||
# #
|
||||
# To Do: #
|
||||
# - #
|
||||
# #
|
||||
# Author(s): #
|
||||
# Markus Fröschle, mfro@mubf.de #
|
||||
# #
|
||||
#--------------------------------------------------------------#
|
||||
# #
|
||||
# Copyright (C) 2015 Markus Fröschle & the ACP project #
|
||||
# #
|
||||
# This source file may be used and distributed without #
|
||||
# restriction provided that this copyright statement is not #
|
||||
# removed from the file and that any derivative work contains #
|
||||
# the original copyright notice and the associated disclaimer. #
|
||||
# #
|
||||
# This source file is free software; you can redistribute it #
|
||||
# and/or modify it under the terms of the GNU Lesser General #
|
||||
# Public License as published by the Free Software Foundation; #
|
||||
# either version 2.1 of the License, or (at your option) any #
|
||||
# later version. #
|
||||
# #
|
||||
# This source is distributed in the hope that it will be #
|
||||
# useful, but WITHOUT ANY WARRANTY; without even the implied #
|
||||
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
|
||||
# PURPOSE. See the GNU Lesser General Public License for more #
|
||||
# details. #
|
||||
# #
|
||||
# You should have received a copy of the GNU Lesser General #
|
||||
# Public License along with this source; if not, download it #
|
||||
# from http://www.gnu.org/licenses/lgpl.html #
|
||||
# #
|
||||
################################################################
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
@@ -51,11 +68,11 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por
|
||||
#
|
||||
# PLL2: i_ddr_clock_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 132 MHz
|
||||
# c1: 132 MHz
|
||||
# c2: 132 MHz
|
||||
# c3: 132 MHz
|
||||
# c4: 66 MHz
|
||||
# c0: 132 MHz 190°
|
||||
# c1: 132 MHz 0°
|
||||
# c2: 132 MHz 180°
|
||||
# c3: 132 MHz 105°
|
||||
# c4: 66 MHz 270°
|
||||
#
|
||||
# PLL3: i_atari_clk_pll
|
||||
# input: MAIN_CLK
|
||||
@@ -101,14 +118,14 @@ derive_clock_uncertainty
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
@@ -122,7 +139,7 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {F
|
||||
#**************************************************************
|
||||
|
||||
#
|
||||
# i_videl_clk is freely programmable
|
||||
# i_video_clk is freely programmable
|
||||
#
|
||||
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
|
||||
@@ -133,9 +150,6 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl
|
||||
# MAIN_CLK to DDR clk and v.v.
|
||||
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
|
||||
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
@@ -174,48 +188,6 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
# Clocks used:
|
||||
# MAIN_CLK 33MHz
|
||||
#
|
||||
# PLL1: i_mfp_acia_clk_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 500 kHz
|
||||
# c1: 2.4576 MHz
|
||||
# c2: 24.576 MHz
|
||||
#
|
||||
# PLL2: i_ddr_clock_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 132 MHz
|
||||
# c1: 132 MHz
|
||||
# c2: 132 MHz
|
||||
# c3: 132 MHz
|
||||
# c4: 66 MHz
|
||||
#
|
||||
# PLL3: i_atari_clk_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 2 MHz
|
||||
# c1: 16 MHz
|
||||
# c2: 25 MHz
|
||||
# c3: 48 MHz
|
||||
#
|
||||
# PLL4_ i_video_clk_pll
|
||||
# input: USB_CLK (48 MHz, PLL3 c3)
|
||||
# c0: 96 MHz, programmable in 1MHz steps
|
||||
|
||||
|
||||
# 66 MHz to 33 MHz
|
||||
set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
|
||||
set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
|
||||
# 33 MHz to 66 MHz
|
||||
set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
|
||||
set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
|
||||
# 132 MHz to 33 MHz
|
||||
set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
|
||||
set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
|
||||
# 33 MHz to 132 MHz
|
||||
set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
|
||||
set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
@@ -238,3 +210,15 @@ set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {
|
||||
#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
|
||||
#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
|
||||
|
||||
# restrict timing of video controller
|
||||
|
||||
#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VA[*]}]
|
||||
#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VA[*]}]
|
||||
|
||||
#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {BA[*]}]
|
||||
#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {BA[*]}]
|
||||
|
||||
#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
|
||||
#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]
|
||||
#set_input_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
|
||||
#set_input_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]
|
||||
|
||||
@@ -1,23 +0,0 @@
|
||||
# Copyright (C) 1991-2008 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "8.1"
|
||||
DATE = "10:07:29 September 03, 2009"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "firebee1"
|
||||
@@ -1,27 +0,0 @@
|
||||
[ProjectWorkspace]
|
||||
ptn_Child1=Frames
|
||||
[ProjectWorkspace.Frames]
|
||||
ptn_Child1=ChildFrames
|
||||
[ProjectWorkspace.Frames.ChildFrames]
|
||||
ptn_Child1=Document-0
|
||||
ptn_Child2=Document-1
|
||||
ptn_Child3=Document-2
|
||||
ptn_Child4=Document-3
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
|
||||
DocPathName=firebee1.bdf
|
||||
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
|
||||
DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
|
||||
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
|
||||
AFC_IN_REPORT=False
|
||||
Reference in New Issue
Block a user