Commit Graph

22 Commits

Author SHA1 Message Date
Markus Fröschle
0fe61bedef fix output delay 2016-01-15 17:38:29 +00:00
Markus Fröschle
11bd410c15 simplify processes 2016-01-15 08:37:40 +00:00
Markus Fröschle
f1f893bc44 fix ports 2016-01-12 17:10:19 +00:00
Markus Fröschle
7d2430a62c reformat converted VHDL 2016-01-12 07:14:33 +00:00
Markus Fröschle
35d70dc637 fix min instead of max 2016-01-11 17:07:35 +00:00
Markus Fröschle
b35e12b329 add more DDR clk signals to sdc 2016-01-11 17:05:39 +00:00
Markus Fröschle
476825a3ba translate interrupt_controller to vhd 2016-01-11 16:11:04 +00:00
Markus Fröschle
b3edfcd457 reformat 2016-01-11 07:13:36 +00:00
Markus Fröschle
5c933580a2 fix ACP web address 2015-11-18 06:41:49 +00:00
Markus Fröschle
fc8034d93b patch with Fredi's lp fix (and others) 2015-10-26 06:48:18 +00:00
Markus Fröschle
56adcdd218 added another false path to fix timing 2015-10-18 01:02:05 +00:00
Markus Fröschle
8b7fe5f731 fix timing (set_false_path was missing) 2015-10-18 00:57:04 +00:00
Markus Fröschle
9180cca701 basically working config. Resolution changes still scramble the screen, however 2015-10-17 09:40:48 +00:00
Markus Fröschle
7e2181fbc9 improved timing, added timing constraints, got rid of CLK_33M
Design compiles and runs, but still has issues with different screen resolutions and video clocks
2015-09-23 09:49:05 +00:00
Markus Fröschle
6f0464a1c7 added derive_clock_uncertainty 2015-09-20 19:50:38 +00:00
Markus Fröschle
d9364d9da5 more false_path settings 2015-09-20 19:24:59 +00:00
Markus Fröschle
5d4920f849 upgrade lpm components 2015-09-20 18:08:31 +00:00
Markus Fröschle
bb0f702a45 reformatted, forced tighter timing
Config works, but screen is still scrambled
2015-09-20 17:13:10 +00:00
Markus Fröschle
fb3fcdf996 add false paths to design constraints 2015-09-20 16:23:52 +00:00
Markus Fröschle
6288a1e16b reformatted. 2015-09-20 14:54:16 +00:00
Markus Fröschle
f416539480 get rid of CLK33M 2015-09-20 12:32:02 +00:00
Markus Fröschle
8ec08da1fd add TimeQuest Synopsis Design Constraint file 2015-09-20 07:01:21 +00:00