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This commit is contained in:
Markus Fröschle
2016-06-02 15:57:06 +00:00
parent ba5713a154
commit f03a1eb525
3 changed files with 1127 additions and 1141 deletions
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302
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
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@@ -22,15 +22,15 @@ library ieee;
entity ddr_ctr is entity ddr_ctr is
port port
( (
FB_ADR : in std_logic_vector(31 downto 0); fb_adr : in std_logic_vector(31 downto 0);
nFB_CS1 : in std_logic; nFB_CS1 : in std_logic;
nFB_CS2 : in std_logic; nFB_CS2 : in std_logic;
nFB_CS3 : in std_logic; nFB_CS3 : in std_logic;
nFB_OE : in std_logic; nFB_OE : in std_logic;
FB_SIZE0 : in std_logic; fb_size0 : in std_logic;
FB_SIZE1 : in std_logic; fb_size1 : in std_logic;
nRSTO : in std_logic; nRSTO : in std_logic;
MAIN_CLK : in std_logic; main_clk : in std_logic;
FB_ALE : in std_logic; FB_ALE : in std_logic;
nFB_WR : in std_logic; nFB_WR : in std_logic;
DDR_SYNC_66M : in std_logic; DDR_SYNC_66M : in std_logic;
@@ -46,16 +46,16 @@ entity ddr_ctr is
nVWE : buffer std_logic; nVWE : buffer std_logic;
nVRAS : buffer std_logic; nVRAS : buffer std_logic;
nVCS : buffer std_logic; nVCS : buffer std_logic;
VCKE : buffer std_logic; vcke : buffer std_logic;
nVCAS : buffer std_logic; nVCAS : buffer std_logic;
FB_LE : buffer std_logic_vector(3 downto 0); fb_le : buffer std_logic_vector(3 downto 0);
FB_VDOE : buffer std_logic_vector(3 downto 0); fb_vdoe : buffer std_logic_vector(3 downto 0);
SR_FIFO_WRE : buffer std_logic; SR_FIFO_WRE : buffer std_logic;
SR_DDR_FB : buffer std_logic; SR_DDR_FB : buffer std_logic;
SR_DDR_WR : buffer std_logic; SR_DDR_WR : buffer std_logic;
SR_DDRWR_D_SEL : buffer std_logic; SR_DDRWR_D_SEL : buffer std_logic;
SR_VDMP : buffer std_logic_vector(7 downto 0); SR_VDMP : buffer std_logic_vector(7 downto 0);
VIDEO_DDR_TA : buffer std_logic; video_ddr_ta : buffer std_logic;
SR_BLITTER_DACK : buffer std_logic; SR_BLITTER_DACK : buffer std_logic;
BA : buffer std_logic_vector(1 downto 0); BA : buffer std_logic_vector(1 downto 0);
DDRWR_D_SEL1 : buffer std_logic; DDRWR_D_SEL1 : buffer std_logic;
@@ -73,13 +73,13 @@ architecture rtl of ddr_ctr is
-- READ FIFO -- READ FIFO
-- CLOSE FIFO BANK -- CLOSE FIFO BANK
-- REFRESH 10X7.5NfS=75NS -- REFRESH 10X7.5NfS=75NS
signal FB_REGDDR_3 : std_logic_vector(2 downto 0); signal fb_regddr_3 : std_logic_vector(2 downto 0);
signal FB_REGDDR_d : std_logic_vector(2 downto 0); signal fb_regddr_d : std_logic_vector(2 downto 0);
signal FB_REGDDR_q : std_logic_vector(2 downto 0); signal fb_regddr_q : std_logic_vector(2 downto 0);
signal DDR_SM_6 : std_logic_vector(5 downto 0); signal DDR_SM_6 : std_logic_vector(5 downto 0);
signal DDR_SM_d : std_logic_vector(5 downto 0); signal DDR_SM_d : std_logic_vector(5 downto 0);
signal DDR_SM_q : std_logic_vector(5 downto 0); signal DDR_SM_q : std_logic_vector(5 downto 0);
signal FB_B : std_logic_vector(3 downto 0); signal fb_b : std_logic_vector(3 downto 0);
signal VA_P : std_logic_vector(12 downto 0); signal VA_P : std_logic_vector(12 downto 0);
signal VA_P_d : std_logic_vector(12 downto 0); signal VA_P_d : std_logic_vector(12 downto 0);
signal VA_P_q : std_logic_vector(12 downto 0); signal VA_P_q : std_logic_vector(12 downto 0);
@@ -97,7 +97,7 @@ architecture rtl of ddr_ctr is
signal MCS_q : std_logic_vector(1 downto 0); signal MCS_q : std_logic_vector(1 downto 0);
signal SR_VDMP_d : std_logic_vector(7 downto 0); signal SR_VDMP_d : std_logic_vector(7 downto 0);
signal SR_VDMP_q : std_logic_vector(7 downto 0); signal SR_VDMP_q : std_logic_vector(7 downto 0);
signal CPU_ROW_ADR : std_logic_vector(12 downto 0); signal cpu_row_adr : std_logic_vector(12 downto 0);
signal CPU_BA : std_logic_vector(1 downto 0); signal CPU_BA : std_logic_vector(1 downto 0);
signal CPU_COL_ADR : std_logic_vector(9 downto 0); signal CPU_COL_ADR : std_logic_vector(9 downto 0);
signal BLITTER_ROW_ADR : std_logic_vector(12 downto 0); signal BLITTER_ROW_ADR : std_logic_vector(12 downto 0);
@@ -131,7 +131,7 @@ architecture rtl of ddr_ctr is
signal VIDEO_ACT_ADR : std_logic_vector(26 downto 0); signal VIDEO_ACT_ADR : std_logic_vector(26 downto 0);
signal u0_data : std_logic_vector(7 downto 0); signal u0_data : std_logic_vector(7 downto 0);
signal u0_tridata : std_logic_vector(7 downto 0); signal u0_tridata : std_logic_vector(7 downto 0);
signal FB_REGDDR_0_clk_ctrl : std_logic; signal fb_regddr_0_clk_ctrl : std_logic;
signal SR_VDMP0_clk_ctrl : std_logic; signal SR_VDMP0_clk_ctrl : std_logic;
signal MCS0_clk_ctrl : std_logic; signal MCS0_clk_ctrl : std_logic;
signal VA_S0_clk_ctrl : std_logic; signal VA_S0_clk_ctrl : std_logic;
@@ -182,8 +182,8 @@ architecture rtl of ddr_ctr is
signal BA1_1 : std_logic; signal BA1_1 : std_logic;
signal BA0_2 : std_logic; signal BA0_2 : std_logic;
signal BA0_1 : std_logic; signal BA0_1 : std_logic;
signal BUS_CYC_d_2 : std_logic; signal bus_cyc_d_2 : std_logic;
signal BUS_CYC_d_1 : std_logic; signal bus_cyc_d_1 : std_logic;
signal FIFO_BANK_OK_d_2 : std_logic; signal FIFO_BANK_OK_d_2 : std_logic;
signal FIFO_BANK_OK_d_1 : std_logic; signal FIFO_BANK_OK_d_1 : std_logic;
signal u0_enabledt : std_logic; signal u0_enabledt : std_logic;
@@ -201,7 +201,7 @@ architecture rtl of ddr_ctr is
signal DDR_REFRESH_REQ_clk : std_logic; signal DDR_REFRESH_REQ_clk : std_logic;
signal DDR_REFRESH_REQ_d : std_logic; signal DDR_REFRESH_REQ_d : std_logic;
signal DDR_REFRESH_REQ : std_logic; signal DDR_REFRESH_REQ : std_logic;
signal DDR_REFRESH_ON : std_logic; signal ddr_refresh_on : std_logic;
signal FIFO_BANK_NOT_OK : std_logic; signal FIFO_BANK_NOT_OK : std_logic;
signal FIFO_BANK_OK_q : std_logic; signal FIFO_BANK_OK_q : std_logic;
signal FIFO_BANK_OK_clk : std_logic; signal FIFO_BANK_OK_clk : std_logic;
@@ -239,11 +239,11 @@ architecture rtl of ddr_ctr is
signal BLITTER_REQ_clk : std_logic; signal BLITTER_REQ_clk : std_logic;
signal BLITTER_REQ_d : std_logic; signal BLITTER_REQ_d : std_logic;
signal BLITTER_REQ : std_logic; signal BLITTER_REQ : std_logic;
signal BUS_CYC_END : std_logic; signal bus_cyc_end : std_logic;
signal BUS_CYC_q : std_logic; signal bus_cyc_q : std_logic;
signal BUS_CYC_clk : std_logic; signal bus_cyc_clk : std_logic;
signal BUS_CYC_d : std_logic; signal bus_cyc_d : std_logic;
signal BUS_CYC : std_logic; signal bus_cyc : std_logic;
signal CPU_AC_q : std_logic; signal CPU_AC_q : std_logic;
signal CPU_AC_clk : std_logic; signal CPU_AC_clk : std_logic;
signal CPU_AC_d : std_logic; signal CPU_AC_d : std_logic;
@@ -259,13 +259,13 @@ architecture rtl of ddr_ctr is
signal SR_DDR_WR_q : std_logic; signal SR_DDR_WR_q : std_logic;
signal SR_DDR_WR_clk : std_logic; signal SR_DDR_WR_clk : std_logic;
signal SR_DDR_WR_d : std_logic; signal SR_DDR_WR_d : std_logic;
signal DDR_CONFIG : std_logic; signal ddr_config : std_logic;
signal DDR_CS_q : std_logic; signal ddr_cs_q : std_logic;
signal DDR_CS_ena : std_logic; signal ddr_cs_ena : std_logic;
signal DDR_CS_clk : std_logic; signal ddr_cs_clk : std_logic;
signal DDR_CS_d : std_logic; signal ddr_cs_d : std_logic;
signal DDR_CS : std_logic; signal ddr_cs : std_logic;
signal DDR_SEL : std_logic; signal ddr_sel : std_logic;
signal CPU_DDR_SYNC_q : std_logic; signal CPU_DDR_SYNC_q : std_logic;
signal CPU_DDR_SYNC_clk : std_logic; signal CPU_DDR_SYNC_clk : std_logic;
signal CPU_DDR_SYNC_d : std_logic; signal CPU_DDR_SYNC_d : std_logic;
@@ -354,10 +354,10 @@ begin
end if; end if;
end process; end process;
process (FB_REGDDR_0_clk_ctrl) process (fb_regddr_0_clk_ctrl)
begin begin
if rising_edge(fb_regddr_0_clk_ctrl) then if rising_edge(fb_regddr_0_clk_ctrl) then
FB_REGDDR_q <= FB_REGDDR_d; fb_regddr_q <= fb_regddr_d;
end if; end if;
end process; end process;
@@ -410,11 +410,11 @@ begin
end if; end if;
end process; end process;
process (DDR_CS_clk) process (ddr_cs_clk)
begin begin
if DDR_CS_clk'event and DDR_CS_clk='1' then if ddr_cs_clk'event and ddr_cs_clk='1' then
if DDR_CS_ena='1' then if ddr_cs_ena='1' then
DDR_CS_q <= DDR_CS_d; ddr_cs_q <= ddr_cs_d;
end if; end if;
end if; end if;
end process; end process;
@@ -433,10 +433,10 @@ begin
end if; end if;
end process; end process;
process (BUS_CYC_clk) process (bus_cyc_clk)
begin begin
if BUS_CYC_clk'event and BUS_CYC_clk='1' then if bus_cyc_clk'event and bus_cyc_clk='1' then
BUS_CYC_q <= BUS_CYC_d; bus_cyc_q <= bus_cyc_d;
end if; end if;
end process; end process;
@@ -617,98 +617,98 @@ begin
-- BYT SELECT -- BYT SELECT
-- ADR==0 -- ADR==0
-- LONG UND LINE -- LONG UND LINE
FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); fb_b(0) <= to_std_logic(fb_adr(1 downto 0) = "00") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0));
-- ADR==1 -- ADR==1
-- HIGH WORD -- HIGH WORD
-- LONG UND LINE -- LONG UND LINE
FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); fb_b(1) <= to_std_logic(fb_adr(1 downto 0) = "01") or (fb_size1 and (not fb_size0) and (not fb_adr(1))) or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0));
-- ADR==2 -- ADR==2
-- LONG UND LINE -- LONG UND LINE
FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); fb_b(2) <= to_std_logic(fb_adr(1 downto 0) = "10") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0));
-- ADR==3 -- ADR==3
-- LOW WORD -- LOW WORD
-- LONG UND LINE -- LONG UND LINE
FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); fb_b(3) <= to_std_logic(fb_adr(1 downto 0) = "11") or (fb_size1 and (not fb_size0) and fb_adr(1)) or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0));
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR_0_clk_ctrl <= MAIN_CLK; fb_regddr_0_clk_ctrl <= main_clk;
process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR) process (fb_regddr_q, ddr_sel, bus_cyc_q, LINE, ddr_cs_q, nFB_OE, main_clk, ddr_config, nFB_WR)
variable stdVec3: std_logic_vector(2 downto 0); variable stdVec3: std_logic_vector(2 downto 0);
begin begin
FB_REGDDR_d <= FB_REGDDR_q; fb_regddr_d <= fb_regddr_q;
fb_vdoe <= (others => '0'); fb_vdoe <= (others => '0');
fb_le <= (others => '0'); fb_le <= (others => '0');
video_ddr_ta <= '0'; video_ddr_ta <= '0';
bus_cyc_end <= '0'; bus_cyc_end <= '0';
stdVec3 := FB_REGDDR_q; stdVec3 := fb_regddr_q;
case stdVec3 is case stdVec3 is
when "000" => when "000" =>
FB_LE(0) <= not nFB_WR; fb_le(0) <= not nFB_WR;
-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' then if (bus_cyc_q or (ddr_sel and LINE and (not nFB_WR))) = '1' then
FB_REGDDR_d <= "001"; fb_regddr_d <= "001";
else else
FB_REGDDR_d <= "000"; fb_regddr_d <= "000";
end if; end if;
when "001" => when "001" =>
if DDR_CS_q = '1' then if ddr_cs_q = '1' then
FB_LE(0) <= not nFB_WR; fb_le(0) <= not nFB_WR;
VIDEO_DDR_TA <= '1'; video_ddr_ta <= '1';
if LINE ='1' then if LINE ='1' then
FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); fb_vdoe(0) <= (not nFB_OE) and (not ddr_config);
FB_REGDDR_d <= "010"; fb_regddr_d <= "010";
else else
BUS_CYC_END <= '1'; bus_cyc_end <= '1';
FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); fb_vdoe(0) <= (not nFB_OE) and (not main_clk) and (not ddr_config);
FB_REGDDR_d <= "000"; fb_regddr_d <= "000";
end if; end if;
else else
FB_REGDDR_d <= "000"; fb_regddr_d <= "000";
end if; end if;
when "010" => when "010" =>
if DDR_CS_q = '1' then if ddr_cs_q = '1' then
FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); fb_vdoe(1) <= (not nFB_OE) and (not ddr_config);
FB_LE(1) <= not nFB_WR; fb_le(1) <= not nFB_WR;
VIDEO_DDR_TA <= '1'; video_ddr_ta <= '1';
FB_REGDDR_d <= "011"; fb_regddr_d <= "011";
else else
FB_REGDDR_d <= "000"; fb_regddr_d <= "000";
end if; end if;
when "011" => when "011" =>
if DDR_CS_q ='1' then if ddr_cs_q ='1' then
FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); fb_vdoe(2) <= (not nFB_OE) and (not ddr_config);
FB_LE(2) <= not nFB_WR; fb_le(2) <= not nFB_WR;
-- BEI LINE WRITE EVT. WARTEN -- BEI LINE WRITE EVT. WARTEN
if ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' then if ((not bus_cyc_q) and LINE and (not nFB_WR)) = '1' then
FB_REGDDR_d <= "011"; fb_regddr_d <= "011";
else else
VIDEO_DDR_TA <= '1'; video_ddr_ta <= '1';
FB_REGDDR_d <= "100"; fb_regddr_d <= "100";
end if; end if;
else else
FB_REGDDR_d <= "000"; fb_regddr_d <= "000";
end if; end if;
when "100" => when "100" =>
if DDR_CS_q = '1' then if ddr_cs_q = '1' then
FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); fb_vdoe(3) <= (not nFB_OE) and (not main_clk) and (not ddr_config);
FB_LE(3) <= not nFB_WR; fb_le(3) <= not nFB_WR;
VIDEO_DDR_TA <= '1'; video_ddr_ta <= '1';
BUS_CYC_END <= '1'; bus_cyc_end <= '1';
FB_REGDDR_d <= "000"; fb_regddr_d <= "000";
else else
FB_REGDDR_d <= "000"; fb_regddr_d <= "000";
end if; end if;
when others => when others =>
@@ -718,17 +718,17 @@ begin
end process; end process;
-- DDR STEUERUNG ----------------------------------------------------- -- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; -- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: vcke; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
VCKE <= VIDEO_RAM_CTR(0); vcke <= VIDEO_RAM_CTR(0);
nVCS <= not VIDEO_RAM_CTR(1); nVCS <= not VIDEO_RAM_CTR(1);
DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); ddr_refresh_on <= VIDEO_RAM_CTR(2);
DDR_CONFIG <= VIDEO_RAM_CTR(3); ddr_config <= VIDEO_RAM_CTR(3);
FIFO_ACTIVE <= VIDEO_RAM_CTR(8); FIFO_ACTIVE <= VIDEO_RAM_CTR(8);
-- ------------------------------ -- ------------------------------
CPU_ROW_ADR <= FB_ADR(26 downto 14); cpu_row_adr <= fb_adr(26 downto 14);
CPU_BA <= FB_ADR(13 downto 12); CPU_BA <= fb_adr(13 downto 12);
CPU_COL_ADR <= FB_ADR(11 downto 2); CPU_COL_ADR <= fb_adr(11 downto 2);
nVRAS <= not VRAS; nVRAS <= not VRAS;
nVCAS <= not VCAS; nVCAS <= not VCAS;
nVWE <= not VWE; nVWE <= not VWE;
@@ -744,33 +744,33 @@ begin
DDRWR_D_SEL1 <= BLITTER_AC_q; DDRWR_D_SEL1 <= BLITTER_AC_q;
-- SELECT LOGIC -- SELECT LOGIC
DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); ddr_sel <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01");
DDR_CS_clk <= MAIN_CLK; ddr_cs_clk <= main_clk;
DDR_CS_ena <= FB_ALE; ddr_cs_ena <= FB_ALE;
DDR_CS_d <= DDR_SEL; ddr_cs_d <= ddr_sel;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
-- CONFIG SOFORT LOS -- CONFIG SOFORT LOS
-- LINE WRITE SPÄTER -- LINE WRITE SPÄTER
CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or CPU_SIG <= (ddr_sel and (nFB_WR or (not LINE)) and (not ddr_config)) or
(DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and (not nFB_WR)); (ddr_sel and ddr_config) or (to_std_logic(fb_regddr_q = "010") and (not nFB_WR));
CPU_REQ_clk <= DDR_SYNC_66M; CPU_REQ_clk <= DDR_SYNC_66M;
-- HALTEN BUS CYC BEGONNEN ODER FERTIG -- HALTEN BUS CYC BEGONNEN ODER FERTIG
CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and fb_regddr_q /= "010"
and FB_REGDDR_q /= "100") and (not BUS_CYC_END) and (not BUS_CYC_q)); and fb_regddr_q /= "100") and (not bus_cyc_end) and (not bus_cyc_q));
BUS_CYC_clk <= DDRCLK0; bus_cyc_clk <= DDRCLK0;
BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); bus_cyc_d_1 <= bus_cyc_q and (not bus_cyc_end);
-- STATE MACHINE SYNCHRONISIEREN ----------------- -- STATE MACHINE SYNCHRONISIEREN -----------------
MCS0_clk_ctrl <= DDRCLK0; MCS0_clk_ctrl <= DDRCLK0;
MCS_d(0) <= MAIN_CLK; MCS_d(0) <= main_clk;
MCS_d(1) <= MCS_q(0); MCS_d(1) <= MCS_q(0);
CPU_DDR_SYNC_clk <= DDRCLK0; CPU_DDR_SYNC_clk <= DDRCLK0;
-- NUR 1 WENN EIN -- NUR 1 WENN EIN
CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and vcke and (not nVCS);
-- ------------------------------------------------- -- -------------------------------------------------
VA_S0_clk_ctrl <= DDRCLK0; VA_S0_clk_ctrl <= DDRCLK0;
@@ -785,12 +785,12 @@ begin
DDR_SM_0_clk_ctrl <= DDRCLK0; DDR_SM_0_clk_ctrl <= DDRCLK0;
process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, ddr_config,
CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, cpu_row_adr, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR,
FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA,
FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, fb_b, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q,
VIDEO_ADR_CNT_q, FIFO_COL_ADR, DDR_SEL, LINE, FIFO_BA, VA_P_q, VIDEO_ADR_CNT_q, FIFO_COL_ADR, ddr_sel, LINE, FIFO_BA, VA_P_q,
BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, fb_size0, fb_size1,
DDR_REFRESH_SIG_q) DDR_REFRESH_SIG_q)
variable stdVec6: std_logic_vector(5 downto 0); variable stdVec6: std_logic_vector(5 downto 0);
begin begin
@@ -806,7 +806,7 @@ begin
(FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d,
SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2,
VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2,
BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2, BA1_2, BA0_2, SR_FIFO_WRE_d, bus_cyc_d_2, VWE, VA10_2,
FIFO_BANK_NOT_OK, VCAS, VRAS) <= FIFO_BANK_NOT_OK, VCAS, VRAS) <=
std_logic_vector'("00000000000000000000000000000"); std_logic_vector'("00000000000000000000000000000");
stdVec6 := DDR_SM_q; stdVec6 := DDR_SM_q;
@@ -818,14 +818,14 @@ begin
-- SYNCHRON UND EIN? -- SYNCHRON UND EIN?
elsif (CPU_DDR_SYNC_q)='1' then elsif (CPU_DDR_SYNC_q)='1' then
-- JA -- JA
if (DDR_CONFIG)='1' then if (ddr_config)='1' then
DDR_SM_d <= "001000"; DDR_SM_d <= "001000";
-- BEI WAIT UND LINE WRITE -- BEI WAIT UND LINE WRITE
elsif (CPU_REQ_q)='1' then elsif (CPU_REQ_q)='1' then
VA_S_d <= CPU_ROW_ADR; VA_S_d <= cpu_row_adr;
BA_S_d <= CPU_BA; BA_S_d <= CPU_BA;
CPU_AC_d <= '1'; CPU_AC_d <= '1';
BUS_CYC_d_2 <= '1'; bus_cyc_d_2 <= '1';
DDR_SM_d <= "000010"; DDR_SM_d <= "000010";
else else
-- FIFO IST DEFAULT -- FIFO IST DEFAULT
@@ -849,7 +849,7 @@ begin
when "000001" => when "000001" =>
-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
if (DDR_SEL and (nFB_WR or (not LINE)))='1' then if (ddr_sel and (nFB_WR or (not LINE)))='1' then
VRAS <= '1'; VRAS <= '1';
(VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14);
(BA1_2, BA0_2) <= FB_AD(13 downto 12); (BA1_2, BA0_2) <= FB_AD(13 downto 12);
@@ -857,7 +857,7 @@ begin
VA_S_d(10) <= '1'; VA_S_d(10) <= '1';
CPU_AC_d <= '1'; CPU_AC_d <= '1';
-- BUS CYCLUS LOSTRETEN -- BUS CYCLUS LOSTRETEN
BUS_CYC_d_2 <= '1'; bus_cyc_d_2 <= '1';
else else
VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q);
(VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q;
@@ -875,7 +875,7 @@ begin
CPU_AC_d <= '1'; CPU_AC_d <= '1';
-- BUS CYCLUS LOSTRETEN -- BUS CYCLUS LOSTRETEN
BUS_CYC_d_2 <= '1'; bus_cyc_d_2 <= '1';
DDR_SM_d <= "000011"; DDR_SM_d <= "000011";
when "000011" => when "000011" =>
@@ -912,7 +912,7 @@ begin
BLITTER_AC_d <= BLITTER_AC_q; BLITTER_AC_d <= BLITTER_AC_q;
VCAS <= '1'; VCAS <= '1';
-- READ DATEN FÜR CPU -- READ DATEN FÃœR CPU
SR_DDR_FB <= CPU_AC_q; SR_DDR_FB <= CPU_AC_q;
-- BLITTER DACK AND BLITTER LATCH DATEN -- BLITTER DACK AND BLITTER LATCH DATEN
@@ -959,7 +959,7 @@ begin
BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA);
-- BYTE ENABLE WRITE -- BYTE ENABLE WRITE
SR_VDMP_d(7 downto 4) <= FB_B; SR_VDMP_d(7 downto 4) <= fb_b;
-- LINE ENABLE WRITE -- LINE ENABLE WRITE
SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111";
@@ -974,7 +974,7 @@ begin
-- WRITE COMMAND CPU UND BLITTER if WRITER -- WRITE COMMAND CPU UND BLITTER if WRITER
SR_DDR_WR_d <= '1'; SR_DDR_WR_d <= '1';
-- 2. HÄLFTE WRITE DATEN SELEKTIEREN -- 2. HÄLFTE WRITE DATEN SELEKTIEREN
SR_DDRWR_D_SEL_d <= '1'; SR_DDRWR_D_SEL_d <= '1';
-- WENN LINE DANN ACTIV -- WENN LINE DANN ACTIV
@@ -988,7 +988,7 @@ begin
-- WRITE COMMAND CPU UND BLITTER if WRITE -- WRITE COMMAND CPU UND BLITTER if WRITE
SR_DDR_WR_d <= '1'; SR_DDR_WR_d <= '1';
-- 2. HÄLFTE WRITE DATEN SELEKTIEREN -- 2. HÄLFTE WRITE DATEN SELEKTIEREN
SR_DDRWR_D_SEL_d <= '1'; SR_DDRWR_D_SEL_d <= '1';
DDR_SM_d <= "010100"; DDR_SM_d <= "010100";
@@ -1131,14 +1131,14 @@ begin
end if; end if;
when "011100" => when "011100" =>
if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then if (ddr_sel and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then
VRAS <= '1'; VRAS <= '1';
(VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14);
(BA1_2, BA0_2) <= FB_AD(13 downto 12); (BA1_2, BA0_2) <= FB_AD(13 downto 12);
CPU_AC_d <= '1'; CPU_AC_d <= '1';
-- BUS CYCLUS LOSTRETEN -- BUS CYCLUS LOSTRETEN
BUS_CYC_d_2 <= '1'; bus_cyc_d_2 <= '1';
-- AUTO PRECHARGE DA NICHT FIFO BANK -- AUTO PRECHARGE DA NICHT FIFO BANK
VA_S_d(10) <= '1'; VA_S_d(10) <= '1';
@@ -1159,7 +1159,7 @@ begin
DDR_SM_d <= "001001"; DDR_SM_d <= "001001";
when "001001" => when "001001" =>
BUS_CYC_d_2 <= CPU_REQ_q; bus_cyc_d_2 <= CPU_REQ_q;
DDR_SM_d <= "001010"; DDR_SM_d <= "001010";
when "001010" => when "001010" =>
@@ -1180,13 +1180,13 @@ begin
when "001101" => when "001101" =>
-- NUR BEI LONG WRITE -- NUR BEI LONG WRITE
VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); VRAS <= FB_AD(18) and (not nFB_WR) and (not fb_size0) and (not fb_size1);
-- NUR BEI LONG WRITE -- NUR BEI LONG WRITE
VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); VCAS <= FB_AD(17) and (not nFB_WR) and (not fb_size0) and (not fb_size1);
-- NUR BEI LONG WRITE -- NUR BEI LONG WRITE
VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); VWE <= FB_AD(16) and (not nFB_WR) and (not fb_size0) and (not fb_size1);
-- CLOSE FIFO BANK -- CLOSE FIFO BANK
DDR_SM_d <= "000111"; DDR_SM_d <= "000111";
@@ -1196,7 +1196,7 @@ begin
-- AUF NOT OK -- AUF NOT OK
FIFO_BANK_NOT_OK <= '1'; FIFO_BANK_NOT_OK <= '1';
-- BÄNKE SCHLIESSEN -- BÄNKE SCHLIESSEN
VRAS <= '1'; VRAS <= '1';
VWE <= '1'; VWE <= '1';
DDR_SM_d <= "000110"; DDR_SM_d <= "000110";
@@ -1205,7 +1205,7 @@ begin
-- AUF NOT OK -- AUF NOT OK
FIFO_BANK_NOT_OK <= '1'; FIFO_BANK_NOT_OK <= '1';
-- BÄNKE SCHLIESSEN -- BÄNKE SCHLIESSEN
VRAS <= '1'; VRAS <= '1';
VWE <= '1'; VWE <= '1';
@@ -1263,7 +1263,7 @@ begin
-- BLITTER ---------------------- -- BLITTER ----------------------
-- --------------------------------------- -- ---------------------------------------
BLITTER_REQ_clk <= DDRCLK0; BLITTER_REQ_clk <= DDRCLK0;
BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); BLITTER_REQ_d <= BLITTER_SIG and (not ddr_config) and vcke and (not nVCS);
BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14);
BLITTER_BA(1) <= BLITTER_ADR(13); BLITTER_BA(1) <= BLITTER_ADR(13);
BLITTER_BA(0) <= BLITTER_ADR(12); BLITTER_BA(0) <= BLITTER_ADR(12);
@@ -1276,7 +1276,7 @@ begin
FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or
(to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and
FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not
STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); STOP_q) and (not ddr_config) and vcke and (not nVCS);
FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10);
FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); FIFO_BA(1) <= VIDEO_ADR_CNT_q(9);
FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); FIFO_BA(0) <= VIDEO_ADR_CNT_q(8);
@@ -1286,7 +1286,7 @@ begin
FIFO_BANK_OK_clk <= DDRCLK0; FIFO_BANK_OK_clk <= DDRCLK0;
FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK);
-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- -- ZÄHLER RÃœCKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC_clk <= DDRCLK0; CLR_FIFO_SYNC_clk <= DDRCLK0;
-- SYNCHRONISIEREN -- SYNCHRONISIEREN
@@ -1296,7 +1296,7 @@ begin
STOP_clk <= DDRCLK0; STOP_clk <= DDRCLK0;
STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q;
-- ZÄHLEN ----------------------------------------------- -- ZÄHLEN -----------------------------------------------
VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0;
VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q;
VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or
@@ -1320,60 +1320,60 @@ begin
-- --------------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------------------
DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; DDR_REFRESH_CNT0_clk_ctrl <= CLK33M;
-- ZÄHLEN 0-2047 -- ZÄHLEN 0-2047
DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + unsigned'("00000000001")); DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + unsigned'("00000000001"));
REFRESH_TIME_clk <= DDRCLK0; REFRESH_TIME_clk <= DDRCLK0;
-- SYNC -- SYNC
REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not MAIN_CLK); REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not main_clk);
DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0;
DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = "100011"); DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = "100011");
-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) -- 9 STÃœCK (8 REFRESH UND 1 ALS VORLAUF)
-- MINUS 1 WENN GEMACHT -- MINUS 1 WENN GEMACHT
DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and
sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)) or (sizeIt(not sizeIt(ddr_refresh_on,4) and sizeIt(not ddr_config,4)) or (sizeIt(not
REFRESH_TIME_q,4) and (std_logic_vector'(unsigned(DDR_REFRESH_SIG_q) - REFRESH_TIME_q,4) and (std_logic_vector'(unsigned(DDR_REFRESH_SIG_q) -
unsigned'("0001"))) and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not unsigned'("0001"))) and sizeIt(ddr_refresh_on,4) and sizeIt(not
DDR_CONFIG,4)); ddr_config,4));
DDR_REFRESH_REQ_clk <= DDRCLK0; DDR_REFRESH_REQ_clk <= DDRCLK0;
DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and ddr_refresh_on and (not REFRESH_TIME_q) and (not ddr_config);
-- --------------------------------------------------------- -- ---------------------------------------------------------
-- VIDEO REGISTER ----------------------- -- VIDEO REGISTER -----------------------
-- ------------------------------------------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; VIDEO_BASE_L_D0_clk_ctrl <= main_clk;
-- 820D/2 -- 820D/2
VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000110"); VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000110");
-- SORRY, NUR 16 BYT GRENZEN -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); VIDEO_BASE_L_D_d <= FB_AD(23 downto 16);
VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and fb_b(1);
VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; VIDEO_BASE_M_D0_clk_ctrl <= main_clk;
-- 8203/2 -- 8203/2
VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000001"); VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000001");
VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); VIDEO_BASE_M_D_d <= FB_AD(23 downto 16);
VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and fb_b(3);
VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; VIDEO_BASE_H_D0_clk_ctrl <= main_clk;
-- 8200-1/2 -- 8200-1/2
VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000000"); VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000000");
VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); VIDEO_BASE_H_D_d <= FB_AD(23 downto 16);
VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(1);
VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; VIDEO_BASE_X_D0_clk_ctrl <= main_clk;
VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); VIDEO_BASE_X_D_d <= FB_AD(26 downto 24);
VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(0);
-- 8209/2 -- 8209/2
VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000100"); VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000100");
-- 8207/2 -- 8207/2
VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000011"); VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000011");
-- 8204,5/2 -- 8204,5/2
VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000010"); VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000010");
-- FB_AD[31..24] = lpm_bustri_BYT( -- FB_AD[31..24] = lpm_bustri_BYT(
-- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[])
@@ -1397,7 +1397,7 @@ begin
-- Assignments added to explicitly combine the -- Assignments added to explicitly combine the
-- effects of multiple drivers in the source -- effects of multiple drivers in the source
FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2;
BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; bus_cyc_d <= bus_cyc_d_1 or bus_cyc_d_2;
BA(0) <= BA0_1 or BA0_2; BA(0) <= BA0_1 or BA0_2;
BA(1) <= BA1_1 or BA1_2; BA(1) <= BA1_1 or BA1_2;
VA(0) <= VA0_1 or VA0_2; VA(0) <= VA0_1 or VA0_2;

475
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
View File

@@ -35,18 +35,18 @@
-- VERZ2_.clk VERZ2_clk -- VERZ2_.clk VERZ2_clk
-- VERZ2_.d VERZ2_d -- VERZ2_.d VERZ2_d
-- VERZ2_ VERZ2 -- VERZ2_ VERZ2
-- CLUT_MUX_AV0_.q CLUT_MUX_AV0_q -- clut_mux_av0_.q clut_mux_av0_q
-- CLUT_MUX_AV0_.prn CLUT_MUX_AV0_prn -- clut_mux_av0_.prn clut_mux_av0_prn
-- CLUT_MUX_AV0_.clrn CLUT_MUX_AV0_clrn -- clut_mux_av0_.clrn clut_mux_av0_clrn
-- CLUT_MUX_AV0_.clk CLUT_MUX_AV0_clk -- clut_mux_av0_.clk clut_mux_av0_clk
-- CLUT_MUX_AV0_.d CLUT_MUX_AV0_d -- clut_mux_av0_.d clut_mux_av0_d
-- CLUT_MUX_AV0_ CLUT_MUX_AV0 -- clut_mux_av0_ clut_mux_av0
-- CLUT_MUX_AV1_.q CLUT_MUX_AV1_q -- clut_mux_av1_.q clut_mux_av1_q
-- CLUT_MUX_AV1_.prn CLUT_MUX_AV1_prn -- clut_mux_av1_.prn clut_mux_av1_prn
-- CLUT_MUX_AV1_.clrn CLUT_MUX_AV1_clrn -- clut_mux_av1_.clrn clut_mux_av1_clrn
-- CLUT_MUX_AV1_.clk CLUT_MUX_AV1_clk -- clut_mux_av1_.clk clut_mux_av1_clk
-- CLUT_MUX_AV1_.d CLUT_MUX_AV1_d -- clut_mux_av1_.d clut_mux_av1_d
-- CLUT_MUX_AV1_ CLUT_MUX_AV1 -- clut_mux_av1_ clut_mux_av1
-- CREATED BY FREDI ASCHWANDEN -- CREATED BY FREDI ASCHWANDEN
@@ -56,6 +56,9 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
library work;
use work.firebee_utils_pkg.all;
entity video_mod_mux_clutctr is entity video_mod_mux_clutctr is
port port
@@ -85,7 +88,7 @@ entity video_mod_mux_clutctr is
FALCON_CLUT_WR : out std_logic_vector(3 downto 0); FALCON_CLUT_WR : out std_logic_vector(3 downto 0);
ST_CLUT_RD : out std_logic; ST_CLUT_RD : out std_logic;
ST_CLUT_WR : out std_logic_vector(1 downto 0); ST_CLUT_WR : out std_logic_vector(1 downto 0);
CLUT_MUX_ADR : out std_logic_vector(3 downto 0); clut_mux_adr : out std_logic_vector(3 downto 0);
HSYNC : out std_logic; HSYNC : out std_logic;
VSYNC : out std_logic; VSYNC : out std_logic;
nBLANK : out std_logic; nBLANK : out std_logic;
@@ -99,7 +102,7 @@ entity video_mod_mux_clutctr is
BLITTER_ON : out std_logic; BLITTER_ON : out std_logic;
VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); VIDEO_RAM_CTR : out std_logic_vector(15 downto 0);
VIDEO_MOD_TA : out std_logic; VIDEO_MOD_TA : out std_logic;
BORDER_COLOR : out std_logic_vector(23 downto 0); border_color : out std_logic_vector(23 downto 0);
CCSEL : out std_logic_vector(2 downto 0); CCSEL : out std_logic_vector(2 downto 0);
ACP_CLUT_WR : out std_logic_vector(3 downto 0); ACP_CLUT_WR : out std_logic_vector(3 downto 0);
INTER_ZEI : out std_logic; INTER_ZEI : out std_logic;
@@ -116,7 +119,7 @@ end video_mod_mux_clutctr;
architecture rtl of video_mod_mux_clutctr is architecture rtl of video_mod_mux_clutctr is
-- DIV. CONTROL REGISTER -- DIV. CONTROL REGISTER
-- BRAUCHT EIN WAITSTAT -- BRAUCHT EIN WAITSTAT
-- LÄNGE HSYNC PULS IN PIXEL_CLK -- LÄNGE HSYNC PULS IN PIXEL_CLK
-- LETZTES PIXEL EINER ZEILE ERREICHT -- LETZTES PIXEL EINER ZEILE ERREICHT
-- ATARI RESOLUTION -- ATARI RESOLUTION
-- HORIZONTAL TIMING 640x480 -- HORIZONTAL TIMING 640x480
@@ -125,42 +128,42 @@ architecture rtl of video_mod_mux_clutctr is
-- VERTIKAL TIMING 320x240 -- VERTIKAL TIMING 320x240
-- HORIZONTAL -- HORIZONTAL
-- VERTIKAL -- VERTIKAL
signal VR_DOUT : std_logic_vector(8 downto 0); signal vr_dout : std_logic_vector(8 downto 0);
signal VR_DOUT_d : std_logic_vector(8 downto 0); signal vr_dout_d : std_logic_vector(8 downto 0);
signal VR_DOUT_q : std_logic_vector(8 downto 0); signal vr_dout_q : std_logic_vector(8 downto 0);
signal VR_FRQ : unsigned(7 downto 0); signal vr_frq : unsigned(7 downto 0);
signal VR_FRQ_d : std_logic_vector(7 downto 0); signal vr_frq_d : std_logic_vector(7 downto 0);
signal VR_FRQ_q : std_logic_vector(7 downto 0); signal vr_frq_q : std_logic_vector(7 downto 0);
signal FB_B : std_logic_vector(3 downto 0); signal FB_B : std_logic_vector(3 downto 0);
signal FB_16B : std_logic_vector(1 downto 0); signal FB_16B : std_logic_vector(1 downto 0);
signal ST_SHIFT_MODE : std_logic_vector(1 downto 0); signal st_shift_mode : std_logic_vector(1 downto 0);
signal ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); signal st_shift_mode_d : std_logic_vector(1 downto 0);
signal ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); signal st_shift_mode_q : std_logic_vector(1 downto 0);
signal FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); signal falcon_shift_mode : std_logic_vector(10 downto 0);
signal FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); signal falcon_shift_mode_d : std_logic_vector(10 downto 0);
signal FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); signal falcon_shift_mode_q : std_logic_vector(10 downto 0);
signal CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); signal clut_mux_adr_d : std_logic_vector(3 downto 0);
signal CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); signal clut_mux_adr_q : std_logic_vector(3 downto 0);
signal CLUT_MUX_AV1 : std_logic_vector(3 downto 0); signal clut_mux_av1 : std_logic_vector(3 downto 0);
signal CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); signal clut_mux_av1_d : std_logic_vector(3 downto 0);
signal CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); signal clut_mux_av1_q : std_logic_vector(3 downto 0);
signal CLUT_MUX_AV0 : std_logic_vector(3 downto 0); signal clut_mux_av0 : std_logic_vector(3 downto 0);
signal CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); signal clut_mux_av0_d : std_logic_vector(3 downto 0);
signal CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); signal clut_mux_av0_q : std_logic_vector(3 downto 0);
signal ACP_VCTR : std_logic_vector(31 downto 0); signal acp_vctr : std_logic_vector(31 downto 0);
signal ACP_VCTR_d : std_logic_vector(31 downto 0); signal acp_vctr_d : std_logic_vector(31 downto 0);
signal ACP_VCTR_q : std_logic_vector(31 downto 0); signal acp_vctr_q : std_logic_vector(31 downto 0);
signal BORDER_COLOR_d : std_logic_vector(23 downto 0); signal border_color_d : std_logic_vector(23 downto 0);
signal BORDER_COLOR_q : std_logic_vector(23 downto 0); signal border_color_q : std_logic_vector(23 downto 0);
signal SYS_CTR : std_logic_vector(6 downto 0); signal sys_ctr : std_logic_vector(6 downto 0);
signal SYS_CTR_d : std_logic_vector(6 downto 0); signal sys_ctr_d : std_logic_vector(6 downto 0);
signal SYS_CTR_q : std_logic_vector(6 downto 0); signal sys_ctr_q : std_logic_vector(6 downto 0);
signal LOF : std_logic_vector(15 downto 0); signal lof : std_logic_vector(15 downto 0);
signal LOF_d : std_logic_vector(15 downto 0); signal lof_d : std_logic_vector(15 downto 0);
signal LOF_q : std_logic_vector(15 downto 0); signal lof_q : std_logic_vector(15 downto 0);
signal LWD : std_logic_vector(15 downto 0); signal lwd : std_logic_vector(15 downto 0);
signal LWD_d : std_logic_vector(15 downto 0); signal lwd_d : std_logic_vector(15 downto 0);
signal LWD_q : std_logic_vector(15 downto 0); signal lwd_q : std_logic_vector(15 downto 0);
signal HSYNC_I : std_logic_vector(7 downto 0); signal HSYNC_I : std_logic_vector(7 downto 0);
signal HSYNC_I_d : std_logic_vector(7 downto 0); signal HSYNC_I_d : std_logic_vector(7 downto 0);
signal HSYNC_I_q : std_logic_vector(7 downto 0); signal HSYNC_I_q : std_logic_vector(7 downto 0);
@@ -266,17 +269,17 @@ architecture rtl of video_mod_mux_clutctr is
signal u0_tridata : std_logic_vector(15 downto 0); signal u0_tridata : std_logic_vector(15 downto 0);
signal u1_data : std_logic_vector(15 downto 0); signal u1_data : std_logic_vector(15 downto 0);
signal u1_tridata : std_logic_vector(15 downto 0); signal u1_tridata : std_logic_vector(15 downto 0);
-- signal ST_SHIFT_MODE0_clk_ctrl : std_logic; -- signal st_shift_mode0_clk_ctrl : std_logic;
signal ST_SHIFT_MODE0_ena_ctrl : std_logic; signal st_shift_mode0_ena_ctrl : std_logic;
-- signal FALCON_SHIFT_MODE0_clk_ctrl : std_logic; -- signal falcon_shift_mode0_clk_ctrl : std_logic;
signal FALCON_SHIFT_MODE8_ena_ctrl : std_logic; signal falcon_shift_mode8_ena_ctrl : std_logic;
signal FALCON_SHIFT_MODE0_ena_ctrl : std_logic; signal falcon_shift_mode0_ena_ctrl : std_logic;
signal ACP_VCTR24_ena_ctrl : std_logic; signal acp_vctr24_ena_ctrl : std_logic;
signal ACP_VCTR16_ena_ctrl : std_logic; signal acp_vctr16_ena_ctrl : std_logic;
signal ACP_VCTR8_ena_ctrl : std_logic; signal acp_vctr8_ena_ctrl : std_logic;
signal ACP_VCTR6_ena_ctrl : std_logic; signal acp_vctr6_ena_ctrl : std_logic;
signal ACP_VCTR0_ena_ctrl : std_logic; signal acp_vctr0_ena_ctrl : std_logic;
signal ATARI_HH24_ena_ctrl : std_logic; signal ATARI_HH24_ena_ctrl : std_logic;
signal ATARI_HH16_ena_ctrl : std_logic; signal ATARI_HH16_ena_ctrl : std_logic;
@@ -295,16 +298,16 @@ architecture rtl of video_mod_mux_clutctr is
signal ATARI_VL16_ena_ctrl : std_logic; signal ATARI_VL16_ena_ctrl : std_logic;
signal ATARI_VL8_ena_ctrl : std_logic; signal ATARI_VL8_ena_ctrl : std_logic;
signal ATARI_VL0_ena_ctrl : std_logic; signal ATARI_VL0_ena_ctrl : std_logic;
signal VR_DOUT0_ena_ctrl : std_logic; signal vr_dout0_ena_ctrl : std_logic;
signal VR_FRQ0_ena_ctrl : std_logic; signal vr_frq0_ena_ctrl : std_logic;
signal BORDER_COLOR16_ena_ctrl : std_logic; signal border_color16_ena_ctrl : std_logic;
signal BORDER_COLOR8_ena_ctrl : std_logic; signal border_color8_ena_ctrl : std_logic;
signal BORDER_COLOR0_ena_ctrl : std_logic; signal border_color0_ena_ctrl : std_logic;
signal SYS_CTR0_ena_ctrl : std_logic; signal sys_ctr0_ena_ctrl : std_logic;
signal LOF8_ena_ctrl : std_logic; signal lof8_ena_ctrl : std_logic;
signal LOF0_ena_ctrl : std_logic; signal lof0_ena_ctrl : std_logic;
signal LWD8_ena_ctrl : std_logic; signal lwd8_ena_ctrl : std_logic;
signal LWD0_ena_ctrl : std_logic; signal lwd0_ena_ctrl : std_logic;
signal HHT8_ena_ctrl : std_logic; signal HHT8_ena_ctrl : std_logic;
signal HHT0_ena_ctrl : std_logic; signal HHT0_ena_ctrl : std_logic;
signal HBE8_ena_ctrl : std_logic; signal HBE8_ena_ctrl : std_logic;
@@ -441,14 +444,14 @@ architecture rtl of video_mod_mux_clutctr is
signal CLUT_TA_q : std_logic; signal CLUT_TA_q : std_logic;
signal CLUT_TA_d : std_logic; signal CLUT_TA_d : std_logic;
signal CLUT_TA : std_logic; signal CLUT_TA : std_logic;
signal LWD_CS : std_logic; signal lwd_CS : std_logic;
signal LOF_CS : std_logic; signal lof_CS : std_logic;
signal SYS_CTR_CS : std_logic; signal sys_ctr_CS : std_logic;
signal ACP_VIDEO_ON : std_logic; signal ACP_VIDEO_ON : std_logic;
signal BORDER_COLOR_CS : std_logic; signal border_color_CS : std_logic;
signal ACP_VCTR_CS : std_logic; signal acp_vctr_CS : std_logic;
signal FALCON_SHIFT_MODE_CS : std_logic; signal falcon_shift_mode_CS : std_logic;
signal ST_SHIFT_MODE_CS : std_logic; signal st_shift_mode_CS : std_logic;
signal ST_CLUT : std_logic; signal ST_CLUT : std_logic;
signal ST_CLUT_CS : std_logic; signal ST_CLUT_CS : std_logic;
signal FALCON_CLUT : std_logic; signal FALCON_CLUT : std_logic;
@@ -493,26 +496,6 @@ architecture rtl of video_mod_mux_clutctr is
end loop; end loop;
return rep; return rep;
end function sizeit; end function sizeit;
-- f_addr_cmp() compares addr against addr_const (only counting from the highest significant bit of the smaller
-- number, ignoring ignore least significant bits) and returns true if both addresses match, false otherwise
function f_addr_cmp(signal addr : std_logic_vector; constant addr_const : std_logic_vector; constant ignore : integer) return boolean is
variable c_len : integer := addr_const'high;
variable a_len : integer := addr'high;
variable len : integer;
variable result : boolean := false;
begin
if c_len < a_len then
len := c_len;
else
len := a_len;
end if;
for i in len downto len - ignore loop
result := addr_const(i) = addr(i);
exit when result = false;
end loop;
return result;
end function f_addr_cmp;
begin begin
-- Sub Module Section -- Sub Module Section
@@ -534,11 +517,11 @@ begin
-- Register Section -- Register Section
CLUT_MUX_ADR <= CLUT_MUX_ADR_q; clut_mux_adr <= clut_mux_adr_q;
-- missing signals that seem to got lost during conversion -- missing signals that seem to got lost during conversion
HSYNC <= HSYNC_q; HSYNC <= HSYNC_q;
ACP_VCTR <= ACP_VCTR_q; acp_vctr <= acp_vctr_q;
RAND <= RAND_q; RAND <= RAND_q;
ATARI_HH <= ATARI_HH_q; ATARI_HH <= ATARI_HH_q;
ATARI_HL <= ATARI_HL_q; ATARI_HL <= ATARI_HL_q;
@@ -550,9 +533,9 @@ begin
VSYNC <= VSYNC_q; VSYNC <= VSYNC_q;
nBLANK <= nBLANK_q; nBLANK <= nBLANK_q;
FIFO_RDE <= FIFO_RDE_q; FIFO_RDE <= FIFO_RDE_q;
BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); border_color(23 downto 16) <= border_color_q(23 downto 16);
BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); border_color(15 downto 8) <= border_color_q(15 downto 8);
BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); border_color(7 downto 0) <= border_color_q(7 downto 0);
CCSEL <= CCSEL_q; CCSEL <= CCSEL_q;
INTER_ZEI <= INTER_ZEI_q; INTER_ZEI <= INTER_ZEI_q;
DOP_FIFO_CLR <= DOP_FIFO_CLR_q; DOP_FIFO_CLR <= DOP_FIFO_CLR_q;
@@ -561,18 +544,18 @@ begin
process (pixel_clk_i) process (pixel_clk_i)
begin begin
if rising_edge(pixel_clk_i) then if rising_edge(pixel_clk_i) then
CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; clut_mux_adr_q <= clut_mux_adr_d;
HSYNC_q <= HSYNC_d; HSYNC_q <= HSYNC_d;
VSYNC_q <= VSYNC_d; VSYNC_q <= VSYNC_d;
nBLANK_q <= nBLANK_d; nBLANK_q <= nBLANK_d;
FIFO_RDE_q <= FIFO_RDE_d; FIFO_RDE_q <= FIFO_RDE_d;
if BORDER_COLOR16_ena_ctrl = '1' then if border_color16_ena_ctrl = '1' then
border_color_q(23 downto 16) <= border_color_d(23 downto 16); border_color_q(23 downto 16) <= border_color_d(23 downto 16);
end if; end if;
if BORDER_COLOR8_ena_ctrl = '1' THEN if border_color8_ena_ctrl = '1' THEN
border_color_q(15 downto 8) <= border_color_d(15 downto 8); border_color_q(15 downto 8) <= border_color_d(15 downto 8);
END IF; END IF;
IF BORDER_COLOR0_ena_ctrl = '1' THEN IF border_color0_ena_ctrl = '1' THEN
border_color_q(7 downto 0) <= border_color_d(7 downto 0); border_color_q(7 downto 0) <= border_color_d(7 downto 0);
END IF; END IF;
CCSEL_q <= CCSEL_d; CCSEL_q <= CCSEL_d;
@@ -602,7 +585,7 @@ begin
END IF; END IF;
END PROCESS; END PROCESS;
VR_FRQ <= unsigned(VR_FRQ_q); vr_frq <= unsigned(vr_frq_q);
PROCESS (main_clk) PROCESS (main_clk)
BEGIN BEGIN
@@ -613,63 +596,63 @@ begin
CLK17M_q <= CLK17M_d; CLK17M_q <= CLK17M_d;
IF VR_DOUT0_ena_ctrl = '1' THEN IF vr_dout0_ena_ctrl = '1' THEN
VR_DOUT_q <= VR_DOUT_d; vr_dout_q <= vr_dout_d;
END IF; END IF;
IF VR_FRQ0_ena_ctrl = '1' THEN IF vr_frq0_ena_ctrl = '1' THEN
VR_FRQ_q <= VR_FRQ_d; vr_frq_q <= vr_frq_d;
END IF; END IF;
IF ST_SHIFT_MODE0_ena_ctrl = '1' THEN IF st_shift_mode0_ena_ctrl = '1' THEN
ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; st_shift_mode_q <= st_shift_mode_d;
END IF; END IF;
IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN IF falcon_shift_mode8_ena_ctrl = '1' THEN
falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8);
END IF; END IF;
IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN IF falcon_shift_mode0_ena_ctrl = '1' THEN
falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0);
END IF; END IF;
IF ACP_VCTR24_ena_ctrl = '1' THEN IF acp_vctr24_ena_ctrl = '1' THEN
ACP_VCTR_q(31 downto 24) <= ACP_VCTR_d(31 downto 24); acp_vctr_q(31 downto 24) <= acp_vctr_d(31 downto 24);
END IF; END IF;
IF ACP_VCTR16_ena_ctrl = '1' THEN IF acp_vctr16_ena_ctrl = '1' THEN
ACP_VCTR_q(23 downto 16) <= ACP_VCTR_d(23 downto 16); acp_vctr_q(23 downto 16) <= acp_vctr_d(23 downto 16);
END IF; END IF;
IF ACP_VCTR8_ena_ctrl = '1' THEN IF acp_vctr8_ena_ctrl = '1' THEN
ACP_VCTR_q(15 downto 8) <= ACP_VCTR_d(15 downto 8); acp_vctr_q(15 downto 8) <= acp_vctr_d(15 downto 8);
END IF; END IF;
IF ACP_VCTR6_ena_ctrl = '1' THEN IF acp_vctr6_ena_ctrl = '1' THEN
ACP_VCTR_q(7 downto 6) <= ACP_VCTR_d(7 downto 6); acp_vctr_q(7 downto 6) <= acp_vctr_d(7 downto 6);
END IF; END IF;
IF ACP_VCTR0_ena_ctrl = '1' THEN IF acp_vctr0_ena_ctrl = '1' THEN
ACP_VCTR_q(5 downto 0) <= ACP_VCTR_d(5 downto 0); acp_vctr_q(5 downto 0) <= acp_vctr_d(5 downto 0);
END IF; END IF;
IF SYS_CTR0_ena_ctrl='1' THEN IF sys_ctr0_ena_ctrl='1' THEN
SYS_CTR_q <= SYS_CTR_d; sys_ctr_q <= sys_ctr_d;
END IF; END IF;
IF LOF8_ena_ctrl = '1' THEN IF lof8_ena_ctrl = '1' THEN
LOF_q(15 downto 8) <= LOF_d(15 downto 8); lof_q(15 downto 8) <= lof_d(15 downto 8);
END IF; END IF;
IF LOF0_ena_ctrl = '1' THEN IF lof0_ena_ctrl = '1' THEN
LOF_q(7 downto 0) <= LOF_d(7 downto 0); lof_q(7 downto 0) <= lof_d(7 downto 0);
END IF; END IF;
IF LWD8_ena_ctrl = '1' THEN IF lwd8_ena_ctrl = '1' THEN
LWD_q(15 downto 8) <= LWD_d(15 downto 8); lwd_q(15 downto 8) <= lwd_d(15 downto 8);
END IF; END IF;
IF LWD0_ena_ctrl = '1' THEN IF lwd0_ena_ctrl = '1' THEN
LWD_q(7 downto 0) <= LWD_d(7 downto 0); lwd_q(7 downto 0) <= lwd_d(7 downto 0);
END IF; END IF;
IF HDB8_ena_ctrl = '1' THEN IF HDB8_ena_ctrl = '1' THEN
@@ -771,8 +754,8 @@ begin
PROCESS (pixel_clk_i) PROCESS (pixel_clk_i)
BEGIN BEGIN
IF rising_edge(pixel_clk_i) THEN IF rising_edge(pixel_clk_i) THEN
CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; clut_mux_av1_q <= clut_mux_av1_d;
CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; clut_mux_av0_q <= clut_mux_av0_d;
CLUT_TA_q <= CLUT_TA_d; CLUT_TA_q <= CLUT_TA_d;
HSYNC_I_q <= HSYNC_I_d; HSYNC_I_q <= HSYNC_I_d;
HSY_LEN_q <= HSY_LEN_d; HSY_LEN_q <= HSY_LEN_d;
@@ -972,31 +955,31 @@ begin
-- $F8260/2 -- $F8260/2
st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0'; st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0';
-- ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000");
ST_SHIFT_MODE_d <= FB_AD(25 downto 24); st_shift_mode_d <= FB_AD(25 downto 24);
ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and FB_B(0);
-- MONO -- MONO
COLOR1_1 <= to_std_logic(ST_SHIFT_MODE_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); COLOR1_1 <= to_std_logic(st_shift_mode_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON);
-- 4 FARBEN -- 4 FARBEN
COLOR2 <= to_std_logic(ST_SHIFT_MODE_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); COLOR2 <= to_std_logic(st_shift_mode_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON);
-- 16 FARBEN -- 16 FARBEN
COLOR4_1 <= to_std_logic(ST_SHIFT_MODE_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON);
-- FALCON SHIFT MODE -- FALCON SHIFT MODE
-- $F8266/2 -- $F8266/2
FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011"); falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011");
FALCON_SHIFT_MODE_d <= FB_AD(26 downto 16); falcon_shift_mode_d <= FB_AD(26 downto 16);
FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(2); falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(2);
FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(3); falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(3);
CLUT_OFF <= FALCON_SHIFT_MODE_q(3 downto 0) and sizeIt(COLOR4_i, 4); CLUT_OFF <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4);
COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR1_2 <= falcon_shift_mode_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON);
COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR8_1 <= falcon_shift_mode_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON);
COLOR16_1 <= FALCON_SHIFT_MODE_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR16_1 <= falcon_shift_mode_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON);
COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON);
-- ACP VIDEO CONTROL -- ACP VIDEO CONTROL
@@ -1015,21 +998,21 @@ begin
-- BIT 26 = STANDARD ATARI SYNCS -- BIT 26 = STANDARD ATARI SYNCS
-- $400/4 -- $400/4
ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000"); acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000");
ACP_VCTR_d(31 downto 8) <= FB_AD(31 downto 8); acp_vctr_d(31 downto 8) <= FB_AD(31 downto 8);
ACP_VCTR_d(5 downto 0) <= FB_AD(5 downto 0); acp_vctr_d(5 downto 0) <= FB_AD(5 downto 0);
ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); acp_vctr24_ena_ctrl <= acp_vctr_CS and FB_B(0) and (not nFB_WR);
ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); acp_vctr16_ena_ctrl <= acp_vctr_CS and FB_B(1) and (not nFB_WR);
ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); acp_vctr8_ena_ctrl <= acp_vctr_CS and FB_B(2) and (not nFB_WR);
ACP_VCTR0_ena_ctrl <= ACP_VCTR_CS and FB_B(3) and (not nFB_WR); acp_vctr0_ena_ctrl <= acp_vctr_CS and FB_B(3) and (not nFB_WR);
ACP_VIDEO_ON <= ACP_VCTR_q(0); ACP_VIDEO_ON <= acp_vctr_q(0);
nPD_VGA <= ACP_VCTR_q(1); nPD_VGA <= acp_vctr_q(1);
-- ATARI MODUS -- ATARI MODUS
-- WENN 1 AUTOMATISCHE AUFLÖSUNG -- WENN 1 AUTOMATISCHE AUFLÖSUNG
ATARI_SYNC <= ACP_VCTR_q(26); ATARI_SYNC <= acp_vctr_q(26);
-- HORIZONTAL TIMING 640x480 -- HORIZONTAL TIMING 640x480
@@ -1076,10 +1059,10 @@ begin
VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1); VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1);
VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VR_WR_q); VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VR_WR_q);
VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY);
VR_DOUT0_ena_ctrl <= not VR_BUSY; vr_dout0_ena_ctrl <= not VR_BUSY;
VR_DOUT_d <= VR_D; vr_dout_d <= VR_D;
VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100"); vr_frq0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100");
VR_FRQ_d <= FB_AD(23 downto 16); vr_frq_d <= FB_AD(23 downto 16);
-- VIDEO PLL RECONFIG -- VIDEO PLL RECONFIG
-- $(F)000'0800 -- $(F)000'0800
@@ -1087,23 +1070,23 @@ begin
VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q); VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q);
-- ---------------------------------------------------------------------------------------------------------------------- -- ----------------------------------------------------------------------------------------------------------------------
VIDEO_RAM_CTR <= ACP_VCTR_q(31 downto 16); VIDEO_RAM_CTR <= acp_vctr_q(31 downto 16);
-- ------------ COLOR MODE IM ACP SETZEN -- ------------ COLOR MODE IM ACP SETZEN
COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; COLOR1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON;
COLOR8_2 <= ACP_VCTR_q(4) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; COLOR8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON;
COLOR16_2 <= ACP_VCTR_q(3) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; COLOR16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and ACP_VIDEO_ON;
COLOR24 <= ACP_VCTR_q(2) and ACP_VIDEO_ON; COLOR24 <= acp_vctr_q(2) and ACP_VIDEO_ON;
ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1); ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1);
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON);
ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON);
ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and FB_AD(0));
FALCON_VIDEO <= ACP_VCTR_q(7); FALCON_VIDEO <= acp_vctr_q(7);
FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16);
ST_VIDEO <= ACP_VCTR_q(6); ST_VIDEO <= acp_vctr_q(6);
ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not COLOR1); ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not COLOR1);
pixel_clk_i <= pixel_clk; pixel_clk_i <= pixel_clk;
@@ -1117,11 +1100,11 @@ begin
-- RANDFARBE -- RANDFARBE
-- $404/4 -- $404/4
BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001"); border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001");
BORDER_COLOR_d <= FB_AD(23 downto 0); border_color_d <= FB_AD(23 downto 0);
BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); border_color16_ena_ctrl <= border_color_CS and FB_B(1) and (not nFB_WR);
BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); border_color8_ena_ctrl <= border_color_CS and FB_B(2) and (not nFB_WR);
BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); border_color0_ena_ctrl <= border_color_CS and FB_B(3) and (not nFB_WR);
-- System Config Register -- System Config Register
-- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi
@@ -1146,27 +1129,28 @@ begin
-- 10 VGA -- 10 VGA
-- 11 TV -- 11 TV
-- $8006/2 -- $8006/2
sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp(FB_ADR, 20x"f8006", 1); sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(FB_ADR, 20x"f8006") = '1';
-- FB_ADR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; -- FB_ADR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0';
-- SYS_CTR_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011"); -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011");
SYS_CTR_d <= FB_AD(22 downto 16); sys_ctr_d <= FB_AD(22 downto 16);
SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and FB_B(3);
BLITTER_ON <= not SYS_CTR_q(3); BLITTER_ON <= not sys_ctr_q(3);
-- LOF -- lof
-- $820E/2 -- $820E/2
LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111"); lof_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111");
LOF_d <= FB_AD(31 downto 16); lof_d <= FB_AD(31 downto 16);
LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); lof8_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(2);
LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); lof0_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(3);
lof <= lof_q;
-- LWD
-- lwd
-- $8210/2 -- $8210/2
LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000"); lwd_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000");
LWD_d <= FB_AD(31 downto 16); lwd_d <= FB_AD(31 downto 16);
LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(0);
LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(1);
-- HORIZONTAL -- HORIZONTAL
-- HHT -- HHT
@@ -1249,7 +1233,8 @@ begin
-- VFT -- VFT
-- $82A2/2 -- $82A2/2
VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001"); -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001");
vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2");
VFT_d <= FB_AD(26 downto 16); VFT_d <= FB_AD(26 downto 16);
VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2);
VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3);
@@ -1269,10 +1254,10 @@ begin
-- - REGISTER OUT -- - REGISTER OUT
-- low word register access -- low word register access
-- u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or -- u0_data <= (sizeIt(st_shift_mode_CS,16) and std_logic_vector'("000000" & st_shift_mode_q & "00000000")) or
-- (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or -- (sizeIt(falcon_shift_mode_CS,16) and std_logic_vector'("00000" & falcon_shift_mode_q)) or
-- (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or -- (sizeIt(sys_ctr_CS,16) and std_logic_vector'("100000000" & sys_ctr_q(6 downto 4) & (not BLITTER_RUN) & sys_ctr_q(2 downto 0))) or
-- (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or -- (sizeIt(lof_CS,16) and lof_q) or (sizeIt(lwd_CS,16) and lwd_q) or
-- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or -- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or
-- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or -- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or
-- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or -- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or
@@ -1287,13 +1272,13 @@ begin
-- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or -- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or
-- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or -- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or
-- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or -- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or
-- (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or -- (sizeIt(acp_vctr_CS,16) and acp_vctr_q(31 downto 16)) or
-- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or
-- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or
-- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or
-- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or
-- (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or -- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or
-- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or -- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or
-- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010"));
FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else
@@ -1320,22 +1305,22 @@ begin
atari_vl_q(31 downto 16) when atari_vl_cs = '1' else atari_vl_q(31 downto 16) when atari_vl_cs = '1' else
"00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else
"0000000" & vr_dout_q when video_pll_config_cs = '1' else "0000000" & vr_dout_q when video_pll_config_cs = '1' else
vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs else vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else
(others => 'Z'); (others => 'Z');
-- u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or
-- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or -- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or
-- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); -- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE);
-- FB_AD(31 downto 16) <= u0_tridata; -- FB_AD(31 downto 16) <= u0_tridata;
-- high word register access -- high word register access
-- u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or -- u1_data <= (sizeIt(acp_vctr_CS,16) and acp_vctr_q(15 downto 0)) or
-- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or
-- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or
-- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or
-- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or
-- (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); -- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0));
-- u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); -- u1_enabledt <= (acp_vctr_CS or border_color_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE);
-- FB_AD(15 downto 0) <= u1_tridata; -- FB_AD(15 downto 0) <= u1_tridata;
fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else
@@ -1346,7 +1331,7 @@ begin
border_color_q(15 downto 0) when border_color_cs = '1' else border_color_q(15 downto 0) when border_color_cs = '1' else
(others => 'Z'); (others => 'Z');
video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or
HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or
VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS;
@@ -1362,12 +1347,12 @@ begin
(CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or (CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or
(CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or (CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or
(CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or
(to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "00")) or (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "00")) or
(to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "01")) or (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "01")) or
(CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9)); (CLK_VIDEO and ACP_VIDEO_ON and acp_vctr_q(9));
-- ------------------------------------------------------------ -- ------------------------------------------------------------
-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
-- -------------------------------------------------------------- -- --------------------------------------------------------------
-- 320 pixels, 32 MHz, RGB -- 320 pixels, 32 MHz, RGB
@@ -1389,9 +1374,9 @@ begin
-- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or
-- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or
-- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or
-- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "00"), 8)) or -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or
-- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "01"), 8)) or -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or
-- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(ACP_VCTR_q(9), 8)); -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(acp_vctr_q(9), 8));
-- MULTIPLIKATIONS FAKTOR -- MULTIPLIKATIONS FAKTOR
MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or
@@ -1414,7 +1399,7 @@ begin
VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and
(unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2)))));
-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q; DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q;
-- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON -- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON
@@ -1493,7 +1478,7 @@ begin
VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and
sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11));
-- ZÄHLER -- ZÄHLER
LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2)));
VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12);
@@ -1505,7 +1490,7 @@ begin
-- 1 ZEILE DAVOR ON OFF -- 1 ZEILE DAVOR ON OFF
DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1))));
-- AM ZEILENENDE ÜBERNEHMEN -- AM ZEILENENDE ÃœBERNEHMEN
DPO_ZL_ena <= LAST_q; DPO_ZL_ena <= LAST_q;
-- BESSER EINZELN WEGEN TIMING -- BESSER EINZELN WEGEN TIMING
@@ -1521,7 +1506,7 @@ begin
VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END);
-- AM ZEILENENDE ÜBERNEHMEN -- AM ZEILENENDE ÃœBERNEHMEN
VCO_ZL_ena <= LAST_q; VCO_ZL_ena <= LAST_q;
-- 1 ZEILE DAVOR ON OFF -- 1 ZEILE DAVOR ON OFF
@@ -1529,7 +1514,7 @@ begin
VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q);
-- VERZÖGERUNG UND SYNC -- VERZÖGERUNG UND SYNC
HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3)));
@@ -1547,7 +1532,7 @@ begin
VSYNC_I0_ena_ctrl <= LAST_q; VSYNC_I0_ena_ctrl <= LAST_q;
-- 3 zeilen vsync length -- 3 zeilen vsync length
-- runterzählen bis 0 -- runterzählen bis 0
VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else
std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= 3x"0" else std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= 3x"0" else
(others => '0'); (others => '0');
@@ -1567,14 +1552,14 @@ begin
VERZ0_d(0) <= DISP_ON_q; VERZ0_d(0) <= DISP_ON_q;
-- VERZ[1][0] = HSYNC_I[] != 0; -- VERZ[1][0] = HSYNC_I[] != 0;
-- NUR MÖGLICH WENN BEIDE -- NUR MÖGLICH WENN BEIDE
VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') VERZ1_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1')
and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and and HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and
VCO_q(6))='1' and HSYNC_I_q = "00000000")); VCO_q(6))='1' and HSYNC_I_q = "00000000"));
-- NUR MÖGLICH WENN BEIDE -- NUR MÖGLICH WENN BEIDE
VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') VERZ2_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1')
and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and and VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and
VCO_q(5))='1' and VSYNC_I_q = "000")); VCO_q(5))='1' and VSYNC_I_q = "000"));
-- nBLANK = VERZ[0][8]; -- nBLANK = VERZ[0][8];
@@ -1583,20 +1568,20 @@ begin
-- nBLANK_d <= DISP_ON_q; -- nBLANK_d <= DISP_ON_q;
-- HSYNC = VERZ[1][9]; -- HSYNC = VERZ[1][9];
-- NUR MÖGLICH WENN BEIDE -- NUR MÖGLICH WENN BEIDE
HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') and
HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and
VCO_q(6))='1' and HSYNC_I_q = "00000000")); VCO_q(6))='1' and HSYNC_I_q = "00000000"));
-- VSYNC = VERZ[2][9]; -- VSYNC = VERZ[2][9];
-- NUR MÖGLICH WENN BEIDE -- NUR MÖGLICH WENN BEIDE
VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') and
VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and
VCO_q(5))='1' and VSYNC_I_q = "000")); VCO_q(5))='1' and VSYNC_I_q = "000"));
nSYNC <= gnd; nSYNC <= gnd;
-- RANDFARBE MACHEN ------------------------------------ -- RANDFARBE MACHEN ------------------------------------
RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25);
RAND_d(1) <= RAND_q(0); RAND_d(1) <= RAND_q(0);
RAND_d(2) <= RAND_q(1); RAND_d(2) <= RAND_q(1);
RAND_d(3) <= RAND_q(2); RAND_d(3) <= RAND_q(2);
@@ -1606,25 +1591,25 @@ begin
-- RAND_ON = RAND[6]; -- RAND_ON = RAND[6];
rand_on <= rand(6); rand_on <= rand(6);
-- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25);
-- -------------------------------------------------------- -- --------------------------------------------------------
CLR_FIFO_ena <= LAST_q; CLR_FIFO_ena <= LAST_q;
-- IN LETZTER ZEILE LÖSCHEN -- IN LETZTER ZEILE LÖSCHEN
CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2)));
START_ZEILE_ena <= LAST_q; START_ZEILE_ena <= LAST_q;
-- ZEILE 1 -- ZEILE 1
START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000");
-- SUB PIXEL ZÄHLER SYNCHRONISIEREN -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q;
-- SUB PIXEL ZÄHLER SYNCHRONISIEREN -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q;
-- SUB PIXEL ZÄHLER SYNCHRONISIEREN -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q;
SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q;
@@ -1632,7 +1617,7 @@ begin
-- count up if display on sonst clear bei sync pix -- count up if display on sonst clear bei sync pix
SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7);
-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or
(to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or
(to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or
@@ -1641,9 +1626,9 @@ begin
(to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and
VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q;
CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 downto 0); clut_mux_av0_d <= SUB_PIXEL_CNT_q(3 downto 0);
CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; clut_mux_av1_d <= clut_mux_av0_q;
CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; clut_mux_adr_d <= clut_mux_av1_q;
-- Assignments added to explicitly combine the -- Assignments added to explicitly combine the

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