From f03a1eb525455b2398b4cf9ccc0d5e305a85c837 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 2 Jun 2016 15:57:06 +0000 Subject: [PATCH] more fixes --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 302 ++-- .../Video/video_mod_mux_clutctr.vhd | 475 +++--- FPGA_Quartus_13.1/firebee1.qsf | 1491 +++++++++-------- 3 files changed, 1127 insertions(+), 1141 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 742660f..c657dd1 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -22,15 +22,15 @@ library ieee; entity ddr_ctr is port ( - FB_ADR : in std_logic_vector(31 downto 0); + fb_adr : in std_logic_vector(31 downto 0); nFB_CS1 : in std_logic; nFB_CS2 : in std_logic; nFB_CS3 : in std_logic; nFB_OE : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; + fb_size0 : in std_logic; + fb_size1 : in std_logic; nRSTO : in std_logic; - MAIN_CLK : in std_logic; + main_clk : in std_logic; FB_ALE : in std_logic; nFB_WR : in std_logic; DDR_SYNC_66M : in std_logic; @@ -46,16 +46,16 @@ entity ddr_ctr is nVWE : buffer std_logic; nVRAS : buffer std_logic; nVCS : buffer std_logic; - VCKE : buffer std_logic; + vcke : buffer std_logic; nVCAS : buffer std_logic; - FB_LE : buffer std_logic_vector(3 downto 0); - FB_VDOE : buffer std_logic_vector(3 downto 0); + fb_le : buffer std_logic_vector(3 downto 0); + fb_vdoe : buffer std_logic_vector(3 downto 0); SR_FIFO_WRE : buffer std_logic; SR_DDR_FB : buffer std_logic; SR_DDR_WR : buffer std_logic; SR_DDRWR_D_SEL : buffer std_logic; SR_VDMP : buffer std_logic_vector(7 downto 0); - VIDEO_DDR_TA : buffer std_logic; + video_ddr_ta : buffer std_logic; SR_BLITTER_DACK : buffer std_logic; BA : buffer std_logic_vector(1 downto 0); DDRWR_D_SEL1 : buffer std_logic; @@ -73,13 +73,13 @@ architecture rtl of ddr_ctr is -- READ FIFO -- CLOSE FIFO BANK -- REFRESH 10X7.5NfS=75NS - signal FB_REGDDR_3 : std_logic_vector(2 downto 0); - signal FB_REGDDR_d : std_logic_vector(2 downto 0); - signal FB_REGDDR_q : std_logic_vector(2 downto 0); + signal fb_regddr_3 : std_logic_vector(2 downto 0); + signal fb_regddr_d : std_logic_vector(2 downto 0); + signal fb_regddr_q : std_logic_vector(2 downto 0); signal DDR_SM_6 : std_logic_vector(5 downto 0); signal DDR_SM_d : std_logic_vector(5 downto 0); signal DDR_SM_q : std_logic_vector(5 downto 0); - signal FB_B : std_logic_vector(3 downto 0); + signal fb_b : std_logic_vector(3 downto 0); signal VA_P : std_logic_vector(12 downto 0); signal VA_P_d : std_logic_vector(12 downto 0); signal VA_P_q : std_logic_vector(12 downto 0); @@ -97,7 +97,7 @@ architecture rtl of ddr_ctr is signal MCS_q : std_logic_vector(1 downto 0); signal SR_VDMP_d : std_logic_vector(7 downto 0); signal SR_VDMP_q : std_logic_vector(7 downto 0); - signal CPU_ROW_ADR : std_logic_vector(12 downto 0); + signal cpu_row_adr : std_logic_vector(12 downto 0); signal CPU_BA : std_logic_vector(1 downto 0); signal CPU_COL_ADR : std_logic_vector(9 downto 0); signal BLITTER_ROW_ADR : std_logic_vector(12 downto 0); @@ -131,7 +131,7 @@ architecture rtl of ddr_ctr is signal VIDEO_ACT_ADR : std_logic_vector(26 downto 0); signal u0_data : std_logic_vector(7 downto 0); signal u0_tridata : std_logic_vector(7 downto 0); - signal FB_REGDDR_0_clk_ctrl : std_logic; + signal fb_regddr_0_clk_ctrl : std_logic; signal SR_VDMP0_clk_ctrl : std_logic; signal MCS0_clk_ctrl : std_logic; signal VA_S0_clk_ctrl : std_logic; @@ -182,8 +182,8 @@ architecture rtl of ddr_ctr is signal BA1_1 : std_logic; signal BA0_2 : std_logic; signal BA0_1 : std_logic; - signal BUS_CYC_d_2 : std_logic; - signal BUS_CYC_d_1 : std_logic; + signal bus_cyc_d_2 : std_logic; + signal bus_cyc_d_1 : std_logic; signal FIFO_BANK_OK_d_2 : std_logic; signal FIFO_BANK_OK_d_1 : std_logic; signal u0_enabledt : std_logic; @@ -201,7 +201,7 @@ architecture rtl of ddr_ctr is signal DDR_REFRESH_REQ_clk : std_logic; signal DDR_REFRESH_REQ_d : std_logic; signal DDR_REFRESH_REQ : std_logic; - signal DDR_REFRESH_ON : std_logic; + signal ddr_refresh_on : std_logic; signal FIFO_BANK_NOT_OK : std_logic; signal FIFO_BANK_OK_q : std_logic; signal FIFO_BANK_OK_clk : std_logic; @@ -239,11 +239,11 @@ architecture rtl of ddr_ctr is signal BLITTER_REQ_clk : std_logic; signal BLITTER_REQ_d : std_logic; signal BLITTER_REQ : std_logic; - signal BUS_CYC_END : std_logic; - signal BUS_CYC_q : std_logic; - signal BUS_CYC_clk : std_logic; - signal BUS_CYC_d : std_logic; - signal BUS_CYC : std_logic; + signal bus_cyc_end : std_logic; + signal bus_cyc_q : std_logic; + signal bus_cyc_clk : std_logic; + signal bus_cyc_d : std_logic; + signal bus_cyc : std_logic; signal CPU_AC_q : std_logic; signal CPU_AC_clk : std_logic; signal CPU_AC_d : std_logic; @@ -259,13 +259,13 @@ architecture rtl of ddr_ctr is signal SR_DDR_WR_q : std_logic; signal SR_DDR_WR_clk : std_logic; signal SR_DDR_WR_d : std_logic; - signal DDR_CONFIG : std_logic; - signal DDR_CS_q : std_logic; - signal DDR_CS_ena : std_logic; - signal DDR_CS_clk : std_logic; - signal DDR_CS_d : std_logic; - signal DDR_CS : std_logic; - signal DDR_SEL : std_logic; + signal ddr_config : std_logic; + signal ddr_cs_q : std_logic; + signal ddr_cs_ena : std_logic; + signal ddr_cs_clk : std_logic; + signal ddr_cs_d : std_logic; + signal ddr_cs : std_logic; + signal ddr_sel : std_logic; signal CPU_DDR_SYNC_q : std_logic; signal CPU_DDR_SYNC_clk : std_logic; signal CPU_DDR_SYNC_d : std_logic; @@ -354,10 +354,10 @@ begin end if; end process; - process (FB_REGDDR_0_clk_ctrl) + process (fb_regddr_0_clk_ctrl) begin if rising_edge(fb_regddr_0_clk_ctrl) then - FB_REGDDR_q <= FB_REGDDR_d; + fb_regddr_q <= fb_regddr_d; end if; end process; @@ -410,11 +410,11 @@ begin end if; end process; - process (DDR_CS_clk) + process (ddr_cs_clk) begin - if DDR_CS_clk'event and DDR_CS_clk='1' then - if DDR_CS_ena='1' then - DDR_CS_q <= DDR_CS_d; + if ddr_cs_clk'event and ddr_cs_clk='1' then + if ddr_cs_ena='1' then + ddr_cs_q <= ddr_cs_d; end if; end if; end process; @@ -433,10 +433,10 @@ begin end if; end process; - process (BUS_CYC_clk) + process (bus_cyc_clk) begin - if BUS_CYC_clk'event and BUS_CYC_clk='1' then - BUS_CYC_q <= BUS_CYC_d; + if bus_cyc_clk'event and bus_cyc_clk='1' then + bus_cyc_q <= bus_cyc_d; end if; end process; @@ -617,98 +617,98 @@ begin -- BYT SELECT -- ADR==0 -- LONG UND LINE - FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(0) <= to_std_logic(fb_adr(1 downto 0) = "00") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(1) <= to_std_logic(fb_adr(1 downto 0) = "01") or (fb_size1 and (not fb_size0) and (not fb_adr(1))) or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(2) <= to_std_logic(fb_adr(1 downto 0) = "10") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(3) <= to_std_logic(fb_adr(1 downto 0) = "11") or (fb_size1 and (not fb_size0) and fb_adr(1)) or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR_0_clk_ctrl <= MAIN_CLK; + fb_regddr_0_clk_ctrl <= main_clk; - process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR) + process (fb_regddr_q, ddr_sel, bus_cyc_q, LINE, ddr_cs_q, nFB_OE, main_clk, ddr_config, nFB_WR) variable stdVec3: std_logic_vector(2 downto 0); begin - FB_REGDDR_d <= FB_REGDDR_q; + fb_regddr_d <= fb_regddr_q; fb_vdoe <= (others => '0'); fb_le <= (others => '0'); video_ddr_ta <= '0'; bus_cyc_end <= '0'; - stdVec3 := FB_REGDDR_q; + stdVec3 := fb_regddr_q; case stdVec3 is when "000" => - FB_LE(0) <= not nFB_WR; + fb_le(0) <= not nFB_WR; -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' then - FB_REGDDR_d <= "001"; + if (bus_cyc_q or (ddr_sel and LINE and (not nFB_WR))) = '1' then + fb_regddr_d <= "001"; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "001" => - if DDR_CS_q = '1' then - FB_LE(0) <= not nFB_WR; - VIDEO_DDR_TA <= '1'; + if ddr_cs_q = '1' then + fb_le(0) <= not nFB_WR; + video_ddr_ta <= '1'; if LINE ='1' then - FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); - FB_REGDDR_d <= "010"; + fb_vdoe(0) <= (not nFB_OE) and (not ddr_config); + fb_regddr_d <= "010"; else - BUS_CYC_END <= '1'; - FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); - FB_REGDDR_d <= "000"; + bus_cyc_end <= '1'; + fb_vdoe(0) <= (not nFB_OE) and (not main_clk) and (not ddr_config); + fb_regddr_d <= "000"; end if; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "010" => - if DDR_CS_q = '1' then - FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(1) <= not nFB_WR; - VIDEO_DDR_TA <= '1'; - FB_REGDDR_d <= "011"; + if ddr_cs_q = '1' then + fb_vdoe(1) <= (not nFB_OE) and (not ddr_config); + fb_le(1) <= not nFB_WR; + video_ddr_ta <= '1'; + fb_regddr_d <= "011"; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "011" => - if DDR_CS_q ='1' then - FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(2) <= not nFB_WR; + if ddr_cs_q ='1' then + fb_vdoe(2) <= (not nFB_OE) and (not ddr_config); + fb_le(2) <= not nFB_WR; -- BEI LINE WRITE EVT. WARTEN - if ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' then - FB_REGDDR_d <= "011"; + if ((not bus_cyc_q) and LINE and (not nFB_WR)) = '1' then + fb_regddr_d <= "011"; else - VIDEO_DDR_TA <= '1'; - FB_REGDDR_d <= "100"; + video_ddr_ta <= '1'; + fb_regddr_d <= "100"; end if; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "100" => - if DDR_CS_q = '1' then - FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); - FB_LE(3) <= not nFB_WR; - VIDEO_DDR_TA <= '1'; - BUS_CYC_END <= '1'; - FB_REGDDR_d <= "000"; + if ddr_cs_q = '1' then + fb_vdoe(3) <= (not nFB_OE) and (not main_clk) and (not ddr_config); + fb_le(3) <= not nFB_WR; + video_ddr_ta <= '1'; + bus_cyc_end <= '1'; + fb_regddr_d <= "000"; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when others => @@ -718,17 +718,17 @@ begin end process; -- DDR STEUERUNG ----------------------------------------------------- - -- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; - VCKE <= VIDEO_RAM_CTR(0); + -- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: vcke; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + vcke <= VIDEO_RAM_CTR(0); nVCS <= not VIDEO_RAM_CTR(1); - DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); - DDR_CONFIG <= VIDEO_RAM_CTR(3); + ddr_refresh_on <= VIDEO_RAM_CTR(2); + ddr_config <= VIDEO_RAM_CTR(3); FIFO_ACTIVE <= VIDEO_RAM_CTR(8); -- ------------------------------ - CPU_ROW_ADR <= FB_ADR(26 downto 14); - CPU_BA <= FB_ADR(13 downto 12); - CPU_COL_ADR <= FB_ADR(11 downto 2); + cpu_row_adr <= fb_adr(26 downto 14); + CPU_BA <= fb_adr(13 downto 12); + CPU_COL_ADR <= fb_adr(11 downto 2); nVRAS <= not VRAS; nVCAS <= not VCAS; nVWE <= not VWE; @@ -744,33 +744,33 @@ begin DDRWR_D_SEL1 <= BLITTER_AC_q; -- SELECT LOGIC - DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); - DDR_CS_clk <= MAIN_CLK; - DDR_CS_ena <= FB_ALE; - DDR_CS_d <= DDR_SEL; + ddr_sel <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); + ddr_cs_clk <= main_clk; + ddr_cs_ena <= FB_ALE; + ddr_cs_d <= ddr_sel; - -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG -- CONFIG SOFORT LOS - -- LINE WRITE SPÄTER - CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or - (DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and (not nFB_WR)); + -- LINE WRITE SPÄTER + CPU_SIG <= (ddr_sel and (nFB_WR or (not LINE)) and (not ddr_config)) or + (ddr_sel and ddr_config) or (to_std_logic(fb_regddr_q = "010") and (not nFB_WR)); CPU_REQ_clk <= DDR_SYNC_66M; -- HALTEN BUS CYC BEGONNEN ODER FERTIG - CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" - and FB_REGDDR_q /= "100") and (not BUS_CYC_END) and (not BUS_CYC_q)); - BUS_CYC_clk <= DDRCLK0; - BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); + CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and fb_regddr_q /= "010" + and fb_regddr_q /= "100") and (not bus_cyc_end) and (not bus_cyc_q)); + bus_cyc_clk <= DDRCLK0; + bus_cyc_d_1 <= bus_cyc_q and (not bus_cyc_end); -- STATE MACHINE SYNCHRONISIEREN ----------------- MCS0_clk_ctrl <= DDRCLK0; - MCS_d(0) <= MAIN_CLK; + MCS_d(0) <= main_clk; MCS_d(1) <= MCS_q(0); CPU_DDR_SYNC_clk <= DDRCLK0; -- NUR 1 WENN EIN - CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); + CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and vcke and (not nVCS); -- ------------------------------------------------- VA_S0_clk_ctrl <= DDRCLK0; @@ -785,12 +785,12 @@ begin DDR_SM_0_clk_ctrl <= DDRCLK0; - process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, - CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, + process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, ddr_config, + cpu_row_adr, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, - FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, - VIDEO_ADR_CNT_q, FIFO_COL_ADR, DDR_SEL, LINE, FIFO_BA, VA_P_q, - BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, + fb_b, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, + VIDEO_ADR_CNT_q, FIFO_COL_ADR, ddr_sel, LINE, FIFO_BA, VA_P_q, + BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, fb_size0, fb_size1, DDR_REFRESH_SIG_q) variable stdVec6: std_logic_vector(5 downto 0); begin @@ -806,7 +806,7 @@ begin (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, - BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2, + BA1_2, BA0_2, SR_FIFO_WRE_d, bus_cyc_d_2, VWE, VA10_2, FIFO_BANK_NOT_OK, VCAS, VRAS) <= std_logic_vector'("00000000000000000000000000000"); stdVec6 := DDR_SM_q; @@ -818,14 +818,14 @@ begin -- SYNCHRON UND EIN? elsif (CPU_DDR_SYNC_q)='1' then -- JA - if (DDR_CONFIG)='1' then + if (ddr_config)='1' then DDR_SM_d <= "001000"; -- BEI WAIT UND LINE WRITE elsif (CPU_REQ_q)='1' then - VA_S_d <= CPU_ROW_ADR; + VA_S_d <= cpu_row_adr; BA_S_d <= CPU_BA; CPU_AC_d <= '1'; - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; DDR_SM_d <= "000010"; else -- FIFO IST DEFAULT @@ -849,7 +849,7 @@ begin when "000001" => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - if (DDR_SEL and (nFB_WR or (not LINE)))='1' then + if (ddr_sel and (nFB_WR or (not LINE)))='1' then VRAS <= '1'; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (BA1_2, BA0_2) <= FB_AD(13 downto 12); @@ -857,7 +857,7 @@ begin VA_S_d(10) <= '1'; CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; else VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; @@ -875,7 +875,7 @@ begin CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; DDR_SM_d <= "000011"; when "000011" => @@ -912,7 +912,7 @@ begin BLITTER_AC_d <= BLITTER_AC_q; VCAS <= '1'; - -- READ DATEN FÜR CPU + -- READ DATEN FÃœR CPU SR_DDR_FB <= CPU_AC_q; -- BLITTER DACK AND BLITTER LATCH DATEN @@ -959,7 +959,7 @@ begin BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); -- BYTE ENABLE WRITE - SR_VDMP_d(7 downto 4) <= FB_B; + SR_VDMP_d(7 downto 4) <= fb_b; -- LINE ENABLE WRITE SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; @@ -974,7 +974,7 @@ begin -- WRITE COMMAND CPU UND BLITTER if WRITER SR_DDR_WR_d <= '1'; - -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL_d <= '1'; -- WENN LINE DANN ACTIV @@ -988,7 +988,7 @@ begin -- WRITE COMMAND CPU UND BLITTER if WRITE SR_DDR_WR_d <= '1'; - -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL_d <= '1'; DDR_SM_d <= "010100"; @@ -1131,14 +1131,14 @@ begin end if; when "011100" => - if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then + if (ddr_sel and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then VRAS <= '1'; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (BA1_2, BA0_2) <= FB_AD(13 downto 12); CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; -- AUTO PRECHARGE DA NICHT FIFO BANK VA_S_d(10) <= '1'; @@ -1159,7 +1159,7 @@ begin DDR_SM_d <= "001001"; when "001001" => - BUS_CYC_d_2 <= CPU_REQ_q; + bus_cyc_d_2 <= CPU_REQ_q; DDR_SM_d <= "001010"; when "001010" => @@ -1180,13 +1180,13 @@ begin when "001101" => -- NUR BEI LONG WRITE - VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + VRAS <= FB_AD(18) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- NUR BEI LONG WRITE - VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + VCAS <= FB_AD(17) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- NUR BEI LONG WRITE - VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + VWE <= FB_AD(16) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- CLOSE FIFO BANK DDR_SM_d <= "000111"; @@ -1196,7 +1196,7 @@ begin -- AUF NOT OK FIFO_BANK_NOT_OK <= '1'; - -- BÄNKE SCHLIESSEN + -- BÄNKE SCHLIESSEN VRAS <= '1'; VWE <= '1'; DDR_SM_d <= "000110"; @@ -1205,7 +1205,7 @@ begin -- AUF NOT OK FIFO_BANK_NOT_OK <= '1'; - -- BÄNKE SCHLIESSEN + -- BÄNKE SCHLIESSEN VRAS <= '1'; VWE <= '1'; @@ -1263,7 +1263,7 @@ begin -- BLITTER ---------------------- -- --------------------------------------- BLITTER_REQ_clk <= DDRCLK0; - BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); + BLITTER_REQ_d <= BLITTER_SIG and (not ddr_config) and vcke and (not nVCS); BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); BLITTER_BA(1) <= BLITTER_ADR(13); BLITTER_BA(0) <= BLITTER_ADR(12); @@ -1276,7 +1276,7 @@ begin FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not - STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); + STOP_q) and (not ddr_config) and vcke and (not nVCS); FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); @@ -1286,7 +1286,7 @@ begin FIFO_BANK_OK_clk <= DDRCLK0; FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); - -- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- + -- ZÄHLER RÃœCKSETZEN WENN CLR FIFO ---------------- CLR_FIFO_SYNC_clk <= DDRCLK0; -- SYNCHRONISIEREN @@ -1296,7 +1296,7 @@ begin STOP_clk <= DDRCLK0; STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; - -- ZÄHLEN ----------------------------------------------- + -- ZÄHLEN ----------------------------------------------- VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or @@ -1320,60 +1320,60 @@ begin -- --------------------------------------------------------------------------------------- DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; - -- ZÄHLEN 0-2047 + -- ZÄHLEN 0-2047 DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + unsigned'("00000000001")); REFRESH_TIME_clk <= DDRCLK0; -- SYNC - REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not MAIN_CLK); + REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not main_clk); DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = "100011"); - -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + -- 9 STÃœCK (8 REFRESH UND 1 ALS VORLAUF) -- MINUS 1 WENN GEMACHT DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and - sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)) or (sizeIt(not + sizeIt(ddr_refresh_on,4) and sizeIt(not ddr_config,4)) or (sizeIt(not REFRESH_TIME_q,4) and (std_logic_vector'(unsigned(DDR_REFRESH_SIG_q) - - unsigned'("0001"))) and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not - DDR_CONFIG,4)); + unsigned'("0001"))) and sizeIt(ddr_refresh_on,4) and sizeIt(not + ddr_config,4)); DDR_REFRESH_REQ_clk <= DDRCLK0; - DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); + DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and ddr_refresh_on and (not REFRESH_TIME_q) and (not ddr_config); -- --------------------------------------------------------- -- VIDEO REGISTER ----------------------- -- ------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_L_D0_clk_ctrl <= main_clk; -- 820D/2 - VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000110"); + VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000110"); -- SORRY, NUR 16 BYT GRENZEN VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); - VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and fb_b(1); + VIDEO_BASE_M_D0_clk_ctrl <= main_clk; -- 8203/2 - VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000001"); + VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000001"); VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); - VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and fb_b(3); + VIDEO_BASE_H_D0_clk_ctrl <= main_clk; -- 8200-1/2 - VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000000"); + VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000000"); VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); - VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(1); + VIDEO_BASE_X_D0_clk_ctrl <= main_clk; VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); - VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); + VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(0); -- 8209/2 - VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000100"); + VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000100"); -- 8207/2 - VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000011"); + VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000011"); -- 8204,5/2 - VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000010"); + VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000010"); -- FB_AD[31..24] = lpm_bustri_BYT( -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) @@ -1397,7 +1397,7 @@ begin -- Assignments added to explicitly combine the -- effects of multiple drivers in the source FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; - BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; + bus_cyc_d <= bus_cyc_d_1 or bus_cyc_d_2; BA(0) <= BA0_1 or BA0_2; BA(1) <= BA1_1 or BA1_2; VA(0) <= VA0_1 or VA0_2; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 7afd582..ce2a412 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -35,18 +35,18 @@ -- VERZ2_.clk VERZ2_clk -- VERZ2_.d VERZ2_d -- VERZ2_ VERZ2 --- CLUT_MUX_AV0_.q CLUT_MUX_AV0_q --- CLUT_MUX_AV0_.prn CLUT_MUX_AV0_prn --- CLUT_MUX_AV0_.clrn CLUT_MUX_AV0_clrn --- CLUT_MUX_AV0_.clk CLUT_MUX_AV0_clk --- CLUT_MUX_AV0_.d CLUT_MUX_AV0_d --- CLUT_MUX_AV0_ CLUT_MUX_AV0 --- CLUT_MUX_AV1_.q CLUT_MUX_AV1_q --- CLUT_MUX_AV1_.prn CLUT_MUX_AV1_prn --- CLUT_MUX_AV1_.clrn CLUT_MUX_AV1_clrn --- CLUT_MUX_AV1_.clk CLUT_MUX_AV1_clk --- CLUT_MUX_AV1_.d CLUT_MUX_AV1_d --- CLUT_MUX_AV1_ CLUT_MUX_AV1 +-- clut_mux_av0_.q clut_mux_av0_q +-- clut_mux_av0_.prn clut_mux_av0_prn +-- clut_mux_av0_.clrn clut_mux_av0_clrn +-- clut_mux_av0_.clk clut_mux_av0_clk +-- clut_mux_av0_.d clut_mux_av0_d +-- clut_mux_av0_ clut_mux_av0 +-- clut_mux_av1_.q clut_mux_av1_q +-- clut_mux_av1_.prn clut_mux_av1_prn +-- clut_mux_av1_.clrn clut_mux_av1_clrn +-- clut_mux_av1_.clk clut_mux_av1_clk +-- clut_mux_av1_.d clut_mux_av1_d +-- clut_mux_av1_ clut_mux_av1 -- CREATED BY FREDI ASCHWANDEN @@ -56,6 +56,9 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; + +library work; + use work.firebee_utils_pkg.all; entity video_mod_mux_clutctr is port @@ -85,7 +88,7 @@ entity video_mod_mux_clutctr is FALCON_CLUT_WR : out std_logic_vector(3 downto 0); ST_CLUT_RD : out std_logic; ST_CLUT_WR : out std_logic_vector(1 downto 0); - CLUT_MUX_ADR : out std_logic_vector(3 downto 0); + clut_mux_adr : out std_logic_vector(3 downto 0); HSYNC : out std_logic; VSYNC : out std_logic; nBLANK : out std_logic; @@ -99,7 +102,7 @@ entity video_mod_mux_clutctr is BLITTER_ON : out std_logic; VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); VIDEO_MOD_TA : out std_logic; - BORDER_COLOR : out std_logic_vector(23 downto 0); + border_color : out std_logic_vector(23 downto 0); CCSEL : out std_logic_vector(2 downto 0); ACP_CLUT_WR : out std_logic_vector(3 downto 0); INTER_ZEI : out std_logic; @@ -116,7 +119,7 @@ end video_mod_mux_clutctr; architecture rtl of video_mod_mux_clutctr is -- DIV. CONTROL REGISTER -- BRAUCHT EIN WAITSTAT - -- LÄNGE HSYNC PULS IN PIXEL_CLK + -- LÄNGE HSYNC PULS IN PIXEL_CLK -- LETZTES PIXEL EINER ZEILE ERREICHT -- ATARI RESOLUTION -- HORIZONTAL TIMING 640x480 @@ -125,42 +128,42 @@ architecture rtl of video_mod_mux_clutctr is -- VERTIKAL TIMING 320x240 -- HORIZONTAL -- VERTIKAL - signal VR_DOUT : std_logic_vector(8 downto 0); - signal VR_DOUT_d : std_logic_vector(8 downto 0); - signal VR_DOUT_q : std_logic_vector(8 downto 0); - signal VR_FRQ : unsigned(7 downto 0); - signal VR_FRQ_d : std_logic_vector(7 downto 0); - signal VR_FRQ_q : std_logic_vector(7 downto 0); + signal vr_dout : std_logic_vector(8 downto 0); + signal vr_dout_d : std_logic_vector(8 downto 0); + signal vr_dout_q : std_logic_vector(8 downto 0); + signal vr_frq : unsigned(7 downto 0); + signal vr_frq_d : std_logic_vector(7 downto 0); + signal vr_frq_q : std_logic_vector(7 downto 0); signal FB_B : std_logic_vector(3 downto 0); signal FB_16B : std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE : std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); - signal FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); - signal FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); - signal FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); - signal CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); - signal CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1 : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0 : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); - signal ACP_VCTR : std_logic_vector(31 downto 0); - signal ACP_VCTR_d : std_logic_vector(31 downto 0); - signal ACP_VCTR_q : std_logic_vector(31 downto 0); - signal BORDER_COLOR_d : std_logic_vector(23 downto 0); - signal BORDER_COLOR_q : std_logic_vector(23 downto 0); - signal SYS_CTR : std_logic_vector(6 downto 0); - signal SYS_CTR_d : std_logic_vector(6 downto 0); - signal SYS_CTR_q : std_logic_vector(6 downto 0); - signal LOF : std_logic_vector(15 downto 0); - signal LOF_d : std_logic_vector(15 downto 0); - signal LOF_q : std_logic_vector(15 downto 0); - signal LWD : std_logic_vector(15 downto 0); - signal LWD_d : std_logic_vector(15 downto 0); - signal LWD_q : std_logic_vector(15 downto 0); + signal st_shift_mode : std_logic_vector(1 downto 0); + signal st_shift_mode_d : std_logic_vector(1 downto 0); + signal st_shift_mode_q : std_logic_vector(1 downto 0); + signal falcon_shift_mode : std_logic_vector(10 downto 0); + signal falcon_shift_mode_d : std_logic_vector(10 downto 0); + signal falcon_shift_mode_q : std_logic_vector(10 downto 0); + signal clut_mux_adr_d : std_logic_vector(3 downto 0); + signal clut_mux_adr_q : std_logic_vector(3 downto 0); + signal clut_mux_av1 : std_logic_vector(3 downto 0); + signal clut_mux_av1_d : std_logic_vector(3 downto 0); + signal clut_mux_av1_q : std_logic_vector(3 downto 0); + signal clut_mux_av0 : std_logic_vector(3 downto 0); + signal clut_mux_av0_d : std_logic_vector(3 downto 0); + signal clut_mux_av0_q : std_logic_vector(3 downto 0); + signal acp_vctr : std_logic_vector(31 downto 0); + signal acp_vctr_d : std_logic_vector(31 downto 0); + signal acp_vctr_q : std_logic_vector(31 downto 0); + signal border_color_d : std_logic_vector(23 downto 0); + signal border_color_q : std_logic_vector(23 downto 0); + signal sys_ctr : std_logic_vector(6 downto 0); + signal sys_ctr_d : std_logic_vector(6 downto 0); + signal sys_ctr_q : std_logic_vector(6 downto 0); + signal lof : std_logic_vector(15 downto 0); + signal lof_d : std_logic_vector(15 downto 0); + signal lof_q : std_logic_vector(15 downto 0); + signal lwd : std_logic_vector(15 downto 0); + signal lwd_d : std_logic_vector(15 downto 0); + signal lwd_q : std_logic_vector(15 downto 0); signal HSYNC_I : std_logic_vector(7 downto 0); signal HSYNC_I_d : std_logic_vector(7 downto 0); signal HSYNC_I_q : std_logic_vector(7 downto 0); @@ -266,17 +269,17 @@ architecture rtl of video_mod_mux_clutctr is signal u0_tridata : std_logic_vector(15 downto 0); signal u1_data : std_logic_vector(15 downto 0); signal u1_tridata : std_logic_vector(15 downto 0); - -- signal ST_SHIFT_MODE0_clk_ctrl : std_logic; - signal ST_SHIFT_MODE0_ena_ctrl : std_logic; - -- signal FALCON_SHIFT_MODE0_clk_ctrl : std_logic; - signal FALCON_SHIFT_MODE8_ena_ctrl : std_logic; - signal FALCON_SHIFT_MODE0_ena_ctrl : std_logic; + -- signal st_shift_mode0_clk_ctrl : std_logic; + signal st_shift_mode0_ena_ctrl : std_logic; + -- signal falcon_shift_mode0_clk_ctrl : std_logic; + signal falcon_shift_mode8_ena_ctrl : std_logic; + signal falcon_shift_mode0_ena_ctrl : std_logic; - signal ACP_VCTR24_ena_ctrl : std_logic; - signal ACP_VCTR16_ena_ctrl : std_logic; - signal ACP_VCTR8_ena_ctrl : std_logic; - signal ACP_VCTR6_ena_ctrl : std_logic; - signal ACP_VCTR0_ena_ctrl : std_logic; + signal acp_vctr24_ena_ctrl : std_logic; + signal acp_vctr16_ena_ctrl : std_logic; + signal acp_vctr8_ena_ctrl : std_logic; + signal acp_vctr6_ena_ctrl : std_logic; + signal acp_vctr0_ena_ctrl : std_logic; signal ATARI_HH24_ena_ctrl : std_logic; signal ATARI_HH16_ena_ctrl : std_logic; @@ -295,16 +298,16 @@ architecture rtl of video_mod_mux_clutctr is signal ATARI_VL16_ena_ctrl : std_logic; signal ATARI_VL8_ena_ctrl : std_logic; signal ATARI_VL0_ena_ctrl : std_logic; - signal VR_DOUT0_ena_ctrl : std_logic; - signal VR_FRQ0_ena_ctrl : std_logic; - signal BORDER_COLOR16_ena_ctrl : std_logic; - signal BORDER_COLOR8_ena_ctrl : std_logic; - signal BORDER_COLOR0_ena_ctrl : std_logic; - signal SYS_CTR0_ena_ctrl : std_logic; - signal LOF8_ena_ctrl : std_logic; - signal LOF0_ena_ctrl : std_logic; - signal LWD8_ena_ctrl : std_logic; - signal LWD0_ena_ctrl : std_logic; + signal vr_dout0_ena_ctrl : std_logic; + signal vr_frq0_ena_ctrl : std_logic; + signal border_color16_ena_ctrl : std_logic; + signal border_color8_ena_ctrl : std_logic; + signal border_color0_ena_ctrl : std_logic; + signal sys_ctr0_ena_ctrl : std_logic; + signal lof8_ena_ctrl : std_logic; + signal lof0_ena_ctrl : std_logic; + signal lwd8_ena_ctrl : std_logic; + signal lwd0_ena_ctrl : std_logic; signal HHT8_ena_ctrl : std_logic; signal HHT0_ena_ctrl : std_logic; signal HBE8_ena_ctrl : std_logic; @@ -441,14 +444,14 @@ architecture rtl of video_mod_mux_clutctr is signal CLUT_TA_q : std_logic; signal CLUT_TA_d : std_logic; signal CLUT_TA : std_logic; - signal LWD_CS : std_logic; - signal LOF_CS : std_logic; - signal SYS_CTR_CS : std_logic; + signal lwd_CS : std_logic; + signal lof_CS : std_logic; + signal sys_ctr_CS : std_logic; signal ACP_VIDEO_ON : std_logic; - signal BORDER_COLOR_CS : std_logic; - signal ACP_VCTR_CS : std_logic; - signal FALCON_SHIFT_MODE_CS : std_logic; - signal ST_SHIFT_MODE_CS : std_logic; + signal border_color_CS : std_logic; + signal acp_vctr_CS : std_logic; + signal falcon_shift_mode_CS : std_logic; + signal st_shift_mode_CS : std_logic; signal ST_CLUT : std_logic; signal ST_CLUT_CS : std_logic; signal FALCON_CLUT : std_logic; @@ -493,26 +496,6 @@ architecture rtl of video_mod_mux_clutctr is end loop; return rep; end function sizeit; - - -- f_addr_cmp() compares addr against addr_const (only counting from the highest significant bit of the smaller - -- number, ignoring ignore least significant bits) and returns true if both addresses match, false otherwise - function f_addr_cmp(signal addr : std_logic_vector; constant addr_const : std_logic_vector; constant ignore : integer) return boolean is - variable c_len : integer := addr_const'high; - variable a_len : integer := addr'high; - variable len : integer; - variable result : boolean := false; - begin - if c_len < a_len then - len := c_len; - else - len := a_len; - end if; - for i in len downto len - ignore loop - result := addr_const(i) = addr(i); - exit when result = false; - end loop; - return result; - end function f_addr_cmp; begin -- Sub Module Section @@ -534,11 +517,11 @@ begin -- Register Section - CLUT_MUX_ADR <= CLUT_MUX_ADR_q; + clut_mux_adr <= clut_mux_adr_q; -- missing signals that seem to got lost during conversion HSYNC <= HSYNC_q; - ACP_VCTR <= ACP_VCTR_q; + acp_vctr <= acp_vctr_q; RAND <= RAND_q; ATARI_HH <= ATARI_HH_q; ATARI_HL <= ATARI_HL_q; @@ -550,9 +533,9 @@ begin VSYNC <= VSYNC_q; nBLANK <= nBLANK_q; FIFO_RDE <= FIFO_RDE_q; - BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); - BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); - BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); + border_color(23 downto 16) <= border_color_q(23 downto 16); + border_color(15 downto 8) <= border_color_q(15 downto 8); + border_color(7 downto 0) <= border_color_q(7 downto 0); CCSEL <= CCSEL_q; INTER_ZEI <= INTER_ZEI_q; DOP_FIFO_CLR <= DOP_FIFO_CLR_q; @@ -561,18 +544,18 @@ begin process (pixel_clk_i) begin if rising_edge(pixel_clk_i) then - CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; + clut_mux_adr_q <= clut_mux_adr_d; HSYNC_q <= HSYNC_d; VSYNC_q <= VSYNC_d; nBLANK_q <= nBLANK_d; FIFO_RDE_q <= FIFO_RDE_d; - if BORDER_COLOR16_ena_ctrl = '1' then + if border_color16_ena_ctrl = '1' then border_color_q(23 downto 16) <= border_color_d(23 downto 16); end if; - if BORDER_COLOR8_ena_ctrl = '1' THEN + if border_color8_ena_ctrl = '1' THEN border_color_q(15 downto 8) <= border_color_d(15 downto 8); END IF; - IF BORDER_COLOR0_ena_ctrl = '1' THEN + IF border_color0_ena_ctrl = '1' THEN border_color_q(7 downto 0) <= border_color_d(7 downto 0); END IF; CCSEL_q <= CCSEL_d; @@ -602,7 +585,7 @@ begin END IF; END PROCESS; - VR_FRQ <= unsigned(VR_FRQ_q); + vr_frq <= unsigned(vr_frq_q); PROCESS (main_clk) BEGIN @@ -613,63 +596,63 @@ begin CLK17M_q <= CLK17M_d; - IF VR_DOUT0_ena_ctrl = '1' THEN - VR_DOUT_q <= VR_DOUT_d; + IF vr_dout0_ena_ctrl = '1' THEN + vr_dout_q <= vr_dout_d; END IF; - IF VR_FRQ0_ena_ctrl = '1' THEN - VR_FRQ_q <= VR_FRQ_d; + IF vr_frq0_ena_ctrl = '1' THEN + vr_frq_q <= vr_frq_d; END IF; - IF ST_SHIFT_MODE0_ena_ctrl = '1' THEN - ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; + IF st_shift_mode0_ena_ctrl = '1' THEN + st_shift_mode_q <= st_shift_mode_d; END IF; - IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN + IF falcon_shift_mode8_ena_ctrl = '1' THEN falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); END IF; - IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN + IF falcon_shift_mode0_ena_ctrl = '1' THEN falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); END IF; - IF ACP_VCTR24_ena_ctrl = '1' THEN - ACP_VCTR_q(31 downto 24) <= ACP_VCTR_d(31 downto 24); + IF acp_vctr24_ena_ctrl = '1' THEN + acp_vctr_q(31 downto 24) <= acp_vctr_d(31 downto 24); END IF; - IF ACP_VCTR16_ena_ctrl = '1' THEN - ACP_VCTR_q(23 downto 16) <= ACP_VCTR_d(23 downto 16); + IF acp_vctr16_ena_ctrl = '1' THEN + acp_vctr_q(23 downto 16) <= acp_vctr_d(23 downto 16); END IF; - IF ACP_VCTR8_ena_ctrl = '1' THEN - ACP_VCTR_q(15 downto 8) <= ACP_VCTR_d(15 downto 8); + IF acp_vctr8_ena_ctrl = '1' THEN + acp_vctr_q(15 downto 8) <= acp_vctr_d(15 downto 8); END IF; - IF ACP_VCTR6_ena_ctrl = '1' THEN - ACP_VCTR_q(7 downto 6) <= ACP_VCTR_d(7 downto 6); + IF acp_vctr6_ena_ctrl = '1' THEN + acp_vctr_q(7 downto 6) <= acp_vctr_d(7 downto 6); END IF; - IF ACP_VCTR0_ena_ctrl = '1' THEN - ACP_VCTR_q(5 downto 0) <= ACP_VCTR_d(5 downto 0); + IF acp_vctr0_ena_ctrl = '1' THEN + acp_vctr_q(5 downto 0) <= acp_vctr_d(5 downto 0); END IF; - IF SYS_CTR0_ena_ctrl='1' THEN - SYS_CTR_q <= SYS_CTR_d; + IF sys_ctr0_ena_ctrl='1' THEN + sys_ctr_q <= sys_ctr_d; END IF; - IF LOF8_ena_ctrl = '1' THEN - LOF_q(15 downto 8) <= LOF_d(15 downto 8); + IF lof8_ena_ctrl = '1' THEN + lof_q(15 downto 8) <= lof_d(15 downto 8); END IF; - IF LOF0_ena_ctrl = '1' THEN - LOF_q(7 downto 0) <= LOF_d(7 downto 0); + IF lof0_ena_ctrl = '1' THEN + lof_q(7 downto 0) <= lof_d(7 downto 0); END IF; - IF LWD8_ena_ctrl = '1' THEN - LWD_q(15 downto 8) <= LWD_d(15 downto 8); + IF lwd8_ena_ctrl = '1' THEN + lwd_q(15 downto 8) <= lwd_d(15 downto 8); END IF; - IF LWD0_ena_ctrl = '1' THEN - LWD_q(7 downto 0) <= LWD_d(7 downto 0); + IF lwd0_ena_ctrl = '1' THEN + lwd_q(7 downto 0) <= lwd_d(7 downto 0); END IF; IF HDB8_ena_ctrl = '1' THEN @@ -771,8 +754,8 @@ begin PROCESS (pixel_clk_i) BEGIN IF rising_edge(pixel_clk_i) THEN - CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; - CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; + clut_mux_av1_q <= clut_mux_av1_d; + clut_mux_av0_q <= clut_mux_av0_d; CLUT_TA_q <= CLUT_TA_d; HSYNC_I_q <= HSYNC_I_d; HSY_LEN_q <= HSY_LEN_d; @@ -972,31 +955,31 @@ begin -- $F8260/2 st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0'; - -- ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); - ST_SHIFT_MODE_d <= FB_AD(25 downto 24); - ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); + -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); + st_shift_mode_d <= FB_AD(25 downto 24); + st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and FB_B(0); -- MONO - COLOR1_1 <= to_std_logic(ST_SHIFT_MODE_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR1_1 <= to_std_logic(st_shift_mode_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); -- 4 FARBEN - COLOR2 <= to_std_logic(ST_SHIFT_MODE_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR2 <= to_std_logic(st_shift_mode_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); -- 16 FARBEN - COLOR4_1 <= to_std_logic(ST_SHIFT_MODE_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); -- FALCON SHIFT MODE -- $F8266/2 - FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011"); - FALCON_SHIFT_MODE_d <= FB_AD(26 downto 16); - FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(2); - FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(3); + falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011"); + falcon_shift_mode_d <= FB_AD(26 downto 16); + falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(2); + falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(3); - CLUT_OFF <= FALCON_SHIFT_MODE_q(3 downto 0) and sizeIt(COLOR4_i, 4); - COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR16_1 <= FALCON_SHIFT_MODE_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + CLUT_OFF <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4); + COLOR1_2 <= falcon_shift_mode_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR8_1 <= falcon_shift_mode_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR16_1 <= falcon_shift_mode_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); -- ACP VIDEO CONTROL @@ -1015,21 +998,21 @@ begin -- BIT 26 = STANDARD ATARI SYNCS -- $400/4 - ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000"); + acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000"); - ACP_VCTR_d(31 downto 8) <= FB_AD(31 downto 8); - ACP_VCTR_d(5 downto 0) <= FB_AD(5 downto 0); + acp_vctr_d(31 downto 8) <= FB_AD(31 downto 8); + acp_vctr_d(5 downto 0) <= FB_AD(5 downto 0); - ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); - ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); - ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); - ACP_VCTR0_ena_ctrl <= ACP_VCTR_CS and FB_B(3) and (not nFB_WR); - ACP_VIDEO_ON <= ACP_VCTR_q(0); - nPD_VGA <= ACP_VCTR_q(1); + acp_vctr24_ena_ctrl <= acp_vctr_CS and FB_B(0) and (not nFB_WR); + acp_vctr16_ena_ctrl <= acp_vctr_CS and FB_B(1) and (not nFB_WR); + acp_vctr8_ena_ctrl <= acp_vctr_CS and FB_B(2) and (not nFB_WR); + acp_vctr0_ena_ctrl <= acp_vctr_CS and FB_B(3) and (not nFB_WR); + ACP_VIDEO_ON <= acp_vctr_q(0); + nPD_VGA <= acp_vctr_q(1); -- ATARI MODUS - -- WENN 1 AUTOMATISCHE AUFLÖSUNG - ATARI_SYNC <= ACP_VCTR_q(26); + -- WENN 1 AUTOMATISCHE AUFLÖSUNG + ATARI_SYNC <= acp_vctr_q(26); -- HORIZONTAL TIMING 640x480 @@ -1076,10 +1059,10 @@ begin VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1); VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VR_WR_q); VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); - VR_DOUT0_ena_ctrl <= not VR_BUSY; - VR_DOUT_d <= VR_D; - VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100"); - VR_FRQ_d <= FB_AD(23 downto 16); + vr_dout0_ena_ctrl <= not VR_BUSY; + vr_dout_d <= VR_D; + vr_frq0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100"); + vr_frq_d <= FB_AD(23 downto 16); -- VIDEO PLL RECONFIG -- $(F)000'0800 @@ -1087,23 +1070,23 @@ begin VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q); -- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR <= ACP_VCTR_q(31 downto 16); + VIDEO_RAM_CTR <= acp_vctr_q(31 downto 16); -- ------------ COLOR MODE IM ACP SETZEN - COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR8_2 <= ACP_VCTR_q(4) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR16_2 <= ACP_VCTR_q(3) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR24 <= ACP_VCTR_q(2) and ACP_VIDEO_ON; + COLOR1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + COLOR8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + COLOR16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + COLOR24 <= acp_vctr_q(2) and ACP_VIDEO_ON; ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1); -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER - ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); - FALCON_VIDEO <= ACP_VCTR_q(7); + acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); + FALCON_VIDEO <= acp_vctr_q(7); FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); - ST_VIDEO <= ACP_VCTR_q(6); + ST_VIDEO <= acp_vctr_q(6); ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not COLOR1); pixel_clk_i <= pixel_clk; @@ -1117,11 +1100,11 @@ begin -- RANDFARBE -- $404/4 - BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001"); - BORDER_COLOR_d <= FB_AD(23 downto 0); - BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); - BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); - BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); + border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001"); + border_color_d <= FB_AD(23 downto 0); + border_color16_ena_ctrl <= border_color_CS and FB_B(1) and (not nFB_WR); + border_color8_ena_ctrl <= border_color_CS and FB_B(2) and (not nFB_WR); + border_color0_ena_ctrl <= border_color_CS and FB_B(3) and (not nFB_WR); -- System Config Register -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi @@ -1146,27 +1129,28 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp(FB_ADR, 20x"f8006", 1); + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(FB_ADR, 20x"f8006") = '1'; -- FB_ADR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; - -- SYS_CTR_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011"); - SYS_CTR_d <= FB_AD(22 downto 16); - SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); - BLITTER_ON <= not SYS_CTR_q(3); + -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011"); + sys_ctr_d <= FB_AD(22 downto 16); + sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and FB_B(3); + BLITTER_ON <= not sys_ctr_q(3); - -- LOF + -- lof -- $820E/2 - LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111"); - LOF_d <= FB_AD(31 downto 16); - LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); - LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); - - -- LWD + lof_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111"); + lof_d <= FB_AD(31 downto 16); + lof8_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(2); + lof0_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(3); + lof <= lof_q; + + -- lwd -- $8210/2 - LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000"); - LWD_d <= FB_AD(31 downto 16); - LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); - LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); + lwd_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000"); + lwd_d <= FB_AD(31 downto 16); + lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(0); + lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(1); -- HORIZONTAL -- HHT @@ -1249,7 +1233,8 @@ begin -- VFT -- $82A2/2 - VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001"); + -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001"); + vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); VFT_d <= FB_AD(26 downto 16); VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); @@ -1269,10 +1254,10 @@ begin -- - REGISTER OUT -- low word register access --- u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or --- (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or --- (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or --- (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or +-- u0_data <= (sizeIt(st_shift_mode_CS,16) and std_logic_vector'("000000" & st_shift_mode_q & "00000000")) or +-- (sizeIt(falcon_shift_mode_CS,16) and std_logic_vector'("00000" & falcon_shift_mode_q)) or +-- (sizeIt(sys_ctr_CS,16) and std_logic_vector'("100000000" & sys_ctr_q(6 downto 4) & (not BLITTER_RUN) & sys_ctr_q(2 downto 0))) or +-- (sizeIt(lof_CS,16) and lof_q) or (sizeIt(lwd_CS,16) and lwd_q) or -- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or -- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or -- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or @@ -1287,13 +1272,13 @@ begin -- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or -- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or -- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or --- (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or +-- (sizeIt(acp_vctr_CS,16) and acp_vctr_q(31 downto 16)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or --- (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or --- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or +-- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or +-- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else @@ -1320,22 +1305,22 @@ begin atari_vl_q(31 downto 16) when atari_vl_cs = '1' else "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else "0000000" & vr_dout_q when video_pll_config_cs = '1' else - vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else (others => 'Z'); --- u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or +-- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or -- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); -- FB_AD(31 downto 16) <= u0_tridata; -- high word register access --- u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or +-- u1_data <= (sizeIt(acp_vctr_CS,16) and acp_vctr_q(15 downto 0)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or --- (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); --- u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); +-- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0)); +-- u1_enabledt <= (acp_vctr_CS or border_color_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); -- FB_AD(15 downto 0) <= u1_tridata; fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else @@ -1346,7 +1331,7 @@ begin border_color_q(15 downto 0) when border_color_cs = '1' else (others => 'Z'); - video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or + video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; @@ -1362,12 +1347,12 @@ begin (CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or (CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or - (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "00")) or - (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "01")) or - (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9)); + (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "00")) or + (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "01")) or + (CLK_VIDEO and ACP_VIDEO_ON and acp_vctr_q(9)); -- ------------------------------------------------------------ - -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK + -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -- -------------------------------------------------------------- -- 320 pixels, 32 MHz, RGB @@ -1389,9 +1374,9 @@ begin -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "00"), 8)) or - -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "01"), 8)) or - -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(ACP_VCTR_q(9), 8)); + -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or + -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or + -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(acp_vctr_q(9), 8)); -- MULTIPLIKATIONS FAKTOR MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or @@ -1414,7 +1399,7 @@ begin VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); --- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START +-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q; -- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON @@ -1493,7 +1478,7 @@ begin VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - -- ZÄHLER + -- ZÄHLER LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); @@ -1505,7 +1490,7 @@ begin -- 1 ZEILE DAVOR ON OFF DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); - -- AM ZEILENENDE ÃœBERNEHMEN + -- AM ZEILENENDE ÃœBERNEHMEN DPO_ZL_ena <= LAST_q; -- BESSER EINZELN WEGEN TIMING @@ -1521,7 +1506,7 @@ begin VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); - -- AM ZEILENENDE ÃœBERNEHMEN + -- AM ZEILENENDE ÃœBERNEHMEN VCO_ZL_ena <= LAST_q; -- 1 ZEILE DAVOR ON OFF @@ -1529,7 +1514,7 @@ begin VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); - -- VERZÖGERUNG UND SYNC + -- VERZÖGERUNG UND SYNC HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); @@ -1547,7 +1532,7 @@ begin VSYNC_I0_ena_ctrl <= LAST_q; -- 3 zeilen vsync length - -- runterzählen bis 0 + -- runterzählen bis 0 VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= 3x"0" else (others => '0'); @@ -1567,14 +1552,14 @@ begin VERZ0_d(0) <= DISP_ON_q; -- VERZ[1][0] = HSYNC_I[] != 0; - -- NUR MÖGLICH WENN BEIDE - VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') - and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + VERZ1_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') + and HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); - -- NUR MÖGLICH WENN BEIDE - VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') - and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + VERZ2_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') + and VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); -- nBLANK = VERZ[0][8]; @@ -1583,20 +1568,20 @@ begin -- nBLANK_d <= DISP_ON_q; -- HSYNC = VERZ[1][9]; - -- NUR MÖGLICH WENN BEIDE - HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and - HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + HSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') and + HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); -- VSYNC = VERZ[2][9]; - -- NUR MÖGLICH WENN BEIDE - VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and - VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + VSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') and + VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); nSYNC <= gnd; -- RANDFARBE MACHEN ------------------------------------ - RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25); RAND_d(1) <= RAND_q(0); RAND_d(2) <= RAND_q(1); RAND_d(3) <= RAND_q(2); @@ -1606,25 +1591,25 @@ begin -- RAND_ON = RAND[6]; rand_on <= rand(6); - -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25); -- -------------------------------------------------------- CLR_FIFO_ena <= LAST_q; - -- IN LETZTER ZEILE LÖSCHEN + -- IN LETZTER ZEILE LÖSCHEN CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); START_ZEILE_ena <= LAST_q; -- ZEILE 1 START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; @@ -1632,7 +1617,7 @@ begin -- count up if display on sonst clear bei sync pix SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); - -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or @@ -1641,9 +1626,9 @@ begin (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 downto 0); - CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; - CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; + clut_mux_av0_d <= SUB_PIXEL_CNT_q(3 downto 0); + clut_mux_av1_d <= clut_mux_av0_q; + clut_mux_adr_d <= clut_mux_av1_q; -- Assignments added to explicitly combine the diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index f42b241..5b8eadb 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,311 +556,312 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file